* [PATCH] ARM: dts: exynos: Add audio power domain support to Exynos542x SoCs
[not found] <CGME20161222141755epcas5p4549c18c84aa823c553bb33a12eb82ee2@epcas5p4.samsung.com>
@ 2016-12-22 14:17 ` Marek Szyprowski
2016-12-23 2:17 ` Krzysztof Kozlowski
0 siblings, 1 reply; 3+ messages in thread
From: Marek Szyprowski @ 2016-12-22 14:17 UTC (permalink / raw)
To: linux-samsung-soc
Cc: Marek Szyprowski, Sylwester Nawrocki, Krzysztof Kozlowski,
Bartlomiej Zolnierkiewicz
Audio power domain includes following hardware modules: Pin controller
for GPZ bank, AudioSS clock controller, PL330 ADMA device and Exynos I2S
controller.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
Currently this domain will not be turned off, because pinctrl and clock
controller don't support runtime PM and PL330 ADMA requires irq-safe runtime
PM. Separate patches for those devices/subsystems will be posted to get
proper runtime PM available and finally let this power domain to be turned
off.
---
arch/arm/boot/dts/exynos5420.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 0154c2e..d9ebc33 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -188,6 +188,7 @@
clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
<&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
+ power-domains = <&mau_pd>;
};
mfc: codec@11000000 {
@@ -317,6 +318,12 @@
clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1";
};
+ mau_pd: power-domain@100440E0 {
+ compatible = "samsung,exynos4210-pd";
+ reg = <0x100440E0 0x20>;
+ #power-domain-cells = <0>;
+ };
+
pinctrl_0: pinctrl@13400000 {
compatible = "samsung,exynos5420-pinctrl";
reg = <0x13400000 0x1000>;
@@ -351,6 +358,7 @@
compatible = "samsung,exynos5420-pinctrl";
reg = <0x03860000 0x1000>;
interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&mau_pd>;
};
amba {
@@ -369,6 +377,7 @@
#dma-cells = <1>;
#dma-channels = <6>;
#dma-requests = <16>;
+ power-domains = <&mau_pd>;
};
pdma0: pdma@121A0000 {
@@ -441,6 +450,7 @@
samsung,idma-addr = <0x03000000>;
pinctrl-names = "default";
pinctrl-0 = <&i2s0_bus>;
+ power-domains = <&mau_pd>;
status = "disabled";
};
--
1.9.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] ARM: dts: exynos: Add audio power domain support to Exynos542x SoCs
2016-12-22 14:17 ` [PATCH] ARM: dts: exynos: Add audio power domain support to Exynos542x SoCs Marek Szyprowski
@ 2016-12-23 2:17 ` Krzysztof Kozlowski
2016-12-23 11:52 ` Marek Szyprowski
0 siblings, 1 reply; 3+ messages in thread
From: Krzysztof Kozlowski @ 2016-12-23 2:17 UTC (permalink / raw)
To: Marek Szyprowski
Cc: linux-samsung-soc, Sylwester Nawrocki, Krzysztof Kozlowski,
Bartlomiej Zolnierkiewicz
On Thu, Dec 22, 2016 at 03:17:44PM +0100, Marek Szyprowski wrote:
> Audio power domain includes following hardware modules: Pin controller
> for GPZ bank, AudioSS clock controller, PL330 ADMA device and Exynos I2S
> controller.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
> Currently this domain will not be turned off, because pinctrl and clock
> controller don't support runtime PM and PL330 ADMA requires irq-safe runtime
> PM. Separate patches for those devices/subsystems will be posted to get
> proper runtime PM available and finally let this power domain to be turned
> off.
> ---
> arch/arm/boot/dts/exynos5420.dtsi | 10 ++++++++++
> 1 file changed, 10 insertions(+)
The issue discovered by me here:
http://lkml.iu.edu/hypermail/linux/kernel/1502.1/01733.html
does not happen anymore?
Best regards,
Krzysztof
> diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
> index 0154c2e..d9ebc33 100644
> --- a/arch/arm/boot/dts/exynos5420.dtsi
> +++ b/arch/arm/boot/dts/exynos5420.dtsi
> @@ -188,6 +188,7 @@
> clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
> <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
> clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
> + power-domains = <&mau_pd>;
> };
>
> mfc: codec@11000000 {
> @@ -317,6 +318,12 @@
> clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1";
> };
>
> + mau_pd: power-domain@100440E0 {
> + compatible = "samsung,exynos4210-pd";
> + reg = <0x100440E0 0x20>;
> + #power-domain-cells = <0>;
> + };
> +
> pinctrl_0: pinctrl@13400000 {
> compatible = "samsung,exynos5420-pinctrl";
> reg = <0x13400000 0x1000>;
> @@ -351,6 +358,7 @@
> compatible = "samsung,exynos5420-pinctrl";
> reg = <0x03860000 0x1000>;
> interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&mau_pd>;
> };
>
> amba {
> @@ -369,6 +377,7 @@
> #dma-cells = <1>;
> #dma-channels = <6>;
> #dma-requests = <16>;
> + power-domains = <&mau_pd>;
> };
>
> pdma0: pdma@121A0000 {
> @@ -441,6 +450,7 @@
> samsung,idma-addr = <0x03000000>;
> pinctrl-names = "default";
> pinctrl-0 = <&i2s0_bus>;
> + power-domains = <&mau_pd>;
> status = "disabled";
> };
>
> --
> 1.9.1
>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] ARM: dts: exynos: Add audio power domain support to Exynos542x SoCs
2016-12-23 2:17 ` Krzysztof Kozlowski
@ 2016-12-23 11:52 ` Marek Szyprowski
0 siblings, 0 replies; 3+ messages in thread
From: Marek Szyprowski @ 2016-12-23 11:52 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: linux-samsung-soc, Sylwester Nawrocki, Bartlomiej Zolnierkiewicz
Hi Krzysztof,
On 2016-12-23 03:17, Krzysztof Kozlowski wrote:
> On Thu, Dec 22, 2016 at 03:17:44PM +0100, Marek Szyprowski wrote:
>> Audio power domain includes following hardware modules: Pin controller
>> for GPZ bank, AudioSS clock controller, PL330 ADMA device and Exynos I2S
>> controller.
>>
>> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
>> ---
>> Currently this domain will not be turned off, because pinctrl and clock
>> controller don't support runtime PM and PL330 ADMA requires irq-safe runtime
>> PM. Separate patches for those devices/subsystems will be posted to get
>> proper runtime PM available and finally let this power domain to be turned
>> off.
>> ---
>> arch/arm/boot/dts/exynos5420.dtsi | 10 ++++++++++
>> 1 file changed, 10 insertions(+)
>
> The issue discovered by me here:
> http://lkml.iu.edu/hypermail/linux/kernel/1502.1/01733.html
> does not happen anymore?
Right, it is still valid if we consider this patch alone. I will move it
then to
Exynos pin controller runtime pm patchset, which solves it. I will send
in a few
minutes.
>
> Best regards,
> Krzysztof
>
>> diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
>> index 0154c2e..d9ebc33 100644
>> --- a/arch/arm/boot/dts/exynos5420.dtsi
>> +++ b/arch/arm/boot/dts/exynos5420.dtsi
>> @@ -188,6 +188,7 @@
>> clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>,
>> <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>;
>> clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
>> + power-domains = <&mau_pd>;
>> };
>>
>> mfc: codec@11000000 {
>> @@ -317,6 +318,12 @@
>> clock-names = "oscclk", "clk0", "clk1", "clk2", "asb0", "asb1";
>> };
>>
>> + mau_pd: power-domain@100440E0 {
>> + compatible = "samsung,exynos4210-pd";
>> + reg = <0x100440E0 0x20>;
>> + #power-domain-cells = <0>;
>> + };
>> +
>> pinctrl_0: pinctrl@13400000 {
>> compatible = "samsung,exynos5420-pinctrl";
>> reg = <0x13400000 0x1000>;
>> @@ -351,6 +358,7 @@
>> compatible = "samsung,exynos5420-pinctrl";
>> reg = <0x03860000 0x1000>;
>> interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
>> + power-domains = <&mau_pd>;
>> };
>>
>> amba {
>> @@ -369,6 +377,7 @@
>> #dma-cells = <1>;
>> #dma-channels = <6>;
>> #dma-requests = <16>;
>> + power-domains = <&mau_pd>;
>> };
>>
>> pdma0: pdma@121A0000 {
>> @@ -441,6 +450,7 @@
>> samsung,idma-addr = <0x03000000>;
>> pinctrl-names = "default";
>> pinctrl-0 = <&i2s0_bus>;
>> + power-domains = <&mau_pd>;
>> status = "disabled";
>> };
>>
>> --
>> 1.9.1
>>
>
>
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland
^ permalink raw reply [flat|nested] 3+ messages in thread
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2016-12-22 14:17 ` [PATCH] ARM: dts: exynos: Add audio power domain support to Exynos542x SoCs Marek Szyprowski
2016-12-23 2:17 ` Krzysztof Kozlowski
2016-12-23 11:52 ` Marek Szyprowski
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