From: Adam Ford <aford173@gmail.com>
To: Jagan Teki <jagan@amarulasolutions.com>
Cc: Andrzej Hajda <andrzej.hajda@intel.com>,
Inki Dae <inki.dae@samsung.com>,
Marek Szyprowski <m.szyprowski@samsung.com>,
Joonyoung Shim <jy0922.shim@samsung.com>,
Seung-Woo Kim <sw0312.kim@samsung.com>,
Kyungmin Park <kyungmin.park@samsung.com>,
Frieder Schrempf <frieder.schrempf@kontron.de>,
Fancy Fang <chen.fang@nxp.com>,
Tim Harvey <tharvey@gateworks.com>,
Michael Nazzareno Trimarchi <michael@amarulasolutions.com>,
Neil Armstrong <narmstrong@baylibre.com>,
Robert Foss <robert.foss@linaro.org>,
Laurent Pinchart <Laurent.pinchart@ideasonboard.com>,
Tommaso Merciai <tommaso.merciai@amarulasolutions.com>,
Marek Vasut <marex@denx.de>,
Matteo Lisi <matteo.lisi@engicam.com>,
dri-devel <dri-devel@lists.freedesktop.org>,
linux-samsung-soc <linux-samsung-soc@vger.kernel.org>,
arm-soc <linux-arm-kernel@lists.infradead.org>,
NXP Linux Team <linux-imx@nxp.com>,
linux-amarula <linux-amarula@amarulasolutions.com>
Subject: Re: [PATCH v4 07/12] drm: bridge: samsung-dsim: Fix PLL_P (PMS_P) offset
Date: Mon, 29 Aug 2022 14:42:00 -0500 [thread overview]
Message-ID: <CAHCN7xKxS6oaX8kGYv_bhWfCFUEMBykN87BwXMPkcCg=OwKXrw@mail.gmail.com> (raw)
In-Reply-To: <20220829184031.1863663-8-jagan@amarulasolutions.com>
On Mon, Aug 29, 2022 at 1:41 PM Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> The i.MX 8M Mini Applications Processor Reference Manual, Rev. 3, 11/2020
> with 13.7.10.1 Master PLL PMS Value setting Register mentioned PMS_P offset
> range from BIT[18-13] and the upstream driver is using the same offset.
>
> However, offset 13 is not working on i.MX8M Mini platforms but downstream
> NXP driver is using 14 [1] and it is working with i.MX8M Mini SoC.
From the line you highlighted in the link, the downstream NXP ones
shows 13 if I'm reading it correctly.
#define PLLCTRL_SET_P(x) REG_PUT(x, 18, 13)
From what I can tell the PMS calculation here needs to be updated for
the Mini because the ranges of the FCO calculator are different. Took
your series and tweaked it a bit [2] which changes a few settings, and
the PMS calculator appears to more closely match the values I get from
the NXP one. I think it could be further tweaked because p min and
p_max also have changed.
>
> Not sure about whether it is reference manual documentation or something
> else but this patch trusts the downstream code and fixes the PLL_P offset.
>
> [1] https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/gpu/drm/bridge/sec-dsim.c?h=imx_5.4.47_2.2.0#n211
>
[2] -https://github.com/aford173/linux/commit/a5fa184160ec9ea45a7546eaa0d8b8fc760cf3d9
> v4, v3, v2:
> * none
>
> v1:
> * updated commit message
> * add downstream driver link
>
> Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> ---
> drivers/gpu/drm/bridge/samsung-dsim.c | 10 ++++++++--
> include/drm/bridge/samsung-dsim.h | 1 +
> 2 files changed, 9 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
> index b6883a6d4681..b6d17c0c9e58 100644
> --- a/drivers/gpu/drm/bridge/samsung-dsim.c
> +++ b/drivers/gpu/drm/bridge/samsung-dsim.c
> @@ -168,7 +168,7 @@
> /* DSIM_PLLCTRL */
> #define DSIM_FREQ_BAND(x) ((x) << 24)
> #define DSIM_PLL_EN (1 << 23)
> -#define DSIM_PLL_P(x) ((x) << 13)
> +#define DSIM_PLL_P(x, offset) ((x) << (offset))
> #define DSIM_PLL_M(x) ((x) << 4)
> #define DSIM_PLL_S(x) ((x) << 1)
>
> @@ -368,6 +368,7 @@ static const struct samsung_dsim_driver_data exynos3_dsi_driver_data = {
> .max_freq = 1000,
> .wait_for_reset = 1,
> .num_bits_resol = 11,
> + .pll_p_offset = 13,
> .reg_values = reg_values,
> .quirks = DSIM_QUIRK_PLAT_DATA,
> };
> @@ -381,6 +382,7 @@ static const struct samsung_dsim_driver_data exynos4_dsi_driver_data = {
> .max_freq = 1000,
> .wait_for_reset = 1,
> .num_bits_resol = 11,
> + .pll_p_offset = 13,
> .reg_values = reg_values,
> .quirks = DSIM_QUIRK_PLAT_DATA,
> };
> @@ -392,6 +394,7 @@ static const struct samsung_dsim_driver_data exynos5_dsi_driver_data = {
> .max_freq = 1000,
> .wait_for_reset = 1,
> .num_bits_resol = 11,
> + .pll_p_offset = 13,
> .reg_values = reg_values,
> .quirks = DSIM_QUIRK_PLAT_DATA,
> };
> @@ -404,6 +407,7 @@ static const struct samsung_dsim_driver_data exynos5433_dsi_driver_data = {
> .max_freq = 1500,
> .wait_for_reset = 0,
> .num_bits_resol = 12,
> + .pll_p_offset = 13,
> .reg_values = exynos5433_reg_values,
> .quirks = DSIM_QUIRK_PLAT_DATA,
> };
> @@ -416,6 +420,7 @@ static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = {
> .max_freq = 1500,
> .wait_for_reset = 1,
> .num_bits_resol = 12,
> + .pll_p_offset = 13,
> .reg_values = exynos5422_reg_values,
> .quirks = DSIM_QUIRK_PLAT_DATA,
> };
> @@ -563,7 +568,8 @@ static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi,
> writel(driver_data->reg_values[PLL_TIMER],
> dsi->reg_base + driver_data->plltmr_reg);
>
> - reg = DSIM_PLL_EN | DSIM_PLL_P(p) | DSIM_PLL_M(m) | DSIM_PLL_S(s);
> + reg = DSIM_PLL_EN | DSIM_PLL_P(p, driver_data->pll_p_offset) |
> + DSIM_PLL_M(m) | DSIM_PLL_S(s);
>
> if (driver_data->has_freqband) {
> static const unsigned long freq_bands[] = {
> diff --git a/include/drm/bridge/samsung-dsim.h b/include/drm/bridge/samsung-dsim.h
> index e15fbfd49efe..95d3f89aec4f 100644
> --- a/include/drm/bridge/samsung-dsim.h
> +++ b/include/drm/bridge/samsung-dsim.h
> @@ -47,6 +47,7 @@ struct samsung_dsim_driver_data {
> unsigned int max_freq;
> unsigned int wait_for_reset;
> unsigned int num_bits_resol;
> + unsigned int pll_p_offset;
> const unsigned int *reg_values;
> enum samsung_dsim_quirks quirks;
> };
> --
> 2.25.1
>
next prev parent reply other threads:[~2022-08-29 19:42 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-29 18:40 [PATCH v4 00/12] drm: bridge: Add Samsung MIPI DSIM bridge Jagan Teki
2022-08-29 18:40 ` [PATCH v4 01/12] drm: exynos: dsi: Restore proper bridge chain order Jagan Teki
2022-08-29 18:40 ` [PATCH v4 03/12] drm: bridge: samsung-dsim: Lookup OF-graph or Child node devices Jagan Teki
2022-08-29 18:40 ` [PATCH v4 04/12] drm: bridge: samsung-dsim: Handle platform init via driver_data Jagan Teki
2022-08-29 18:40 ` [PATCH v4 05/12] drm: bridge: samsung-dsim: Mark PHY as optional Jagan Teki
2022-08-29 18:40 ` [PATCH v4 06/12] drm: bridge: samsung-dsim: Handle proper DSI host initialization Jagan Teki
2022-08-29 18:40 ` [PATCH v4 07/12] drm: bridge: samsung-dsim: Fix PLL_P (PMS_P) offset Jagan Teki
2022-08-29 19:42 ` Adam Ford [this message]
2022-09-14 8:22 ` Jagan Teki
2022-08-29 18:40 ` [PATCH v4 08/12] drm: bridge: samsung-dsim: Add atomic_check Jagan Teki
2022-08-29 18:40 ` [PATCH v4 09/12] drm: bridge: samsung-dsim: Add atomic_get_input_bus_fmts Jagan Teki
2022-08-29 18:40 ` [PATCH v4 10/12] drm: bridge: samsung-dsim: Add input_bus_flags Jagan Teki
2022-08-29 18:40 ` [PATCH v4 11/12] dt-bindings: display: exynos: dsim: Add NXP i.MX8MM support Jagan Teki
2022-08-29 18:40 ` [PATCH v4 12/12] drm: bridge: samsung-dsim: Add " Jagan Teki
[not found] ` <CGME20220829184118eucas1p2cda47fa166cafcb904800a55a5f66180@eucas1p2.samsung.com>
[not found] ` <20220829184031.1863663-3-jagan@amarulasolutions.com>
2022-09-02 10:47 ` [PATCH v4 02/12] drm: bridge: Add Samsung DSIM bridge driver Marek Szyprowski
2022-09-05 11:24 ` Marek Szyprowski
2022-09-06 19:07 ` Jagan Teki
2022-09-07 10:04 ` Marek Szyprowski
2022-09-12 14:52 ` Frieder Schrempf
2022-09-13 17:29 ` Jagan Teki
2022-09-14 9:21 ` Marek Szyprowski
2022-09-14 9:39 ` Jagan Teki
2022-09-16 8:28 ` Marek Szyprowski
2022-09-16 10:21 ` Jagan Teki
2022-09-19 6:22 ` Marek Szyprowski
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