* [v2 1/5] mpt3sas: don't change the dma coherent mask after allocations
2020-04-23 7:23 [v2 0/5] mpt3sas: Fix changing coherent mask after allocation Suganath Prabu
@ 2020-04-23 7:23 ` Suganath Prabu
2020-04-23 7:23 ` [v2 2/5] mpt3sas: Rename function name is_MSB_are_same Suganath Prabu
` (4 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Suganath Prabu @ 2020-04-23 7:23 UTC (permalink / raw)
To: linux-scsi
Cc: hch, Sathya.Prakash, sreekanth.reddy, Suganath Prabu, Christoph Hellwig
From: Christoph Hellwig <hch@lst.de>
The DMA layer does not allow changing the DMA coherent mask after
there are outstanding allocations.
Reported-by: Abdul Haleem <abdhalee@linux.vnet.ibm.com>
Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Suganath Prabu <suganath-prabu.subramani@broadcom.com>
---
v2:
Initial patch was always setting dma coherent mask to 32 bit,
now dma coherent mask is setting to either 32 bit or 63/64 bit
based on controller capability.
drivers/scsi/mpt3sas/mpt3sas_base.c | 67 +++++++++++--------------------------
drivers/scsi/mpt3sas/mpt3sas_base.h | 2 --
2 files changed, 19 insertions(+), 50 deletions(-)
diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c b/drivers/scsi/mpt3sas/mpt3sas_base.c
index 663782b..b8679c2 100644
--- a/drivers/scsi/mpt3sas/mpt3sas_base.c
+++ b/drivers/scsi/mpt3sas/mpt3sas_base.c
@@ -2806,58 +2806,38 @@ _base_build_sg_ieee(struct MPT3SAS_ADAPTER *ioc, void *psge,
static int
_base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev)
{
- u64 required_mask, coherent_mask;
struct sysinfo s;
- /* Set 63 bit DMA mask for all SAS3 and SAS35 controllers */
- int dma_mask = (ioc->hba_mpi_version_belonged > MPI2_VERSION) ? 63 : 64;
-
- if (ioc->is_mcpu_endpoint)
- goto try_32bit;
+ int dma_mask;
- required_mask = dma_get_required_mask(&pdev->dev);
- if (sizeof(dma_addr_t) == 4 || required_mask == 32)
- goto try_32bit;
-
- if (ioc->dma_mask)
- coherent_mask = DMA_BIT_MASK(dma_mask);
+ if (ioc->is_mcpu_endpoint ||
+ sizeof(dma_addr_t) == 4 ||
+ dma_get_required_mask(&pdev->dev) <= 32)
+ dma_mask = 32;
+ /* Set 63 bit DMA mask for all SAS3 and SAS35 controllers */
+ else if (ioc->hba_mpi_version_belonged > MPI2_VERSION)
+ dma_mask = 63;
else
- coherent_mask = DMA_BIT_MASK(32);
+ dma_mask = 64;
if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(dma_mask)) ||
- dma_set_coherent_mask(&pdev->dev, coherent_mask))
- goto try_32bit;
-
- ioc->base_add_sg_single = &_base_add_sg_single_64;
- ioc->sge_size = sizeof(Mpi2SGESimple64_t);
- ioc->dma_mask = dma_mask;
- goto out;
-
- try_32bit:
- if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
+ dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(dma_mask)))
return -ENODEV;
- ioc->base_add_sg_single = &_base_add_sg_single_32;
- ioc->sge_size = sizeof(Mpi2SGESimple32_t);
- ioc->dma_mask = 32;
- out:
+ if (dma_mask > 32) {
+ ioc->base_add_sg_single = &_base_add_sg_single_64;
+ ioc->sge_size = sizeof(Mpi2SGESimple64_t);
+ } else {
+ ioc->base_add_sg_single = &_base_add_sg_single_32;
+ ioc->sge_size = sizeof(Mpi2SGESimple32_t);
+ }
+
si_meminfo(&s);
ioc_info(ioc, "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n",
- ioc->dma_mask, convert_to_kb(s.totalram));
+ dma_mask, convert_to_kb(s.totalram));
return 0;
}
-static int
-_base_change_consistent_dma_mask(struct MPT3SAS_ADAPTER *ioc,
- struct pci_dev *pdev)
-{
- if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(ioc->dma_mask))) {
- if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
- return -ENODEV;
- }
- return 0;
-}
-
/**
* _base_check_enable_msix - checks MSIX capabable.
* @ioc: per adapter object
@@ -5169,14 +5149,6 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc)
total_sz += sz;
} while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count));
- if (ioc->dma_mask > 32) {
- if (_base_change_consistent_dma_mask(ioc, ioc->pdev) != 0) {
- ioc_warn(ioc, "no suitable consistent DMA mask for %s\n",
- pci_name(ioc->pdev));
- goto out;
- }
- }
-
ioc->scsiio_depth = ioc->hba_queue_depth -
ioc->hi_priority_depth - ioc->internal_depth;
@@ -7158,7 +7130,6 @@ mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc)
ioc->smp_affinity_enable = smp_affinity_enable;
ioc->rdpq_array_enable_assigned = 0;
- ioc->dma_mask = 0;
if (ioc->is_aero_ioc)
ioc->base_readl = &_base_readl_aero;
else
diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.h b/drivers/scsi/mpt3sas/mpt3sas_base.h
index e719715..caae040 100644
--- a/drivers/scsi/mpt3sas/mpt3sas_base.h
+++ b/drivers/scsi/mpt3sas/mpt3sas_base.h
@@ -1026,7 +1026,6 @@ typedef void (*MPT3SAS_FLUSH_RUNNING_CMDS)(struct MPT3SAS_ADAPTER *ioc);
* @ir_firmware: IR firmware present
* @bars: bitmask of BAR's that must be configured
* @mask_interrupts: ignore interrupt
- * @dma_mask: used to set the consistent dma mask
* @pci_access_mutex: Mutex to synchronize ioctl, sysfs show path and
* pci resource handling
* @fault_reset_work_q_name: fw fault work queue
@@ -1205,7 +1204,6 @@ struct MPT3SAS_ADAPTER {
u8 ir_firmware;
int bars;
u8 mask_interrupts;
- int dma_mask;
/* fw fault handler */
char fault_reset_work_q_name[20];
--
1.8.3.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [v2 2/5] mpt3sas: Rename function name is_MSB_are_same
2020-04-23 7:23 [v2 0/5] mpt3sas: Fix changing coherent mask after allocation Suganath Prabu
2020-04-23 7:23 ` [v2 1/5] mpt3sas: don't change the dma coherent mask after allocations Suganath Prabu
@ 2020-04-23 7:23 ` Suganath Prabu
2020-04-23 7:23 ` [v2 3/5] mpt3sas: Separate out RDPQ allocation to new function Suganath Prabu
` (3 subsequent siblings)
5 siblings, 0 replies; 11+ messages in thread
From: Suganath Prabu @ 2020-04-23 7:23 UTC (permalink / raw)
To: linux-scsi; +Cc: hch, Sathya.Prakash, sreekanth.reddy, Suganath Prabu
Rename is_MSB_are_same() to mpt3sas_check_same_4gb_region()
for better readability.
Signed-off-by: Suganath Prabu <suganath-prabu.subramani@broadcom.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
---
drivers/scsi/mpt3sas/mpt3sas_base.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c b/drivers/scsi/mpt3sas/mpt3sas_base.c
index b8679c2..f98c7f6 100644
--- a/drivers/scsi/mpt3sas/mpt3sas_base.c
+++ b/drivers/scsi/mpt3sas/mpt3sas_base.c
@@ -4915,7 +4915,7 @@ _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc)
}
/**
- * is_MSB_are_same - checks whether all reply queues in a set are
+ * mpt3sas_check_same_4gb_region - checks whether all reply queues in a set are
* having same upper 32bits in their base memory address.
* @reply_pool_start_address: Base address of a reply queue set
* @pool_sz: Size of single Reply Descriptor Post Queues pool size
@@ -4925,7 +4925,7 @@ _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc)
*/
static int
-is_MSB_are_same(long reply_pool_start_address, u32 pool_sz)
+mpt3sas_check_same_4gb_region(long reply_pool_start_address, u32 pool_sz)
{
long reply_pool_end_address;
@@ -5377,7 +5377,7 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc)
* Actual requirement is not alignment, but we need start and end of
* DMA address must have same upper 32 bit address.
*/
- if (!is_MSB_are_same((long)ioc->sense, sz)) {
+ if (!mpt3sas_check_same_4gb_region((long)ioc->sense, sz)) {
//Release Sense pool & Reallocate
dma_pool_free(ioc->sense_dma_pool, ioc->sense, ioc->sense_dma);
dma_pool_destroy(ioc->sense_dma_pool);
--
1.8.3.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [v2 3/5] mpt3sas: Separate out RDPQ allocation to new function.
2020-04-23 7:23 [v2 0/5] mpt3sas: Fix changing coherent mask after allocation Suganath Prabu
2020-04-23 7:23 ` [v2 1/5] mpt3sas: don't change the dma coherent mask after allocations Suganath Prabu
2020-04-23 7:23 ` [v2 2/5] mpt3sas: Rename function name is_MSB_are_same Suganath Prabu
@ 2020-04-23 7:23 ` Suganath Prabu
2020-04-23 7:54 ` Christoph Hellwig
2020-04-23 7:23 ` [v2 4/5] mpt3sas: Handle RDPQ DMA allocation in same 4G region Suganath Prabu
` (2 subsequent siblings)
5 siblings, 1 reply; 11+ messages in thread
From: Suganath Prabu @ 2020-04-23 7:23 UTC (permalink / raw)
To: linux-scsi; +Cc: hch, Sathya.Prakash, sreekanth.reddy, Suganath Prabu
For readability separate out RDPQ allocations to new function
base_alloc_rdpq_dma_pool().
Signed-off-by: Suganath Prabu <suganath-prabu.subramani@broadcom.com>
---
drivers/scsi/mpt3sas/mpt3sas_base.c | 79 +++++++++++++++++++++----------------
1 file changed, 45 insertions(+), 34 deletions(-)
diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c b/drivers/scsi/mpt3sas/mpt3sas_base.c
index f98c7f6..0588941 100644
--- a/drivers/scsi/mpt3sas/mpt3sas_base.c
+++ b/drivers/scsi/mpt3sas/mpt3sas_base.c
@@ -4939,6 +4939,49 @@ mpt3sas_check_same_4gb_region(long reply_pool_start_address, u32 pool_sz)
}
/**
+ * base_alloc_rdpq_dma_pool - Allocating DMA'able memory
+ * for reply queues.
+ * @ioc: per adapter object
+ * @sz: DMA Pool size
+ * Return: 0 for success, non-zero for failure.
+ */
+static int
+base_alloc_rdpq_dma_pool(struct MPT3SAS_ADAPTER *ioc, int sz)
+{
+ int i;
+ int count = ioc->rdpq_array_enable ? ioc->reply_queue_count : 1;
+
+ ioc->reply_post = kcalloc(count, sizeof(struct reply_post_struct),
+ GFP_KERNEL);
+ if (!ioc->reply_post)
+ return -ENOMEM;
+ ioc->reply_post_free_dma_pool =
+ dma_pool_create("reply_post_free pool",
+ &ioc->pdev->dev, sz, 16, 0);
+ if (!ioc->reply_post_free_dma_pool)
+ return -ENOMEM;
+ i = 0;
+ do {
+ ioc->reply_post[i].reply_post_free =
+ dma_pool_zalloc(ioc->reply_post_free_dma_pool,
+ GFP_KERNEL,
+ &ioc->reply_post[i].reply_post_free_dma);
+ if (!ioc->reply_post[i].reply_post_free)
+ return -ENOMEM;
+ dinitprintk(ioc,
+ ioc_info(ioc, "reply post free pool (0x%p): depth(%d),"
+ "element_size(%d), pool_size(%d kB)\n",
+ ioc->reply_post[i].reply_post_free,
+ ioc->reply_post_queue_depth, 8, sz / 1024));
+ dinitprintk(ioc,
+ ioc_info(ioc, "reply_post_free_dma = (0x%llx)\n",
+ (u64)ioc->reply_post[i].reply_post_free_dma));
+
+ } while (ioc->rdpq_array_enable && ++i < ioc->reply_queue_count);
+ return 0;
+}
+
+/**
* _base_allocate_memory_pools - allocate start of day memory pools
* @ioc: per adapter object
*
@@ -5113,41 +5156,9 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc)
sz = reply_post_free_sz;
if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable)
sz *= ioc->reply_queue_count;
-
- ioc->reply_post = kcalloc((ioc->rdpq_array_enable) ?
- (ioc->reply_queue_count):1,
- sizeof(struct reply_post_struct), GFP_KERNEL);
-
- if (!ioc->reply_post) {
- ioc_err(ioc, "reply_post_free pool: kcalloc failed\n");
+ if (base_alloc_rdpq_dma_pool(ioc, sz))
goto out;
- }
- ioc->reply_post_free_dma_pool = dma_pool_create("reply_post_free pool",
- &ioc->pdev->dev, sz, 16, 0);
- if (!ioc->reply_post_free_dma_pool) {
- ioc_err(ioc, "reply_post_free pool: dma_pool_create failed\n");
- goto out;
- }
- i = 0;
- do {
- ioc->reply_post[i].reply_post_free =
- dma_pool_zalloc(ioc->reply_post_free_dma_pool,
- GFP_KERNEL,
- &ioc->reply_post[i].reply_post_free_dma);
- if (!ioc->reply_post[i].reply_post_free) {
- ioc_err(ioc, "reply_post_free pool: dma_pool_alloc failed\n");
- goto out;
- }
- dinitprintk(ioc,
- ioc_info(ioc, "reply post free pool (0x%p): depth(%d), element_size(%d), pool_size(%d kB)\n",
- ioc->reply_post[i].reply_post_free,
- ioc->reply_post_queue_depth,
- 8, sz / 1024));
- dinitprintk(ioc,
- ioc_info(ioc, "reply_post_free_dma = (0x%llx)\n",
- (u64)ioc->reply_post[i].reply_post_free_dma));
- total_sz += sz;
- } while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count));
+ total_sz += sz * (!ioc->rdpq_array_enable ? 1 : ioc->reply_queue_count);
ioc->scsiio_depth = ioc->hba_queue_depth -
ioc->hi_priority_depth - ioc->internal_depth;
--
1.8.3.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [v2 4/5] mpt3sas: Handle RDPQ DMA allocation in same 4G region
2020-04-23 7:23 [v2 0/5] mpt3sas: Fix changing coherent mask after allocation Suganath Prabu
` (2 preceding siblings ...)
2020-04-23 7:23 ` [v2 3/5] mpt3sas: Separate out RDPQ allocation to new function Suganath Prabu
@ 2020-04-23 7:23 ` Suganath Prabu
2020-04-23 7:55 ` Christoph Hellwig
2020-05-21 15:12 ` Tomas Henzl
2020-04-23 7:23 ` [v2 5/5] mpt3sas: Update mpt3sas version to 33.101.00.00 Suganath Prabu
2020-04-24 17:09 ` [v2 0/5] mpt3sas: Fix changing coherent mask after allocation Martin K. Petersen
5 siblings, 2 replies; 11+ messages in thread
From: Suganath Prabu @ 2020-04-23 7:23 UTC (permalink / raw)
To: linux-scsi; +Cc: hch, Sathya.Prakash, sreekanth.reddy, Suganath Prabu
For INVADER_SERIES each set of 8 reply queues (0 - 7, 8 - 15,..) and
VENTURA_SERIES each set of 16 reply queues (0 - 15, 16 - 31,..) should
be within 4 GB boundary. Driver uses limitation of VENTURA_SERIES to
manage INVADER_SERIES as well. So here driver is allocating the DMA able
memory for RDPQ's accordingly.
1) At driver load, set DMA Mask to 64 and allocate memory for RDPQ's.
2) Check if allocated resources for RDPQ are in the same 4GB range.
3) If #2 is true, continue with 64 bit DMA and go to #6
4) If #2 is false, then free all the resources from #1.
5) Set DMA mask to 32 and allocate RDPQ's.
6) Proceed with driver loading and other allocations
---
v1 Change log:
1) Use one dma pool for RDPQ's, thus removes the logic of using second
dma pool with align.
v2 Change log:
Added flag use_32bit_dma. If this flag is true, 32 bit coharent
dma is used.
Signed-off-by: Suganath Prabu <suganath-prabu.subramani@broadcom.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
---
drivers/scsi/mpt3sas/mpt3sas_base.c | 152 +++++++++++++++++++++++++-----------
drivers/scsi/mpt3sas/mpt3sas_base.h | 3 +
2 files changed, 109 insertions(+), 46 deletions(-)
diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c b/drivers/scsi/mpt3sas/mpt3sas_base.c
index 0588941..af30e74 100644
--- a/drivers/scsi/mpt3sas/mpt3sas_base.c
+++ b/drivers/scsi/mpt3sas/mpt3sas_base.c
@@ -2810,7 +2810,7 @@ _base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev)
int dma_mask;
if (ioc->is_mcpu_endpoint ||
- sizeof(dma_addr_t) == 4 ||
+ sizeof(dma_addr_t) == 4 || ioc->use_32bit_dma ||
dma_get_required_mask(&pdev->dev) <= 32)
dma_mask = 32;
/* Set 63 bit DMA mask for all SAS3 and SAS35 controllers */
@@ -4807,8 +4807,8 @@ _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc)
{
int i = 0;
int j = 0;
+ int dma_alloc_count = 0;
struct chain_tracker *ct;
- struct reply_post_struct *rps;
dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
@@ -4850,29 +4850,34 @@ _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc)
}
if (ioc->reply_post) {
- do {
- rps = &ioc->reply_post[i];
- if (rps->reply_post_free) {
- dma_pool_free(
- ioc->reply_post_free_dma_pool,
- rps->reply_post_free,
- rps->reply_post_free_dma);
- dexitprintk(ioc,
- ioc_info(ioc, "reply_post_free_pool(0x%p): free\n",
- rps->reply_post_free));
- rps->reply_post_free = NULL;
+ dma_alloc_count = DIV_ROUND_UP(ioc->reply_queue_count,
+ RDPQ_MAX_INDEX_IN_ONE_CHUNK);
+ for (i = 0; i < ioc->reply_queue_count; i++) {
+ if (i % RDPQ_MAX_INDEX_IN_ONE_CHUNK == 0
+ && dma_alloc_count) {
+ if (ioc->reply_post[i].reply_post_free) {
+ dma_pool_free(
+ ioc->reply_post_free_dma_pool,
+ ioc->reply_post[i].reply_post_free,
+ ioc->reply_post[i].reply_post_free_dma);
+ dexitprintk(ioc, ioc_info(ioc,
+ "reply_post_free_pool(0x%p): free\n",
+ ioc->reply_post[i].reply_post_free));
+ ioc->reply_post[i].reply_post_free =
+ NULL;
+ }
+ --dma_alloc_count;
}
- } while (ioc->rdpq_array_enable &&
- (++i < ioc->reply_queue_count));
+ }
+ dma_pool_destroy(ioc->reply_post_free_dma_pool);
if (ioc->reply_post_free_array &&
ioc->rdpq_array_enable) {
dma_pool_free(ioc->reply_post_free_array_dma_pool,
- ioc->reply_post_free_array,
- ioc->reply_post_free_array_dma);
+ ioc->reply_post_free_array,
+ ioc->reply_post_free_array_dma);
ioc->reply_post_free_array = NULL;
}
dma_pool_destroy(ioc->reply_post_free_array_dma_pool);
- dma_pool_destroy(ioc->reply_post_free_dma_pool);
kfree(ioc->reply_post);
}
@@ -4948,36 +4953,75 @@ mpt3sas_check_same_4gb_region(long reply_pool_start_address, u32 pool_sz)
static int
base_alloc_rdpq_dma_pool(struct MPT3SAS_ADAPTER *ioc, int sz)
{
- int i;
+ int i = 0;
+ u32 dma_alloc_count = 0;
+ int reply_post_free_sz = ioc->reply_post_queue_depth *
+ sizeof(Mpi2DefaultReplyDescriptor_t);
int count = ioc->rdpq_array_enable ? ioc->reply_queue_count : 1;
ioc->reply_post = kcalloc(count, sizeof(struct reply_post_struct),
GFP_KERNEL);
if (!ioc->reply_post)
return -ENOMEM;
+ /*
+ * For INVADER_SERIES each set of 8 reply queues(0-7, 8-15, ..) and
+ * VENTURA_SERIES each set of 16 reply queues(0-15, 16-31, ..) should
+ * be within 4GB boundary i.e reply queues in a set must have same
+ * upper 32-bits in their memory address. so here driver is allocating
+ * the DMA'able memory for reply queues according.
+ * Driver uses limitation of
+ * VENTURA_SERIES to manage INVADER_SERIES as well.
+ */
+ dma_alloc_count = DIV_ROUND_UP(ioc->reply_queue_count,
+ RDPQ_MAX_INDEX_IN_ONE_CHUNK);
ioc->reply_post_free_dma_pool =
- dma_pool_create("reply_post_free pool",
- &ioc->pdev->dev, sz, 16, 0);
+ dma_pool_create("reply_post_free pool",
+ &ioc->pdev->dev, sz, 16, 0);
if (!ioc->reply_post_free_dma_pool)
return -ENOMEM;
- i = 0;
- do {
- ioc->reply_post[i].reply_post_free =
- dma_pool_zalloc(ioc->reply_post_free_dma_pool,
- GFP_KERNEL,
- &ioc->reply_post[i].reply_post_free_dma);
- if (!ioc->reply_post[i].reply_post_free)
- return -ENOMEM;
- dinitprintk(ioc,
- ioc_info(ioc, "reply post free pool (0x%p): depth(%d),"
- "element_size(%d), pool_size(%d kB)\n",
- ioc->reply_post[i].reply_post_free,
- ioc->reply_post_queue_depth, 8, sz / 1024));
- dinitprintk(ioc,
- ioc_info(ioc, "reply_post_free_dma = (0x%llx)\n",
- (u64)ioc->reply_post[i].reply_post_free_dma));
+ for (i = 0; i < ioc->reply_queue_count; i++) {
+ if ((i % RDPQ_MAX_INDEX_IN_ONE_CHUNK == 0) && dma_alloc_count) {
+ ioc->reply_post[i].reply_post_free =
+ dma_pool_alloc(ioc->reply_post_free_dma_pool,
+ GFP_KERNEL,
+ &ioc->reply_post[i].reply_post_free_dma);
+ if (!ioc->reply_post[i].reply_post_free)
+ return -ENOMEM;
+ /*
+ * Each set of RDPQ pool must satisfy 4gb boundary
+ * restriction.
+ * 1) Check if allocated resources for RDPQ pool are in
+ * the same 4GB range.
+ * 2) If #1 is true, continue with 64 bit DMA.
+ * 3) If #1 is false, return 1. which means free all the
+ * resources and set DMA mask to 32 and allocate.
+ */
+ if (!mpt3sas_check_same_4gb_region(
+ (long)ioc->reply_post[i].reply_post_free, sz)) {
+ dinitprintk(ioc,
+ ioc_err(ioc, "bad Replypost free pool(0x%p)"
+ "reply_post_free_dma = (0x%llx)\n",
+ ioc->reply_post[i].reply_post_free,
+ (unsigned long long)
+ ioc->reply_post[i].reply_post_free_dma));
+ return -EAGAIN;
+ }
+ memset(ioc->reply_post[i].reply_post_free, 0,
+ RDPQ_MAX_INDEX_IN_ONE_CHUNK *
+ reply_post_free_sz);
+ dma_alloc_count--;
- } while (ioc->rdpq_array_enable && ++i < ioc->reply_queue_count);
+ } else {
+ ioc->reply_post[i].reply_post_free =
+ (Mpi2ReplyDescriptorsUnion_t *)
+ ((long)ioc->reply_post[i-1].reply_post_free
+ + reply_post_free_sz);
+ ioc->reply_post[i].reply_post_free_dma =
+ (dma_addr_t)
+ (ioc->reply_post[i-1].reply_post_free_dma +
+ reply_post_free_sz);
+ }
+ }
return 0;
}
@@ -4995,10 +5039,12 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc)
u16 chains_needed_per_io;
u32 sz, total_sz, reply_post_free_sz, reply_post_free_array_sz;
u32 retry_sz;
+ u32 rdpq_sz = 0;
u16 max_request_credit, nvme_blocks_needed;
unsigned short sg_tablesize;
u16 sge_size;
int i, j;
+ int ret = 0;
struct chain_tracker *ct;
dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
@@ -5152,14 +5198,28 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc)
/* reply post queue, 16 byte align */
reply_post_free_sz = ioc->reply_post_queue_depth *
sizeof(Mpi2DefaultReplyDescriptor_t);
-
- sz = reply_post_free_sz;
+ rdpq_sz = reply_post_free_sz * RDPQ_MAX_INDEX_IN_ONE_CHUNK;
if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable)
- sz *= ioc->reply_queue_count;
- if (base_alloc_rdpq_dma_pool(ioc, sz))
- goto out;
- total_sz += sz * (!ioc->rdpq_array_enable ? 1 : ioc->reply_queue_count);
-
+ rdpq_sz = reply_post_free_sz * ioc->reply_queue_count;
+ ret = base_alloc_rdpq_dma_pool(ioc, rdpq_sz);
+ if (ret == -EAGAIN) {
+ /*
+ * Free allocated bad RDPQ memory pools.
+ * Change dma coherent mask to 32 bit and reallocate RDPQ
+ */
+ _base_release_memory_pools(ioc);
+ ioc->use_32bit_dma = true;
+ if (_base_config_dma_addressing(ioc, ioc->pdev) != 0) {
+ ioc_err(ioc,
+ "32 DMA mask failed %s\n", pci_name(ioc->pdev));
+ return -ENODEV;
+ }
+ if (base_alloc_rdpq_dma_pool(ioc, rdpq_sz))
+ return -ENOMEM;
+ } else if (ret == -ENOMEM)
+ return -ENOMEM;
+ total_sz = rdpq_sz * (!ioc->rdpq_array_enable ? 1 :
+ DIV_ROUND_UP(ioc->reply_queue_count, RDPQ_MAX_INDEX_IN_ONE_CHUNK));
ioc->scsiio_depth = ioc->hba_queue_depth -
ioc->hi_priority_depth - ioc->internal_depth;
@@ -5171,7 +5231,6 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc)
ioc_info(ioc, "scsi host: can_queue depth (%d)\n",
ioc->shost->can_queue));
-
/* contiguous pool for request and chains, 16 byte align, one extra "
* "frame for smid=0
*/
@@ -7141,6 +7200,7 @@ mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc)
ioc->smp_affinity_enable = smp_affinity_enable;
ioc->rdpq_array_enable_assigned = 0;
+ ioc->use_32bit_dma = 0;
if (ioc->is_aero_ioc)
ioc->base_readl = &_base_readl_aero;
else
diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.h b/drivers/scsi/mpt3sas/mpt3sas_base.h
index caae040..5a83971 100644
--- a/drivers/scsi/mpt3sas/mpt3sas_base.h
+++ b/drivers/scsi/mpt3sas/mpt3sas_base.h
@@ -367,6 +367,7 @@ struct mpt3sas_nvme_cmd {
#define MPT3SAS_HIGH_IOPS_REPLY_QUEUES 8
#define MPT3SAS_HIGH_IOPS_BATCH_COUNT 16
#define MPT3SAS_GEN35_MAX_MSIX_QUEUES 128
+#define RDPQ_MAX_INDEX_IN_ONE_CHUNK 16
/* OEM Specific Flags will come from OEM specific header files */
struct Mpi2ManufacturingPage10_t {
@@ -1063,6 +1064,7 @@ typedef void (*MPT3SAS_FLUSH_RUNNING_CMDS)(struct MPT3SAS_ADAPTER *ioc);
* @thresh_hold: Max number of reply descriptors processed
* before updating Host Index
* @drv_support_bitmap: driver's supported feature bit map
+ * @use_32bit_dma: Flag to use 32 bit consistent dma mask
* @scsi_io_cb_idx: shost generated commands
* @tm_cb_idx: task management commands
* @scsih_cb_idx: scsih internal commands
@@ -1252,6 +1254,7 @@ struct MPT3SAS_ADAPTER {
u8 high_iops_queues;
u32 drv_support_bitmap;
bool enable_sdev_max_qd;
+ bool use_32bit_dma;
/* internal commands, callback index */
u8 scsi_io_cb_idx;
--
1.8.3.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [v2 4/5] mpt3sas: Handle RDPQ DMA allocation in same 4G region
2020-04-23 7:23 ` [v2 4/5] mpt3sas: Handle RDPQ DMA allocation in same 4G region Suganath Prabu
@ 2020-04-23 7:55 ` Christoph Hellwig
2020-05-21 15:12 ` Tomas Henzl
1 sibling, 0 replies; 11+ messages in thread
From: Christoph Hellwig @ 2020-04-23 7:55 UTC (permalink / raw)
To: Suganath Prabu; +Cc: linux-scsi, hch, Sathya.Prakash, sreekanth.reddy
Looks good,
Reviewed-by: Christoph Hellwig <hch@lst.de>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [v2 4/5] mpt3sas: Handle RDPQ DMA allocation in same 4G region
2020-04-23 7:23 ` [v2 4/5] mpt3sas: Handle RDPQ DMA allocation in same 4G region Suganath Prabu
2020-04-23 7:55 ` Christoph Hellwig
@ 2020-05-21 15:12 ` Tomas Henzl
2020-05-22 5:57 ` Sreekanth Reddy
1 sibling, 1 reply; 11+ messages in thread
From: Tomas Henzl @ 2020-05-21 15:12 UTC (permalink / raw)
To: Suganath Prabu, linux-scsi; +Cc: hch, Sathya.Prakash, sreekanth.reddy
On 4/23/20 9:23 AM, Suganath Prabu wrote:
> For INVADER_SERIES each set of 8 reply queues (0 - 7, 8 - 15,..) and
> VENTURA_SERIES each set of 16 reply queues (0 - 15, 16 - 31,..) should
> be within 4 GB boundary. Driver uses limitation of VENTURA_SERIES to
> manage INVADER_SERIES as well. So here driver is allocating the DMA able
> memory for RDPQ's accordingly.
>
> 1) At driver load, set DMA Mask to 64 and allocate memory for RDPQ's.
> 2) Check if allocated resources for RDPQ are in the same 4GB range.
> 3) If #2 is true, continue with 64 bit DMA and go to #6
> 4) If #2 is false, then free all the resources from #1.
> 5) Set DMA mask to 32 and allocate RDPQ's.
> 6) Proceed with driver loading and other allocations
> ---
> v1 Change log:
> 1) Use one dma pool for RDPQ's, thus removes the logic of using second
> dma pool with align.
> v2 Change log:
> Added flag use_32bit_dma. If this flag is true, 32 bit coharent
> dma is used.
>
> Signed-off-by: Suganath Prabu <suganath-prabu.subramani@broadcom.com>
> Reviewed-by: Christoph Hellwig <hch@lst.de>
> ---
> drivers/scsi/mpt3sas/mpt3sas_base.c | 152 +++++++++++++++++++++++++-----------
> drivers/scsi/mpt3sas/mpt3sas_base.h | 3 +
> 2 files changed, 109 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c b/drivers/scsi/mpt3sas/mpt3sas_base.c
> index 0588941..af30e74 100644
> --- a/drivers/scsi/mpt3sas/mpt3sas_base.c
> +++ b/drivers/scsi/mpt3sas/mpt3sas_base.c
> @@ -2810,7 +2810,7 @@ _base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev)
> int dma_mask;
>
> if (ioc->is_mcpu_endpoint ||
> - sizeof(dma_addr_t) == 4 ||
> + sizeof(dma_addr_t) == 4 || ioc->use_32bit_dma ||
> dma_get_required_mask(&pdev->dev) <= 32)
> dma_mask = 32;
> /* Set 63 bit DMA mask for all SAS3 and SAS35 controllers */
> @@ -4807,8 +4807,8 @@ _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc)
> {
> int i = 0;
> int j = 0;
> + int dma_alloc_count = 0;
> struct chain_tracker *ct;
> - struct reply_post_struct *rps;
>
> dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
>
> @@ -4850,29 +4850,34 @@ _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc)
> }
>
> if (ioc->reply_post) {
> - do {
> - rps = &ioc->reply_post[i];
> - if (rps->reply_post_free) {
> - dma_pool_free(
> - ioc->reply_post_free_dma_pool,
> - rps->reply_post_free,
> - rps->reply_post_free_dma);
> - dexitprintk(ioc,
> - ioc_info(ioc, "reply_post_free_pool(0x%p): free\n",
> - rps->reply_post_free));
> - rps->reply_post_free = NULL;
> + dma_alloc_count = DIV_ROUND_UP(ioc->reply_queue_count,
> + RDPQ_MAX_INDEX_IN_ONE_CHUNK);
> + for (i = 0; i < ioc->reply_queue_count; i++) {
> + if (i % RDPQ_MAX_INDEX_IN_ONE_CHUNK == 0
> + && dma_alloc_count) {
> + if (ioc->reply_post[i].reply_post_free) {
> + dma_pool_free(
> + ioc->reply_post_free_dma_pool,
> + ioc->reply_post[i].reply_post_free,
> + ioc->reply_post[i].reply_post_free_dma);
> + dexitprintk(ioc, ioc_info(ioc,
> + "reply_post_free_pool(0x%p): free\n",
> + ioc->reply_post[i].reply_post_free));
> + ioc->reply_post[i].reply_post_free =
> + NULL;
> + }
> + --dma_alloc_count;
> }
> - } while (ioc->rdpq_array_enable &&
> - (++i < ioc->reply_queue_count));
> + }
> + dma_pool_destroy(ioc->reply_post_free_dma_pool);
> if (ioc->reply_post_free_array &&
> ioc->rdpq_array_enable) {
> dma_pool_free(ioc->reply_post_free_array_dma_pool,
> - ioc->reply_post_free_array,
> - ioc->reply_post_free_array_dma);
> + ioc->reply_post_free_array,
> + ioc->reply_post_free_array_dma);
> ioc->reply_post_free_array = NULL;
> }
> dma_pool_destroy(ioc->reply_post_free_array_dma_pool);
> - dma_pool_destroy(ioc->reply_post_free_dma_pool);
> kfree(ioc->reply_post);
> }
>
> @@ -4948,36 +4953,75 @@ mpt3sas_check_same_4gb_region(long reply_pool_start_address, u32 pool_sz)
> static int
> base_alloc_rdpq_dma_pool(struct MPT3SAS_ADAPTER *ioc, int sz)
> {
> - int i;
> + int i = 0;
> + u32 dma_alloc_count = 0;
> + int reply_post_free_sz = ioc->reply_post_queue_depth *
> + sizeof(Mpi2DefaultReplyDescriptor_t);
> int count = ioc->rdpq_array_enable ? ioc->reply_queue_count : 1;
>
> ioc->reply_post = kcalloc(count, sizeof(struct reply_post_struct),
> GFP_KERNEL);
> if (!ioc->reply_post)
> return -ENOMEM;
> + /*
> + * For INVADER_SERIES each set of 8 reply queues(0-7, 8-15, ..) and
> + * VENTURA_SERIES each set of 16 reply queues(0-15, 16-31, ..) should
> + * be within 4GB boundary i.e reply queues in a set must have same
> + * upper 32-bits in their memory address. so here driver is allocating
> + * the DMA'able memory for reply queues according.
> + * Driver uses limitation of
> + * VENTURA_SERIES to manage INVADER_SERIES as well.
> + */
> + dma_alloc_count = DIV_ROUND_UP(ioc->reply_queue_count,
> + RDPQ_MAX_INDEX_IN_ONE_CHUNK);
> ioc->reply_post_free_dma_pool =
> - dma_pool_create("reply_post_free pool",
> - &ioc->pdev->dev, sz, 16, 0);
> + dma_pool_create("reply_post_free pool",
> + &ioc->pdev->dev, sz, 16, 0);
> if (!ioc->reply_post_free_dma_pool)
> return -ENOMEM;
> - i = 0;
> - do {
> - ioc->reply_post[i].reply_post_free =
> - dma_pool_zalloc(ioc->reply_post_free_dma_pool,
> - GFP_KERNEL,
> - &ioc->reply_post[i].reply_post_free_dma);
> - if (!ioc->reply_post[i].reply_post_free)
> - return -ENOMEM;
> - dinitprintk(ioc,
> - ioc_info(ioc, "reply post free pool (0x%p): depth(%d),"
> - "element_size(%d), pool_size(%d kB)\n",
> - ioc->reply_post[i].reply_post_free,
> - ioc->reply_post_queue_depth, 8, sz / 1024));
> - dinitprintk(ioc,
> - ioc_info(ioc, "reply_post_free_dma = (0x%llx)\n",
> - (u64)ioc->reply_post[i].reply_post_free_dma));
> + for (i = 0; i < ioc->reply_queue_count; i++) {
> + if ((i % RDPQ_MAX_INDEX_IN_ONE_CHUNK == 0) && dma_alloc_count) {
> + ioc->reply_post[i].reply_post_free =
ioc->reply_post is allocated with 'count' size, which may be smaller
than ioc->reply_queue_count
Probably this causes some older systems to not boot.
The problem should be fixed before it comes to mainline.
Cheers,
tomash
> + dma_pool_alloc(ioc->reply_post_free_dma_pool,
> + GFP_KERNEL,
> + &ioc->reply_post[i].reply_post_free_dma);
> + if (!ioc->reply_post[i].reply_post_free)
> + return -ENOMEM;
> + /*
> + * Each set of RDPQ pool must satisfy 4gb boundary
> + * restriction.
> + * 1) Check if allocated resources for RDPQ pool are in
> + * the same 4GB range.
> + * 2) If #1 is true, continue with 64 bit DMA.
> + * 3) If #1 is false, return 1. which means free all the
> + * resources and set DMA mask to 32 and allocate.
> + */
> + if (!mpt3sas_check_same_4gb_region(
> + (long)ioc->reply_post[i].reply_post_free, sz)) {
> + dinitprintk(ioc,
> + ioc_err(ioc, "bad Replypost free pool(0x%p)"
> + "reply_post_free_dma = (0x%llx)\n",
> + ioc->reply_post[i].reply_post_free,
> + (unsigned long long)
> + ioc->reply_post[i].reply_post_free_dma));
> + return -EAGAIN;
> + }
> + memset(ioc->reply_post[i].reply_post_free, 0,
> + RDPQ_MAX_INDEX_IN_ONE_CHUNK *
> + reply_post_free_sz);
> + dma_alloc_count--;
>
> - } while (ioc->rdpq_array_enable && ++i < ioc->reply_queue_count);
> + } else {
> + ioc->reply_post[i].reply_post_free =
> + (Mpi2ReplyDescriptorsUnion_t *)
> + ((long)ioc->reply_post[i-1].reply_post_free
> + + reply_post_free_sz);
> + ioc->reply_post[i].reply_post_free_dma =
> + (dma_addr_t)
> + (ioc->reply_post[i-1].reply_post_free_dma +
> + reply_post_free_sz);
> + }
> + }
> return 0;
> }
>
> @@ -4995,10 +5039,12 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc)
> u16 chains_needed_per_io;
> u32 sz, total_sz, reply_post_free_sz, reply_post_free_array_sz;
> u32 retry_sz;
> + u32 rdpq_sz = 0;
> u16 max_request_credit, nvme_blocks_needed;
> unsigned short sg_tablesize;
> u16 sge_size;
> int i, j;
> + int ret = 0;
> struct chain_tracker *ct;
>
> dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
> @@ -5152,14 +5198,28 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc)
> /* reply post queue, 16 byte align */
> reply_post_free_sz = ioc->reply_post_queue_depth *
> sizeof(Mpi2DefaultReplyDescriptor_t);
> -
> - sz = reply_post_free_sz;
> + rdpq_sz = reply_post_free_sz * RDPQ_MAX_INDEX_IN_ONE_CHUNK;
> if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable)
> - sz *= ioc->reply_queue_count;
> - if (base_alloc_rdpq_dma_pool(ioc, sz))
> - goto out;
> - total_sz += sz * (!ioc->rdpq_array_enable ? 1 : ioc->reply_queue_count);
> -
> + rdpq_sz = reply_post_free_sz * ioc->reply_queue_count;
> + ret = base_alloc_rdpq_dma_pool(ioc, rdpq_sz);
> + if (ret == -EAGAIN) {
> + /*
> + * Free allocated bad RDPQ memory pools.
> + * Change dma coherent mask to 32 bit and reallocate RDPQ
> + */
> + _base_release_memory_pools(ioc);
> + ioc->use_32bit_dma = true;
> + if (_base_config_dma_addressing(ioc, ioc->pdev) != 0) {
> + ioc_err(ioc,
> + "32 DMA mask failed %s\n", pci_name(ioc->pdev));
> + return -ENODEV;
> + }
> + if (base_alloc_rdpq_dma_pool(ioc, rdpq_sz))
> + return -ENOMEM;
> + } else if (ret == -ENOMEM)
> + return -ENOMEM;
> + total_sz = rdpq_sz * (!ioc->rdpq_array_enable ? 1 :
> + DIV_ROUND_UP(ioc->reply_queue_count, RDPQ_MAX_INDEX_IN_ONE_CHUNK));
> ioc->scsiio_depth = ioc->hba_queue_depth -
> ioc->hi_priority_depth - ioc->internal_depth;
>
> @@ -5171,7 +5231,6 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc)
> ioc_info(ioc, "scsi host: can_queue depth (%d)\n",
> ioc->shost->can_queue));
>
> -
> /* contiguous pool for request and chains, 16 byte align, one extra "
> * "frame for smid=0
> */
> @@ -7141,6 +7200,7 @@ mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc)
> ioc->smp_affinity_enable = smp_affinity_enable;
>
> ioc->rdpq_array_enable_assigned = 0;
> + ioc->use_32bit_dma = 0;
> if (ioc->is_aero_ioc)
> ioc->base_readl = &_base_readl_aero;
> else
> diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.h b/drivers/scsi/mpt3sas/mpt3sas_base.h
> index caae040..5a83971 100644
> --- a/drivers/scsi/mpt3sas/mpt3sas_base.h
> +++ b/drivers/scsi/mpt3sas/mpt3sas_base.h
> @@ -367,6 +367,7 @@ struct mpt3sas_nvme_cmd {
> #define MPT3SAS_HIGH_IOPS_REPLY_QUEUES 8
> #define MPT3SAS_HIGH_IOPS_BATCH_COUNT 16
> #define MPT3SAS_GEN35_MAX_MSIX_QUEUES 128
> +#define RDPQ_MAX_INDEX_IN_ONE_CHUNK 16
>
> /* OEM Specific Flags will come from OEM specific header files */
> struct Mpi2ManufacturingPage10_t {
> @@ -1063,6 +1064,7 @@ typedef void (*MPT3SAS_FLUSH_RUNNING_CMDS)(struct MPT3SAS_ADAPTER *ioc);
> * @thresh_hold: Max number of reply descriptors processed
> * before updating Host Index
> * @drv_support_bitmap: driver's supported feature bit map
> + * @use_32bit_dma: Flag to use 32 bit consistent dma mask
> * @scsi_io_cb_idx: shost generated commands
> * @tm_cb_idx: task management commands
> * @scsih_cb_idx: scsih internal commands
> @@ -1252,6 +1254,7 @@ struct MPT3SAS_ADAPTER {
> u8 high_iops_queues;
> u32 drv_support_bitmap;
> bool enable_sdev_max_qd;
> + bool use_32bit_dma;
>
> /* internal commands, callback index */
> u8 scsi_io_cb_idx;
>
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [v2 4/5] mpt3sas: Handle RDPQ DMA allocation in same 4G region
2020-05-21 15:12 ` Tomas Henzl
@ 2020-05-22 5:57 ` Sreekanth Reddy
0 siblings, 0 replies; 11+ messages in thread
From: Sreekanth Reddy @ 2020-05-22 5:57 UTC (permalink / raw)
To: Tomas Henzl
Cc: Suganath Prabu, linux-scsi, Christoph Hellwig,
Sathya Prakash Veerichetty
On Thu, May 21, 2020 at 8:42 PM Tomas Henzl <thenzl@redhat.com> wrote:
>
> On 4/23/20 9:23 AM, Suganath Prabu wrote:
> > For INVADER_SERIES each set of 8 reply queues (0 - 7, 8 - 15,..) and
> > VENTURA_SERIES each set of 16 reply queues (0 - 15, 16 - 31,..) should
> > be within 4 GB boundary. Driver uses limitation of VENTURA_SERIES to
> > manage INVADER_SERIES as well. So here driver is allocating the DMA able
> > memory for RDPQ's accordingly.
> >
> > 1) At driver load, set DMA Mask to 64 and allocate memory for RDPQ's.
> > 2) Check if allocated resources for RDPQ are in the same 4GB range.
> > 3) If #2 is true, continue with 64 bit DMA and go to #6
> > 4) If #2 is false, then free all the resources from #1.
> > 5) Set DMA mask to 32 and allocate RDPQ's.
> > 6) Proceed with driver loading and other allocations
> > ---
> > v1 Change log:
> > 1) Use one dma pool for RDPQ's, thus removes the logic of using second
> > dma pool with align.
> > v2 Change log:
> > Added flag use_32bit_dma. If this flag is true, 32 bit coharent
> > dma is used.
> >
> > Signed-off-by: Suganath Prabu <suganath-prabu.subramani@broadcom.com>
> > Reviewed-by: Christoph Hellwig <hch@lst.de>
> > ---
> > drivers/scsi/mpt3sas/mpt3sas_base.c | 152 +++++++++++++++++++++++++-----------
> > drivers/scsi/mpt3sas/mpt3sas_base.h | 3 +
> > 2 files changed, 109 insertions(+), 46 deletions(-)
> >
> > diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c b/drivers/scsi/mpt3sas/mpt3sas_base.c
> > index 0588941..af30e74 100644
> > --- a/drivers/scsi/mpt3sas/mpt3sas_base.c
> > +++ b/drivers/scsi/mpt3sas/mpt3sas_base.c
> > @@ -2810,7 +2810,7 @@ _base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev)
> > int dma_mask;
> >
> > if (ioc->is_mcpu_endpoint ||
> > - sizeof(dma_addr_t) == 4 ||
> > + sizeof(dma_addr_t) == 4 || ioc->use_32bit_dma ||
> > dma_get_required_mask(&pdev->dev) <= 32)
> > dma_mask = 32;
> > /* Set 63 bit DMA mask for all SAS3 and SAS35 controllers */
> > @@ -4807,8 +4807,8 @@ _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc)
> > {
> > int i = 0;
> > int j = 0;
> > + int dma_alloc_count = 0;
> > struct chain_tracker *ct;
> > - struct reply_post_struct *rps;
> >
> > dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
> >
> > @@ -4850,29 +4850,34 @@ _base_release_memory_pools(struct MPT3SAS_ADAPTER *ioc)
> > }
> >
> > if (ioc->reply_post) {
> > - do {
> > - rps = &ioc->reply_post[i];
> > - if (rps->reply_post_free) {
> > - dma_pool_free(
> > - ioc->reply_post_free_dma_pool,
> > - rps->reply_post_free,
> > - rps->reply_post_free_dma);
> > - dexitprintk(ioc,
> > - ioc_info(ioc, "reply_post_free_pool(0x%p): free\n",
> > - rps->reply_post_free));
> > - rps->reply_post_free = NULL;
> > + dma_alloc_count = DIV_ROUND_UP(ioc->reply_queue_count,
> > + RDPQ_MAX_INDEX_IN_ONE_CHUNK);
> > + for (i = 0; i < ioc->reply_queue_count; i++) {
> > + if (i % RDPQ_MAX_INDEX_IN_ONE_CHUNK == 0
> > + && dma_alloc_count) {
> > + if (ioc->reply_post[i].reply_post_free) {
> > + dma_pool_free(
> > + ioc->reply_post_free_dma_pool,
> > + ioc->reply_post[i].reply_post_free,
> > + ioc->reply_post[i].reply_post_free_dma);
> > + dexitprintk(ioc, ioc_info(ioc,
> > + "reply_post_free_pool(0x%p): free\n",
> > + ioc->reply_post[i].reply_post_free));
> > + ioc->reply_post[i].reply_post_free =
> > + NULL;
> > + }
> > + --dma_alloc_count;
> > }
> > - } while (ioc->rdpq_array_enable &&
> > - (++i < ioc->reply_queue_count));
> > + }
> > + dma_pool_destroy(ioc->reply_post_free_dma_pool);
> > if (ioc->reply_post_free_array &&
> > ioc->rdpq_array_enable) {
> > dma_pool_free(ioc->reply_post_free_array_dma_pool,
> > - ioc->reply_post_free_array,
> > - ioc->reply_post_free_array_dma);
> > + ioc->reply_post_free_array,
> > + ioc->reply_post_free_array_dma);
> > ioc->reply_post_free_array = NULL;
> > }
> > dma_pool_destroy(ioc->reply_post_free_array_dma_pool);
> > - dma_pool_destroy(ioc->reply_post_free_dma_pool);
> > kfree(ioc->reply_post);
> > }
> >
> > @@ -4948,36 +4953,75 @@ mpt3sas_check_same_4gb_region(long reply_pool_start_address, u32 pool_sz)
> > static int
> > base_alloc_rdpq_dma_pool(struct MPT3SAS_ADAPTER *ioc, int sz)
> > {
> > - int i;
> > + int i = 0;
> > + u32 dma_alloc_count = 0;
> > + int reply_post_free_sz = ioc->reply_post_queue_depth *
> > + sizeof(Mpi2DefaultReplyDescriptor_t);
> > int count = ioc->rdpq_array_enable ? ioc->reply_queue_count : 1;
> >
> > ioc->reply_post = kcalloc(count, sizeof(struct reply_post_struct),
> > GFP_KERNEL);
> > if (!ioc->reply_post)
> > return -ENOMEM;
> > + /*
> > + * For INVADER_SERIES each set of 8 reply queues(0-7, 8-15, ..) and
> > + * VENTURA_SERIES each set of 16 reply queues(0-15, 16-31, ..) should
> > + * be within 4GB boundary i.e reply queues in a set must have same
> > + * upper 32-bits in their memory address. so here driver is allocating
> > + * the DMA'able memory for reply queues according.
> > + * Driver uses limitation of
> > + * VENTURA_SERIES to manage INVADER_SERIES as well.
> > + */
> > + dma_alloc_count = DIV_ROUND_UP(ioc->reply_queue_count,
> > + RDPQ_MAX_INDEX_IN_ONE_CHUNK);
> > ioc->reply_post_free_dma_pool =
> > - dma_pool_create("reply_post_free pool",
> > - &ioc->pdev->dev, sz, 16, 0);
> > + dma_pool_create("reply_post_free pool",
> > + &ioc->pdev->dev, sz, 16, 0);
> > if (!ioc->reply_post_free_dma_pool)
> > return -ENOMEM;
> > - i = 0;
> > - do {
> > - ioc->reply_post[i].reply_post_free =
> > - dma_pool_zalloc(ioc->reply_post_free_dma_pool,
> > - GFP_KERNEL,
> > - &ioc->reply_post[i].reply_post_free_dma);
> > - if (!ioc->reply_post[i].reply_post_free)
> > - return -ENOMEM;
> > - dinitprintk(ioc,
> > - ioc_info(ioc, "reply post free pool (0x%p): depth(%d),"
> > - "element_size(%d), pool_size(%d kB)\n",
> > - ioc->reply_post[i].reply_post_free,
> > - ioc->reply_post_queue_depth, 8, sz / 1024));
> > - dinitprintk(ioc,
> > - ioc_info(ioc, "reply_post_free_dma = (0x%llx)\n",
> > - (u64)ioc->reply_post[i].reply_post_free_dma));
> > + for (i = 0; i < ioc->reply_queue_count; i++) {
> > + if ((i % RDPQ_MAX_INDEX_IN_ONE_CHUNK == 0) && dma_alloc_count) {
> > + ioc->reply_post[i].reply_post_free =
> ioc->reply_post is allocated with 'count' size, which may be smaller
> than ioc->reply_queue_count
> Probably this causes some older systems to not boot.
> The problem should be fixed before it comes to mainline.
>
> Cheers,
> tomash
Tomash, thanks for identifying this bug. We will post the fix patch today.
Thanks,
Sreekanth
>
>
> > + dma_pool_alloc(ioc->reply_post_free_dma_pool,
> > + GFP_KERNEL,
> > + &ioc->reply_post[i].reply_post_free_dma);
> > + if (!ioc->reply_post[i].reply_post_free)
> > + return -ENOMEM;
> > + /*
> > + * Each set of RDPQ pool must satisfy 4gb boundary
> > + * restriction.
> > + * 1) Check if allocated resources for RDPQ pool are in
> > + * the same 4GB range.
> > + * 2) If #1 is true, continue with 64 bit DMA.
> > + * 3) If #1 is false, return 1. which means free all the
> > + * resources and set DMA mask to 32 and allocate.
> > + */
> > + if (!mpt3sas_check_same_4gb_region(
> > + (long)ioc->reply_post[i].reply_post_free, sz)) {
> > + dinitprintk(ioc,
> > + ioc_err(ioc, "bad Replypost free pool(0x%p)"
> > + "reply_post_free_dma = (0x%llx)\n",
> > + ioc->reply_post[i].reply_post_free,
> > + (unsigned long long)
> > + ioc->reply_post[i].reply_post_free_dma));
> > + return -EAGAIN;
> > + }
> > + memset(ioc->reply_post[i].reply_post_free, 0,
> > + RDPQ_MAX_INDEX_IN_ONE_CHUNK *
> > + reply_post_free_sz);
> > + dma_alloc_count--;
> >
> > - } while (ioc->rdpq_array_enable && ++i < ioc->reply_queue_count);
> > + } else {
> > + ioc->reply_post[i].reply_post_free =
> > + (Mpi2ReplyDescriptorsUnion_t *)
> > + ((long)ioc->reply_post[i-1].reply_post_free
> > + + reply_post_free_sz);
> > + ioc->reply_post[i].reply_post_free_dma =
> > + (dma_addr_t)
> > + (ioc->reply_post[i-1].reply_post_free_dma +
> > + reply_post_free_sz);
> > + }
> > + }
> > return 0;
> > }
> >
> > @@ -4995,10 +5039,12 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc)
> > u16 chains_needed_per_io;
> > u32 sz, total_sz, reply_post_free_sz, reply_post_free_array_sz;
> > u32 retry_sz;
> > + u32 rdpq_sz = 0;
> > u16 max_request_credit, nvme_blocks_needed;
> > unsigned short sg_tablesize;
> > u16 sge_size;
> > int i, j;
> > + int ret = 0;
> > struct chain_tracker *ct;
> >
> > dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
> > @@ -5152,14 +5198,28 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc)
> > /* reply post queue, 16 byte align */
> > reply_post_free_sz = ioc->reply_post_queue_depth *
> > sizeof(Mpi2DefaultReplyDescriptor_t);
> > -
> > - sz = reply_post_free_sz;
> > + rdpq_sz = reply_post_free_sz * RDPQ_MAX_INDEX_IN_ONE_CHUNK;
> > if (_base_is_controller_msix_enabled(ioc) && !ioc->rdpq_array_enable)
> > - sz *= ioc->reply_queue_count;
> > - if (base_alloc_rdpq_dma_pool(ioc, sz))
> > - goto out;
> > - total_sz += sz * (!ioc->rdpq_array_enable ? 1 : ioc->reply_queue_count);
> > -
> > + rdpq_sz = reply_post_free_sz * ioc->reply_queue_count;
> > + ret = base_alloc_rdpq_dma_pool(ioc, rdpq_sz);
> > + if (ret == -EAGAIN) {
> > + /*
> > + * Free allocated bad RDPQ memory pools.
> > + * Change dma coherent mask to 32 bit and reallocate RDPQ
> > + */
> > + _base_release_memory_pools(ioc);
> > + ioc->use_32bit_dma = true;
> > + if (_base_config_dma_addressing(ioc, ioc->pdev) != 0) {
> > + ioc_err(ioc,
> > + "32 DMA mask failed %s\n", pci_name(ioc->pdev));
> > + return -ENODEV;
> > + }
> > + if (base_alloc_rdpq_dma_pool(ioc, rdpq_sz))
> > + return -ENOMEM;
> > + } else if (ret == -ENOMEM)
> > + return -ENOMEM;
> > + total_sz = rdpq_sz * (!ioc->rdpq_array_enable ? 1 :
> > + DIV_ROUND_UP(ioc->reply_queue_count, RDPQ_MAX_INDEX_IN_ONE_CHUNK));
> > ioc->scsiio_depth = ioc->hba_queue_depth -
> > ioc->hi_priority_depth - ioc->internal_depth;
> >
> > @@ -5171,7 +5231,6 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc)
> > ioc_info(ioc, "scsi host: can_queue depth (%d)\n",
> > ioc->shost->can_queue));
> >
> > -
> > /* contiguous pool for request and chains, 16 byte align, one extra "
> > * "frame for smid=0
> > */
> > @@ -7141,6 +7200,7 @@ mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc)
> > ioc->smp_affinity_enable = smp_affinity_enable;
> >
> > ioc->rdpq_array_enable_assigned = 0;
> > + ioc->use_32bit_dma = 0;
> > if (ioc->is_aero_ioc)
> > ioc->base_readl = &_base_readl_aero;
> > else
> > diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.h b/drivers/scsi/mpt3sas/mpt3sas_base.h
> > index caae040..5a83971 100644
> > --- a/drivers/scsi/mpt3sas/mpt3sas_base.h
> > +++ b/drivers/scsi/mpt3sas/mpt3sas_base.h
> > @@ -367,6 +367,7 @@ struct mpt3sas_nvme_cmd {
> > #define MPT3SAS_HIGH_IOPS_REPLY_QUEUES 8
> > #define MPT3SAS_HIGH_IOPS_BATCH_COUNT 16
> > #define MPT3SAS_GEN35_MAX_MSIX_QUEUES 128
> > +#define RDPQ_MAX_INDEX_IN_ONE_CHUNK 16
> >
> > /* OEM Specific Flags will come from OEM specific header files */
> > struct Mpi2ManufacturingPage10_t {
> > @@ -1063,6 +1064,7 @@ typedef void (*MPT3SAS_FLUSH_RUNNING_CMDS)(struct MPT3SAS_ADAPTER *ioc);
> > * @thresh_hold: Max number of reply descriptors processed
> > * before updating Host Index
> > * @drv_support_bitmap: driver's supported feature bit map
> > + * @use_32bit_dma: Flag to use 32 bit consistent dma mask
> > * @scsi_io_cb_idx: shost generated commands
> > * @tm_cb_idx: task management commands
> > * @scsih_cb_idx: scsih internal commands
> > @@ -1252,6 +1254,7 @@ struct MPT3SAS_ADAPTER {
> > u8 high_iops_queues;
> > u32 drv_support_bitmap;
> > bool enable_sdev_max_qd;
> > + bool use_32bit_dma;
> >
> > /* internal commands, callback index */
> > u8 scsi_io_cb_idx;
> >
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [v2 5/5] mpt3sas: Update mpt3sas version to 33.101.00.00
2020-04-23 7:23 [v2 0/5] mpt3sas: Fix changing coherent mask after allocation Suganath Prabu
` (3 preceding siblings ...)
2020-04-23 7:23 ` [v2 4/5] mpt3sas: Handle RDPQ DMA allocation in same 4G region Suganath Prabu
@ 2020-04-23 7:23 ` Suganath Prabu
2020-04-24 17:09 ` [v2 0/5] mpt3sas: Fix changing coherent mask after allocation Martin K. Petersen
5 siblings, 0 replies; 11+ messages in thread
From: Suganath Prabu @ 2020-04-23 7:23 UTC (permalink / raw)
To: linux-scsi; +Cc: hch, Sathya.Prakash, sreekanth.reddy, Suganath Prabu
Update mpt3sas driver version from 33.100.00.00 to
33.101.00.00
Signed-off-by: Suganath Prabu <suganath-prabu.subramani@broadcom.com>
---
drivers/scsi/mpt3sas/mpt3sas_base.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.h b/drivers/scsi/mpt3sas/mpt3sas_base.h
index 5a83971..c574379 100644
--- a/drivers/scsi/mpt3sas/mpt3sas_base.h
+++ b/drivers/scsi/mpt3sas/mpt3sas_base.h
@@ -76,9 +76,9 @@
#define MPT3SAS_DRIVER_NAME "mpt3sas"
#define MPT3SAS_AUTHOR "Avago Technologies <MPT-FusionLinux.pdl@avagotech.com>"
#define MPT3SAS_DESCRIPTION "LSI MPT Fusion SAS 3.0 Device Driver"
-#define MPT3SAS_DRIVER_VERSION "33.100.00.00"
+#define MPT3SAS_DRIVER_VERSION "33.101.00.00"
#define MPT3SAS_MAJOR_VERSION 33
-#define MPT3SAS_MINOR_VERSION 100
+#define MPT3SAS_MINOR_VERSION 101
#define MPT3SAS_BUILD_VERSION 0
#define MPT3SAS_RELEASE_VERSION 00
--
1.8.3.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [v2 0/5] mpt3sas: Fix changing coherent mask after allocation
2020-04-23 7:23 [v2 0/5] mpt3sas: Fix changing coherent mask after allocation Suganath Prabu
` (4 preceding siblings ...)
2020-04-23 7:23 ` [v2 5/5] mpt3sas: Update mpt3sas version to 33.101.00.00 Suganath Prabu
@ 2020-04-24 17:09 ` Martin K. Petersen
5 siblings, 0 replies; 11+ messages in thread
From: Martin K. Petersen @ 2020-04-24 17:09 UTC (permalink / raw)
To: Suganath Prabu; +Cc: linux-scsi, hch, Sathya.Prakash, sreekanth.reddy
Suganath,
> * Set the coherent dma mask to 64 bit and then allocate RDPQ pools,
> make sure that each of the RDPQ pools satisfies the 4gb boundary
> restriction. if any of the RDPQ pool doesn't satisfies this
> restriction then deallocate the pools and reallocate them after
> changing the coherent dma mask to 32 bit.
> * With this there is no need to change DMA coherent mask when there
> are outstanding allocations in mpt3sas.
> * Code-Refactoring
Applied to 5.8/scsi-queue, thanks!
--
Martin K. Petersen Oracle Linux Engineering
^ permalink raw reply [flat|nested] 11+ messages in thread