[PATCH v1 0/4] scsi: ufs-mediatek: provide power management

[PATCH v1 0/4] scsi: ufs-mediatek: provide power management

[Stanley Chu]

The patch set provides power management on MediaTek Chipsets by

1. Introduce reference clock control
2. Configure customized auto-hibernate timer
3. Enable clk-gating with customized delayed timer value

Stanley Chu (4):
  scsi: ufs-mediatek: introduce reference clock control
  scsi: ufs: export ufshcd_auto_hibern8_update for vendor usage
  scsi: ufs-mediatek: configure customized auto-hibern8 timer
  scsi: ufs-mediatek: configure and enable clk-gating

 drivers/scsi/ufs/ufs-mediatek.c | 93 +++++++++++++++++++++++++++++++--
 drivers/scsi/ufs/ufs-mediatek.h | 20 ++++++-
 drivers/scsi/ufs/ufs-sysfs.c    | 20 -------
 drivers/scsi/ufs/ufshcd.c       | 18 +++++++
 drivers/scsi/ufs/ufshcd.h       |  1 +
 5 files changed, 126 insertions(+), 26 deletions(-)

-- 
2.18.0

[PATCH v1 1/4] scsi: ufs-mediatek: introduce reference clock control

[Stanley Chu]

Introduce reference clock control in MediaTek Chipset in order
to disable it if it is not necessary by UFS device to save system power.

Currently reference clock can be disabled during system suspend, runtime
suspend and clock-gating after link enters hibernate state.

Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
---
 drivers/scsi/ufs/ufs-mediatek.c | 64 ++++++++++++++++++++++++++++++---
 drivers/scsi/ufs/ufs-mediatek.h | 20 +++++++++--
 2 files changed, 78 insertions(+), 6 deletions(-)

diff --git a/drivers/scsi/ufs/ufs-mediatek.c b/drivers/scsi/ufs/ufs-mediatek.c
index 6a3ec11b16db..690483c78212 100644
--- a/drivers/scsi/ufs/ufs-mediatek.c
+++ b/drivers/scsi/ufs/ufs-mediatek.c
@@ -18,6 +18,11 @@
 #include "unipro.h"
 #include "ufs-mediatek.h"
 
+#define ufs_mtk_ref_clk_notify(on, res) \
+	arm_smccc_smc(MTK_SIP_UFS_CONTROL, \
+		      UFS_MTK_SIP_REF_CLK_NOTIFICATION, \
+		      on, 0, 0, 0, 0, 0, &(res))
+
 static void ufs_mtk_cfg_unipro_cg(struct ufs_hba *hba, bool enable)
 {
 	u32 tmp;
@@ -83,6 +88,49 @@ static int ufs_mtk_bind_mphy(struct ufs_hba *hba)
 	return err;
 }
 
+static int ufs_mtk_setup_ref_clk(struct ufs_hba *hba, bool on)
+{
+	struct ufs_mtk_host *host = ufshcd_get_variant(hba);
+	struct arm_smccc_res res;
+	unsigned long timeout;
+	u32 value;
+
+	if (host->ref_clk_enabled == on)
+		return 0;
+
+	if (on) {
+		ufs_mtk_ref_clk_notify(on, res);
+		ufshcd_writel(hba, REFCLK_REQUEST, REG_UFS_REFCLK_CTRL);
+	} else {
+		ufshcd_writel(hba, REFCLK_RELEASE, REG_UFS_REFCLK_CTRL);
+	}
+
+	/* Wait for ack */
+	timeout = jiffies + msecs_to_jiffies(REFCLK_REQ_TIMEOUT_MS);
+	do {
+		value = ufshcd_readl(hba, REG_UFS_REFCLK_CTRL);
+
+		/* Wait until ack bit equals to req bit */
+		if (((value & REFCLK_ACK) >> 1) == (value & REFCLK_REQUEST))
+			goto out;
+
+		usleep_range(100, 200);
+	} while (time_before(jiffies, timeout));
+
+	dev_err(hba->dev, "missing ack of refclk req, reg: 0x%x\n", value);
+
+	ufs_mtk_ref_clk_notify(host->ref_clk_enabled, res);
+
+	return -ETIMEDOUT;
+
+out:
+	host->ref_clk_enabled = on;
+	if (!on)
+		ufs_mtk_ref_clk_notify(on, res);
+
+	return 0;
+}
+
 /**
  * ufs_mtk_setup_clocks - enables/disable clocks
  * @hba: host controller instance
@@ -107,12 +155,16 @@ static int ufs_mtk_setup_clocks(struct ufs_hba *hba, bool on,
 
 	switch (status) {
 	case PRE_CHANGE:
-		if (!on)
+		if (!on) {
+			ufs_mtk_setup_ref_clk(hba, on);
 			ret = phy_power_off(host->mphy);
+		}
 		break;
 	case POST_CHANGE:
-		if (on)
+		if (on) {
 			ret = phy_power_on(host->mphy);
+			ufs_mtk_setup_ref_clk(hba, on);
+		}
 		break;
 	}
 
@@ -299,8 +351,10 @@ static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
 {
 	struct ufs_mtk_host *host = ufshcd_get_variant(hba);
 
-	if (ufshcd_is_link_hibern8(hba))
+	if (ufshcd_is_link_hibern8(hba)) {
 		phy_power_off(host->mphy);
+		ufs_mtk_setup_ref_clk(hba, false);
+	}
 
 	return 0;
 }
@@ -309,8 +363,10 @@ static int ufs_mtk_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
 {
 	struct ufs_mtk_host *host = ufshcd_get_variant(hba);
 
-	if (ufshcd_is_link_hibern8(hba))
+	if (ufshcd_is_link_hibern8(hba)) {
+		ufs_mtk_setup_ref_clk(hba, true);
 		phy_power_on(host->mphy);
+	}
 
 	return 0;
 }
diff --git a/drivers/scsi/ufs/ufs-mediatek.h b/drivers/scsi/ufs/ufs-mediatek.h
index b03f601d3a9e..14f8a8357c09 100644
--- a/drivers/scsi/ufs/ufs-mediatek.h
+++ b/drivers/scsi/ufs/ufs-mediatek.h
@@ -6,7 +6,21 @@
 #ifndef _UFS_MEDIATEK_H
 #define _UFS_MEDIATEK_H
 
-#include <linux/bitops.h>
+/*
+ * Vendor specific UFSHCI Registers
+ */
+#define REG_UFS_REFCLK_CTRL         0x144
+
+/*
+ * Ref-clk control
+ *
+ * Values for register REG_UFS_REFCLK_CTRL
+ */
+#define REFCLK_RELEASE              0x0
+#define REFCLK_REQUEST              BIT(0)
+#define REFCLK_ACK                  BIT(1)
+
+#define REFCLK_REQ_TIMEOUT_MS       3
 
 /*
  * Vendor specific pre-defined parameters
@@ -34,7 +48,8 @@
 /*
  * SiP commands
  */
-#define UFS_MTK_SIP_DEVICE_RESET    BIT(1)
+#define UFS_MTK_SIP_DEVICE_RESET          BIT(1)
+#define UFS_MTK_SIP_REF_CLK_NOTIFICATION  BIT(3)
 
 /*
  * VS_DEBUGCLOCKENABLE
@@ -55,6 +70,7 @@ enum {
 struct ufs_mtk_host {
 	struct ufs_hba *hba;
 	struct phy *mphy;
+	bool ref_clk_enabled;
 };
 
 #endif /* !_UFS_MEDIATEK_H */
-- 
2.18.0

[PATCH v1 2/4] scsi: ufs: export ufshcd_auto_hibern8_update for vendor usage

[Stanley Chu]

Export ufshcd_auto_hibern8_update to allow vendors to use common
interface to customize auto-hibernate timer.

Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
---
 drivers/scsi/ufs/ufs-sysfs.c | 20 --------------------
 drivers/scsi/ufs/ufshcd.c    | 18 ++++++++++++++++++
 drivers/scsi/ufs/ufshcd.h    |  1 +
 3 files changed, 19 insertions(+), 20 deletions(-)

diff --git a/drivers/scsi/ufs/ufs-sysfs.c b/drivers/scsi/ufs/ufs-sysfs.c
index ad2abc96c0f1..720be3f64be7 100644
--- a/drivers/scsi/ufs/ufs-sysfs.c
+++ b/drivers/scsi/ufs/ufs-sysfs.c
@@ -118,26 +118,6 @@ static ssize_t spm_target_link_state_show(struct device *dev,
 				ufs_pm_lvl_states[hba->spm_lvl].link_state));
 }
 
-static void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit)
-{
-	unsigned long flags;
-
-	if (!ufshcd_is_auto_hibern8_supported(hba))
-		return;
-
-	spin_lock_irqsave(hba->host->host_lock, flags);
-	if (hba->ahit != ahit)
-		hba->ahit = ahit;
-	spin_unlock_irqrestore(hba->host->host_lock, flags);
-	if (!pm_runtime_suspended(hba->dev)) {
-		pm_runtime_get_sync(hba->dev);
-		ufshcd_hold(hba, false);
-		ufshcd_auto_hibern8_enable(hba);
-		ufshcd_release(hba);
-		pm_runtime_put(hba->dev);
-	}
-}
-
 /* Convert Auto-Hibernate Idle Timer register value to microseconds */
 static int ufshcd_ahit_to_us(u32 ahit)
 {
diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
index b5966faf3e98..589f519316aa 100644
--- a/drivers/scsi/ufs/ufshcd.c
+++ b/drivers/scsi/ufs/ufshcd.c
@@ -3956,6 +3956,24 @@ static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
 	return ret;
 }
 
+void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit)
+{
+	unsigned long flags;
+
+	if (!(hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT))
+		return;
+
+	spin_lock_irqsave(hba->host->host_lock, flags);
+	if (hba->ahit == ahit)
+		goto out_unlock;
+	hba->ahit = ahit;
+	if (!pm_runtime_suspended(hba->dev))
+		ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
+out_unlock:
+	spin_unlock_irqrestore(hba->host->host_lock, flags);
+}
+EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update);
+
 void ufshcd_auto_hibern8_enable(struct ufs_hba *hba)
 {
 	unsigned long flags;
diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
index 2740f6941ec6..86586a0b9aa5 100644
--- a/drivers/scsi/ufs/ufshcd.h
+++ b/drivers/scsi/ufs/ufshcd.h
@@ -927,6 +927,7 @@ int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
 	enum flag_idn idn, bool *flag_res);
 
 void ufshcd_auto_hibern8_enable(struct ufs_hba *hba);
+void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit);
 
 #define SD_ASCII_STD true
 #define SD_RAW false
-- 
2.18.0

[PATCH v1 3/4] scsi: ufs-mediatek: configure customized auto-hibern8 timer

[Stanley Chu]

Configure customized auto-hibern8 timer in MediaTek Chipsets.

Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
---
 drivers/scsi/ufs/ufs-mediatek.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/scsi/ufs/ufs-mediatek.c b/drivers/scsi/ufs/ufs-mediatek.c
index 690483c78212..71e2e0e4ea11 100644
--- a/drivers/scsi/ufs/ufs-mediatek.c
+++ b/drivers/scsi/ufs/ufs-mediatek.c
@@ -7,6 +7,7 @@
  */
 
 #include <linux/arm-smccc.h>
+#include <linux/bitfield.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/phy/phy.h>
@@ -300,6 +301,13 @@ static int ufs_mtk_post_link(struct ufs_hba *hba)
 	/* enable unipro clock gating feature */
 	ufs_mtk_cfg_unipro_cg(hba, true);
 
+	/* configure auto-hibern8 timer to 10ms */
+	if (ufshcd_is_auto_hibern8_supported(hba)) {
+		ufshcd_auto_hibern8_update(hba,
+			FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 10) |
+			FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3));
+	}
+
 	return 0;
 }
 
-- 
2.18.0

[PATCH v1 4/4] scsi: ufs-mediatek: configure and enable clk-gating

[Stanley Chu]

Enable clk-gating with customized delayed timer value in
MediaTek Chipsets.

Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
---
 drivers/scsi/ufs/ufs-mediatek.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/drivers/scsi/ufs/ufs-mediatek.c b/drivers/scsi/ufs/ufs-mediatek.c
index 71e2e0e4ea11..282ad06ec846 100644
--- a/drivers/scsi/ufs/ufs-mediatek.c
+++ b/drivers/scsi/ufs/ufs-mediatek.c
@@ -205,6 +205,9 @@ static int ufs_mtk_init(struct ufs_hba *hba)
 	/* Enable runtime autosuspend */
 	hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND;
 
+	/* Enable clock-gating */
+	hba->caps |= UFSHCD_CAP_CLK_GATING;
+
 	/*
 	 * ufshcd_vops_init() is invoked after
 	 * ufshcd_setup_clock(true) in ufshcd_hba_init() thus
@@ -293,6 +296,23 @@ static int ufs_mtk_pre_link(struct ufs_hba *hba)
 	return ret;
 }
 
+static void ufs_mtk_setup_clk_gating(struct ufs_hba *hba)
+{
+	unsigned long flags;
+	u32 ah_ms;
+
+	if (ufshcd_is_clkgating_allowed(hba)) {
+		if (ufshcd_is_auto_hibern8_supported(hba) && hba->ahit)
+			ah_ms = FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK,
+					  hba->ahit);
+		else
+			ah_ms = 10;
+		spin_lock_irqsave(hba->host->host_lock, flags);
+		hba->clk_gating.delay_ms = ah_ms + 5;
+		spin_unlock_irqrestore(hba->host->host_lock, flags);
+	}
+}
+
 static int ufs_mtk_post_link(struct ufs_hba *hba)
 {
 	/* disable device LCC */
@@ -308,6 +328,8 @@ static int ufs_mtk_post_link(struct ufs_hba *hba)
 			FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3));
 	}
 
+	ufs_mtk_setup_clk_gating(hba);
+
 	return 0;
 }
 
-- 
2.18.0

Re: [PATCH v1 2/4] scsi: ufs: export ufshcd_auto_hibern8_update for vendor usage

[Asutosh Das (asd)]

On 12/13/2019 12:11 AM, Stanley Chu wrote:
> Export ufshcd_auto_hibern8_update to allow vendors to use common
> interface to customize auto-hibernate timer.
> 
> Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>
> ---
>   drivers/scsi/ufs/ufs-sysfs.c | 20 --------------------
>   drivers/scsi/ufs/ufshcd.c    | 18 ++++++++++++++++++
>   drivers/scsi/ufs/ufshcd.h    |  1 +
>   3 files changed, 19 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/scsi/ufs/ufs-sysfs.c b/drivers/scsi/ufs/ufs-sysfs.c
> index ad2abc96c0f1..720be3f64be7 100644
> --- a/drivers/scsi/ufs/ufs-sysfs.c
> +++ b/drivers/scsi/ufs/ufs-sysfs.c
> @@ -118,26 +118,6 @@ static ssize_t spm_target_link_state_show(struct device *dev,
>   				ufs_pm_lvl_states[hba->spm_lvl].link_state));
>   }
>   
> -static void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit)
> -{
> -	unsigned long flags;
> -
> -	if (!ufshcd_is_auto_hibern8_supported(hba))
> -		return;
> -
> -	spin_lock_irqsave(hba->host->host_lock, flags);
> -	if (hba->ahit != ahit)
> -		hba->ahit = ahit;
> -	spin_unlock_irqrestore(hba->host->host_lock, flags);
> -	if (!pm_runtime_suspended(hba->dev)) {
> -		pm_runtime_get_sync(hba->dev);
> -		ufshcd_hold(hba, false);
> -		ufshcd_auto_hibern8_enable(hba);
> -		ufshcd_release(hba);
> -		pm_runtime_put(hba->dev);
> -	}
> -}
> -
>   /* Convert Auto-Hibernate Idle Timer register value to microseconds */
>   static int ufshcd_ahit_to_us(u32 ahit)
>   {
> diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
> index b5966faf3e98..589f519316aa 100644
> --- a/drivers/scsi/ufs/ufshcd.c
> +++ b/drivers/scsi/ufs/ufshcd.c
> @@ -3956,6 +3956,24 @@ static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
>   	return ret;
>   }
>   
> +void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit)
> +{
> +	unsigned long flags;
> +
> +	if (!(hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT))
> +		return;
> +
> +	spin_lock_irqsave(hba->host->host_lock, flags);
> +	if (hba->ahit == ahit)
> +		goto out_unlock;
> +	hba->ahit = ahit;
> +	if (!pm_runtime_suspended(hba->dev))
> +		ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
> +out_unlock:
> +	spin_unlock_irqrestore(hba->host->host_lock, flags);
> +}
> +EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update);
> +
>   void ufshcd_auto_hibern8_enable(struct ufs_hba *hba)
>   {
>   	unsigned long flags;
> diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
> index 2740f6941ec6..86586a0b9aa5 100644
> --- a/drivers/scsi/ufs/ufshcd.h
> +++ b/drivers/scsi/ufs/ufshcd.h
> @@ -927,6 +927,7 @@ int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
>   	enum flag_idn idn, bool *flag_res);
>   
>   void ufshcd_auto_hibern8_enable(struct ufs_hba *hba);
> +void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit);
>   
>   #define SD_ASCII_STD true
>   #define SD_RAW false
> 

Looks good to me.

Reviewed-by: Asutosh Das <asutoshd@codeaurora.org>

-- 
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
Linux Foundation Collaborative Project

Re: [PATCH v1 1/4] scsi: ufs-mediatek: introduce reference clock control

[Alim Akhtar]

On Fri, Dec 13, 2019 at 2:23 PM Stanley Chu <stanley.chu@mediatek.com> wrote:
>
> Introduce reference clock control in MediaTek Chipset in order
> to disable it if it is not necessary by UFS device to save system power.
>
> Currently reference clock can be disabled during system suspend, runtime
> suspend and clock-gating after link enters hibernate state.
>
> Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>

> ---
>  drivers/scsi/ufs/ufs-mediatek.c | 64 ++++++++++++++++++++++++++++++---
>  drivers/scsi/ufs/ufs-mediatek.h | 20 +++++++++--
>  2 files changed, 78 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/scsi/ufs/ufs-mediatek.c b/drivers/scsi/ufs/ufs-mediatek.c
> index 6a3ec11b16db..690483c78212 100644
> --- a/drivers/scsi/ufs/ufs-mediatek.c
> +++ b/drivers/scsi/ufs/ufs-mediatek.c
> @@ -18,6 +18,11 @@
>  #include "unipro.h"
>  #include "ufs-mediatek.h"
>
> +#define ufs_mtk_ref_clk_notify(on, res) \
> +       arm_smccc_smc(MTK_SIP_UFS_CONTROL, \
> +                     UFS_MTK_SIP_REF_CLK_NOTIFICATION, \
> +                     on, 0, 0, 0, 0, 0, &(res))
> +
>  static void ufs_mtk_cfg_unipro_cg(struct ufs_hba *hba, bool enable)
>  {
>         u32 tmp;
> @@ -83,6 +88,49 @@ static int ufs_mtk_bind_mphy(struct ufs_hba *hba)
>         return err;
>  }
>
> +static int ufs_mtk_setup_ref_clk(struct ufs_hba *hba, bool on)
> +{
> +       struct ufs_mtk_host *host = ufshcd_get_variant(hba);
> +       struct arm_smccc_res res;
> +       unsigned long timeout;
> +       u32 value;
> +
> +       if (host->ref_clk_enabled == on)
> +               return 0;
> +
> +       if (on) {
> +               ufs_mtk_ref_clk_notify(on, res);
> +               ufshcd_writel(hba, REFCLK_REQUEST, REG_UFS_REFCLK_CTRL);
> +       } else {
> +               ufshcd_writel(hba, REFCLK_RELEASE, REG_UFS_REFCLK_CTRL);
> +       }
> +
> +       /* Wait for ack */
> +       timeout = jiffies + msecs_to_jiffies(REFCLK_REQ_TIMEOUT_MS);
> +       do {
> +               value = ufshcd_readl(hba, REG_UFS_REFCLK_CTRL);
> +
> +               /* Wait until ack bit equals to req bit */
> +               if (((value & REFCLK_ACK) >> 1) == (value & REFCLK_REQUEST))
> +                       goto out;
> +
> +               usleep_range(100, 200);
> +       } while (time_before(jiffies, timeout));
> +
> +       dev_err(hba->dev, "missing ack of refclk req, reg: 0x%x\n", value);
> +
> +       ufs_mtk_ref_clk_notify(host->ref_clk_enabled, res);
> +
> +       return -ETIMEDOUT;
> +
> +out:
> +       host->ref_clk_enabled = on;
> +       if (!on)
> +               ufs_mtk_ref_clk_notify(on, res);
> +
> +       return 0;
> +}
> +
>  /**
>   * ufs_mtk_setup_clocks - enables/disable clocks
>   * @hba: host controller instance
> @@ -107,12 +155,16 @@ static int ufs_mtk_setup_clocks(struct ufs_hba *hba, bool on,
>
>         switch (status) {
>         case PRE_CHANGE:
> -               if (!on)
> +               if (!on) {
> +                       ufs_mtk_setup_ref_clk(hba, on);
>                         ret = phy_power_off(host->mphy);
> +               }
>                 break;
>         case POST_CHANGE:
> -               if (on)
> +               if (on) {
>                         ret = phy_power_on(host->mphy);
> +                       ufs_mtk_setup_ref_clk(hba, on);
> +               }
>                 break;
>         }
>
> @@ -299,8 +351,10 @@ static int ufs_mtk_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op)
>  {
>         struct ufs_mtk_host *host = ufshcd_get_variant(hba);
>
> -       if (ufshcd_is_link_hibern8(hba))
> +       if (ufshcd_is_link_hibern8(hba)) {
>                 phy_power_off(host->mphy);
> +               ufs_mtk_setup_ref_clk(hba, false);
> +       }
>
>         return 0;
>  }
> @@ -309,8 +363,10 @@ static int ufs_mtk_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
>  {
>         struct ufs_mtk_host *host = ufshcd_get_variant(hba);
>
> -       if (ufshcd_is_link_hibern8(hba))
> +       if (ufshcd_is_link_hibern8(hba)) {
> +               ufs_mtk_setup_ref_clk(hba, true);
>                 phy_power_on(host->mphy);
> +       }
>
>         return 0;
>  }
> diff --git a/drivers/scsi/ufs/ufs-mediatek.h b/drivers/scsi/ufs/ufs-mediatek.h
> index b03f601d3a9e..14f8a8357c09 100644
> --- a/drivers/scsi/ufs/ufs-mediatek.h
> +++ b/drivers/scsi/ufs/ufs-mediatek.h
> @@ -6,7 +6,21 @@
>  #ifndef _UFS_MEDIATEK_H
>  #define _UFS_MEDIATEK_H
>
> -#include <linux/bitops.h>
> +/*
> + * Vendor specific UFSHCI Registers
> + */
> +#define REG_UFS_REFCLK_CTRL         0x144
> +
> +/*
> + * Ref-clk control
> + *
> + * Values for register REG_UFS_REFCLK_CTRL
> + */
> +#define REFCLK_RELEASE              0x0
> +#define REFCLK_REQUEST              BIT(0)
> +#define REFCLK_ACK                  BIT(1)
> +
> +#define REFCLK_REQ_TIMEOUT_MS       3
>
>  /*
>   * Vendor specific pre-defined parameters
> @@ -34,7 +48,8 @@
>  /*
>   * SiP commands
>   */
> -#define UFS_MTK_SIP_DEVICE_RESET    BIT(1)
> +#define UFS_MTK_SIP_DEVICE_RESET          BIT(1)
> +#define UFS_MTK_SIP_REF_CLK_NOTIFICATION  BIT(3)
>
>  /*
>   * VS_DEBUGCLOCKENABLE
> @@ -55,6 +70,7 @@ enum {
>  struct ufs_mtk_host {
>         struct ufs_hba *hba;
>         struct phy *mphy;
> +       bool ref_clk_enabled;
>  };
>
>  #endif /* !_UFS_MEDIATEK_H */
> --
> 2.18.0



-- 
Regards,
Alim

Re: [PATCH v1 3/4] scsi: ufs-mediatek: configure customized auto-hibern8 timer

[Alim Akhtar]

On Fri, Dec 13, 2019 at 3:04 PM Stanley Chu <stanley.chu@mediatek.com> wrote:
>
> Configure customized auto-hibern8 timer in MediaTek Chipsets.
>
> Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
> ---
>  drivers/scsi/ufs/ufs-mediatek.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/drivers/scsi/ufs/ufs-mediatek.c b/drivers/scsi/ufs/ufs-mediatek.c
> index 690483c78212..71e2e0e4ea11 100644
> --- a/drivers/scsi/ufs/ufs-mediatek.c
> +++ b/drivers/scsi/ufs/ufs-mediatek.c
> @@ -7,6 +7,7 @@
>   */
>
>  #include <linux/arm-smccc.h>
> +#include <linux/bitfield.h>
>  #include <linux/of.h>
>  #include <linux/of_address.h>
>  #include <linux/phy/phy.h>
> @@ -300,6 +301,13 @@ static int ufs_mtk_post_link(struct ufs_hba *hba)
>         /* enable unipro clock gating feature */
>         ufs_mtk_cfg_unipro_cg(hba, true);
>
> +       /* configure auto-hibern8 timer to 10ms */
> +       if (ufshcd_is_auto_hibern8_supported(hba)) {
> +               ufshcd_auto_hibern8_update(hba,
> +                       FIELD_PREP(UFSHCI_AHIBERN8_TIMER_MASK, 10) |
> +                       FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3));
> +       }
> +
>         return 0;
>  }
>
> --
> 2.18.0



-- 
Regards,
Alim

Re: [PATCH v1 2/4] scsi: ufs: export ufshcd_auto_hibern8_update for vendor usage

[Alim Akhtar]

On Fri, Dec 13, 2019 at 2:07 PM Stanley Chu <stanley.chu@mediatek.com> wrote:
>
> Export ufshcd_auto_hibern8_update to allow vendors to use common
> interface to customize auto-hibernate timer.
>
> Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>

> ---
>  drivers/scsi/ufs/ufs-sysfs.c | 20 --------------------
>  drivers/scsi/ufs/ufshcd.c    | 18 ++++++++++++++++++
>  drivers/scsi/ufs/ufshcd.h    |  1 +
>  3 files changed, 19 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/scsi/ufs/ufs-sysfs.c b/drivers/scsi/ufs/ufs-sysfs.c
> index ad2abc96c0f1..720be3f64be7 100644
> --- a/drivers/scsi/ufs/ufs-sysfs.c
> +++ b/drivers/scsi/ufs/ufs-sysfs.c
> @@ -118,26 +118,6 @@ static ssize_t spm_target_link_state_show(struct device *dev,
>                                 ufs_pm_lvl_states[hba->spm_lvl].link_state));
>  }
>
> -static void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit)
> -{
> -       unsigned long flags;
> -
> -       if (!ufshcd_is_auto_hibern8_supported(hba))
> -               return;
> -
> -       spin_lock_irqsave(hba->host->host_lock, flags);
> -       if (hba->ahit != ahit)
> -               hba->ahit = ahit;
> -       spin_unlock_irqrestore(hba->host->host_lock, flags);
> -       if (!pm_runtime_suspended(hba->dev)) {
> -               pm_runtime_get_sync(hba->dev);
> -               ufshcd_hold(hba, false);
> -               ufshcd_auto_hibern8_enable(hba);
> -               ufshcd_release(hba);
> -               pm_runtime_put(hba->dev);
> -       }
> -}
> -
>  /* Convert Auto-Hibernate Idle Timer register value to microseconds */
>  static int ufshcd_ahit_to_us(u32 ahit)
>  {
> diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c
> index b5966faf3e98..589f519316aa 100644
> --- a/drivers/scsi/ufs/ufshcd.c
> +++ b/drivers/scsi/ufs/ufshcd.c
> @@ -3956,6 +3956,24 @@ static int ufshcd_uic_hibern8_exit(struct ufs_hba *hba)
>         return ret;
>  }
>
> +void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit)
> +{
> +       unsigned long flags;
> +
> +       if (!(hba->capabilities & MASK_AUTO_HIBERN8_SUPPORT))
> +               return;
> +
> +       spin_lock_irqsave(hba->host->host_lock, flags);
> +       if (hba->ahit == ahit)
> +               goto out_unlock;
> +       hba->ahit = ahit;
> +       if (!pm_runtime_suspended(hba->dev))
> +               ufshcd_writel(hba, hba->ahit, REG_AUTO_HIBERNATE_IDLE_TIMER);
> +out_unlock:
> +       spin_unlock_irqrestore(hba->host->host_lock, flags);
> +}
> +EXPORT_SYMBOL_GPL(ufshcd_auto_hibern8_update);
> +
>  void ufshcd_auto_hibern8_enable(struct ufs_hba *hba)
>  {
>         unsigned long flags;
> diff --git a/drivers/scsi/ufs/ufshcd.h b/drivers/scsi/ufs/ufshcd.h
> index 2740f6941ec6..86586a0b9aa5 100644
> --- a/drivers/scsi/ufs/ufshcd.h
> +++ b/drivers/scsi/ufs/ufshcd.h
> @@ -927,6 +927,7 @@ int ufshcd_query_flag(struct ufs_hba *hba, enum query_opcode opcode,
>         enum flag_idn idn, bool *flag_res);
>
>  void ufshcd_auto_hibern8_enable(struct ufs_hba *hba);
> +void ufshcd_auto_hibern8_update(struct ufs_hba *hba, u32 ahit);
>
>  #define SD_ASCII_STD true
>  #define SD_RAW false
> --
> 2.18.0



-- 
Regards,
Alim

Re: [PATCH v1 4/4] scsi: ufs-mediatek: configure and enable clk-gating

[Alim Akhtar]

On Fri, Dec 13, 2019 at 2:42 PM Stanley Chu <stanley.chu@mediatek.com> wrote:
>
> Enable clk-gating with customized delayed timer value in
> MediaTek Chipsets.
>
> Signed-off-by: Stanley Chu <stanley.chu@mediatek.com>

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>

> ---
>  drivers/scsi/ufs/ufs-mediatek.c | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
>
> diff --git a/drivers/scsi/ufs/ufs-mediatek.c b/drivers/scsi/ufs/ufs-mediatek.c
> index 71e2e0e4ea11..282ad06ec846 100644
> --- a/drivers/scsi/ufs/ufs-mediatek.c
> +++ b/drivers/scsi/ufs/ufs-mediatek.c
> @@ -205,6 +205,9 @@ static int ufs_mtk_init(struct ufs_hba *hba)
>         /* Enable runtime autosuspend */
>         hba->caps |= UFSHCD_CAP_RPM_AUTOSUSPEND;
>
> +       /* Enable clock-gating */
> +       hba->caps |= UFSHCD_CAP_CLK_GATING;
> +
>         /*
>          * ufshcd_vops_init() is invoked after
>          * ufshcd_setup_clock(true) in ufshcd_hba_init() thus
> @@ -293,6 +296,23 @@ static int ufs_mtk_pre_link(struct ufs_hba *hba)
>         return ret;
>  }
>
> +static void ufs_mtk_setup_clk_gating(struct ufs_hba *hba)
> +{
> +       unsigned long flags;
> +       u32 ah_ms;
> +
> +       if (ufshcd_is_clkgating_allowed(hba)) {
> +               if (ufshcd_is_auto_hibern8_supported(hba) && hba->ahit)
> +                       ah_ms = FIELD_GET(UFSHCI_AHIBERN8_TIMER_MASK,
> +                                         hba->ahit);
> +               else
> +                       ah_ms = 10;
> +               spin_lock_irqsave(hba->host->host_lock, flags);
> +               hba->clk_gating.delay_ms = ah_ms + 5;
> +               spin_unlock_irqrestore(hba->host->host_lock, flags);
> +       }
> +}
> +
>  static int ufs_mtk_post_link(struct ufs_hba *hba)
>  {
>         /* disable device LCC */
> @@ -308,6 +328,8 @@ static int ufs_mtk_post_link(struct ufs_hba *hba)
>                         FIELD_PREP(UFSHCI_AHIBERN8_SCALE_MASK, 3));
>         }
>
> +       ufs_mtk_setup_clk_gating(hba);
> +
>         return 0;
>  }
>
> --
> 2.18.0



-- 
Regards,
Alim

Re: [PATCH v1 0/4] scsi: ufs-mediatek: provide power management

[Martin K. Petersen]

Stanley,

> The patch set provides power management on MediaTek Chipsets by

Had to apply this by hand. Please make sure you prepare patch
submissions against my "queue" branch.

-- 
Martin K. Petersen	Oracle Linux Engineering

Re: [PATCH v1 0/4] scsi: ufs-mediatek: provide power management

[Stanley Chu]

Hi Martin,

Thank you so much and sorry for your inconvenience.

I was based on the latest linux-next commit in my submission time. I
will be more careful and use your "queue" branch instead for submission.

BTW, sorry again because this series actually require a header file
present by below patch in another series which was submitted earlier
than this series,

"soc: mediatek: add header for SiP service interface"

Otherwise missing header "include/linux/soc/mediatek/mtk_sip_svc.h" will
cause build error if MediaTek UFS driver is enabled.

Hope "soc: mediatek: add header for SiP service interface" could be
merged soon, or please rollback this series first if build error happens
and wait until above patch is merged.

To prevent this error, I shall merge both series and provide a new
combined series. If you want me to do so, please kindly let me know.
Sorry for this again.

On Thu, 2019-12-19 at 18:17 -0500, Martin K. Petersen wrote:
> Stanley,
> 
> > The patch set provides power management on MediaTek Chipsets by
> 
> Had to apply this by hand. Please make sure you prepare patch
> submissions against my "queue" branch.
> 

Thanks,
Stanley

Re: [PATCH v1 0/4] scsi: ufs-mediatek: provide power management

[Martin K. Petersen]

Stanley,

> Otherwise missing header "include/linux/soc/mediatek/mtk_sip_svc.h"
> will cause build error if MediaTek UFS driver is enabled.

Thanks for the heads-up. I obviously don't have an easy way to verify. I
did check after applying to see if there was a way I could trigger a
build of the driver on a non MediaTek platform. But that didn't appear
to be trivial.

-- 
Martin K. Petersen	Oracle Linux Engineering