From: Akash Asthana <akashast@codeaurora.org>
To: Doug Anderson <dianders@chromium.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Wolfram Sang <wsa@the-dreams.de>, Mark Brown <broonie@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Rob Herring <robh+dt@kernel.org>,
linux-i2c@vger.kernel.org, linux-spi <linux-spi@vger.kernel.org>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@vger.kernel.org>, Stephen Boyd <swboyd@chromium.org>,
Manu Gautam <mgautam@codeaurora.org>,
linux-arm-msm <linux-arm-msm@vger.kernel.org>,
linux-serial@vger.kernel.org,
Matthias Kaehlcke <mka@chromium.org>,
Evan Green <evgreen@chromium.org>,
msavaliy@codeaurora.org, Rajendra Nayak <rnayak@codeaurora.org>
Subject: Re: [PATCH V7 RESEND 4/7] spi: spi-geni-qcom: Add interconnect support
Date: Tue, 23 Jun 2020 16:03:05 +0530 [thread overview]
Message-ID: <4160ce9e-ee40-703c-1f13-c20ab90e0a96@codeaurora.org> (raw)
In-Reply-To: <CAD=FV=XwV-8J9-j1j2gwQ08oF8izDv=hB9vj_SogbagOBQfN6Q@mail.gmail.com>
Hi Doug,
On 6/23/2020 10:36 AM, Doug Anderson wrote:
> Hi,
>
> On Mon, Jun 8, 2020 at 10:57 PM Akash Asthana <akashast@codeaurora.org> wrote:
>> Get the interconnect paths for SPI based Serial Engine device
>> and vote according to the current bus speed of the driver.
>>
>> Signed-off-by: Akash Asthana <akashast@codeaurora.org>
>> Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
>> ---
>> Changes in V2:
>> - As per Bjorn's comment, removed se == NULL check from geni_spi_icc_get
>> - As per Bjorn's comment, removed code to set se->icc_path* to NULL in failure
>> - As per Bjorn's comment, introduced and using devm_of_icc_get API for getting
>> path handle
>> - As per Matthias comment, added error handling for icc_set_bw call
>>
>> Changes in V3:
>> - As per Matthias's comment, use helper ICC function from geni-se driver.
>>
>> Changes in V4:
>> - Move peak_bw guess as twice of avg_bw if nothing mentioned explicitly
>> to ICC core.
>>
>> Changes in V5:
>> - Use icc_enable/disable in power on/off call.
>> - Save some non-zero avg/peak value to ICC core by calling geni_icc_set_bw
>> from probe so that when resume/icc_enable is called NOC are running at
>> some non-zero value. No need to call icc_disable after BW vote because
>> device will resume and suspend before probe return and will leave ICC in
>> disabled state.
>>
>> Changes in V6:
>> - No change
>>
>> Changes in V7:
>> - As per Matthias's comment removed usage of peak_bw variable because we don't
>> have explicit peak requirement, we were voting peak = avg and this can be
>> tracked using single variable for avg bw.
>>
>> drivers/spi/spi-geni-qcom.c | 29 ++++++++++++++++++++++++++++-
>> 1 file changed, 28 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c
>> index c397242..2ace5c5 100644
>> --- a/drivers/spi/spi-geni-qcom.c
>> +++ b/drivers/spi/spi-geni-qcom.c
>> @@ -234,6 +234,12 @@ static int setup_fifo_params(struct spi_device *spi_slv,
>> return ret;
>> }
>>
>> + /* Set BW quota for CPU as driver supports FIFO mode only. */
>> + se->icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(mas->cur_speed_hz);
>> + ret = geni_icc_set_bw(se);
>> + if (ret)
>> + return ret;
>> +
> I haven't done a deep review of your patch, but a quick drive-by
> review since I happened to notice it while looking at this driver.
> You should probably also update the other path that's adjusting the
> "mas->cur_speed_hz" variable. Specifically see setup_fifo_xfer().
>
> For bonus points, you could even unify the two paths. Perhaps you
> could pick <https://crrev.com/c/2259624> and include it in your series
> (remove the WIP if you do).
Yeah, we can adjust ICC vote per transfer like we are doing for clock.
I will include your patch to v8 series.
Thanks for review.
regards,
Akash
>
> -Doug
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,\na Linux Foundation Collaborative Project
next prev parent reply other threads:[~2020-06-23 10:33 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-09 5:56 [PATCH V7 RESEND 0/7] Add interconnect support to QSPI and QUP drivers Akash Asthana
2020-06-09 5:56 ` [PATCH V7 RESEND 1/7] soc: qcom: geni: Support for ICC voting Akash Asthana
2020-06-09 5:56 ` [PATCH V7 RESEND 2/7] soc: qcom-geni-se: Add interconnect support to fix earlycon crash Akash Asthana
2020-06-09 5:56 ` [PATCH V7 RESEND 3/7] i2c: i2c-qcom-geni: Add interconnect support Akash Asthana
2020-06-09 5:56 ` [PATCH V7 RESEND 4/7] spi: spi-geni-qcom: " Akash Asthana
2020-06-09 13:41 ` Mark Brown
2020-06-10 11:27 ` Akash Asthana
2020-06-10 13:53 ` Mark Brown
2020-06-23 5:06 ` Doug Anderson
2020-06-23 10:33 ` Akash Asthana [this message]
2020-06-09 5:56 ` [PATCH V7 RESEND 5/7] tty: serial: qcom_geni_serial: " Akash Asthana
2020-06-09 5:56 ` [PATCH V7 RESEND 6/7] spi: spi-qcom-qspi: " Akash Asthana
2020-06-15 7:27 ` Akash Asthana
2020-06-15 12:01 ` Mark Brown
2020-06-09 5:56 ` [PATCH V7 RESEND 7/7] arm64: dts: sc7180: Add interconnect for QUP and QSPI Akash Asthana
2020-06-09 15:38 ` [PATCH V7 RESEND 0/7] Add interconnect support to QSPI and QUP drivers Matthias Kaehlcke
2020-06-10 11:46 ` Akash Asthana
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