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From: Claudiu Zissulescu <Claudiu.Zissulescu@synopsys.com>
To: Vineet Gupta <Vineet.Gupta1@synopsys.com>,
	"gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>
Cc: Vineet Gupta <Vineet.Gupta1@synopsys.com>,
	"linux-snps-arc@lists.infradead.org"
	<linux-snps-arc@lists.infradead.org>,
	"andrew.burgess@embecosm.com" <andrew.burgess@embecosm.com>
Subject: RE: [PATCH] PR 92846: [ARC] generate signaling FDCMPF for hard float comparisons
Date: Tue, 10 Dec 2019 09:12:34 +0000
Message-ID: <BYAPR12MB301302F82982712931B60172CA5B0@BYAPR12MB3013.namprd12.prod.outlook.com> (raw)
In-Reply-To: <20191209190218.20544-1-vgupta@synopsys.com>

Hi,

Thank you for your contribution, I'll push it asap. As far as I understand, you need this patch both in gcc9 branch and mainline.

Cheers,
Claudiu

> -----Original Message-----
> From: Vineet Gupta [mailto:vgupta@synopsys.com]
> Sent: Monday, December 09, 2019 8:02 PM
> To: gcc-patches@gcc.gnu.org
> Cc: Claudiu Zissulescu <claziss@synopsys.com>;
> andrew.burgess@embecosm.com; linux-snps-arc@lists.infradead.org;
> Vineet Gupta <vgupta@synopsys.com>
> Subject: [PATCH] PR 92846: [ARC] generate signaling FDCMPF for hard float
> comparisons
> 
> ARC gcc generates FDCMP instructions which raises Invalid operation for
> signaling NaN only. This causes glibc iseqsig() primitives to fail (in
> the current ongoing glibc port to ARC)
> 
> So split up the hard float compares into two categories and for unordered
> compares generate the FDCMPF instruction (vs. FDCMP) which raises
> exception
> for either NaNs.
> 
> With this fix testsuite/gcc.dg/torture/pr52451.c passes for ARC.
> 
> Also passes 6 additional tests in glibc testsuite (test*iseqsig) and no
> regressions
> 
> gcc/
> xxxx-xx-xx  Vineet Gupta  <vgupta@synopsys.com>
> 
> 	* config/arc/arc-modes.def (CC_FPUE): New Mode CC_FPUE which
> 	helps codegen generate exceptions even for quiet NaN.
> 	* config/arc/arc.c (arc_init_reg_tables): Handle New CC_FPUE mode.
> 	(get_arc_condition_code): Likewise.
> 	(arc_select_cc_mode): LT, LE, GT, GE to use the New CC_FPUE
> mode.
> 	* config/arc/arc.h (REVERSE_CONDITION): Handle New CC_FPUE
> mode.
> 	* config/arc/predicates.md (proper_comparison_operator):
> Likewise.
> 	* config/arc/fpu.md (cmpsf_fpu_trap): New Pattern for CC_FPUE.
> 	(cmpdf_fpu_trap): Likewise.
> 
> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
> ---
>  gcc/config/arc/arc-modes.def |  1 +
>  gcc/config/arc/arc.c         |  8 ++++++--
>  gcc/config/arc/arc.h         |  2 +-
>  gcc/config/arc/fpu.md        | 24 ++++++++++++++++++++++++
>  gcc/config/arc/predicates.md |  1 +
>  5 files changed, 33 insertions(+), 3 deletions(-)
> 
> diff --git a/gcc/config/arc/arc-modes.def b/gcc/config/arc/arc-modes.def
> index 36a2f4abfb25..d16b6a289a15 100644
> --- a/gcc/config/arc/arc-modes.def
> +++ b/gcc/config/arc/arc-modes.def
> @@ -38,4 +38,5 @@ VECTOR_MODES (INT, 16);       /* V16QI V8HI V4SI V2DI
> */
> 
>  /* FPU condition flags.  */
>  CC_MODE (CC_FPU);
> +CC_MODE (CC_FPUE);
>  CC_MODE (CC_FPU_UNEQ);
> diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
> index 28305f459dcd..cbb95d6e9043 100644
> --- a/gcc/config/arc/arc.c
> +++ b/gcc/config/arc/arc.c
> @@ -1564,6 +1564,7 @@ get_arc_condition_code (rtx comparison)
>  	default : gcc_unreachable ();
>  	}
>      case E_CC_FPUmode:
> +    case E_CC_FPUEmode:
>        switch (GET_CODE (comparison))
>  	{
>  	case EQ	       : return ARC_CC_EQ;
> @@ -1686,11 +1687,13 @@ arc_select_cc_mode (enum rtx_code op, rtx x,
> rtx y)
>        case UNLE:
>        case UNGT:
>        case UNGE:
> +	return CC_FPUmode;
> +
>        case LT:
>        case LE:
>        case GT:
>        case GE:
> -	return CC_FPUmode;
> +	return CC_FPUEmode;
> 
>        case LTGT:
>        case UNEQ:
> @@ -1844,7 +1847,7 @@ arc_init_reg_tables (void)
>  	  if (i == (int) CCmode || i == (int) CC_ZNmode || i == (int) CC_Zmode
>  	      || i == (int) CC_Cmode
>  	      || i == CC_FP_GTmode || i == CC_FP_GEmode || i ==
> CC_FP_ORDmode
> -	      || i == CC_FPUmode || i == CC_FPU_UNEQmode)
> +	      || i == CC_FPUmode || i == CC_FPUEmode || i ==
> CC_FPU_UNEQmode)
>  	    arc_mode_class[i] = 1 << (int) C_MODE;
>  	  else
>  	    arc_mode_class[i] = 0;
> @@ -8401,6 +8404,7 @@ arc_reorg (void)
> 
>  	  /* Avoid FPU instructions.  */
>  	  if ((GET_MODE (XEXP (XEXP (pc_target, 0), 0)) == CC_FPUmode)
> +	      || (GET_MODE (XEXP (XEXP (pc_target, 0), 0)) == CC_FPUEmode)
>  	      || (GET_MODE (XEXP (XEXP (pc_target, 0), 0)) ==
> CC_FPU_UNEQmode))
>  	    continue;
> 
> diff --git a/gcc/config/arc/arc.h b/gcc/config/arc/arc.h
> index 4d7ac3281b41..c08ca3d0d432 100644
> --- a/gcc/config/arc/arc.h
> +++ b/gcc/config/arc/arc.h
> @@ -1531,7 +1531,7 @@ enum arc_function_type {
>    (((MODE) == CC_FP_GTmode || (MODE) == CC_FP_GEmode		 \
>      || (MODE) == CC_FP_UNEQmode || (MODE) == CC_FP_ORDmode	 \
>      || (MODE) == CC_FPXmode || (MODE) == CC_FPU_UNEQmode	 \
> -    || (MODE) == CC_FPUmode)					 \
> +    || (MODE) == CC_FPUmode || (MODE) == CC_FPUEmode)		 \
>     ? reverse_condition_maybe_unordered ((CODE))			 \
>     : reverse_condition ((CODE)))
> 
> diff --git a/gcc/config/arc/fpu.md b/gcc/config/arc/fpu.md
> index 6289e9c3f593..6729795de542 100644
> --- a/gcc/config/arc/fpu.md
> +++ b/gcc/config/arc/fpu.md
> @@ -242,6 +242,18 @@
>     (set_attr "type" "fpu")
>     (set_attr "predicable" "yes")])
> 
> +(define_insn "*cmpsf_fpu_trap"
> +  [(set (reg:CC_FPUE CC_REG)
> +	(compare:CC_FPUE (match_operand:SF 0 "register_operand"  "r,
> r,r")
> +			(match_operand:SF 1 "nonmemory_operand"
> "r,CfZ,F")))]
> +  "TARGET_FP_SP_BASE"
> +  "fscmpf%?\\t%0,%1"
> +  [(set_attr "length" "4,4,8")
> +   (set_attr "iscompact" "false")
> +   (set_attr "cond" "set")
> +   (set_attr "type" "fpu")
> +   (set_attr "predicable" "yes")])
> +
>  (define_insn "*cmpsf_fpu_uneq"
>    [(set (reg:CC_FPU_UNEQ CC_REG)
>  	(compare:CC_FPU_UNEQ
> @@ -338,6 +350,18 @@
>     (set_attr "type" "fpu")
>     (set_attr "predicable" "yes")])
> 
> +(define_insn "*cmpdf_fpu_trap"
> +  [(set (reg:CC_FPUE CC_REG)
> +	(compare:CC_FPUE (match_operand:DF 0 "even_register_operand"
> "r")
> +			(match_operand:DF 1 "even_register_operand"
> "r")))]
> +  "TARGET_FP_DP_BASE"
> +  "fdcmpf%? %0, %1"
> +  [(set_attr "length" "4")
> +   (set_attr "iscompact" "false")
> +   (set_attr "cond" "set")
> +   (set_attr "type" "fpu")
> +   (set_attr "predicable" "yes")])
> +
>  (define_insn "*cmpdf_fpu_uneq"
>    [(set (reg:CC_FPU_UNEQ CC_REG)
>  	(compare:CC_FPU_UNEQ
> diff --git a/gcc/config/arc/predicates.md b/gcc/config/arc/predicates.md
> index e0013b32f0f5..4d2ad7ba6789 100644
> --- a/gcc/config/arc/predicates.md
> +++ b/gcc/config/arc/predicates.md
> @@ -439,6 +439,7 @@
>  	      || code == ORDERED || code == UNORDERED);
> 
>      case E_CC_FPUmode:
> +    case E_CC_FPUEmode:
>        return 1;
>      case E_CC_FPU_UNEQmode:
>        return 1;
> --
> 2.20.1


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Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-09 19:02 Vineet Gupta
2019-12-10  9:12 ` Claudiu Zissulescu [this message]
2019-12-10 22:46   ` Vineet Gupta
2019-12-12  9:40     ` Claudiu Zissulescu Ianculescu
2020-01-14 23:49 ` Vineet Gupta
2020-01-15  0:06   ` Vineet Gupta

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