[PATCH 0/5] OMAP: McSPI: Implement McSPI in HWMOD way

[PATCH 0/5] OMAP: McSPI: Implement McSPI in HWMOD way

[Charulatha V]

This patch series implements McSPI Module in HWMOD FW way
and use the runtime PM layer.

This patch series is created on "origin/pm-wip/hwmods-omap4" with
McSPI slave mode patches (url given below) on top of it.
https://patchwork.kernel.org/patch/79677/
Updated McSPI slave mode patches will be posted shortly by Govindraj.
McSPI slave mode patches were already discussed on open source mailing
list and they are almost towards the end of final rebased version.
Hence hwmod patches are created on top of McSPI slave mode patch
series to avoid major rework later on.

Benoit Cousson (1):
  OMAP4 HWMOD: Add mcspi hwmods.

Charulatha V (3):
  OMAP2420: McSPI: Add mcspi hwmod
  OMAP2430 : McSPI: Add mcspi hwmod data
  OMAP3 HWMOD: Add mcspi hwmods.

Govindraj.R (1):
  OMAP McSPI: Adapt McSPI driver to use omap hwmod

 arch/arm/mach-omap2/clock3xxx_data.c       |    4 +
 arch/arm/mach-omap2/devices.c              |  233 +++++++++---------------
 arch/arm/mach-omap2/omap_hwmod_2420_data.c |  138 ++++++++++++++
 arch/arm/mach-omap2/omap_hwmod_2430_data.c |  196 ++++++++++++++++++++
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |  252 +++++++++++++++++++++++++
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |  244 +++++++++++++++++++++++++
 arch/arm/plat-omap/include/plat/mcspi.h    |   27 +++
 drivers/spi/omap2_mcspi.c                  |  273 +++++++++-------------------
 8 files changed, 1034 insertions(+), 333 deletions(-)

[PATCH 1/5] OMAP2420: McSPI: Add mcspi hwmod

[Charulatha V]

This patch updates the omap2420 hwmod data with the
McSPI info.

Signed-off-by: Charulatha V <charu@ti.com>
Signed-off-by: Partha Basak <p-basak2@ti.com>
Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_2420_data.c |  138 ++++++++++++++++++++++++++++
 1 files changed, 138 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 3cc768e..7d1a0ff 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -15,6 +15,7 @@
 #include <mach/irqs.h>
 #include <plat/cpu.h>
 #include <plat/dma.h>
+#include <plat/mcspi.h>
 
 #include "omap_hwmod_common_data.h"
 
@@ -33,6 +34,8 @@ static struct omap_hwmod omap2420_mpu_hwmod;
 static struct omap_hwmod omap2420_iva_hwmod;
 static struct omap_hwmod omap2420_l3_main_hwmod;
 static struct omap_hwmod omap2420_l4_core_hwmod;
+static struct omap_hwmod omap2420_mcspi1_hwmod;
+static struct omap_hwmod omap2420_mcspi2_hwmod;
 
 /* L3 -> L4_CORE interface */
 static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
@@ -72,6 +75,42 @@ static struct omap_hwmod omap2420_l3_main_hwmod = {
 
 static struct omap_hwmod omap2420_l4_wkup_hwmod;
 
+/* L4 CORE -> MCSPI1 interface */
+static struct omap_hwmod_addr_space omap2420_mcspi1_addr_space[] = {
+	{
+		.pa_start	= 0x48098000,
+		.pa_end		= 0x480980ff,
+		.flags		= ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = {
+	.master		= &omap2420_l4_core_hwmod,
+	.slave		= &omap2420_mcspi1_hwmod,
+	.clk		= "mcspi1_ick",
+	.addr		= omap2420_mcspi1_addr_space,
+	.addr_cnt	= ARRAY_SIZE(omap2420_mcspi1_addr_space),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> MCSPI2 interface */
+static struct omap_hwmod_addr_space omap2420_mcspi2_addr_space[] = {
+	{
+		.pa_start	= 0x4809a000,
+		.pa_end		= 0x4809a0ff,
+		.flags		= ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = {
+	.master		= &omap2420_l4_core_hwmod,
+	.slave		= &omap2420_mcspi2_hwmod,
+	.clk		= "mcspi2_ick",
+	.addr		= omap2420_mcspi2_addr_space,
+	.addr_cnt	= ARRAY_SIZE(omap2420_mcspi2_addr_space),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* L4_CORE -> L4_WKUP interface */
 static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
 	.master	= &omap2420_l4_core_hwmod,
@@ -165,12 +204,111 @@ static struct omap_hwmod omap2420_iva_hwmod = {
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
 };
 
+/* SPI common */
+static struct omap_hwmod_class_sysconfig omap2420_mcspi_sysc = {
+	.rev_offs	= 0x0000,
+	.sysc_offs	= 0x0010,
+	.syss_offs	= 0x0014,
+	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+				SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+				SYSC_HAS_AUTOIDLE),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+	.sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2420_mcspi_class = {
+	.name = "mcspi",
+	.sysc = &omap2420_mcspi_sysc,
+};
+
+/* SPI1 */
+static struct omap_hwmod_irq_info omap2420_mcspi1_mpu_irqs[] = {
+	{ .irq = INT_24XX_SPI1_IRQ }, /* 65 */
+};
+
+static struct omap_hwmod_dma_info omap2420_mcspi1_sdma_reqs[] = {
+	{ .name = "rx0", .dma_req = OMAP24XX_DMA_SPI1_RX0 }, /* 35 */
+	{ .name = "rx1", .dma_req = OMAP24XX_DMA_SPI1_RX1 }, /* 37 */
+	{ .name = "rx2", .dma_req = OMAP24XX_DMA_SPI1_RX2 }, /* 39 */
+	{ .name = "rx3", .dma_req = OMAP24XX_DMA_SPI1_RX3 }, /* 41 */
+	{ .name = "tx0", .dma_req = OMAP24XX_DMA_SPI1_TX0 }, /* 34 */
+	{ .name = "tx1", .dma_req = OMAP24XX_DMA_SPI1_TX1 }, /* 36 */
+	{ .name = "tx2", .dma_req = OMAP24XX_DMA_SPI1_TX2 }, /* 38 */
+	{ .name = "tx3", .dma_req = OMAP24XX_DMA_SPI1_TX3 }, /* 40 */
+};
+
+static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = {
+	&omap2420_l4_core__mcspi1,
+};
+
+static struct omap_hwmod omap2420_mcspi1_hwmod = {
+	.name		= "mcspi1_hwmod",
+	.mpu_irqs	= omap2420_mcspi1_mpu_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(omap2420_mcspi1_mpu_irqs),
+	.sdma_reqs	= omap2420_mcspi1_sdma_reqs,
+	.sdma_reqs_cnt	= ARRAY_SIZE(omap2420_mcspi1_sdma_reqs),
+	.main_clk	= "mcspi1_fck",
+	.prcm		= {
+		.omap2 = {
+			.module_offs = CORE_MOD,
+			.prcm_reg_id = 1,
+			.module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP24XX_EN_MCSPI1_SHIFT,
+		},
+	},
+	.slaves		= omap2420_mcspi1_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap2420_mcspi1_slaves),
+	.class		= &omap2420_mcspi_class,
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
+/* SPI2 */
+static struct omap_hwmod_irq_info omap2420_mcspi2_mpu_irqs[] = {
+	{ .irq = INT_24XX_SPI2_IRQ }, /* 66 */
+};
+
+static struct omap_hwmod_dma_info omap2420_mcspi2_sdma_reqs[] = {
+	{ .name = "rx0", .dma_req = OMAP24XX_DMA_SPI2_RX0 }, /* 43 */
+	{ .name = "rx1", .dma_req = OMAP24XX_DMA_SPI2_RX1 }, /* 45 */
+	{ .name = "tx0", .dma_req = OMAP24XX_DMA_SPI2_TX0 }, /* 42 */
+	{ .name = "tx1", .dma_req = OMAP24XX_DMA_SPI2_TX1 }, /* 44 */
+};
+
+static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = {
+	&omap2420_l4_core__mcspi2,
+};
+
+static struct omap_hwmod omap2420_mcspi2_hwmod = {
+	.name		= "mcspi2_hwmod",
+	.mpu_irqs	= omap2420_mcspi2_mpu_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(omap2420_mcspi2_mpu_irqs),
+	.sdma_reqs	= omap2420_mcspi2_sdma_reqs,
+	.sdma_reqs_cnt	= ARRAY_SIZE(omap2420_mcspi2_sdma_reqs),
+	.main_clk	= "mcspi2_fck",
+	.prcm		= {
+		.omap2 = {
+			.module_offs = CORE_MOD,
+			.prcm_reg_id = 1,
+			.module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP24XX_EN_MCSPI2_SHIFT,
+		},
+	},
+	.slaves		= omap2420_mcspi2_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap2420_mcspi2_slaves),
+	.class		= &omap2420_mcspi_class,
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
+};
+
 static __initdata struct omap_hwmod *omap2420_hwmods[] = {
 	&omap2420_l3_main_hwmod,
 	&omap2420_l4_core_hwmod,
 	&omap2420_l4_wkup_hwmod,
 	&omap2420_mpu_hwmod,
 	&omap2420_iva_hwmod,
+	&omap2420_mcspi1_hwmod,
+	&omap2420_mcspi2_hwmod,
 	NULL,
 };
 
-- 
1.6.3.3

[PATCH 2/5] OMAP2430 : McSPI: Add mcspi hwmod data

[Charulatha V]

Update the 2430 hwmod dat file with McSPI info.

Signed-off-by: Charulatha V <charu@ti.com>
Signed-off-by: Partha Basak <p-basak2@ti.com>
Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_2430_data.c |  196 ++++++++++++++++++++++++++++
 1 files changed, 196 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 4526628..52eeadd 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -15,6 +15,7 @@
 #include <mach/irqs.h>
 #include <plat/cpu.h>
 #include <plat/dma.h>
+#include <plat/mcspi.h>
 
 #include "omap_hwmod_common_data.h"
 
@@ -71,6 +72,9 @@ static struct omap_hwmod omap2430_l3_main_hwmod = {
 };
 
 static struct omap_hwmod omap2430_l4_wkup_hwmod;
+static struct omap_hwmod omap2430_mcspi1_hwmod;
+static struct omap_hwmod omap2430_mcspi2_hwmod;
+static struct omap_hwmod omap2430_mcspi3_hwmod;
 
 /* L4_CORE -> L4_WKUP interface */
 static struct omap_hwmod_ocp_if omap2430_l4_core__l4_wkup = {
@@ -110,6 +114,60 @@ static struct omap_hwmod_ocp_if *omap2430_l4_wkup_slaves[] = {
 static struct omap_hwmod_ocp_if *omap2430_l4_wkup_masters[] = {
 };
 
+/* L4 CORE -> MCSPI1 interface */
+static struct omap_hwmod_addr_space omap2430_mcspi1_addr_space[] = {
+	{
+		.pa_start	= 0x48098000,
+		.pa_end		= 0x480980ff,
+		.flags		= ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi1 = {
+	.master		= &omap2430_l4_core_hwmod,
+	.slave		= &omap2430_mcspi1_hwmod,
+	.clk		= "mcspi1_ick",
+	.addr		= omap2430_mcspi1_addr_space,
+	.addr_cnt	= ARRAY_SIZE(omap2430_mcspi1_addr_space),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> MCSPI2 interface */
+static struct omap_hwmod_addr_space omap2430_mcspi2_addr_space[] = {
+	{
+		.pa_start	= 0x4809a000,
+		.pa_end		= 0x4809a0ff,
+		.flags		= ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi2 = {
+	.master		= &omap2430_l4_core_hwmod,
+	.slave		= &omap2430_mcspi2_hwmod,
+	.clk		= "mcspi2_ick",
+	.addr		= omap2430_mcspi2_addr_space,
+	.addr_cnt	= ARRAY_SIZE(omap2430_mcspi2_addr_space),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> MCSPI3 interface */
+static struct omap_hwmod_addr_space omap2430_mcspi3_addr_space[] = {
+	{
+		.pa_start	= 0x480b8000,
+		.pa_end		= 0x480b80ff,
+		.flags		= ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if omap2430_l4_core__mcspi3 = {
+	.master		= &omap2430_l4_core_hwmod,
+	.slave		= &omap2430_mcspi3_hwmod,
+	.clk		= "mcspi3_ick",
+	.addr		= omap2430_mcspi3_addr_space,
+	.addr_cnt	= ARRAY_SIZE(omap2430_mcspi3_addr_space),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 /* L4 WKUP */
 static struct omap_hwmod omap2430_l4_wkup_hwmod = {
 	.name		= "l4_wkup",
@@ -165,12 +223,150 @@ static struct omap_hwmod omap2430_iva_hwmod = {
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 };
 
+/* SPI common */
+static struct omap_hwmod_class_sysconfig omap2430_mcspi_sysc = {
+	.rev_offs	= 0x0000,
+	.sysc_offs	= 0x0010,
+	.syss_offs	= 0x0014,
+	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+				SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+				SYSC_HAS_AUTOIDLE),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+	.sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2430_mcspi_class = {
+	.name = "mcspi",
+	.sysc = &omap2430_mcspi_sysc,
+};
+
+/* SPI1 */
+static struct omap_hwmod_irq_info omap2430_mcspi1_mpu_irqs[] = {
+	{ .irq = INT_24XX_SPI1_IRQ }, /* 65 */
+};
+
+static struct omap_hwmod_dma_info omap2430_mcspi1_sdma_reqs[] = {
+	{ .name = "rx0", .dma_req = OMAP24XX_DMA_SPI1_RX0 }, /* 35 */
+	{ .name = "rx1", .dma_req = OMAP24XX_DMA_SPI1_RX1 }, /* 37 */
+	{ .name = "rx2", .dma_req = OMAP24XX_DMA_SPI1_RX2 }, /* 39 */
+	{ .name = "rx3", .dma_req = OMAP24XX_DMA_SPI1_RX3 }, /* 41 */
+	{ .name = "tx0", .dma_req = OMAP24XX_DMA_SPI1_TX0 }, /* 34 */
+	{ .name = "tx1", .dma_req = OMAP24XX_DMA_SPI1_TX1 }, /* 36 */
+	{ .name = "tx2", .dma_req = OMAP24XX_DMA_SPI1_TX2 }, /* 38 */
+	{ .name = "tx3", .dma_req = OMAP24XX_DMA_SPI1_TX3 }, /* 40 */
+};
+
+static struct omap_hwmod_ocp_if *omap2430_mcspi1_slaves[] = {
+	&omap2430_l4_core__mcspi1,
+};
+
+static struct omap_hwmod omap2430_mcspi1_hwmod = {
+	.name		= "mcspi1_hwmod",
+	.mpu_irqs	= omap2430_mcspi1_mpu_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(omap2430_mcspi1_mpu_irqs),
+	.sdma_reqs	= omap2430_mcspi1_sdma_reqs,
+	.sdma_reqs_cnt	= ARRAY_SIZE(omap2430_mcspi1_sdma_reqs),
+	.main_clk	= "mcspi1_fck",
+	.prcm		= {
+		.omap2 = {
+			.module_offs = CORE_MOD,
+			.prcm_reg_id = 1,
+			.module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP24XX_EN_MCSPI1_SHIFT,
+		},
+	},
+	.slaves		= omap2430_mcspi1_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap2430_mcspi1_slaves),
+	.class		= &omap2430_mcspi_class,
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* SPI2 */
+static struct omap_hwmod_irq_info omap2430_mcspi2_mpu_irqs[] = {
+	{ .irq = INT_24XX_SPI2_IRQ }, /* 66 */
+};
+
+static struct omap_hwmod_dma_info omap2430_mcspi2_sdma_reqs[] = {
+	{ .name = "rx0", .dma_req = OMAP24XX_DMA_SPI2_RX0 }, /* 43 */
+	{ .name = "rx1", .dma_req = OMAP24XX_DMA_SPI2_RX1 }, /* 45 */
+	{ .name = "tx0", .dma_req = OMAP24XX_DMA_SPI2_TX0 }, /* 42 */
+	{ .name = "tx1", .dma_req = OMAP24XX_DMA_SPI2_TX1 }, /* 44 */
+};
+
+static struct omap_hwmod_ocp_if *omap2430_mcspi2_slaves[] = {
+	&omap2430_l4_core__mcspi2,
+};
+
+static struct omap_hwmod omap2430_mcspi2_hwmod = {
+	.name		= "mcspi2_hwmod",
+	.mpu_irqs	= omap2430_mcspi2_mpu_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(omap2430_mcspi2_mpu_irqs),
+	.sdma_reqs	= omap2430_mcspi2_sdma_reqs,
+	.sdma_reqs_cnt	= ARRAY_SIZE(omap2430_mcspi2_sdma_reqs),
+	.main_clk	= "mcspi2_fck",
+	.prcm		= {
+		.omap2 = {
+			.module_offs = CORE_MOD,
+			.prcm_reg_id = 1,
+			.module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP24XX_EN_MCSPI2_SHIFT,
+		},
+	},
+	.slaves		= omap2430_mcspi2_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap2430_mcspi2_slaves),
+	.class		= &omap2430_mcspi_class,
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
+/* SPI3 */
+static struct omap_hwmod_irq_info omap2430_mcspi3_mpu_irqs[] = {
+	{ .irq = INT_24XX_SPI3_IRQ }, /* 91 */
+};
+
+static struct omap_hwmod_dma_info omap2430_mcspi3_sdma_reqs[] = {
+	{ .name = "rx0", .dma_req = OMAP24XX_DMA_SPI3_RX0 }, /* 15 */
+	{ .name = "rx1", .dma_req = OMAP24XX_DMA_SPI3_RX1 }, /* 23 */
+	{ .name = "tx0", .dma_req = OMAP24XX_DMA_SPI3_TX0 }, /* 14 */
+	{ .name = "tx1", .dma_req = OMAP24XX_DMA_SPI3_TX1 }, /* 22 */
+};
+
+static struct omap_hwmod_ocp_if *omap2430_mcspi3_slaves[] = {
+	&omap2430_l4_core__mcspi3,
+};
+
+static struct omap_hwmod omap2430_mcspi3_hwmod = {
+	.name		= "mcspi3_hwmod",
+	.mpu_irqs	= omap2430_mcspi3_mpu_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(omap2430_mcspi3_mpu_irqs),
+	.sdma_reqs	= omap2430_mcspi3_sdma_reqs,
+	.sdma_reqs_cnt	= ARRAY_SIZE(omap2430_mcspi3_sdma_reqs),
+	.main_clk	= "mcspi3_fck",
+	.prcm		= {
+		.omap2 = {
+			.module_offs = CORE_MOD,
+			.prcm_reg_id = 2,
+			.module_bit = OMAP2430_EN_MCSPI3_SHIFT,
+			.idlest_reg_id = 2,
+			.idlest_idle_bit = OMAP24XX_EN_MCSPI2_SHIFT,
+		},
+	},
+	.slaves		= omap2430_mcspi3_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap2430_mcspi3_slaves),
+	.class		= &omap2430_mcspi_class,
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
+};
+
 static __initdata struct omap_hwmod *omap2430_hwmods[] = {
 	&omap2430_l3_main_hwmod,
 	&omap2430_l4_core_hwmod,
 	&omap2430_l4_wkup_hwmod,
 	&omap2430_mpu_hwmod,
 	&omap2430_iva_hwmod,
+	&omap2430_mcspi1_hwmod,
+	&omap2430_mcspi2_hwmod,
+	&omap2430_mcspi3_hwmod,
 	NULL,
 };
 
-- 
1.6.3.3

[PATCH 3/5] OMAP3 HWMOD: Add mcspi hwmods.

[Charulatha V]

Update omap3 hwmod file with mcspi info.

Signed-off-by: Charulatha V <charu@ti.com>
Signed-off-by: Partha Basak <p-basak2@ti.com>
Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |  252 ++++++++++++++++++++++++++++
 1 files changed, 252 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 5d8eb58..88ba29e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -17,6 +17,7 @@
 #include <mach/irqs.h>
 #include <plat/cpu.h>
 #include <plat/dma.h>
+#include <plat/mcspi.h>
 
 #include "omap_hwmod_common_data.h"
 
@@ -36,6 +37,10 @@ static struct omap_hwmod omap3xxx_iva_hwmod;
 static struct omap_hwmod omap3xxx_l3_main_hwmod;
 static struct omap_hwmod omap3xxx_l4_core_hwmod;
 static struct omap_hwmod omap3xxx_l4_per_hwmod;
+static struct omap_hwmod omap34xx_mcspi1;
+static struct omap_hwmod omap34xx_mcspi2;
+static struct omap_hwmod omap34xx_mcspi3;
+static struct omap_hwmod omap34xx_mcspi4;
 
 /* L3 -> L4_CORE interface */
 static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_core = {
@@ -197,6 +202,249 @@ static struct omap_hwmod omap3xxx_iva_hwmod = {
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 };
 
+/* L4 CORE -> MCSPI1 interface */
+static struct omap_hwmod_addr_space omap34xx_mcspi1_addr_space[] = {
+	{
+		.pa_start	= 0x48098000,
+		.pa_end		= 0x480980ff,
+		.flags		= ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi1 = {
+	.master		= &omap3xxx_l4_core_hwmod,
+	.slave		= &omap34xx_mcspi1,
+	.clk		= "mcspi1_ick",
+	.addr		= omap34xx_mcspi1_addr_space,
+	.addr_cnt	= ARRAY_SIZE(omap34xx_mcspi1_addr_space),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> MCSPI2 interface */
+static struct omap_hwmod_addr_space omap34xx_mcspi2_addr_space[] = {
+	{
+		.pa_start	= 0x4809a000,
+		.pa_end		= 0x4809a0ff,
+		.flags		= ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi2 = {
+	.master		= &omap3xxx_l4_core_hwmod,
+	.slave		= &omap34xx_mcspi2,
+	.clk		= "mcspi2_ick",
+	.addr		= omap34xx_mcspi2_addr_space,
+	.addr_cnt	= ARRAY_SIZE(omap34xx_mcspi2_addr_space),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> MCSPI3 interface */
+static struct omap_hwmod_addr_space omap34xx_mcspi3_addr_space[] = {
+	{
+		.pa_start	= 0x480b8000,
+		.pa_end		= 0x480b80ff,
+		.flags		= ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi3 = {
+	.master		= &omap3xxx_l4_core_hwmod,
+	.slave		= &omap34xx_mcspi3,
+	.clk		= "mcspi3_ick",
+	.addr		= omap34xx_mcspi3_addr_space,
+	.addr_cnt	= ARRAY_SIZE(omap34xx_mcspi3_addr_space),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* L4 CORE -> MCSPI4 interface */
+static struct omap_hwmod_addr_space omap34xx_mcspi4_addr_space[] = {
+	{
+		.pa_start	= 0x480ba000,
+		.pa_end		= 0x480ba0ff,
+		.flags		= ADDR_TYPE_RT,
+	},
+};
+
+static struct omap_hwmod_ocp_if omap34xx_l4_core__mcspi4 = {
+	.master		= &omap3xxx_l4_core_hwmod,
+	.slave		= &omap34xx_mcspi4,
+	.clk		= "mcspi4_ick",
+	.addr		= omap34xx_mcspi4_addr_space,
+	.addr_cnt	= ARRAY_SIZE(omap34xx_mcspi4_addr_space),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* SPI common */
+static struct omap_hwmod_class_sysconfig omap34xx_mcspi_sysc = {
+	.rev_offs	= 0x0000,
+	.sysc_offs	= 0x0010,
+	.syss_offs	= 0x0014,
+	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+				SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET |
+				SYSC_HAS_AUTOIDLE),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+	.sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap34xx_mcspi_class = {
+	.name = "mcspi",
+	.sysc = &omap34xx_mcspi_sysc,
+};
+
+/* SPI1 */
+static struct omap_hwmod_irq_info omap34xx_mcspi1_mpu_irqs[] = {
+	{ .name = "irq", .irq = INT_24XX_SPI1_IRQ }, /* 65 */
+};
+
+static struct omap_hwmod_dma_info omap34xx_mcspi1_sdma_reqs[] = {
+	{ .name = "tx0", .dma_req = OMAP24XX_DMA_SPI1_TX0 }, /* 34 */
+	{ .name = "tx2", .dma_req = OMAP24XX_DMA_SPI1_TX2 }, /* 38 */
+	{ .name = "rx1", .dma_req = OMAP24XX_DMA_SPI1_RX1 }, /* 37 */
+	{ .name = "tx1", .dma_req = OMAP24XX_DMA_SPI1_TX1 }, /* 36 */
+	{ .name = "rx0", .dma_req = OMAP24XX_DMA_SPI1_RX0 }, /* 35 */
+	{ .name = "rx2", .dma_req = OMAP24XX_DMA_SPI1_RX2 }, /* 39 */
+	{ .name = "rx3", .dma_req = OMAP24XX_DMA_SPI1_RX3 }, /* 41 */
+	{ .name = "tx3", .dma_req = OMAP24XX_DMA_SPI1_TX3 }, /* 40 */
+};
+
+static struct omap_hwmod_ocp_if *omap34xx_mcspi1_slaves[] = {
+	&omap34xx_l4_core__mcspi1,
+};
+
+static struct omap_hwmod omap34xx_mcspi1 = {
+	.name		= "mcspi1",
+	.mpu_irqs	= omap34xx_mcspi1_mpu_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(omap34xx_mcspi1_mpu_irqs),
+	.sdma_reqs	= omap34xx_mcspi1_sdma_reqs,
+	.sdma_reqs_cnt	= ARRAY_SIZE(omap34xx_mcspi1_sdma_reqs),
+	.main_clk	= "mcspi1_fck",
+	.prcm		= {
+		.omap2 = {
+			.module_offs = CORE_MOD,
+			.prcm_reg_id = 1,
+			.module_bit = OMAP3430_EN_MCSPI1_SHIFT,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP3430_EN_MCSPI1_SHIFT,
+		},
+	},
+	.slaves		= omap34xx_mcspi1_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap34xx_mcspi1_slaves),
+	.class		= &omap34xx_mcspi_class,
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* SPI2 */
+static struct omap_hwmod_irq_info omap34xx_mcspi2_mpu_irqs[] = {
+	{ .name = "irq", .irq = INT_24XX_SPI2_IRQ }, /* 66 */
+};
+
+static struct omap_hwmod_dma_info omap34xx_mcspi2_sdma_reqs[] = {
+	{ .name = "tx0", .dma_req = OMAP24XX_DMA_SPI2_TX0 }, /* 42 */
+	{ .name = "tx1", .dma_req = OMAP24XX_DMA_SPI2_TX1 }, /* 44 */
+	{ .name = "rx0", .dma_req = OMAP24XX_DMA_SPI2_RX0 }, /* 43 */
+	{ .name = "rx1", .dma_req = OMAP24XX_DMA_SPI2_RX1 }, /* 45 */
+};
+
+static struct omap_hwmod_ocp_if *omap34xx_mcspi2_slaves[] = {
+	&omap34xx_l4_core__mcspi2,
+};
+
+static struct omap_hwmod omap34xx_mcspi2 = {
+	.name		= "mcspi2",
+	.mpu_irqs	= omap34xx_mcspi2_mpu_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(omap34xx_mcspi2_mpu_irqs),
+	.sdma_reqs	= omap34xx_mcspi2_sdma_reqs,
+	.sdma_reqs_cnt	= ARRAY_SIZE(omap34xx_mcspi2_sdma_reqs),
+	.main_clk	= "mcspi2_fck",
+	.prcm		= {
+		.omap2 = {
+			.module_offs = CORE_MOD,
+			.prcm_reg_id = 1,
+			.module_bit = OMAP3430_EN_MCSPI2_SHIFT,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP3430_EN_MCSPI2_SHIFT,
+		},
+	},
+	.slaves		= omap34xx_mcspi2_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap34xx_mcspi2_slaves),
+	.class		= &omap34xx_mcspi_class,
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* SPI3 */
+static struct omap_hwmod_irq_info omap34xx_mcspi3_mpu_irqs[] = {
+	{ .name = "irq", .irq = INT_24XX_SPI3_IRQ }, /* 91 */
+};
+
+static struct omap_hwmod_dma_info omap34xx_mcspi3_sdma_reqs[] = {
+	{ .name = "tx0", .dma_req = OMAP24XX_DMA_SPI3_TX0 }, /* 14 */
+	{ .name = "tx1", .dma_req = OMAP24XX_DMA_SPI3_TX1 }, /* 22 */
+	{ .name = "rx0", .dma_req = OMAP24XX_DMA_SPI3_RX0 }, /* 15 */
+	{ .name = "rx1", .dma_req = OMAP24XX_DMA_SPI3_RX1 }, /* 23 */
+};
+
+static struct omap_hwmod_ocp_if *omap34xx_mcspi3_slaves[] = {
+	&omap34xx_l4_core__mcspi3,
+};
+
+static struct omap_hwmod omap34xx_mcspi3 = {
+	.name		= "mcspi3",
+	.mpu_irqs	= omap34xx_mcspi3_mpu_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(omap34xx_mcspi3_mpu_irqs),
+	.sdma_reqs	= omap34xx_mcspi3_sdma_reqs,
+	.sdma_reqs_cnt	= ARRAY_SIZE(omap34xx_mcspi3_sdma_reqs),
+	.main_clk	= "mcspi3_fck",
+	.prcm		= {
+		.omap2 = {
+			.module_offs = CORE_MOD,
+			.prcm_reg_id = 1,
+			.module_bit = OMAP3430_EN_MCSPI3_SHIFT,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP3430_EN_MCSPI3_SHIFT,
+		},
+	},
+	.slaves		= omap34xx_mcspi3_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap34xx_mcspi3_slaves),
+	.class		= &omap34xx_mcspi_class,
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
+/* SPI4 */
+static struct omap_hwmod_irq_info omap34xx_mcspi4_mpu_irqs[] = {
+	{ .name = "irq", .irq = INT_34XX_SPI4_IRQ }, /* 48 */
+};
+
+static struct omap_hwmod_dma_info omap34xx_mcspi4_sdma_reqs[] = {
+	{ .name = "tx0", .dma_req = OMAP34XX_DMA_SPI4_TX0 }, /* 69 */
+	{ .name = "rx0", .dma_req = OMAP34XX_DMA_SPI4_RX0 }, /* 70 */
+};
+
+static struct omap_hwmod_ocp_if *omap34xx_mcspi4_slaves[] = {
+	&omap34xx_l4_core__mcspi4,
+};
+
+static struct omap_hwmod omap34xx_mcspi4 = {
+	.name		= "mcspi4",
+	.mpu_irqs	= omap34xx_mcspi4_mpu_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(omap34xx_mcspi4_mpu_irqs),
+	.sdma_reqs	= omap34xx_mcspi4_sdma_reqs,
+	.sdma_reqs_cnt	= ARRAY_SIZE(omap34xx_mcspi4_sdma_reqs),
+	.main_clk	= "mcspi4_fck",
+	.prcm		= {
+		.omap2 = {
+			.module_offs = CORE_MOD,
+			.prcm_reg_id = 1,
+			.module_bit = OMAP3430_EN_MCSPI4_SHIFT,
+			.idlest_reg_id = 1,
+			.idlest_idle_bit = OMAP3430_EN_MCSPI4_SHIFT,
+		},
+	},
+	.slaves		= omap34xx_mcspi4_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap34xx_mcspi4_slaves),
+	.class		= &omap34xx_mcspi_class,
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
+};
+
 static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
 	&omap3xxx_l3_main_hwmod,
 	&omap3xxx_l4_core_hwmod,
@@ -204,6 +452,10 @@ static __initdata struct omap_hwmod *omap3xxx_hwmods[] = {
 	&omap3xxx_l4_wkup_hwmod,
 	&omap3xxx_mpu_hwmod,
 	&omap3xxx_iva_hwmod,
+	&omap34xx_mcspi1,
+	&omap34xx_mcspi2,
+	&omap34xx_mcspi3,
+	&omap34xx_mcspi4,
 	NULL,
 };
 
-- 
1.6.3.3

[PATCH 4/5] OMAP4 HWMOD: Add mcspi hwmods.

[Charulatha V]

From: Benoit Cousson <b-cousson@ti.com>

Update omap4 hwmod file with mcspi info.

This patch is extracted from the below patch sent by Benoit
OMAP4: hwmod: Add partial hwmod support for OMAP4430 ES1.0
https://patchwork.kernel.org/patch/99052/

Signed-off-by: Benoit Cousson <b-cousson@ti.com>
Signed-off-by: Charulatha V <charu@ti.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Kevin Hilman <khilman@deeprootsystems.com>
Cc: Rajendra Nayak <rnayak@ti.com>
---
 arch/arm/mach-omap2/omap_hwmod_44xx_data.c |  244 ++++++++++++++++++++++++++++
 1 files changed, 244 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index e20b0ee..dd31cc1 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -452,6 +452,245 @@ static struct omap_hwmod omap44xx_mpu_hwmod = {
 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
 };
 
+/*
+ * 'mcspi' class
+ * multichannel serial port interface (mcspi) / master/slave synchronous serial
+ * bus
+ */
+
+static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = {
+	.rev_offs	= 0x0000,
+	.sysc_offs	= 0x0010,
+	.syss_offs	= 0x0114,
+	.sysc_flags	= (SYSC_HAS_SIDLEMODE | SYSC_HAS_EMUFREE |
+			   SYSC_HAS_SOFTRESET),
+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+	.sysc_fields	= &omap_hwmod_sysc_type2,
+};
+
+static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = {
+	.name = "mcspi",
+	.sysc = &omap44xx_mcspi_sysc,
+};
+
+/* mcspi1 */
+static struct omap_hwmod omap44xx_mcspi1_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = {
+	{ .irq = 65 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = {
+	{ .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START },
+	{ .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START },
+	{ .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START },
+	{ .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = {
+	{
+		.pa_start	= 0x48098000,
+		.pa_end		= 0x480981ff,
+		.flags		= ADDR_TYPE_RT
+	},
+};
+
+/* l4_per -> mcspi1 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = {
+	.master		= &omap44xx_l4_per_hwmod,
+	.slave		= &omap44xx_mcspi1_hwmod,
+	.clk		= "l4_div_ck",
+	.addr		= omap44xx_mcspi1_addrs,
+	.addr_cnt	= ARRAY_SIZE(omap44xx_mcspi1_addrs),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcspi1 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcspi1_slaves[] = {
+	&omap44xx_l4_per__mcspi1,
+};
+
+static struct omap_hwmod omap44xx_mcspi1_hwmod = {
+	.name		= "mcspi1",
+	.class		= &omap44xx_mcspi_hwmod_class,
+	.mpu_irqs	= omap44xx_mcspi1_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_mcspi1_irqs),
+	.sdma_reqs	= omap44xx_mcspi1_sdma_reqs,
+	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_mcspi1_sdma_reqs),
+	.main_clk	= "mcspi1_fck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_reg = OMAP4430_CM_L4PER_MCSPI1_CLKCTRL,
+		},
+	},
+	.slaves		= omap44xx_mcspi1_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap44xx_mcspi1_slaves),
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* mcspi2 */
+static struct omap_hwmod omap44xx_mcspi2_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = {
+	{ .irq = 66 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = {
+	{ .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START },
+	{ .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = {
+	{
+		.pa_start	= 0x4809a000,
+		.pa_end		= 0x4809a1ff,
+		.flags		= ADDR_TYPE_RT
+	},
+};
+
+/* l4_per -> mcspi2 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = {
+	.master		= &omap44xx_l4_per_hwmod,
+	.slave		= &omap44xx_mcspi2_hwmod,
+	.clk		= "l4_div_ck",
+	.addr		= omap44xx_mcspi2_addrs,
+	.addr_cnt	= ARRAY_SIZE(omap44xx_mcspi2_addrs),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcspi2 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcspi2_slaves[] = {
+	&omap44xx_l4_per__mcspi2,
+};
+
+static struct omap_hwmod omap44xx_mcspi2_hwmod = {
+	.name		= "mcspi2",
+	.class		= &omap44xx_mcspi_hwmod_class,
+	.mpu_irqs	= omap44xx_mcspi2_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_mcspi2_irqs),
+	.sdma_reqs	= omap44xx_mcspi2_sdma_reqs,
+	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_mcspi2_sdma_reqs),
+	.main_clk	= "mcspi2_fck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_reg = OMAP4430_CM_L4PER_MCSPI2_CLKCTRL,
+		},
+	},
+	.slaves		= omap44xx_mcspi2_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap44xx_mcspi2_slaves),
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* mcspi3 */
+static struct omap_hwmod omap44xx_mcspi3_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = {
+	{ .irq = 91 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = {
+	{ .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START },
+	{ .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = {
+	{
+		.pa_start	= 0x480b8000,
+		.pa_end		= 0x480b81ff,
+		.flags		= ADDR_TYPE_RT
+	},
+};
+
+/* l4_per -> mcspi3 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = {
+	.master		= &omap44xx_l4_per_hwmod,
+	.slave		= &omap44xx_mcspi3_hwmod,
+	.clk		= "l4_div_ck",
+	.addr		= omap44xx_mcspi3_addrs,
+	.addr_cnt	= ARRAY_SIZE(omap44xx_mcspi3_addrs),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcspi3 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcspi3_slaves[] = {
+	&omap44xx_l4_per__mcspi3,
+};
+
+static struct omap_hwmod omap44xx_mcspi3_hwmod = {
+	.name		= "mcspi3",
+	.class		= &omap44xx_mcspi_hwmod_class,
+	.mpu_irqs	= omap44xx_mcspi3_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_mcspi3_irqs),
+	.sdma_reqs	= omap44xx_mcspi3_sdma_reqs,
+	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_mcspi3_sdma_reqs),
+	.main_clk	= "mcspi3_fck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_reg = OMAP4430_CM_L4PER_MCSPI3_CLKCTRL,
+		},
+	},
+	.slaves		= omap44xx_mcspi3_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap44xx_mcspi3_slaves),
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
+/* mcspi4 */
+static struct omap_hwmod omap44xx_mcspi4_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = {
+	{ .irq = 48 + OMAP44XX_IRQ_GIC_START },
+};
+
+static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = {
+	{ .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START },
+	{ .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = {
+	{
+		.pa_start	= 0x480ba000,
+		.pa_end		= 0x480ba1ff,
+		.flags		= ADDR_TYPE_RT
+	},
+};
+
+/* l4_per -> mcspi4 */
+static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = {
+	.master		= &omap44xx_l4_per_hwmod,
+	.slave		= &omap44xx_mcspi4_hwmod,
+	.clk		= "l4_div_ck",
+	.addr		= omap44xx_mcspi4_addrs,
+	.addr_cnt	= ARRAY_SIZE(omap44xx_mcspi4_addrs),
+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+/* mcspi4 slave ports */
+static struct omap_hwmod_ocp_if *omap44xx_mcspi4_slaves[] = {
+	&omap44xx_l4_per__mcspi4,
+};
+
+static struct omap_hwmod omap44xx_mcspi4_hwmod = {
+	.name		= "mcspi4",
+	.class		= &omap44xx_mcspi_hwmod_class,
+	.mpu_irqs	= omap44xx_mcspi4_irqs,
+	.mpu_irqs_cnt	= ARRAY_SIZE(omap44xx_mcspi4_irqs),
+	.sdma_reqs	= omap44xx_mcspi4_sdma_reqs,
+	.sdma_reqs_cnt	= ARRAY_SIZE(omap44xx_mcspi4_sdma_reqs),
+	.main_clk	= "mcspi4_fck",
+	.prcm = {
+		.omap4 = {
+			.clkctrl_reg = OMAP4430_CM_L4PER_MCSPI4_CLKCTRL,
+		},
+	},
+	.slaves		= omap44xx_mcspi4_slaves,
+	.slaves_cnt	= ARRAY_SIZE(omap44xx_mcspi4_slaves),
+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP4430),
+};
+
 static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
 	/* dmm class */
 	&omap44xx_dmm_hwmod,
@@ -472,6 +711,11 @@ static __initdata struct omap_hwmod *omap44xx_hwmods[] = {
 
 	/* mpu class */
 	&omap44xx_mpu_hwmod,
+	/* mcspi class */
+	&omap44xx_mcspi1_hwmod,
+	&omap44xx_mcspi2_hwmod,
+	&omap44xx_mcspi3_hwmod,
+	&omap44xx_mcspi4_hwmod,
 	NULL,
 };
 
-- 
1.6.3.3

[PATCH 5/5] OMAP McSPI: Adapt McSPI driver to use omap hwmod

[Charulatha V]

From: Govindraj.R <govindraj.raja@ti.com>

This patch converts the McSPI driver to use pm_runtime apis while
implementing it in HWMOD FW way.

Signed-off-by: Charulatha V <charu@ti.com>
Signed-off-by: Partha Basak <p-basak2@ti.com>
Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
---
 arch/arm/mach-omap2/clock3xxx_data.c    |    4 +
 arch/arm/mach-omap2/devices.c           |  233 ++++++++++-----------------
 arch/arm/plat-omap/include/plat/mcspi.h |   27 +++
 drivers/spi/omap2_mcspi.c               |  273 ++++++++++---------------------
 4 files changed, 204 insertions(+), 333 deletions(-)

diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 138646d..9482e4d 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -1558,6 +1558,7 @@ static struct clk mcspi4_fck = {
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_MCSPI4_SHIFT,
 	.recalc		= &followparent_recalc,
+	.clkdm_name	= "core_l4_clkdm",
 };
 
 static struct clk mcspi3_fck = {
@@ -1567,6 +1568,7 @@ static struct clk mcspi3_fck = {
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_MCSPI3_SHIFT,
 	.recalc		= &followparent_recalc,
+	.clkdm_name	= "core_l4_clkdm",
 };
 
 static struct clk mcspi2_fck = {
@@ -1576,6 +1578,7 @@ static struct clk mcspi2_fck = {
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_MCSPI2_SHIFT,
 	.recalc		= &followparent_recalc,
+	.clkdm_name	= "core_l4_clkdm",
 };
 
 static struct clk mcspi1_fck = {
@@ -1585,6 +1588,7 @@ static struct clk mcspi1_fck = {
 	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
 	.enable_bit	= OMAP3430_EN_MCSPI1_SHIFT,
 	.recalc		= &followparent_recalc,
+	.clkdm_name	= "core_l4_clkdm",
 };
 
 static struct clk uart2_fck = {
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index fa99da1..a869c35 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -15,6 +15,8 @@
 #include <linux/platform_device.h>
 #include <linux/io.h>
 #include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/slab.h>
 
 #include <mach/hardware.h>
 #include <mach/irqs.h>
@@ -239,170 +241,103 @@ static inline void omap_init_sti(void) {}
 
 #include <plat/mcspi.h>
 
-#define OMAP2_MCSPI1_BASE		0x48098000
-#define OMAP2_MCSPI2_BASE		0x4809a000
-#define OMAP2_MCSPI3_BASE		0x480b8000
-#define OMAP2_MCSPI4_BASE		0x480ba000
-
-#define OMAP4_MCSPI1_BASE		0x48098100
-#define OMAP4_MCSPI2_BASE		0x4809a100
-#define OMAP4_MCSPI3_BASE		0x480b8100
-#define OMAP4_MCSPI4_BASE		0x480ba100
-
-static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
-	.num_cs		= 4,
-	.force_cs_mode	= 1,
-};
-
-static struct resource omap2_mcspi1_resources[] = {
-	{
-		.start		= OMAP2_MCSPI1_BASE,
-		.end		= OMAP2_MCSPI1_BASE + 0xff,
-		.flags		= IORESOURCE_MEM,
-	},
-};
-
-static struct platform_device omap2_mcspi1 = {
-	.name		= "omap2_mcspi",
-	.id		= 1,
-	.num_resources	= ARRAY_SIZE(omap2_mcspi1_resources),
-	.resource	= omap2_mcspi1_resources,
-	.dev		= {
-		.platform_data = &omap2_mcspi1_config,
-	},
-};
-
-static struct omap2_mcspi_platform_config omap2_mcspi2_config = {
-	.num_cs		= 2,
-	.mode		= OMAP2_MCSPI_MASTER,
-	.dma_mode	= 0,
-	.force_cs_mode	= 0,
-	.fifo_depth	= 0,
-};
-
-static struct resource omap2_mcspi2_resources[] = {
-	{
-		.start		= OMAP2_MCSPI2_BASE,
-		.end		= OMAP2_MCSPI2_BASE + 0xff,
-		.flags		= IORESOURCE_MEM,
-	},
-};
-
-static struct platform_device omap2_mcspi2 = {
-	.name		= "omap2_mcspi",
-	.id		= 2,
-	.num_resources	= ARRAY_SIZE(omap2_mcspi2_resources),
-	.resource	= omap2_mcspi2_resources,
-	.dev		= {
-		.platform_data = &omap2_mcspi2_config,
-	},
-};
-
-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
-	defined(CONFIG_ARCH_OMAP4)
-static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
-	.num_cs		= 2,
-};
-
-static struct resource omap2_mcspi3_resources[] = {
-	{
-	.start		= OMAP2_MCSPI3_BASE,
-	.end		= OMAP2_MCSPI3_BASE + 0xff,
-	.flags		= IORESOURCE_MEM,
-	},
-};
-
-static struct platform_device omap2_mcspi3 = {
-	.name		= "omap2_mcspi",
-	.id		= 3,
-	.num_resources	= ARRAY_SIZE(omap2_mcspi3_resources),
-	.resource	= omap2_mcspi3_resources,
-	.dev		= {
-		.platform_data = &omap2_mcspi3_config,
-	},
-};
-#endif
-
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
-static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
-	.num_cs		= 1,
-};
-
-static struct resource omap2_mcspi4_resources[] = {
-	{
-		.start		= OMAP2_MCSPI4_BASE,
-		.end		= OMAP2_MCSPI4_BASE + 0xff,
-		.flags		= IORESOURCE_MEM,
-	},
-};
-
-static struct platform_device omap2_mcspi4 = {
-	.name		= "omap2_mcspi",
-	.id		= 4,
-	.num_resources	= ARRAY_SIZE(omap2_mcspi4_resources),
-	.resource	= omap2_mcspi4_resources,
-	.dev		= {
-		.platform_data = &omap2_mcspi4_config,
-	},
-};
-#endif
-
-#ifdef CONFIG_ARCH_OMAP4
-static inline void omap4_mcspi_fixup(void)
+struct omap_device_pm_latency omap_mcspi_latency[] = {
+	[0] = {
+		.deactivate_func = omap_device_idle_hwmods,
+		.activate_func   = omap_device_enable_hwmods,
+		.flags		 = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
+	},
+};
+
+static const u16 omap2_reg_map[] = {
+	[OMAP2_MCSPI_REVISION]		= 0x00,
+	[OMAP2_MCSPI_SYSCONFIG]		= 0x10,
+	[OMAP2_MCSPI_SYSSTATUS]		= 0x14,
+	[OMAP2_MCSPI_IRQSTATUS]		= 0x18,
+	[OMAP2_MCSPI_IRQENABLE]		= 0x1c,
+	[OMAP2_MCSPI_WAKEUPENABLE]	= 0x20,
+	[OMAP2_MCSPI_SYST]		= 0x24,
+	[OMAP2_MCSPI_MODULCTRL]		= 0x28,
+	[OMAP2_MCSPI_XFERLEVEL]		= 0x7c,
+	[OMAP2_MCSPI_CHCONF0]		= 0x2c,
+	[OMAP2_MCSPI_CHSTAT0]		= 0x30,
+	[OMAP2_MCSPI_CHCTRL0]		= 0x34,
+	[OMAP2_MCSPI_TX0]		= 0x38,
+	[OMAP2_MCSPI_RX0]		= 0x3c,
+};
+
+static const u16 omap4_reg_map[] = {
+	[OMAP2_MCSPI_REVISION]		= 0x100,
+	[OMAP2_MCSPI_SYSCONFIG]		= 0x110,
+	[OMAP2_MCSPI_SYSSTATUS]		= 0x114,
+	[OMAP2_MCSPI_IRQSTATUS]		= 0x118,
+	[OMAP2_MCSPI_IRQENABLE]		= 0x01c,
+	[OMAP2_MCSPI_WAKEUPENABLE]	= 0x120,
+	[OMAP2_MCSPI_SYST]		= 0x124,
+	[OMAP2_MCSPI_MODULCTRL]		= 0x128,
+	[OMAP2_MCSPI_XFERLEVEL]		= 0x17c,
+	[OMAP2_MCSPI_CHCONF0]		= 0x12c,
+	[OMAP2_MCSPI_CHSTAT0]		= 0x130,
+	[OMAP2_MCSPI_CHCTRL0]		= 0x134,
+	[OMAP2_MCSPI_TX0]		= 0x138,
+	[OMAP2_MCSPI_RX0]		= 0x13c,
+	[OMAP2_MCSPI_HL_REV]		= 0x000,
+	[OMAP2_MCSPI_HL_HWINFO]		= 0x004,
+	[OMAP2_MCSPI_HL_SYSCONFIG]	= 0x010,
+};
+
+static int omap_mcspi_init(struct omap_hwmod *oh, void *user)
 {
-	omap2_mcspi1_resources[0].start	= OMAP4_MCSPI1_BASE;
-	omap2_mcspi1_resources[0].end	= OMAP4_MCSPI1_BASE + 0xff;
-	omap2_mcspi2_resources[0].start	= OMAP4_MCSPI2_BASE;
-	omap2_mcspi2_resources[0].end	= OMAP4_MCSPI2_BASE + 0xff;
-	omap2_mcspi3_resources[0].start	= OMAP4_MCSPI3_BASE;
-	omap2_mcspi3_resources[0].end	= OMAP4_MCSPI3_BASE + 0xff;
-	omap2_mcspi4_resources[0].start	= OMAP4_MCSPI4_BASE;
-	omap2_mcspi4_resources[0].end	= OMAP4_MCSPI4_BASE + 0xff;
-}
-#else
-static inline void omap4_mcspi_fixup(void)
-{
-}
-#endif
+	struct omap_device *od;
+	char *name = "omap2_mcspi";
+	struct omap2_mcspi_platform_config *pdata;
+	static int spi_num;
+
+	pdata = kzalloc(sizeof(struct omap2_mcspi_platform_config),
+				GFP_KERNEL);
+	if (!pdata) {
+		pr_err("\nMemory allocation for Mcspi device failed\n");
+		return -ENOMEM;
+	}
 
-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
-	defined(CONFIG_ARCH_OMAP4)
-static inline void omap2_mcspi3_init(void)
-{
-	platform_device_register(&omap2_mcspi3);
-}
-#else
-static inline void omap2_mcspi3_init(void)
-{
-}
-#endif
+	switch (spi_num) {
+	case 0:
+		pdata->num_cs = 4;
+		pdata->force_cs_mode = 1;
+		break;
+	case 1:
+		pdata->num_cs = 2;
+		pdata->mode = OMAP2_MCSPI_MASTER;
+		pdata->dma_mode = 1;
+		pdata->force_cs_mode = 0;
+		pdata->fifo_depth = 0;
+		break;
+	case 2:
+		pdata->num_cs = 2;
+		break;
+	case 3:
+		pdata->num_cs = 1;
+		break;
+	}
 
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
-static inline void omap2_mcspi4_init(void)
-{
-	platform_device_register(&omap2_mcspi4);
-}
-#else
-static inline void omap2_mcspi4_init(void)
-{
+	if (cpu_is_omap44xx())
+		pdata->regs_data = (u16 *)omap4_reg_map;
+	else
+		pdata->regs_data = (u16 *)omap2_reg_map;
+
+	od = omap_device_build(name, spi_num + 1, oh, pdata,
+				sizeof(*pdata),	omap_mcspi_latency,
+				ARRAY_SIZE(omap_mcspi_latency), 0);
+	WARN(IS_ERR(od), "\nCant build omap_device for %s:%s\n",
+				name, oh->name);
+	spi_num++;
+	return 0;
 }
-#endif
 
 static void omap_init_mcspi(void)
 {
-	if (cpu_is_omap44xx())
-		omap4_mcspi_fixup();
-
-	platform_device_register(&omap2_mcspi1);
-	platform_device_register(&omap2_mcspi2);
-
-	if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
-		omap2_mcspi3_init();
-
-	if (cpu_is_omap343x() || cpu_is_omap44xx())
-		omap2_mcspi4_init();
+	omap_hwmod_for_each_by_class("mcspi", omap_mcspi_init, NULL);
 }
-
 #else
 static inline void omap_init_mcspi(void) {}
 #endif
diff --git a/arch/arm/plat-omap/include/plat/mcspi.h b/arch/arm/plat-omap/include/plat/mcspi.h
index 23b928b..27161be 100644
--- a/arch/arm/plat-omap/include/plat/mcspi.h
+++ b/arch/arm/plat-omap/include/plat/mcspi.h
@@ -1,6 +1,10 @@
 #ifndef _OMAP2_MCSPI_H
 #define _OMAP2_MCSPI_H
 
+#if defined CONFIG_ARCH_OMAP2PLUS
+#include <plat/omap_hwmod.h>
+#include <plat/omap_device.h>
+
 #define OMAP2_MCSPI_MASTER		0
 #define OMAP2_MCSPI_SLAVE		1
 
@@ -30,6 +34,7 @@ struct omap2_mcspi_platform_config {
 	u8	dma_mode;
 	u8	force_cs_mode;
 	unsigned short fifo_depth;
+	u16	*regs_data;
 };
 
 struct omap2_mcspi_device_config {
@@ -39,4 +44,26 @@ struct omap2_mcspi_device_config {
 	unsigned single_channel:1;
 };
 
+enum {
+	OMAP2_MCSPI_REVISION = 0,
+	OMAP2_MCSPI_SYSCONFIG,
+	OMAP2_MCSPI_SYSSTATUS,
+	OMAP2_MCSPI_IRQSTATUS,
+	OMAP2_MCSPI_IRQENABLE,
+	OMAP2_MCSPI_WAKEUPENABLE,
+	OMAP2_MCSPI_SYST,
+	OMAP2_MCSPI_MODULCTRL,
+	OMAP2_MCSPI_XFERLEVEL,
+	OMAP2_MCSPI_CHCONF0,
+	OMAP2_MCSPI_CHSTAT0,
+	OMAP2_MCSPI_CHCTRL0,
+	OMAP2_MCSPI_TX0,
+	OMAP2_MCSPI_RX0,
+	OMAP2_MCSPI_HL_REV,
+	OMAP2_MCSPI_HL_HWINFO,
+	OMAP2_MCSPI_HL_SYSCONFIG,
+};
+
+#endif
+
 #endif
diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
index 0c9d1be..44a8bb0 100644
--- a/drivers/spi/omap2_mcspi.c
+++ b/drivers/spi/omap2_mcspi.c
@@ -33,6 +33,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/slab.h>
+#include <linux/pm_runtime.h>
 
 #include <linux/spi/spi.h>
 
@@ -43,35 +44,11 @@
 #define OMAP2_MCSPI_MAX_FREQ		48000000
 #define OMAP2_MCSPI_MAX_FIFODEPTH       64
 
-/* OMAP2 has 3 SPI controllers, while OMAP3 has 4 */
+/* OMAP2 has 3 SPI controllers, while OMAP3/4 has 4 */
 #define OMAP2_MCSPI_MAX_CTRL 		4
 
-#define OMAP2_MCSPI_REVISION		0x00
-#define OMAP2_MCSPI_SYSCONFIG		0x10
-#define OMAP2_MCSPI_SYSSTATUS		0x14
-#define OMAP2_MCSPI_IRQSTATUS		0x18
-#define OMAP2_MCSPI_IRQENABLE		0x1c
-#define OMAP2_MCSPI_WAKEUPENABLE	0x20
-#define OMAP2_MCSPI_SYST		0x24
-#define OMAP2_MCSPI_MODULCTRL		0x28
-#define OMAP2_MCSPI_XFERLEVEL		0x7c
-
-/* per-channel banks, 0x14 bytes each, first is: */
-#define OMAP2_MCSPI_CHCONF0		0x2c
-#define OMAP2_MCSPI_CHSTAT0		0x30
-#define OMAP2_MCSPI_CHCTRL0		0x34
-#define OMAP2_MCSPI_TX0			0x38
-#define OMAP2_MCSPI_RX0			0x3c
-
 /* per-register bitmasks: */
 
-#define OMAP2_MCSPI_SYSCONFIG_SMARTIDLE	BIT(4)
-#define OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP	BIT(2)
-#define OMAP2_MCSPI_SYSCONFIG_AUTOIDLE	BIT(0)
-#define OMAP2_MCSPI_SYSCONFIG_SOFTRESET	BIT(1)
-
-#define OMAP2_MCSPI_SYSSTATUS_RESETDONE	BIT(0)
-
 #define OMAP2_MCSPI_MODULCTRL_SINGLE	BIT(0)
 #define OMAP2_MCSPI_MODULCTRL_MS	BIT(2)
 #define OMAP2_MCSPI_MODULCTRL_STEST	BIT(3)
@@ -127,10 +104,9 @@ struct omap2_mcspi {
 	spinlock_t		lock;
 	struct list_head	msg_queue;
 	struct spi_master	*master;
-	struct clk		*ick;
-	struct clk		*fck;
 	/* Virtual base address of the controller */
 	void __iomem		*base;
+	u16			*regs;
 	unsigned long		phys;
 	/* SPI1 has 4 channels, while SPI2 has 2 */
 	struct omap2_mcspi_dma	*dma_channels;
@@ -138,6 +114,7 @@ struct omap2_mcspi {
 	u8			dma_mode;
 	u8			force_cs_mode;
 	u16			fifo_depth;
+	struct  device          *dev;
 };
 
 struct omap2_mcspi_cs {
@@ -153,7 +130,6 @@ struct omap2_mcspi_cs {
  * corresponding registers are modified.
  */
 struct omap2_mcspi_regs {
-	u32 sysconfig;
 	u32 modulctrl;
 	u32 wakeupenable;
 	struct list_head cs;
@@ -206,29 +182,33 @@ static inline void mcspi_write_reg(struct spi_master *master,
 {
 	struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 
-	__raw_writel(val, mcspi->base + idx);
+	__raw_writel(val, mcspi->base + mcspi->regs[idx]);
 }
 
 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
 {
 	struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 
-	return __raw_readl(mcspi->base + idx);
+	return __raw_readl(mcspi->base + mcspi->regs[idx]);
 }
 
 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
 		int idx, u32 val)
 {
 	struct omap2_mcspi_cs	*cs = spi->controller_state;
+	struct spi_master *master = spi->master;
+	struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 
-	__raw_writel(val, cs->base +  idx);
+	__raw_writel(val, cs->base + mcspi->regs[idx]);
 }
 
 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
 {
 	struct omap2_mcspi_cs	*cs = spi->controller_state;
+	struct spi_master *master = spi->master;
+	struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 
-	return __raw_readl(cs->base + idx);
+	return __raw_readl(cs->base + mcspi->regs[idx]);
 }
 
 static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
@@ -454,32 +434,23 @@ static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
 	mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL,
 			omap2_mcspi_ctx[spi_cntrl->bus_num - 1].modulctrl);
 
-	mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_SYSCONFIG,
-			omap2_mcspi_ctx[spi_cntrl->bus_num - 1].sysconfig);
-
 	mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE,
 			omap2_mcspi_ctx[spi_cntrl->bus_num - 1].wakeupenable);
 
 	list_for_each_entry(cs, &omap2_mcspi_ctx[spi_cntrl->bus_num - 1].cs,
 			node)
-		__raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
+		__raw_writel(cs->chconf0, cs->base +
+				mcspi->regs[OMAP2_MCSPI_CHCONF0]);
 }
-static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi)
+
+static inline void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi)
 {
-	clk_disable(mcspi->ick);
-	clk_disable(mcspi->fck);
+	pm_runtime_put_sync(mcspi->dev);
 }
 
-static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi)
+static inline int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi)
 {
-	if (clk_enable(mcspi->ick))
-		return -ENODEV;
-	if (clk_enable(mcspi->fck))
-		return -ENODEV;
-
-	omap2_mcspi_restore_ctx(mcspi);
-
-	return 0;
+	return pm_runtime_get_sync(mcspi->dev);
 }
 
 static unsigned
@@ -499,7 +470,7 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
 
 	mcspi = spi_master_get_devdata(spi->master);
 	mcspi_dma = &mcspi->dma_channels[spi->chip_select];
-	irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS;
+	irqstat_reg = mcspi->base + mcspi->regs[OMAP2_MCSPI_IRQSTATUS];
 	l = mcspi_cached_chconf0(spi);
 
 	count = xfer->len;
@@ -507,8 +478,8 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
 	word_len = cs->word_len;
 
 	base = cs->phys;
-	tx_reg = base + OMAP2_MCSPI_TX0;
-	rx_reg = base + OMAP2_MCSPI_RX0;
+	tx_reg = base + mcspi->regs[OMAP2_MCSPI_TX0];
+	rx_reg = base + mcspi->regs[OMAP2_MCSPI_RX0];
 	rx = xfer->rx_buf;
 	tx = xfer->tx_buf;
 
@@ -692,9 +663,9 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
 
 	/* We store the pre-calculated register addresses on stack to speed
 	 * up the transfer loop. */
-	tx_reg		= base + OMAP2_MCSPI_TX0;
-	rx_reg		= base + OMAP2_MCSPI_RX0;
-	chstat_reg	= base + OMAP2_MCSPI_CHSTAT0;
+	tx_reg		= base + mcspi->regs[OMAP2_MCSPI_TX0];
+	rx_reg		= base + mcspi->regs[OMAP2_MCSPI_RX0];
+	chstat_reg	= base + mcspi->regs[OMAP2_MCSPI_CHSTAT0];
 
 	if (word_len <= 8) {
 		u8		*rx;
@@ -1047,7 +1018,7 @@ static int omap2_mcspi_setup(struct spi_device *spi)
 			return ret;
 	}
 
-	if (omap2_mcspi_enable_clocks(mcspi))
+	if (omap2_mcspi_enable_clocks(mcspi) < 0)
 		return -ENODEV;
 
 	ret = omap2_mcspi_setup_transfer(spi, NULL);
@@ -1091,10 +1062,11 @@ static void omap2_mcspi_work(struct work_struct *work)
 	struct omap2_mcspi	*mcspi;
 
 	mcspi = container_of(work, struct omap2_mcspi, work);
-	spin_lock_irq(&mcspi->lock);
 
 	if (omap2_mcspi_enable_clocks(mcspi))
-		goto out;
+		return;
+
+	spin_lock_irq(&mcspi->lock);
 
 	/* We only enable one channel at a time -- the one whose message is
 	 * at the head of the queue -- although this controller would gladly
@@ -1169,7 +1141,7 @@ static void omap2_mcspi_work(struct work_struct *work)
 				/* RX_ONLY mode needs dummy data in TX reg */
 				if (t->tx_buf == NULL)
 					__raw_writel(0, cs->base
-							+ OMAP2_MCSPI_TX0);
+						+ mcspi->regs[OMAP2_MCSPI_TX0]);
 
 				if (m->is_dma_mapped ||
 					t->len >= DMA_MIN_BYTES ||
@@ -1218,10 +1190,9 @@ static void omap2_mcspi_work(struct work_struct *work)
 		spin_lock_irq(&mcspi->lock);
 	}
 
-	omap2_mcspi_disable_clocks(mcspi);
-
-out:
 	spin_unlock_irq(&mcspi->lock);
+
+	omap2_mcspi_disable_clocks(mcspi);
 }
 
 static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
@@ -1315,21 +1286,9 @@ static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi)
 	u32			tmp;
 	u32			error = 0;
 
-	if (omap2_mcspi_enable_clocks(mcspi))
+	if (omap2_mcspi_enable_clocks(mcspi) < 0)
 		return -1;
 
-	mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
-			OMAP2_MCSPI_SYSCONFIG_SOFTRESET);
-	do {
-		tmp = mcspi_read_reg(master, OMAP2_MCSPI_SYSSTATUS);
-	} while (!(tmp & OMAP2_MCSPI_SYSSTATUS_RESETDONE));
-
-	tmp = OMAP2_MCSPI_SYSCONFIG_AUTOIDLE |
-		OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP |
-		OMAP2_MCSPI_SYSCONFIG_SMARTIDLE;
-	mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG, tmp);
-	omap2_mcspi_ctx[master->bus_num - 1].sysconfig = tmp;
-
 	tmp = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
 	mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, tmp);
 	omap2_mcspi_ctx[master->bus_num - 1].wakeupenable = tmp;
@@ -1343,52 +1302,22 @@ static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi)
 	return error;
 }
 
-static u8 __initdata spi1_rxdma_id [] = {
-	OMAP24XX_DMA_SPI1_RX0,
-	OMAP24XX_DMA_SPI1_RX1,
-	OMAP24XX_DMA_SPI1_RX2,
-	OMAP24XX_DMA_SPI1_RX3,
-};
-
-static u8 __initdata spi1_txdma_id [] = {
-	OMAP24XX_DMA_SPI1_TX0,
-	OMAP24XX_DMA_SPI1_TX1,
-	OMAP24XX_DMA_SPI1_TX2,
-	OMAP24XX_DMA_SPI1_TX3,
-};
-
-static u8 __initdata spi2_rxdma_id[] = {
-	OMAP24XX_DMA_SPI2_RX0,
-	OMAP24XX_DMA_SPI2_RX1,
-};
-
-static u8 __initdata spi2_txdma_id[] = {
-	OMAP24XX_DMA_SPI2_TX0,
-	OMAP24XX_DMA_SPI2_TX1,
-};
-
-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
-	|| defined(CONFIG_ARCH_OMAP4)
-static u8 __initdata spi3_rxdma_id[] = {
-	OMAP24XX_DMA_SPI3_RX0,
-	OMAP24XX_DMA_SPI3_RX1,
-};
+static int omap_mcspi_runtime_suspend(struct device *dev)
+{
+	return 0;
+}
 
-static u8 __initdata spi3_txdma_id[] = {
-	OMAP24XX_DMA_SPI3_TX0,
-	OMAP24XX_DMA_SPI3_TX1,
-};
-#endif
+static int omap_mcspi_runtime_resume(struct device *dev)
+{
+	struct omap2_mcspi	*mcspi;
+	struct spi_master	*master;
 
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
-static u8 __initdata spi4_rxdma_id[] = {
-	OMAP34XX_DMA_SPI4_RX0,
-};
+	master = dev_get_drvdata(dev);
+	mcspi = spi_master_get_devdata(master);
+	omap2_mcspi_restore_ctx(mcspi);
 
-static u8 __initdata spi4_txdma_id[] = {
-	OMAP34XX_DMA_SPI4_TX0,
-};
-#endif
+	return 0;
+}
 
 static int __init omap2_mcspi_probe(struct platform_device *pdev)
 {
@@ -1398,38 +1327,6 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
 	struct omap2_mcspi	*mcspi;
 	struct resource		*r;
 	int			status = 0, i;
-	const u8		*rxdma_id, *txdma_id;
-	unsigned		num_chipselect;
-
-	switch (pdev->id) {
-	case 1:
-		rxdma_id = spi1_rxdma_id;
-		txdma_id = spi1_txdma_id;
-		num_chipselect = 4;
-		break;
-	case 2:
-		rxdma_id = spi2_rxdma_id;
-		txdma_id = spi2_txdma_id;
-		num_chipselect = 2;
-		break;
-#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
-	|| defined(CONFIG_ARCH_OMAP4)
-	case 3:
-		rxdma_id = spi3_rxdma_id;
-		txdma_id = spi3_txdma_id;
-		num_chipselect = 2;
-		break;
-#endif
-#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
-	case 4:
-		rxdma_id = spi4_rxdma_id;
-		txdma_id = spi4_txdma_id;
-		num_chipselect = 1;
-		break;
-#endif
-	default:
-		return -EINVAL;
-	}
 
 	master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
 	if (master == NULL) {
@@ -1446,7 +1343,7 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
 	master->setup = omap2_mcspi_setup;
 	master->transfer = omap2_mcspi_transfer;
 	master->cleanup = omap2_mcspi_cleanup;
-	master->num_chipselect = num_chipselect;
+	master->num_chipselect = pdata->num_cs;
 
 	dev_set_drvdata(&pdev->dev, master);
 
@@ -1455,6 +1352,7 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
 	mcspi->mcspi_mode = OMAP2_MCSPI_MASTER;
 	mcspi->dma_mode = pdata->dma_mode;
 	mcspi->force_cs_mode = pdata->force_cs_mode;
+	mcspi->regs = pdata->regs_data;
 
 	if (pdata->fifo_depth <= OMAP2_MCSPI_MAX_FIFODEPTH)
 		mcspi->fifo_depth = pdata->fifo_depth;
@@ -1479,63 +1377,67 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
 	if (!mcspi->base) {
 		dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
 		status = -ENOMEM;
-		goto err1aa;
+		goto err2;
 	}
 
+	mcspi->dev = &pdev->dev;
 	INIT_WORK(&mcspi->work, omap2_mcspi_work);
 
 	spin_lock_init(&mcspi->lock);
 	INIT_LIST_HEAD(&mcspi->msg_queue);
 	INIT_LIST_HEAD(&omap2_mcspi_ctx[master->bus_num - 1].cs);
 
-	mcspi->ick = clk_get(&pdev->dev, "ick");
-	if (IS_ERR(mcspi->ick)) {
-		dev_dbg(&pdev->dev, "can't get mcspi_ick\n");
-		status = PTR_ERR(mcspi->ick);
-		goto err1a;
-	}
-	mcspi->fck = clk_get(&pdev->dev, "fck");
-	if (IS_ERR(mcspi->fck)) {
-		dev_dbg(&pdev->dev, "can't get mcspi_fck\n");
-		status = PTR_ERR(mcspi->fck);
-		goto err2;
-	}
-
 	mcspi->dma_channels = kcalloc(master->num_chipselect,
 			sizeof(struct omap2_mcspi_dma),
 			GFP_KERNEL);
 
 	if (mcspi->dma_channels == NULL)
-		goto err3;
+		goto err2;
 
-	for (i = 0; i < num_chipselect; i++) {
+	for (i = 0; i < pdata->num_cs; i++) {
+		char dma_ch_name[14];
+		struct resource *dma_res;
+
+		sprintf(dma_ch_name, "rx%d", i);
+		dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
+							dma_ch_name);
+		if (!dma_res) {
+			dev_dbg(&pdev->dev, "cannot get DMA RX channel\n");
+			status = -ENODEV;
+			break;
+		}
 		mcspi->dma_channels[i].dma_rx_channel = -1;
-		mcspi->dma_channels[i].dma_rx_sync_dev = rxdma_id[i];
+		mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start;
+
+		sprintf(dma_ch_name, "tx%d", i);
+		dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
+							dma_ch_name);
+		if (!dma_res) {
+			dev_dbg(&pdev->dev, "cannot get DMA TX channel\n");
+			status = -ENODEV;
+			break;
+		}
 		mcspi->dma_channels[i].dma_tx_channel = -1;
-		mcspi->dma_channels[i].dma_tx_sync_dev = txdma_id[i];
+		mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
 	}
 
-	if (omap2_mcspi_reset(mcspi) < 0)
-		goto err4;
+	pm_runtime_enable(&pdev->dev);
+	if (status || omap2_mcspi_reset(mcspi) < 0)
+		goto err3;
 
 	status = spi_register_master(master);
 	if (status < 0)
 		goto err4;
 
 	return status;
-
 err4:
-	kfree(mcspi->dma_channels);
+	spi_master_put(master);
 err3:
-	clk_put(mcspi->fck);
+	kfree(mcspi->dma_channels);
 err2:
-	clk_put(mcspi->ick);
-err1a:
-	iounmap(mcspi->base);
-err1aa:
 	release_mem_region(r->start, (r->end - r->start) + 1);
+	iounmap(mcspi->base);
 err1:
-	spi_master_put(master);
 	return status;
 }
 
@@ -1551,9 +1453,7 @@ static int __exit omap2_mcspi_remove(struct platform_device *pdev)
 	mcspi = spi_master_get_devdata(master);
 	dma_channels = mcspi->dma_channels;
 
-	clk_put(mcspi->fck);
-	clk_put(mcspi->ick);
-
+	omap2_mcspi_disable_clocks(mcspi);
 	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	release_mem_region(r->start, (r->end - r->start) + 1);
 
@@ -1568,15 +1468,20 @@ static int __exit omap2_mcspi_remove(struct platform_device *pdev)
 /* work with hotplug and coldplug */
 MODULE_ALIAS("platform:omap2_mcspi");
 
+static const struct dev_pm_ops omap_mcspi_dev_pm_ops = {
+	.runtime_suspend = omap_mcspi_runtime_suspend,
+	.runtime_resume	= omap_mcspi_runtime_resume,
+};
+
 static struct platform_driver omap2_mcspi_driver = {
 	.driver = {
-		.name =		"omap2_mcspi",
-		.owner =	THIS_MODULE,
+		.name	= "omap2_mcspi",
+		.owner	= THIS_MODULE,
+		.pm	= &omap_mcspi_dev_pm_ops,
 	},
 	.remove =	__exit_p(omap2_mcspi_remove),
 };
 
-
 static int __init omap2_mcspi_init(void)
 {
 	omap2_mcspi_wq = create_singlethread_workqueue(
-- 
1.6.3.3

Re: [PATCH 5/5] OMAP McSPI: Adapt McSPI driver to use omap hwmod

[Grant Likely]

On Fri, Aug 13, 2010 at 8:05 AM, Charulatha V <charu@ti.com> wrote:
> From: Govindraj.R <govindraj.raja@ti.com>
>
> This patch converts the McSPI driver to use pm_runtime apis while
> implementing it in HWMOD FW way.

Hi Govindraj,

Some comments below.  Short version is that this patch seems to lump a
number of (mostly) unrelated changes (the register map, HWMOD stuff,
and runtime pm) that makes it hard to review and understand.  I could
use some help understanding what the intent of the patch is, and it
would also help to split it up.

Cheers,
g.

>
> Signed-off-by: Charulatha V <charu@ti.com>
> Signed-off-by: Partha Basak <p-basak2@ti.com>
> Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
> ---
>  arch/arm/mach-omap2/clock3xxx_data.c    |    4 +
>  arch/arm/mach-omap2/devices.c           |  233 ++++++++++-----------------
>  arch/arm/plat-omap/include/plat/mcspi.h |   27 +++
>  drivers/spi/omap2_mcspi.c               |  273 ++++++++++---------------------
>  4 files changed, 204 insertions(+), 333 deletions(-)
>
> diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
> index 138646d..9482e4d 100644
> --- a/arch/arm/mach-omap2/clock3xxx_data.c
> +++ b/arch/arm/mach-omap2/clock3xxx_data.c
> @@ -1558,6 +1558,7 @@ static struct clk mcspi4_fck = {
>        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
>        .enable_bit     = OMAP3430_EN_MCSPI4_SHIFT,
>        .recalc         = &followparent_recalc,
> +       .clkdm_name     = "core_l4_clkdm",
>  };
>
>  static struct clk mcspi3_fck = {
> @@ -1567,6 +1568,7 @@ static struct clk mcspi3_fck = {
>        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
>        .enable_bit     = OMAP3430_EN_MCSPI3_SHIFT,
>        .recalc         = &followparent_recalc,
> +       .clkdm_name     = "core_l4_clkdm",
>  };
>
>  static struct clk mcspi2_fck = {
> @@ -1576,6 +1578,7 @@ static struct clk mcspi2_fck = {
>        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
>        .enable_bit     = OMAP3430_EN_MCSPI2_SHIFT,
>        .recalc         = &followparent_recalc,
> +       .clkdm_name     = "core_l4_clkdm",
>  };
>
>  static struct clk mcspi1_fck = {
> @@ -1585,6 +1588,7 @@ static struct clk mcspi1_fck = {
>        .enable_reg     = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
>        .enable_bit     = OMAP3430_EN_MCSPI1_SHIFT,
>        .recalc         = &followparent_recalc,
> +       .clkdm_name     = "core_l4_clkdm",
>  };
>
>  static struct clk uart2_fck = {
> diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
> index fa99da1..a869c35 100644
> --- a/arch/arm/mach-omap2/devices.c
> +++ b/arch/arm/mach-omap2/devices.c
> @@ -15,6 +15,8 @@
>  #include <linux/platform_device.h>
>  #include <linux/io.h>
>  #include <linux/clk.h>
> +#include <linux/err.h>
> +#include <linux/slab.h>
>
>  #include <mach/hardware.h>
>  #include <mach/irqs.h>
> @@ -239,170 +241,103 @@ static inline void omap_init_sti(void) {}
>
>  #include <plat/mcspi.h>
>
> -#define OMAP2_MCSPI1_BASE              0x48098000
> -#define OMAP2_MCSPI2_BASE              0x4809a000
> -#define OMAP2_MCSPI3_BASE              0x480b8000
> -#define OMAP2_MCSPI4_BASE              0x480ba000
> -
> -#define OMAP4_MCSPI1_BASE              0x48098100
> -#define OMAP4_MCSPI2_BASE              0x4809a100
> -#define OMAP4_MCSPI3_BASE              0x480b8100
> -#define OMAP4_MCSPI4_BASE              0x480ba100
> -
> -static struct omap2_mcspi_platform_config omap2_mcspi1_config = {
> -       .num_cs         = 4,
> -       .force_cs_mode  = 1,
> -};
> -
> -static struct resource omap2_mcspi1_resources[] = {
> -       {
> -               .start          = OMAP2_MCSPI1_BASE,
> -               .end            = OMAP2_MCSPI1_BASE + 0xff,
> -               .flags          = IORESOURCE_MEM,
> -       },
> -};
> -
> -static struct platform_device omap2_mcspi1 = {
> -       .name           = "omap2_mcspi",
> -       .id             = 1,
> -       .num_resources  = ARRAY_SIZE(omap2_mcspi1_resources),
> -       .resource       = omap2_mcspi1_resources,
> -       .dev            = {
> -               .platform_data = &omap2_mcspi1_config,
> -       },
> -};
> -
> -static struct omap2_mcspi_platform_config omap2_mcspi2_config = {
> -       .num_cs         = 2,
> -       .mode           = OMAP2_MCSPI_MASTER,
> -       .dma_mode       = 0,
> -       .force_cs_mode  = 0,
> -       .fifo_depth     = 0,
> -};
> -
> -static struct resource omap2_mcspi2_resources[] = {
> -       {
> -               .start          = OMAP2_MCSPI2_BASE,
> -               .end            = OMAP2_MCSPI2_BASE + 0xff,
> -               .flags          = IORESOURCE_MEM,
> -       },
> -};
> -
> -static struct platform_device omap2_mcspi2 = {
> -       .name           = "omap2_mcspi",
> -       .id             = 2,
> -       .num_resources  = ARRAY_SIZE(omap2_mcspi2_resources),
> -       .resource       = omap2_mcspi2_resources,
> -       .dev            = {
> -               .platform_data = &omap2_mcspi2_config,
> -       },
> -};
> -
> -#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
> -       defined(CONFIG_ARCH_OMAP4)
> -static struct omap2_mcspi_platform_config omap2_mcspi3_config = {
> -       .num_cs         = 2,
> -};
> -
> -static struct resource omap2_mcspi3_resources[] = {
> -       {
> -       .start          = OMAP2_MCSPI3_BASE,
> -       .end            = OMAP2_MCSPI3_BASE + 0xff,
> -       .flags          = IORESOURCE_MEM,
> -       },
> -};
> -
> -static struct platform_device omap2_mcspi3 = {
> -       .name           = "omap2_mcspi",
> -       .id             = 3,
> -       .num_resources  = ARRAY_SIZE(omap2_mcspi3_resources),
> -       .resource       = omap2_mcspi3_resources,
> -       .dev            = {
> -               .platform_data = &omap2_mcspi3_config,
> -       },
> -};
> -#endif
> -
> -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
> -static struct omap2_mcspi_platform_config omap2_mcspi4_config = {
> -       .num_cs         = 1,
> -};
> -
> -static struct resource omap2_mcspi4_resources[] = {
> -       {
> -               .start          = OMAP2_MCSPI4_BASE,
> -               .end            = OMAP2_MCSPI4_BASE + 0xff,
> -               .flags          = IORESOURCE_MEM,
> -       },
> -};
> -
> -static struct platform_device omap2_mcspi4 = {
> -       .name           = "omap2_mcspi",
> -       .id             = 4,
> -       .num_resources  = ARRAY_SIZE(omap2_mcspi4_resources),
> -       .resource       = omap2_mcspi4_resources,
> -       .dev            = {
> -               .platform_data = &omap2_mcspi4_config,
> -       },
> -};
> -#endif
> -
> -#ifdef CONFIG_ARCH_OMAP4
> -static inline void omap4_mcspi_fixup(void)
> +struct omap_device_pm_latency omap_mcspi_latency[] = {
> +       [0] = {
> +               .deactivate_func = omap_device_idle_hwmods,
> +               .activate_func   = omap_device_enable_hwmods,
> +               .flags           = OMAP_DEVICE_LATENCY_AUTO_ADJUST,
> +       },
> +};
> +
> +static const u16 omap2_reg_map[] = {
> +       [OMAP2_MCSPI_REVISION]          = 0x00,
> +       [OMAP2_MCSPI_SYSCONFIG]         = 0x10,
> +       [OMAP2_MCSPI_SYSSTATUS]         = 0x14,
> +       [OMAP2_MCSPI_IRQSTATUS]         = 0x18,
> +       [OMAP2_MCSPI_IRQENABLE]         = 0x1c,
> +       [OMAP2_MCSPI_WAKEUPENABLE]      = 0x20,
> +       [OMAP2_MCSPI_SYST]              = 0x24,
> +       [OMAP2_MCSPI_MODULCTRL]         = 0x28,
> +       [OMAP2_MCSPI_XFERLEVEL]         = 0x7c,
> +       [OMAP2_MCSPI_CHCONF0]           = 0x2c,
> +       [OMAP2_MCSPI_CHSTAT0]           = 0x30,
> +       [OMAP2_MCSPI_CHCTRL0]           = 0x34,
> +       [OMAP2_MCSPI_TX0]               = 0x38,
> +       [OMAP2_MCSPI_RX0]               = 0x3c,
> +};
> +
> +static const u16 omap4_reg_map[] = {
> +       [OMAP2_MCSPI_REVISION]          = 0x100,
> +       [OMAP2_MCSPI_SYSCONFIG]         = 0x110,
> +       [OMAP2_MCSPI_SYSSTATUS]         = 0x114,
> +       [OMAP2_MCSPI_IRQSTATUS]         = 0x118,
> +       [OMAP2_MCSPI_IRQENABLE]         = 0x01c,
> +       [OMAP2_MCSPI_WAKEUPENABLE]      = 0x120,
> +       [OMAP2_MCSPI_SYST]              = 0x124,
> +       [OMAP2_MCSPI_MODULCTRL]         = 0x128,
> +       [OMAP2_MCSPI_XFERLEVEL]         = 0x17c,
> +       [OMAP2_MCSPI_CHCONF0]           = 0x12c,
> +       [OMAP2_MCSPI_CHSTAT0]           = 0x130,
> +       [OMAP2_MCSPI_CHCTRL0]           = 0x134,
> +       [OMAP2_MCSPI_TX0]               = 0x138,
> +       [OMAP2_MCSPI_RX0]               = 0x13c,
> +       [OMAP2_MCSPI_HL_REV]            = 0x000,
> +       [OMAP2_MCSPI_HL_HWINFO]         = 0x004,
> +       [OMAP2_MCSPI_HL_SYSCONFIG]      = 0x010,
> +};

Other than an 0x100 offset for omap4 and the addition of revision
registers, these two register maps are identical.  Is it really worth
having a complete register map table for two things that aren't really
different?  It looks overengineered.

Personally I'd handle this by having two base address pointers; the
regs pointer and the info/revision pointer.  omap4 would have the
revision base set, and omap2 would not.

> +
> +static int omap_mcspi_init(struct omap_hwmod *oh, void *user)
>  {
> -       omap2_mcspi1_resources[0].start = OMAP4_MCSPI1_BASE;
> -       omap2_mcspi1_resources[0].end   = OMAP4_MCSPI1_BASE + 0xff;
> -       omap2_mcspi2_resources[0].start = OMAP4_MCSPI2_BASE;
> -       omap2_mcspi2_resources[0].end   = OMAP4_MCSPI2_BASE + 0xff;
> -       omap2_mcspi3_resources[0].start = OMAP4_MCSPI3_BASE;
> -       omap2_mcspi3_resources[0].end   = OMAP4_MCSPI3_BASE + 0xff;
> -       omap2_mcspi4_resources[0].start = OMAP4_MCSPI4_BASE;
> -       omap2_mcspi4_resources[0].end   = OMAP4_MCSPI4_BASE + 0xff;
> -}
> -#else
> -static inline void omap4_mcspi_fixup(void)
> -{
> -}
> -#endif
> +       struct omap_device *od;
> +       char *name = "omap2_mcspi";
> +       struct omap2_mcspi_platform_config *pdata;
> +       static int spi_num;
> +
> +       pdata = kzalloc(sizeof(struct omap2_mcspi_platform_config),
> +                               GFP_KERNEL);
> +       if (!pdata) {
> +               pr_err("\nMemory allocation for Mcspi device failed\n");
> +               return -ENOMEM;
> +       }
>
> -#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) || \
> -       defined(CONFIG_ARCH_OMAP4)
> -static inline void omap2_mcspi3_init(void)
> -{
> -       platform_device_register(&omap2_mcspi3);
> -}
> -#else
> -static inline void omap2_mcspi3_init(void)
> -{
> -}
> -#endif
> +       switch (spi_num) {
> +       case 0:
> +               pdata->num_cs = 4;
> +               pdata->force_cs_mode = 1;
> +               break;
> +       case 1:
> +               pdata->num_cs = 2;
> +               pdata->mode = OMAP2_MCSPI_MASTER;
> +               pdata->dma_mode = 1;
> +               pdata->force_cs_mode = 0;
> +               pdata->fifo_depth = 0;
> +               break;
> +       case 2:
> +               pdata->num_cs = 2;
> +               break;
> +       case 3:
> +               pdata->num_cs = 1;
> +               break;
> +       }

HWMOD appears to have the purpose of making device instantiation data
driven.  If so, shouldn't these parameters also be extracted from the
HWMOD data?

> -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
> -static inline void omap2_mcspi4_init(void)
> -{
> -       platform_device_register(&omap2_mcspi4);
> -}
> -#else
> -static inline void omap2_mcspi4_init(void)
> -{
> +       if (cpu_is_omap44xx())
> +               pdata->regs_data = (u16 *)omap4_reg_map;
> +       else
> +               pdata->regs_data = (u16 *)omap2_reg_map;
> +
> +       od = omap_device_build(name, spi_num + 1, oh, pdata,
> +                               sizeof(*pdata), omap_mcspi_latency,
> +                               ARRAY_SIZE(omap_mcspi_latency), 0);
> +       WARN(IS_ERR(od), "\nCant build omap_device for %s:%s\n",
> +                               name, oh->name);
> +       spi_num++;
> +       return 0;
>  }
> -#endif
>
>  static void omap_init_mcspi(void)
>  {
> -       if (cpu_is_omap44xx())
> -               omap4_mcspi_fixup();
> -
> -       platform_device_register(&omap2_mcspi1);
> -       platform_device_register(&omap2_mcspi2);
> -
> -       if (cpu_is_omap2430() || cpu_is_omap343x() || cpu_is_omap44xx())
> -               omap2_mcspi3_init();
> -
> -       if (cpu_is_omap343x() || cpu_is_omap44xx())
> -               omap2_mcspi4_init();
> +       omap_hwmod_for_each_by_class("mcspi", omap_mcspi_init, NULL);
>  }
> -
>  #else
>  static inline void omap_init_mcspi(void) {}
>  #endif
> diff --git a/arch/arm/plat-omap/include/plat/mcspi.h b/arch/arm/plat-omap/include/plat/mcspi.h
> index 23b928b..27161be 100644
> --- a/arch/arm/plat-omap/include/plat/mcspi.h
> +++ b/arch/arm/plat-omap/include/plat/mcspi.h
> @@ -1,6 +1,10 @@
>  #ifndef _OMAP2_MCSPI_H
>  #define _OMAP2_MCSPI_H
>
> +#if defined CONFIG_ARCH_OMAP2PLUS
> +#include <plat/omap_hwmod.h>
> +#include <plat/omap_device.h>
> +
>  #define OMAP2_MCSPI_MASTER             0
>  #define OMAP2_MCSPI_SLAVE              1
>
> @@ -30,6 +34,7 @@ struct omap2_mcspi_platform_config {
>        u8      dma_mode;
>        u8      force_cs_mode;
>        unsigned short fifo_depth;
> +       u16     *regs_data;
>  };
>
>  struct omap2_mcspi_device_config {
> @@ -39,4 +44,26 @@ struct omap2_mcspi_device_config {
>        unsigned single_channel:1;
>  };
>
> +enum {
> +       OMAP2_MCSPI_REVISION = 0,
> +       OMAP2_MCSPI_SYSCONFIG,
> +       OMAP2_MCSPI_SYSSTATUS,
> +       OMAP2_MCSPI_IRQSTATUS,
> +       OMAP2_MCSPI_IRQENABLE,
> +       OMAP2_MCSPI_WAKEUPENABLE,
> +       OMAP2_MCSPI_SYST,
> +       OMAP2_MCSPI_MODULCTRL,
> +       OMAP2_MCSPI_XFERLEVEL,
> +       OMAP2_MCSPI_CHCONF0,
> +       OMAP2_MCSPI_CHSTAT0,
> +       OMAP2_MCSPI_CHCTRL0,
> +       OMAP2_MCSPI_TX0,
> +       OMAP2_MCSPI_RX0,
> +       OMAP2_MCSPI_HL_REV,
> +       OMAP2_MCSPI_HL_HWINFO,
> +       OMAP2_MCSPI_HL_SYSCONFIG,
> +};
> +
> +#endif
> +
>  #endif
> diff --git a/drivers/spi/omap2_mcspi.c b/drivers/spi/omap2_mcspi.c
> index 0c9d1be..44a8bb0 100644
> --- a/drivers/spi/omap2_mcspi.c
> +++ b/drivers/spi/omap2_mcspi.c
> @@ -33,6 +33,7 @@
>  #include <linux/clk.h>
>  #include <linux/io.h>
>  #include <linux/slab.h>
> +#include <linux/pm_runtime.h>
>
>  #include <linux/spi/spi.h>
>
> @@ -43,35 +44,11 @@
>  #define OMAP2_MCSPI_MAX_FREQ           48000000
>  #define OMAP2_MCSPI_MAX_FIFODEPTH       64
>
> -/* OMAP2 has 3 SPI controllers, while OMAP3 has 4 */
> +/* OMAP2 has 3 SPI controllers, while OMAP3/4 has 4 */
>  #define OMAP2_MCSPI_MAX_CTRL           4
>
> -#define OMAP2_MCSPI_REVISION           0x00
> -#define OMAP2_MCSPI_SYSCONFIG          0x10
> -#define OMAP2_MCSPI_SYSSTATUS          0x14
> -#define OMAP2_MCSPI_IRQSTATUS          0x18
> -#define OMAP2_MCSPI_IRQENABLE          0x1c
> -#define OMAP2_MCSPI_WAKEUPENABLE       0x20
> -#define OMAP2_MCSPI_SYST               0x24
> -#define OMAP2_MCSPI_MODULCTRL          0x28
> -#define OMAP2_MCSPI_XFERLEVEL          0x7c
> -
> -/* per-channel banks, 0x14 bytes each, first is: */
> -#define OMAP2_MCSPI_CHCONF0            0x2c
> -#define OMAP2_MCSPI_CHSTAT0            0x30
> -#define OMAP2_MCSPI_CHCTRL0            0x34
> -#define OMAP2_MCSPI_TX0                        0x38
> -#define OMAP2_MCSPI_RX0                        0x3c
> -
>  /* per-register bitmasks: */
>
> -#define OMAP2_MCSPI_SYSCONFIG_SMARTIDLE        BIT(4)
> -#define OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP        BIT(2)
> -#define OMAP2_MCSPI_SYSCONFIG_AUTOIDLE BIT(0)
> -#define OMAP2_MCSPI_SYSCONFIG_SOFTRESET        BIT(1)
> -
> -#define OMAP2_MCSPI_SYSSTATUS_RESETDONE        BIT(0)
> -
>  #define OMAP2_MCSPI_MODULCTRL_SINGLE   BIT(0)
>  #define OMAP2_MCSPI_MODULCTRL_MS       BIT(2)
>  #define OMAP2_MCSPI_MODULCTRL_STEST    BIT(3)
> @@ -127,10 +104,9 @@ struct omap2_mcspi {
>        spinlock_t              lock;
>        struct list_head        msg_queue;
>        struct spi_master       *master;
> -       struct clk              *ick;
> -       struct clk              *fck;
>        /* Virtual base address of the controller */
>        void __iomem            *base;
> +       u16                     *regs;

would void __iomem * be more appropriate for regs?  I imagine regs
should never be dereferenced directly.

>        unsigned long           phys;
>        /* SPI1 has 4 channels, while SPI2 has 2 */
>        struct omap2_mcspi_dma  *dma_channels;
> @@ -138,6 +114,7 @@ struct omap2_mcspi {
>        u8                      dma_mode;
>        u8                      force_cs_mode;
>        u16                     fifo_depth;
> +       struct  device          *dev;
>  };
>
>  struct omap2_mcspi_cs {
> @@ -153,7 +130,6 @@ struct omap2_mcspi_cs {
>  * corresponding registers are modified.
>  */
>  struct omap2_mcspi_regs {
> -       u32 sysconfig;
>        u32 modulctrl;
>        u32 wakeupenable;
>        struct list_head cs;
> @@ -206,29 +182,33 @@ static inline void mcspi_write_reg(struct spi_master *master,
>  {
>        struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
>
> -       __raw_writel(val, mcspi->base + idx);
> +       __raw_writel(val, mcspi->base + mcspi->regs[idx]);
>  }
>
>  static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
>  {
>        struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
>
> -       return __raw_readl(mcspi->base + idx);
> +       return __raw_readl(mcspi->base + mcspi->regs[idx]);
>  }
>
>  static inline void mcspi_write_cs_reg(const struct spi_device *spi,
>                int idx, u32 val)
>  {
>        struct omap2_mcspi_cs   *cs = spi->controller_state;
> +       struct spi_master *master = spi->master;
> +       struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
>
> -       __raw_writel(val, cs->base +  idx);
> +       __raw_writel(val, cs->base + mcspi->regs[idx]);
>  }
>
>  static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
>  {
>        struct omap2_mcspi_cs   *cs = spi->controller_state;
> +       struct spi_master *master = spi->master;
> +       struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
>
> -       return __raw_readl(cs->base + idx);
> +       return __raw_readl(cs->base + mcspi->regs[idx]);
>  }
>
>  static inline u32 mcspi_cached_chconf0(const struct spi_device *spi)
> @@ -454,32 +434,23 @@ static void omap2_mcspi_restore_ctx(struct omap2_mcspi *mcspi)
>        mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_MODULCTRL,
>                        omap2_mcspi_ctx[spi_cntrl->bus_num - 1].modulctrl);
>
> -       mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_SYSCONFIG,
> -                       omap2_mcspi_ctx[spi_cntrl->bus_num - 1].sysconfig);
> -
>        mcspi_write_reg(spi_cntrl, OMAP2_MCSPI_WAKEUPENABLE,
>                        omap2_mcspi_ctx[spi_cntrl->bus_num - 1].wakeupenable);
>
>        list_for_each_entry(cs, &omap2_mcspi_ctx[spi_cntrl->bus_num - 1].cs,
>                        node)
> -               __raw_writel(cs->chconf0, cs->base + OMAP2_MCSPI_CHCONF0);
> +               __raw_writel(cs->chconf0, cs->base +
> +                               mcspi->regs[OMAP2_MCSPI_CHCONF0]);
>  }
> -static void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi)
> +
> +static inline void omap2_mcspi_disable_clocks(struct omap2_mcspi *mcspi)
>  {
> -       clk_disable(mcspi->ick);
> -       clk_disable(mcspi->fck);
> +       pm_runtime_put_sync(mcspi->dev);
>  }
>
> -static int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi)
> +static inline int omap2_mcspi_enable_clocks(struct omap2_mcspi *mcspi)
>  {
> -       if (clk_enable(mcspi->ick))
> -               return -ENODEV;
> -       if (clk_enable(mcspi->fck))
> -               return -ENODEV;
> -
> -       omap2_mcspi_restore_ctx(mcspi);
> -
> -       return 0;
> +       return pm_runtime_get_sync(mcspi->dev);
>  }
>
>  static unsigned
> @@ -499,7 +470,7 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
>
>        mcspi = spi_master_get_devdata(spi->master);
>        mcspi_dma = &mcspi->dma_channels[spi->chip_select];
> -       irqstat_reg = mcspi->base + OMAP2_MCSPI_IRQSTATUS;
> +       irqstat_reg = mcspi->base + mcspi->regs[OMAP2_MCSPI_IRQSTATUS];
>        l = mcspi_cached_chconf0(spi);
>
>        count = xfer->len;
> @@ -507,8 +478,8 @@ omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
>        word_len = cs->word_len;
>
>        base = cs->phys;
> -       tx_reg = base + OMAP2_MCSPI_TX0;
> -       rx_reg = base + OMAP2_MCSPI_RX0;
> +       tx_reg = base + mcspi->regs[OMAP2_MCSPI_TX0];
> +       rx_reg = base + mcspi->regs[OMAP2_MCSPI_RX0];
>        rx = xfer->rx_buf;
>        tx = xfer->tx_buf;
>
> @@ -692,9 +663,9 @@ omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
>
>        /* We store the pre-calculated register addresses on stack to speed
>         * up the transfer loop. */
> -       tx_reg          = base + OMAP2_MCSPI_TX0;
> -       rx_reg          = base + OMAP2_MCSPI_RX0;
> -       chstat_reg      = base + OMAP2_MCSPI_CHSTAT0;
> +       tx_reg          = base + mcspi->regs[OMAP2_MCSPI_TX0];
> +       rx_reg          = base + mcspi->regs[OMAP2_MCSPI_RX0];
> +       chstat_reg      = base + mcspi->regs[OMAP2_MCSPI_CHSTAT0];
>
>        if (word_len <= 8) {
>                u8              *rx;
> @@ -1047,7 +1018,7 @@ static int omap2_mcspi_setup(struct spi_device *spi)
>                        return ret;
>        }
>
> -       if (omap2_mcspi_enable_clocks(mcspi))
> +       if (omap2_mcspi_enable_clocks(mcspi) < 0)
>                return -ENODEV;
>
>        ret = omap2_mcspi_setup_transfer(spi, NULL);
> @@ -1091,10 +1062,11 @@ static void omap2_mcspi_work(struct work_struct *work)
>        struct omap2_mcspi      *mcspi;
>
>        mcspi = container_of(work, struct omap2_mcspi, work);
> -       spin_lock_irq(&mcspi->lock);
>
>        if (omap2_mcspi_enable_clocks(mcspi))
> -               goto out;
> +               return;
> +
> +       spin_lock_irq(&mcspi->lock);
>
>        /* We only enable one channel at a time -- the one whose message is
>         * at the head of the queue -- although this controller would gladly
> @@ -1169,7 +1141,7 @@ static void omap2_mcspi_work(struct work_struct *work)
>                                /* RX_ONLY mode needs dummy data in TX reg */
>                                if (t->tx_buf == NULL)
>                                        __raw_writel(0, cs->base
> -                                                       + OMAP2_MCSPI_TX0);
> +                                               + mcspi->regs[OMAP2_MCSPI_TX0]);
>
>                                if (m->is_dma_mapped ||
>                                        t->len >= DMA_MIN_BYTES ||
> @@ -1218,10 +1190,9 @@ static void omap2_mcspi_work(struct work_struct *work)
>                spin_lock_irq(&mcspi->lock);
>        }
>
> -       omap2_mcspi_disable_clocks(mcspi);
> -
> -out:
>        spin_unlock_irq(&mcspi->lock);
> +
> +       omap2_mcspi_disable_clocks(mcspi);
>  }
>
>  static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
> @@ -1315,21 +1286,9 @@ static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi)
>        u32                     tmp;
>        u32                     error = 0;
>
> -       if (omap2_mcspi_enable_clocks(mcspi))
> +       if (omap2_mcspi_enable_clocks(mcspi) < 0)
>                return -1;
>
> -       mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
> -                       OMAP2_MCSPI_SYSCONFIG_SOFTRESET);
> -       do {
> -               tmp = mcspi_read_reg(master, OMAP2_MCSPI_SYSSTATUS);
> -       } while (!(tmp & OMAP2_MCSPI_SYSSTATUS_RESETDONE));
> -
> -       tmp = OMAP2_MCSPI_SYSCONFIG_AUTOIDLE |
> -               OMAP2_MCSPI_SYSCONFIG_ENAWAKEUP |
> -               OMAP2_MCSPI_SYSCONFIG_SMARTIDLE;
> -       mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG, tmp);
> -       omap2_mcspi_ctx[master->bus_num - 1].sysconfig = tmp;
> -
>        tmp = OMAP2_MCSPI_WAKEUPENABLE_WKEN;
>        mcspi_write_reg(master, OMAP2_MCSPI_WAKEUPENABLE, tmp);
>        omap2_mcspi_ctx[master->bus_num - 1].wakeupenable = tmp;
> @@ -1343,52 +1302,22 @@ static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi)
>        return error;
>  }
>
> -static u8 __initdata spi1_rxdma_id [] = {
> -       OMAP24XX_DMA_SPI1_RX0,
> -       OMAP24XX_DMA_SPI1_RX1,
> -       OMAP24XX_DMA_SPI1_RX2,
> -       OMAP24XX_DMA_SPI1_RX3,
> -};
> -
> -static u8 __initdata spi1_txdma_id [] = {
> -       OMAP24XX_DMA_SPI1_TX0,
> -       OMAP24XX_DMA_SPI1_TX1,
> -       OMAP24XX_DMA_SPI1_TX2,
> -       OMAP24XX_DMA_SPI1_TX3,
> -};
> -
> -static u8 __initdata spi2_rxdma_id[] = {
> -       OMAP24XX_DMA_SPI2_RX0,
> -       OMAP24XX_DMA_SPI2_RX1,
> -};
> -
> -static u8 __initdata spi2_txdma_id[] = {
> -       OMAP24XX_DMA_SPI2_TX0,
> -       OMAP24XX_DMA_SPI2_TX1,
> -};
> -
> -#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
> -       || defined(CONFIG_ARCH_OMAP4)
> -static u8 __initdata spi3_rxdma_id[] = {
> -       OMAP24XX_DMA_SPI3_RX0,
> -       OMAP24XX_DMA_SPI3_RX1,
> -};
> +static int omap_mcspi_runtime_suspend(struct device *dev)
> +{
> +       return 0;
> +}
>
> -static u8 __initdata spi3_txdma_id[] = {
> -       OMAP24XX_DMA_SPI3_TX0,
> -       OMAP24XX_DMA_SPI3_TX1,
> -};
> -#endif
> +static int omap_mcspi_runtime_resume(struct device *dev)
> +{
> +       struct omap2_mcspi      *mcspi;
> +       struct spi_master       *master;
>
> -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
> -static u8 __initdata spi4_rxdma_id[] = {
> -       OMAP34XX_DMA_SPI4_RX0,
> -};
> +       master = dev_get_drvdata(dev);
> +       mcspi = spi_master_get_devdata(master);
> +       omap2_mcspi_restore_ctx(mcspi);
>
> -static u8 __initdata spi4_txdma_id[] = {
> -       OMAP34XX_DMA_SPI4_TX0,
> -};
> -#endif
> +       return 0;
> +}
>
>  static int __init omap2_mcspi_probe(struct platform_device *pdev)
>  {
> @@ -1398,38 +1327,6 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
>        struct omap2_mcspi      *mcspi;
>        struct resource         *r;
>        int                     status = 0, i;
> -       const u8                *rxdma_id, *txdma_id;
> -       unsigned                num_chipselect;
> -
> -       switch (pdev->id) {
> -       case 1:
> -               rxdma_id = spi1_rxdma_id;
> -               txdma_id = spi1_txdma_id;
> -               num_chipselect = 4;
> -               break;
> -       case 2:
> -               rxdma_id = spi2_rxdma_id;
> -               txdma_id = spi2_txdma_id;
> -               num_chipselect = 2;
> -               break;
> -#if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3) \
> -       || defined(CONFIG_ARCH_OMAP4)
> -       case 3:
> -               rxdma_id = spi3_rxdma_id;
> -               txdma_id = spi3_txdma_id;
> -               num_chipselect = 2;
> -               break;
> -#endif
> -#if defined(CONFIG_ARCH_OMAP3) || defined(CONFIG_ARCH_OMAP4)
> -       case 4:
> -               rxdma_id = spi4_rxdma_id;
> -               txdma_id = spi4_txdma_id;
> -               num_chipselect = 1;
> -               break;
> -#endif
> -       default:
> -               return -EINVAL;
> -       }

This seems appropriate.  It makes sense to make things like assigned
dma ids more data driven and remove the hard coded case tables.

>
>        master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
>        if (master == NULL) {
> @@ -1446,7 +1343,7 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
>        master->setup = omap2_mcspi_setup;
>        master->transfer = omap2_mcspi_transfer;
>        master->cleanup = omap2_mcspi_cleanup;
> -       master->num_chipselect = num_chipselect;
> +       master->num_chipselect = pdata->num_cs;
>
>        dev_set_drvdata(&pdev->dev, master);
>
> @@ -1455,6 +1352,7 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
>        mcspi->mcspi_mode = OMAP2_MCSPI_MASTER;
>        mcspi->dma_mode = pdata->dma_mode;
>        mcspi->force_cs_mode = pdata->force_cs_mode;
> +       mcspi->regs = pdata->regs_data;
>
>        if (pdata->fifo_depth <= OMAP2_MCSPI_MAX_FIFODEPTH)
>                mcspi->fifo_depth = pdata->fifo_depth;
> @@ -1479,63 +1377,67 @@ static int __init omap2_mcspi_probe(struct platform_device *pdev)
>        if (!mcspi->base) {
>                dev_dbg(&pdev->dev, "can't ioremap MCSPI\n");
>                status = -ENOMEM;
> -               goto err1aa;
> +               goto err2;
>        }
>
> +       mcspi->dev = &pdev->dev;
>        INIT_WORK(&mcspi->work, omap2_mcspi_work);
>
>        spin_lock_init(&mcspi->lock);
>        INIT_LIST_HEAD(&mcspi->msg_queue);
>        INIT_LIST_HEAD(&omap2_mcspi_ctx[master->bus_num - 1].cs);
>
> -       mcspi->ick = clk_get(&pdev->dev, "ick");
> -       if (IS_ERR(mcspi->ick)) {
> -               dev_dbg(&pdev->dev, "can't get mcspi_ick\n");
> -               status = PTR_ERR(mcspi->ick);
> -               goto err1a;
> -       }
> -       mcspi->fck = clk_get(&pdev->dev, "fck");
> -       if (IS_ERR(mcspi->fck)) {
> -               dev_dbg(&pdev->dev, "can't get mcspi_fck\n");
> -               status = PTR_ERR(mcspi->fck);
> -               goto err2;
> -       }
> -

I'm obviously missing some context here.  The driver doesn't seem to
manage the clocks anymore.  What code does now?

>        mcspi->dma_channels = kcalloc(master->num_chipselect,
>                        sizeof(struct omap2_mcspi_dma),
>                        GFP_KERNEL);
>
>        if (mcspi->dma_channels == NULL)
> -               goto err3;
> +               goto err2;
>
> -       for (i = 0; i < num_chipselect; i++) {
> +       for (i = 0; i < pdata->num_cs; i++) {
> +               char dma_ch_name[14];
> +               struct resource *dma_res;
> +
> +               sprintf(dma_ch_name, "rx%d", i);
> +               dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
> +                                                       dma_ch_name);
> +               if (!dma_res) {
> +                       dev_dbg(&pdev->dev, "cannot get DMA RX channel\n");
> +                       status = -ENODEV;
> +                       break;
> +               }
>                mcspi->dma_channels[i].dma_rx_channel = -1;
> -               mcspi->dma_channels[i].dma_rx_sync_dev = rxdma_id[i];
> +               mcspi->dma_channels[i].dma_rx_sync_dev = dma_res->start;
> +
> +               sprintf(dma_ch_name, "tx%d", i);
> +               dma_res = platform_get_resource_byname(pdev, IORESOURCE_DMA,
> +                                                       dma_ch_name);
> +               if (!dma_res) {
> +                       dev_dbg(&pdev->dev, "cannot get DMA TX channel\n");
> +                       status = -ENODEV;
> +                       break;
> +               }
>                mcspi->dma_channels[i].dma_tx_channel = -1;
> -               mcspi->dma_channels[i].dma_tx_sync_dev = txdma_id[i];
> +               mcspi->dma_channels[i].dma_tx_sync_dev = dma_res->start;
>        }
>
> -       if (omap2_mcspi_reset(mcspi) < 0)
> -               goto err4;
> +       pm_runtime_enable(&pdev->dev);
> +       if (status || omap2_mcspi_reset(mcspi) < 0)
> +               goto err3;
>
>        status = spi_register_master(master);
>        if (status < 0)
>                goto err4;
>
>        return status;
> -
>  err4:
> -       kfree(mcspi->dma_channels);
> +       spi_master_put(master);
>  err3:
> -       clk_put(mcspi->fck);
> +       kfree(mcspi->dma_channels);
>  err2:
> -       clk_put(mcspi->ick);
> -err1a:
> -       iounmap(mcspi->base);
> -err1aa:
>        release_mem_region(r->start, (r->end - r->start) + 1);
> +       iounmap(mcspi->base);
>  err1:
> -       spi_master_put(master);
>        return status;
>  }
>
> @@ -1551,9 +1453,7 @@ static int __exit omap2_mcspi_remove(struct platform_device *pdev)
>        mcspi = spi_master_get_devdata(master);
>        dma_channels = mcspi->dma_channels;
>
> -       clk_put(mcspi->fck);
> -       clk_put(mcspi->ick);
> -
> +       omap2_mcspi_disable_clocks(mcspi);
>        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>        release_mem_region(r->start, (r->end - r->start) + 1);
>
> @@ -1568,15 +1468,20 @@ static int __exit omap2_mcspi_remove(struct platform_device *pdev)
>  /* work with hotplug and coldplug */
>  MODULE_ALIAS("platform:omap2_mcspi");
>
> +static const struct dev_pm_ops omap_mcspi_dev_pm_ops = {
> +       .runtime_suspend = omap_mcspi_runtime_suspend,
> +       .runtime_resume = omap_mcspi_runtime_resume,
> +};
> +
>  static struct platform_driver omap2_mcspi_driver = {
>        .driver = {
> -               .name =         "omap2_mcspi",
> -               .owner =        THIS_MODULE,
> +               .name   = "omap2_mcspi",
> +               .owner  = THIS_MODULE,
> +               .pm     = &omap_mcspi_dev_pm_ops,

nit: Unrelated whitespace changes.

>        },
>        .remove =       __exit_p(omap2_mcspi_remove),
>  };
>
> -
>  static int __init omap2_mcspi_init(void)
>  {
>        omap2_mcspi_wq = create_singlethread_workqueue(
> --
> 1.6.3.3
>
>



-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
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Re: [PATCH 5/5] OMAP McSPI: Adapt McSPI driver to use omap hwmod

[Govindraj]

Grant,

Thanks for the review. Comments inlined.


On Sat, Aug 14, 2010 at 4:39 AM, Grant Likely <grant.likely@secretlab.ca> wrote:
> On Fri, Aug 13, 2010 at 8:05 AM, Charulatha V <charu@ti.com> wrote:
>> From: Govindraj.R <govindraj.raja@ti.com>
>>
>> This patch converts the McSPI driver to use pm_runtime apis while
>> implementing it in HWMOD FW way.
>
> Hi Govindraj,
>
> Some comments below.  Short version is that this patch seems to lump a
> number of (mostly) unrelated changes (the register map, HWMOD stuff,
> and runtime pm) that makes it hard to review and understand.  I could
> use some help understanding what the intent of the patch is, and it
> would also help to split it up.
>
> Cheers,
> g.

Sure, I will split this patch as below.

1.) reg map update
2.) hwmod update(like removing dma macros etc.) + runtime (if split,
git bisect can break)
     (Since clock handling will be done with hwmod)

<snip>

>> +       [OMAP2_MCSPI_RX0]               = 0x13c,
>> +       [OMAP2_MCSPI_HL_REV]            = 0x000,
>> +       [OMAP2_MCSPI_HL_HWINFO]         = 0x004,
>> +       [OMAP2_MCSPI_HL_SYSCONFIG]      = 0x010,
>> +};
>
> Other than an 0x100 offset for omap4 and the addition of revision
> registers, these two register maps are identical.  Is it really worth
> having a complete register map table for two things that aren't really
> different?  It looks overengineered.
>
> Personally I'd handle this by having two base address pointers; the
> regs pointer and the info/revision pointer.  omap4 would have the
> revision base set, and omap2 would not.
>

Yes will have a single table for register offset, pass a
0x100(probably named as offset deviation)
value from platform data to be added while read/write to registers for
omap4 and others can have 0

<snip>

>> +               pdata->num_cs = 2;
>> +               pdata->mode = OMAP2_MCSPI_MASTER;
>> +               pdata->dma_mode = 1;
>> +               pdata->force_cs_mode = 0;
>> +               pdata->fifo_depth = 0;
>> +               break;
>> +       case 2:
>> +               pdata->num_cs = 2;
>> +               break;
>> +       case 3:
>> +               pdata->num_cs = 1;
>> +               break;
>> +       }
>
> HWMOD appears to have the purpose of making device instantiation data
> driven.  If so, shouldn't these parameters also be extracted from the
> HWMOD data?

Yes these params can be passed from hwmod data
This has to part of dev attribute data that can be passed from hwmod data.


<snip>

>> -       mcspi->ick = clk_get(&pdev->dev, "ick");
>> -       if (IS_ERR(mcspi->ick)) {
>> -               dev_dbg(&pdev->dev, "can't get mcspi_ick\n");
>> -               status = PTR_ERR(mcspi->ick);
>> -               goto err1a;
>> -       }
>> -       mcspi->fck = clk_get(&pdev->dev, "fck");
>> -       if (IS_ERR(mcspi->fck)) {
>> -               dev_dbg(&pdev->dev, "can't get mcspi_fck\n");
>> -               status = PTR_ERR(mcspi->fck);
>> -               goto err2;
>> -       }
>> -
>
> I'm obviously missing some context here.  The driver doesn't seem to
> manage the clocks anymore.  What code does now?

hwmod layer is handling all clocks now.

<snip>

>> +
>>  static struct platform_driver omap2_mcspi_driver = {
>>        .driver = {
>> -               .name =         "omap2_mcspi",
>> -               .owner =        THIS_MODULE,
>> +               .name   = "omap2_mcspi",
>> +               .owner  = THIS_MODULE,
>> +               .pm     = &omap_mcspi_dev_pm_ops,
>
> nit: Unrelated whitespace changes.
>

Will correct this in next version.

---
Regards,
Govindraj.R
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RE: [PATCH 1/5] OMAP2420: McSPI: Add mcspi hwmod

[Kalliguddi, Hema]

Hi,
 

>-----Original Message-----
>From: linux-omap-owner@vger.kernel.org 
>[mailto:linux-omap-owner@vger.kernel.org] On Behalf Of 
>Varadarajan, Charulatha
>Sent: Friday, August 13, 2010 7:35 PM
>To: linux-omap@vger.kernel.org
>Cc: khilman@deeprootsystems.com; paul@pwsan.com; Cousson, 
>Benoit; tony@atomide.com; grant.likely@secretlab.ca; 
>dbrownell@users.sourceforge.net; 
>spi-devel-general@lists.sourceforge.net; Nayak, Rajendra; 
>Basak, Partha; Varadarajan, Charulatha; Raja, Govindraj
>Subject: [PATCH 1/5] OMAP2420: McSPI: Add mcspi hwmod
>
>This patch updates the omap2420 hwmod data with the
>McSPI info.
>
>Signed-off-by: Charulatha V <charu@ti.com>
>Signed-off-by: Partha Basak <p-basak2@ti.com>
>Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
>---
> arch/arm/mach-omap2/omap_hwmod_2420_data.c |  138 
>++++++++++++++++++++++++++++
> 1 files changed, 138 insertions(+), 0 deletions(-)
>
>diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c 
>b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
>index 3cc768e..7d1a0ff 100644
>--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
>+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
>@@ -15,6 +15,7 @@
> #include <mach/irqs.h>
> #include <plat/cpu.h>
> #include <plat/dma.h>
>+#include <plat/mcspi.h>
> 
> #include "omap_hwmod_common_data.h"
> 
>@@ -33,6 +34,8 @@ static struct omap_hwmod omap2420_mpu_hwmod;
> static struct omap_hwmod omap2420_iva_hwmod;
> static struct omap_hwmod omap2420_l3_main_hwmod;
> static struct omap_hwmod omap2420_l4_core_hwmod;
>+static struct omap_hwmod omap2420_mcspi1_hwmod;
>+static struct omap_hwmod omap2420_mcspi2_hwmod;
> 
> /* L3 -> L4_CORE interface */
> static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
>@@ -72,6 +75,42 @@ static struct omap_hwmod omap2420_l3_main_hwmod = {
> 
> static struct omap_hwmod omap2420_l4_wkup_hwmod;
> 
>+/* L4 CORE -> MCSPI1 interface */
>+static struct omap_hwmod_addr_space omap2420_mcspi1_addr_space[] = {
>+	{
>+		.pa_start	= 0x48098000,
>+		.pa_end		= 0x480980ff,
>+		.flags		= ADDR_TYPE_RT,
>+	},
>+};

Align all of them to one tab..

>+
>+static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = {
>+	.master		= &omap2420_l4_core_hwmod,
>+	.slave		= &omap2420_mcspi1_hwmod,
>+	.clk		= "mcspi1_ick",
>+	.addr		= omap2420_mcspi1_addr_space,
>+	.addr_cnt	= ARRAY_SIZE(omap2420_mcspi1_addr_space),
>+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>+};
>+
>+/* L4 CORE -> MCSPI2 interface */
>+static struct omap_hwmod_addr_space omap2420_mcspi2_addr_space[] = {
>+	{
>+		.pa_start	= 0x4809a000,
>+		.pa_end		= 0x4809a0ff,
>+		.flags		= ADDR_TYPE_RT,
>+	},
>+};
>+

Ditto align to one tab

>+static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = {
>+	.master		= &omap2420_l4_core_hwmod,
>+	.slave		= &omap2420_mcspi2_hwmod,
>+	.clk		= "mcspi2_ick",
>+	.addr		= omap2420_mcspi2_addr_space,
>+	.addr_cnt	= ARRAY_SIZE(omap2420_mcspi2_addr_space),
>+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
>+};
>+
> /* L4_CORE -> L4_WKUP interface */
> static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = {
> 	.master	= &omap2420_l4_core_hwmod,
>@@ -165,12 +204,111 @@ static struct omap_hwmod omap2420_iva_hwmod = {
> 	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420)
> };
> 
>+/* SPI common */
>+static struct omap_hwmod_class_sysconfig omap2420_mcspi_sysc = {
>+	.rev_offs	= 0x0000,
>+	.sysc_offs	= 0x0010,
>+	.syss_offs	= 0x0014,
>+	.sysc_flags	= (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
>+				SYSC_HAS_ENAWAKEUP | 
>SYSC_HAS_SOFTRESET |
>+				SYSC_HAS_AUTOIDLE),
>+	.idlemodes	= (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
>+	.sysc_fields    = &omap_hwmod_sysc_type1,
>+};
>+
>+static struct omap_hwmod_class omap2420_mcspi_class = {
>+	.name = "mcspi",
>+	.sysc = &omap2420_mcspi_sysc,
>+};
>+
>+/* SPI1 */
>+static struct omap_hwmod_irq_info omap2420_mcspi1_mpu_irqs[] = {
>+	{ .irq = INT_24XX_SPI1_IRQ }, /* 65 */
>+};
>+
>+static struct omap_hwmod_dma_info omap2420_mcspi1_sdma_reqs[] = {
>+	{ .name = "rx0", .dma_req = OMAP24XX_DMA_SPI1_RX0 }, /* 35 */
>+	{ .name = "rx1", .dma_req = OMAP24XX_DMA_SPI1_RX1 }, /* 37 */
>+	{ .name = "rx2", .dma_req = OMAP24XX_DMA_SPI1_RX2 }, /* 39 */
>+	{ .name = "rx3", .dma_req = OMAP24XX_DMA_SPI1_RX3 }, /* 41 */
>+	{ .name = "tx0", .dma_req = OMAP24XX_DMA_SPI1_TX0 }, /* 34 */
>+	{ .name = "tx1", .dma_req = OMAP24XX_DMA_SPI1_TX1 }, /* 36 */
>+	{ .name = "tx2", .dma_req = OMAP24XX_DMA_SPI1_TX2 }, /* 38 */
>+	{ .name = "tx3", .dma_req = OMAP24XX_DMA_SPI1_TX3 }, /* 40 */
>+};
>+
>+static struct omap_hwmod_ocp_if *omap2420_mcspi1_slaves[] = {
>+	&omap2420_l4_core__mcspi1,
>+};
>+
>+static struct omap_hwmod omap2420_mcspi1_hwmod = {
>+	.name		= "mcspi1_hwmod",
>+	.mpu_irqs	= omap2420_mcspi1_mpu_irqs,
>+	.mpu_irqs_cnt	= ARRAY_SIZE(omap2420_mcspi1_mpu_irqs),
>+	.sdma_reqs	= omap2420_mcspi1_sdma_reqs,
>+	.sdma_reqs_cnt	= ARRAY_SIZE(omap2420_mcspi1_sdma_reqs),
>+	.main_clk	= "mcspi1_fck",
>+	.prcm		= {
>+		.omap2 = {
>+			.module_offs = CORE_MOD,
>+			.prcm_reg_id = 1,
>+			.module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
>+			.idlest_reg_id = 1,
>+			.idlest_idle_bit = OMAP24XX_EN_MCSPI1_SHIFT,
>+		},
>+	},
>+	.slaves		= omap2420_mcspi1_slaves,
>+	.slaves_cnt	= ARRAY_SIZE(omap2420_mcspi1_slaves),
>+	.class		= &omap2420_mcspi_class,
>+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
>+};
>+
>+/* SPI2 */
>+static struct omap_hwmod_irq_info omap2420_mcspi2_mpu_irqs[] = {
>+	{ .irq = INT_24XX_SPI2_IRQ }, /* 66 */
>+};
>+
>+static struct omap_hwmod_dma_info omap2420_mcspi2_sdma_reqs[] = {
>+	{ .name = "rx0", .dma_req = OMAP24XX_DMA_SPI2_RX0 }, /* 43 */
>+	{ .name = "rx1", .dma_req = OMAP24XX_DMA_SPI2_RX1 }, /* 45 */
>+	{ .name = "tx0", .dma_req = OMAP24XX_DMA_SPI2_TX0 }, /* 42 */
>+	{ .name = "tx1", .dma_req = OMAP24XX_DMA_SPI2_TX1 }, /* 44 */
>+};
>+
>+static struct omap_hwmod_ocp_if *omap2420_mcspi2_slaves[] = {
>+	&omap2420_l4_core__mcspi2,
>+};
>+
>+static struct omap_hwmod omap2420_mcspi2_hwmod = {
>+	.name		= "mcspi2_hwmod",
>+	.mpu_irqs	= omap2420_mcspi2_mpu_irqs,
>+	.mpu_irqs_cnt	= ARRAY_SIZE(omap2420_mcspi2_mpu_irqs),
>+	.sdma_reqs	= omap2420_mcspi2_sdma_reqs,
>+	.sdma_reqs_cnt	= ARRAY_SIZE(omap2420_mcspi2_sdma_reqs),
>+	.main_clk	= "mcspi2_fck",
>+	.prcm		= {
>+		.omap2 = {
>+			.module_offs = CORE_MOD,
>+			.prcm_reg_id = 1,
>+			.module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
>+			.idlest_reg_id = 1,
>+			.idlest_idle_bit = OMAP24XX_EN_MCSPI2_SHIFT,
>+		},
>+	},
>+	.slaves		= omap2420_mcspi2_slaves,
>+	.slaves_cnt	= ARRAY_SIZE(omap2420_mcspi2_slaves),
>+	.class		= &omap2420_mcspi_class,
>+	.omap_chip	= OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
>+};
>+
> static __initdata struct omap_hwmod *omap2420_hwmods[] = {
> 	&omap2420_l3_main_hwmod,
> 	&omap2420_l4_core_hwmod,
> 	&omap2420_l4_wkup_hwmod,
> 	&omap2420_mpu_hwmod,
> 	&omap2420_iva_hwmod,
>+	&omap2420_mcspi1_hwmod,
>+	&omap2420_mcspi2_hwmod,
> 	NULL,
> };
> 
>-- 
>1.6.3.3
>
>--
>To unsubscribe from this list: send the line "unsubscribe 
>linux-omap" in
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>

RE: [PATCH 1/5] OMAP2420: McSPI: Add mcspi hwmod

[Varadarajan, Charulatha]

Hema,

> 
> 
> >-----Original Message-----
> >From: linux-omap-owner@vger.kernel.org
> >[mailto:linux-omap-owner@vger.kernel.org] On Behalf Of
> >Varadarajan, Charulatha
> >Sent: Friday, August 13, 2010 7:35 PM
> >To: linux-omap@vger.kernel.org
> >Cc: khilman@deeprootsystems.com; paul@pwsan.com; Cousson,
> >Benoit; tony@atomide.com; grant.likely@secretlab.ca;
> >dbrownell@users.sourceforge.net;
> >spi-devel-general@lists.sourceforge.net; Nayak, Rajendra;
> >Basak, Partha; Varadarajan, Charulatha; Raja, Govindraj
> >Subject: [PATCH 1/5] OMAP2420: McSPI: Add mcspi hwmod
> >
> >This patch updates the omap2420 hwmod data with the
> >McSPI info.
> >
> >Signed-off-by: Charulatha V <charu@ti.com>
> >Signed-off-by: Partha Basak <p-basak2@ti.com>
> >Signed-off-by: Govindraj.R <govindraj.raja@ti.com>
> >---
> > arch/arm/mach-omap2/omap_hwmod_2420_data.c |  138
> >++++++++++++++++++++++++++++
> > 1 files changed, 138 insertions(+), 0 deletions(-)
> >
> >diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
> >b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
> >index 3cc768e..7d1a0ff 100644
> >--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
> >+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
> >@@ -15,6 +15,7 @@
> > #include <mach/irqs.h>
> > #include <plat/cpu.h>
> > #include <plat/dma.h>
> >+#include <plat/mcspi.h>
> >
> > #include "omap_hwmod_common_data.h"
> >
> >@@ -33,6 +34,8 @@ static struct omap_hwmod omap2420_mpu_hwmod;
> > static struct omap_hwmod omap2420_iva_hwmod;
> > static struct omap_hwmod omap2420_l3_main_hwmod;
> > static struct omap_hwmod omap2420_l4_core_hwmod;
> >+static struct omap_hwmod omap2420_mcspi1_hwmod;
> >+static struct omap_hwmod omap2420_mcspi2_hwmod;
> >
> > /* L3 -> L4_CORE interface */
> > static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = {
> >@@ -72,6 +75,42 @@ static struct omap_hwmod omap2420_l3_main_hwmod = {
> >
> > static struct omap_hwmod omap2420_l4_wkup_hwmod;
> >
> >+/* L4 CORE -> MCSPI1 interface */
> >+static struct omap_hwmod_addr_space omap2420_mcspi1_addr_space[] = {
> >+	{
> >+		.pa_start	= 0x48098000,
> >+		.pa_end		= 0x480980ff,
> >+		.flags		= ADDR_TYPE_RT,
> >+	},
> >+};
> 
> Align all of them to one tab..

If you apply the patch, you would see them aligned to one tab.
 
> 
> >+
> >+static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = {
> >+	.master		= &omap2420_l4_core_hwmod,
> >+	.slave		= &omap2420_mcspi1_hwmod,
> >+	.clk		= "mcspi1_ick",
> >+	.addr		= omap2420_mcspi1_addr_space,
> >+	.addr_cnt	= ARRAY_SIZE(omap2420_mcspi1_addr_space),
> >+	.user		= OCP_USER_MPU | OCP_USER_SDMA,
> >+};
> >+
> >+/* L4 CORE -> MCSPI2 interface */
> >+static struct omap_hwmod_addr_space omap2420_mcspi2_addr_space[] = {
> >+	{
> >+		.pa_start	= 0x4809a000,
> >+		.pa_end		= 0x4809a0ff,
> >+		.flags		= ADDR_TYPE_RT,
> >+	},
> >+};
> >+
> 
> Ditto align to one tab

Ditto :)

> 
> >+static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = {
> >+	.master		= &omap2420_l4_core_hwmod,
.
.
[snip]
.
.

Re: [PATCH 0/5] OMAP: McSPI: Implement McSPI in HWMOD way

[Grant Likely]

On Fri, Aug 13, 2010 at 8:05 AM, Charulatha V <charu@ti.com> wrote:
> This patch series implements McSPI Module in HWMOD FW way
> and use the runtime PM layer.

Hi Charulatha,

I'll go through and review the patches, but I'm unfamiliar with HWMOD.
 Is there a description of HWMOD that you can point me at?

Thanks,
g.

>
> This patch series is created on "origin/pm-wip/hwmods-omap4" with
> McSPI slave mode patches (url given below) on top of it.
> https://patchwork.kernel.org/patch/79677/
> Updated McSPI slave mode patches will be posted shortly by Govindraj.
> McSPI slave mode patches were already discussed on open source mailing
> list and they are almost towards the end of final rebased version.
> Hence hwmod patches are created on top of McSPI slave mode patch
> series to avoid major rework later on.
>
> Benoit Cousson (1):
>  OMAP4 HWMOD: Add mcspi hwmods.
>
> Charulatha V (3):
>  OMAP2420: McSPI: Add mcspi hwmod
>  OMAP2430 : McSPI: Add mcspi hwmod data
>  OMAP3 HWMOD: Add mcspi hwmods.
>
> Govindraj.R (1):
>  OMAP McSPI: Adapt McSPI driver to use omap hwmod
>
>  arch/arm/mach-omap2/clock3xxx_data.c       |    4 +
>  arch/arm/mach-omap2/devices.c              |  233 +++++++++---------------
>  arch/arm/mach-omap2/omap_hwmod_2420_data.c |  138 ++++++++++++++
>  arch/arm/mach-omap2/omap_hwmod_2430_data.c |  196 ++++++++++++++++++++
>  arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |  252 +++++++++++++++++++++++++
>  arch/arm/mach-omap2/omap_hwmod_44xx_data.c |  244 +++++++++++++++++++++++++
>  arch/arm/plat-omap/include/plat/mcspi.h    |   27 +++
>  drivers/spi/omap2_mcspi.c                  |  273 +++++++++-------------------
>  8 files changed, 1034 insertions(+), 333 deletions(-)
>
>



-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.
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RE: [PATCH 0/5] OMAP: McSPI: Implement McSPI in HWMOD way

[Varadarajan, Charulatha]

> -----Original Message-----
> From: glikely@secretlab.ca [mailto:glikely@secretlab.ca] On Behalf Of
> Grant Likely
> Sent: Saturday, August 14, 2010 4:15 AM
> To: Varadarajan, Charulatha
> Cc: linux-omap@vger.kernel.org; khilman@deeprootsystems.com;
> paul@pwsan.com; Cousson, Benoit; tony@atomide.com;
> dbrownell@users.sourceforge.net; spi-devel-general@lists.sourceforge.net;
> Nayak, Rajendra; Basak, Partha; Raja, Govindraj
> Subject: Re: [PATCH 0/5] OMAP: McSPI: Implement McSPI in HWMOD way
> 
> On Fri, Aug 13, 2010 at 8:05 AM, Charulatha V <charu@ti.com> wrote:
> > This patch series implements McSPI Module in HWMOD FW way
> > and use the runtime PM layer.
> 
> Hi Charulatha,
> 
> I'll go through and review the patches, but I'm unfamiliar with HWMOD.
>  Is there a description of HWMOD that you can point me at?

The following link could be of some help:
http://omappedia.org/wiki/HWMOD#Steps_involved_in_HWMOD

> 
> Thanks,
> g.
> 
> >
> > This patch series is created on "origin/pm-wip/hwmods-omap4" with
> > McSPI slave mode patches (url given below) on top of it.
> > https://patchwork.kernel.org/patch/79677/
> > Updated McSPI slave mode patches will be posted shortly by Govindraj.
> > McSPI slave mode patches were already discussed on open source mailing
> > list and they are almost towards the end of final rebased version.
> > Hence hwmod patches are created on top of McSPI slave mode patch
> > series to avoid major rework later on.
> >
> > Benoit Cousson (1):
> >  OMAP4 HWMOD: Add mcspi hwmods.
> >
> > Charulatha V (3):
> >  OMAP2420: McSPI: Add mcspi hwmod
> >  OMAP2430 : McSPI: Add mcspi hwmod data
> >  OMAP3 HWMOD: Add mcspi hwmods.
> >
> > Govindraj.R (1):
> >  OMAP McSPI: Adapt McSPI driver to use omap hwmod
> >
> >  arch/arm/mach-omap2/clock3xxx_data.c       |    4 +
> >  arch/arm/mach-omap2/devices.c              |  233 +++++++++------------
> ---
> >  arch/arm/mach-omap2/omap_hwmod_2420_data.c |  138 ++++++++++++++
> >  arch/arm/mach-omap2/omap_hwmod_2430_data.c |  196 ++++++++++++++++++++
> >  arch/arm/mach-omap2/omap_hwmod_3xxx_data.c |  252
> +++++++++++++++++++++++++
> >  arch/arm/mach-omap2/omap_hwmod_44xx_data.c |  244
> +++++++++++++++++++++++++
> >  arch/arm/plat-omap/include/plat/mcspi.h    |   27 +++
> >  drivers/spi/omap2_mcspi.c                  |  273 +++++++++------------
> -------
> >  8 files changed, 1034 insertions(+), 333 deletions(-)
> >
> >
> 
> 
> 
> --
> Grant Likely, B.Sc., P.Eng.
> Secret Lab Technologies Ltd.
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Re: [PATCH 0/5] OMAP: McSPI: Implement McSPI in HWMOD way

[Kevin Hilman]

Grant Likely <grant.likely@secretlab.ca> writes:

> On Fri, Aug 13, 2010 at 8:05 AM, Charulatha V <charu@ti.com> wrote:
>> This patch series implements McSPI Module in HWMOD FW way
>> and use the runtime PM layer.
>
> Hi Charulatha,
>
> I'll go through and review the patches, but I'm unfamiliar with HWMOD.
> Is there a description of HWMOD that you can point me at?

Hi Grant,

If you want to skip my rambling, the source for omap_hwmod is in mainline:

   arch/arm/mach-omap2/omap_hwmod.c
   arch/arm/plat-omap/include/plat/omap_hwmod.h

omap_hwmod is short for OMAP hardware module.  It is essentially a
central way of describing each IP block in an OMAP SoC, and the way they
are connected together to make an SoC.  An omap_hwmod for a given IP
block contains base address, IRQs, DMA channels etc. (as would a device
tree node) but also includes information on any master/slave interfaces
to model how IP blocks are connected on the SoC and many other details.
With my PM hat on, the most important part of an omap_hwmod is that it
also defines lots of details about the PM register and capabilities of a
given IP block.

Part of omap_hwmod is the data (which is now auto-generated for current
and future OMAPs), and the other part is the code.  In the code, the
omap_hwmod layer also provides an API so that functionality common to
all IP blocks (clock management, power states, idle modes, resets, etc.)
can be handled in a common way.

Drivers do not interact directly with omap_hwmod and it is considered
OMAP core code.  In other threads, you've seen a little bit of the
omap_device layer.  The omap_device layer encapsulates the omap_hwmod
layer.  An omap_device consists of at least one (but possibly several)
omap_hwmods.  Drivers do not interact directly with omap_device either,
but instead use runtime PM to trigger the custom bus code which would
call omap_device_* which in turn would call into omap_hwmod_*.  Also,
from the omap_hwmod data, platform_devices are generated (including
resources) so drivers get the common data in standard ways.

So, with that background, we're going through some major work in several
OMAP drivers to convert them to work across multiple OMAP SoCs (OMAP2, 3
and 4.)  To make the drivers more general, this means adding the hwmod
data for the device IP, building the omap_device for the device and
converting the driver to use runtime PM instead of direct clock management.

You see all these changes happening in a single patch because the are
quite dependent on one another.  This driver seems to have needed pretty
significant cleanup as well, so I agree that this last patch should be
broken up into parts.  

I think it could be broken up into at least two parts:
cleanup/restructure work to handle more data coming via platform_data,
followed by the conversion to runtime PM.

Kevin

Re: [PATCH 0/5] OMAP: McSPI: Implement McSPI in HWMOD way

[Grant Likely]

On Thu, Aug 19, 2010 at 05:56:43PM -0700, Kevin Hilman wrote:
> Grant Likely <grant.likely@secretlab.ca> writes:
> 
> > On Fri, Aug 13, 2010 at 8:05 AM, Charulatha V <charu@ti.com> wrote:
> >> This patch series implements McSPI Module in HWMOD FW way
> >> and use the runtime PM layer.
> >
> > Hi Charulatha,
> >
> > I'll go through and review the patches, but I'm unfamiliar with HWMOD.
> > Is there a description of HWMOD that you can point me at?
> 
> Hi Grant,
> 
> If you want to skip my rambling, the source for omap_hwmod is in mainline:
> 
>    arch/arm/mach-omap2/omap_hwmod.c
>    arch/arm/plat-omap/include/plat/omap_hwmod.h
> 
> omap_hwmod is short for OMAP hardware module.  It is essentially a
> central way of describing each IP block in an OMAP SoC, and the way they
> are connected together to make an SoC.  An omap_hwmod for a given IP
> block contains base address, IRQs, DMA channels etc. (as would a device
> tree node) but also includes information on any master/slave interfaces
> to model how IP blocks are connected on the SoC and many other details.

Hi Kevin,

This seems to be a common issue for more than just OMAP SoCs, and I've
seen a number of approaches to solving it; both internal to the kernel
(AMBA bus, HWMOD, ad-hoc pdata, etc) and via external data (FDT, SFI).
It doesn't seem like there is a lot of cross-pollination going on
either.

I'm thinking about scheduling a discussion in the embedded
microconference at Plumbers to talk about the encoding and handling of
SoC and machine interconnection data.  There should be enough examples
now that we can agree on some common infrastructure for handling these
kinds of things without inventing new infrastructure from scratch for
each SoC family.  What do you think?

[...]
> You see all these changes happening in a single patch because the are
> quite dependent on one another.  This driver seems to have needed pretty
> significant cleanup as well, so I agree that this last patch should be
> broken up into parts.  
> 
> I think it could be broken up into at least two parts:
> cleanup/restructure work to handle more data coming via platform_data,
> followed by the conversion to runtime PM.

Yes, I like to see refactoring work separated from functional changes
as much as possible.

g.

Re: [PATCH 0/5] OMAP: McSPI: Implement McSPI in HWMOD way

[Kevin Hilman]

Grant Likely <grant.likely@secretlab.ca> writes:

> On Thu, Aug 19, 2010 at 05:56:43PM -0700, Kevin Hilman wrote:
>> Grant Likely <grant.likely@secretlab.ca> writes:
>> 
>> > On Fri, Aug 13, 2010 at 8:05 AM, Charulatha V <charu@ti.com> wrote:
>> >> This patch series implements McSPI Module in HWMOD FW way
>> >> and use the runtime PM layer.
>> >
>> > Hi Charulatha,
>> >
>> > I'll go through and review the patches, but I'm unfamiliar with HWMOD.
>> > Is there a description of HWMOD that you can point me at?
>> 
>> Hi Grant,
>> 
>> If you want to skip my rambling, the source for omap_hwmod is in mainline:
>> 
>>    arch/arm/mach-omap2/omap_hwmod.c
>>    arch/arm/plat-omap/include/plat/omap_hwmod.h
>> 
>> omap_hwmod is short for OMAP hardware module.  It is essentially a
>> central way of describing each IP block in an OMAP SoC, and the way they
>> are connected together to make an SoC.  An omap_hwmod for a given IP
>> block contains base address, IRQs, DMA channels etc. (as would a device
>> tree node) but also includes information on any master/slave interfaces
>> to model how IP blocks are connected on the SoC and many other details.
>
> Hi Kevin,
>
> This seems to be a common issue for more than just OMAP SoCs, and I've
> seen a number of approaches to solving it; both internal to the kernel
> (AMBA bus, HWMOD, ad-hoc pdata, etc) and via external data (FDT, SFI).
> It doesn't seem like there is a lot of cross-pollination going on
> either.
>
> I'm thinking about scheduling a discussion in the embedded
> microconference at Plumbers to talk about the encoding and handling of
> SoC and machine interconnection data.  There should be enough examples
> now that we can agree on some common infrastructure for handling these
> kinds of things without inventing new infrastructure from scratch for
> each SoC family.  What do you think?

The discussion is certainly worthwhile, and I would love to participate.
As with everything, the devil is in the details.  And I'm afraid that
while at a high-level, describing one SoC or another might look similar,
when it gets down to the details, there will be *tons* of things that
are unique to each SoC.

For example, if you look into the omap_hwmod code and data structures,
you will see that most of the stuff described in there is extremly OMAP
specific (mostly clock/power related), and only ever visible to OMAP
specific code.

The question to me is what is the end goal of having a common
infrastructure to model SoC-unique features that are only touched by
SoC-specific code?  And who would maintain such an infrastructure?

Personally, I would rather keep focus on infrastructure efforts that
would actually be common across SoCs (common kernel binaries, etc.) and
visible to drivers (PM frameworks like CPUidle, runtime PM, etc.)  All
the gory SoC specifics should be hidden by the SoC-specific
implementations of these frameworks, and maintained by folks who really
understand the SoC.  So, all that that I question the need for a common
framework to define SoC internals.

That being said, I'm totally in favor of the direction that the FDT is
going in, and very much support the ways it will unify much of the
hardware description.  However, I think it has limits.  And at least for
OMAP, I envision using the device tree to describe connections at the
board level, but continuing to use omap_hwmod to describe the SoC
itself.

Kevin

Re: [PATCH 0/5] OMAP: McSPI: Implement McSPI in HWMOD way

[Grant Likely]

On Fri, Sep 10, 2010 at 03:15:35PM -0700, Kevin Hilman wrote:
> Grant Likely <grant.likely@secretlab.ca> writes:
> 
> > On Thu, Aug 19, 2010 at 05:56:43PM -0700, Kevin Hilman wrote:
> >> Grant Likely <grant.likely@secretlab.ca> writes:
> >> 
> >> > On Fri, Aug 13, 2010 at 8:05 AM, Charulatha V <charu@ti.com> wrote:
> >> >> This patch series implements McSPI Module in HWMOD FW way
> >> >> and use the runtime PM layer.
> >> >
> >> > Hi Charulatha,
> >> >
> >> > I'll go through and review the patches, but I'm unfamiliar with HWMOD.
> >> > Is there a description of HWMOD that you can point me at?
> >> 
> >> Hi Grant,
> >> 
> >> If you want to skip my rambling, the source for omap_hwmod is in mainline:
> >> 
> >>    arch/arm/mach-omap2/omap_hwmod.c
> >>    arch/arm/plat-omap/include/plat/omap_hwmod.h
> >> 
> >> omap_hwmod is short for OMAP hardware module.  It is essentially a
> >> central way of describing each IP block in an OMAP SoC, and the way they
> >> are connected together to make an SoC.  An omap_hwmod for a given IP
> >> block contains base address, IRQs, DMA channels etc. (as would a device
> >> tree node) but also includes information on any master/slave interfaces
> >> to model how IP blocks are connected on the SoC and many other details.
> >
> > Hi Kevin,
> >
> > This seems to be a common issue for more than just OMAP SoCs, and I've
> > seen a number of approaches to solving it; both internal to the kernel
> > (AMBA bus, HWMOD, ad-hoc pdata, etc) and via external data (FDT, SFI).
> > It doesn't seem like there is a lot of cross-pollination going on
> > either.
> >
> > I'm thinking about scheduling a discussion in the embedded
> > microconference at Plumbers to talk about the encoding and handling of
> > SoC and machine interconnection data.  There should be enough examples
> > now that we can agree on some common infrastructure for handling these
> > kinds of things without inventing new infrastructure from scratch for
> > each SoC family.  What do you think?
> 
> The discussion is certainly worthwhile, and I would love to participate.
> As with everything, the devil is in the details.  And I'm afraid that
> while at a high-level, describing one SoC or another might look similar,
> when it gets down to the details, there will be *tons* of things that
> are unique to each SoC.
> 
> For example, if you look into the omap_hwmod code and data structures,
> you will see that most of the stuff described in there is extremly OMAP
> specific (mostly clock/power related), and only ever visible to OMAP
> specific code.
> 
> The question to me is what is the end goal of having a common
> infrastructure to model SoC-unique features that are only touched by
> SoC-specific code?  And who would maintain such an infrastructure?

You're right, there is no point generalizing stuff that is truly SoC
specific.  I'm interested in identifying the bits and techniques that
are useful to other SoCs and architectures.

I'm happy to maintain any infrastructure if need be.

> Personally, I would rather keep focus on infrastructure efforts that
> would actually be common across SoCs (common kernel binaries, etc.) and
> visible to drivers (PM frameworks like CPUidle, runtime PM, etc.)  All
> the gory SoC specifics should be hidden by the SoC-specific
> implementations of these frameworks, and maintained by folks who really
> understand the SoC.

Yes, I agree.

> So, all that that I question the need for a common
> framework to define SoC internals.

Well for an example, we've talked a lot about the platform_bus_type.
Associativity between devices (parent/child) is a core part of the
Linux device model, and it is a common problem to know what the device
topology is for handing init and PM ordering.  I'd like to know what
topology you need to describe for the OMAP SoCs.  Does the Linux
driver model topology provide any of the information you need, or does
OMAP HWMOD implement its own topology infrastructure?  What is missing
from the driver model that requires a lookaside to HWMOD to obtain the
SoC topology?

I'm certainly not arguing that all SoC specific infrastructure needs
to be generalized.  Rather I want to find common features and
techniques that can be used by SoC specific code.

> That being said, I'm totally in favor of the direction that the FDT is
> going in, and very much support the ways it will unify much of the
> hardware description.  However, I think it has limits.

Of course it does; it's only a data structure!  :-D  It can encode
data about the hardware; but it cannot describe operating system
behaviour.

> And at least for
> OMAP, I envision using the device tree to describe connections at the
> board level, but continuing to use omap_hwmod to describe the SoC
> itself.

At the very least, the structure of the SoC probably needs to be
reflected in the device tree.  A lot of the time nodes for internal
SoC devices end up becoming 'handles' to describe attachments to
external hardware.  ie. i2c device nodes hanging off an SoC i2c
controller, or interrupt connections.  Since those nodes have to be
there anyway, it is useful (and less confusing) to have them reflect
the actual internal structure of the SoC.

>From my brief look, it appears that omap_hwmod consists of two parts;
a set of data structures and code that define the behaviour of the
kernel, and the per-SoC data that populates the tables.  There is no
doubt that the structure definitions and support code are part of the
kernel.  They are kernel implementation details.

The data could either be kept in the kernel, or be populated from the
device tree.  My *preference* is certainly to encode data about the
SoC into the device tree, mostly because I've seen it as valuable on
the other SoCs I've worked on (it is convenient to have all the data
in one place, and it results in high associativity between related
information.  ie. don't need to do use odd methods like
spi_register_board_info() to associate devices with the bus they are
attached to).

However, it doesn't have to be implement that way so long as there is
a method to reliably associate device tree nodes with data already
encoded into the kernel.

anyway...

What I'm thinking about doing at the embedded microconf is asking a
few people (you included) to speak briefly about what they are doing
to describe their platforms, and see if any common functionality
bubbles to the top.  I think it is to easy to get focused on our own
problem domain and miss that others are working on very similar
problems in isolation.

g.

Re: [PATCH 0/5] OMAP: McSPI: Implement McSPI in HWMOD way

[Kevin Hilman]

Grant Likely <grant.likely@secretlab.ca> writes:

[...]

> What I'm thinking about doing at the embedded microconf is asking a
> few people (you included) to speak briefly about what they are doing
> to describe their platforms, and see if any common functionality
> bubbles to the top.  

Sounds great.

> I think it is to easy to get focused on our own problem domain and
> miss that others are working on very similar problems in isolation.

Completely agree.

Looking forward to LPC.

Kevin