[PATCH 0/6] add spi support for i.MX51 in the existing spi_imx driver

[PATCH 0/6] add spi support for i.MX51 in the existing spi_imx driver

[Jason Wang]

Some explanations:

This patchset is to add SPI support in the existing spi_imx driver for
i.MX51 and add SPI relating stuffs for mx51_3ds board level.

i.MX51 has two eCSPI controllers and one CSPI controller, CSPI
controller is 100% compatible with the one of i.MX35, so we don't need
to add new functions for this CSPI, only bind it with i.MX35 together,
while eCSPI isn't compatible with existing controllers of i.MX
platforms, so i add new functions for these two eCSPIs in the existing
spi_imx driver.

If these patches pass review, the first patch 0001-xxx.patch should be
merged by Grant.likely; other patches(0002-0006) are based off
imx-for-2.6.37 and should be handled by Sascha.

On mx51_3ds board, there is a SPI NOR flash connected through eCSPI2,
i have validated this patchset using this SPI NOR flash, see results:
(bootlogs)
<snip>
m25p80 spi1.1: found sst25vf016b, expected m25p80
m25p80 spi1.1: sst25vf016b (2048 Kbytes)
spi_imx spi_imx.1: probed
<snip>
(target tty console)
# cat /proc/mtd
dev:    size   erasesize  name
mtd0: 00200000 00001000 "spi1.1"
# mtd_debug read /dev/mtd0 0 0x100 /a.txt
Copied 256 bytes from address 0x00000000 in flash to /a.txt
# hexdump a.txt 
0000000 0000 eb00 0b53 eb00 002c e28f 0c00 e890
0000010 a000 e08a b000 e08b 7001 e24a 000b e15a
0000020 0000 1a00 0b4b eb00 000f e8ba e018 e24f
0000030 0001 e313 f003 1047 ff13 e12f 3720 0000
0000040 3730 0000 3000 e3b0 4000 e3b0 5000 e3b0
0000050 6000 e3b0 2010 e252 0078 28a1 fffc 8aff
0000060 2e82 e1b0 0030 28a1 3000 4581 ff1e e12f
0000070 e004 e52d 7000 e10f 700f e3c7 6001 e287
0000080 f006 e12f 0001 e040 d000 e1a0 6002 e287
0000090 f006 e12f 0001 e040 d000 e1a0 6006 e287
00000a0 f006 e12f 0001 e040 d000 e1a0 6007 e287
00000b0 f006 e12f 0001 e040 d000 e1a0 600b e287
00000c0 f006 e12f 0001 e040 d000 e1a0 600f e287
00000d0 f006 e12f 0001 e040 d000 e1a0 6003 e287
00000e0 60c0 e3c6 f006 e12f f004 e49d f003 e320
00000f0 ff1e e12f 4001 e92d 0f11 ee11 0001 e380


Thanks,
Jason.

[PATCH 1/6] spi-imx: add CSPI and eCSPI support for i.MX51 MCU

[Jason Wang]

There are 3 SPI controllers on i.MX51, one is called CSPI and is
100% compatible with the one on i.MX35, the other two are called
eCSPI and are not compatible with existing controllers on other
i.MX platforms, here we add support of these three controllers in
the imx spi driver.

Signed-off-by: Jason Wang <jason77.wang@gmail.com>
---
 drivers/spi/spi_imx.c |  135 +++++++++++++++++++++++++++++++++++++++++++++++--
 1 files changed, 131 insertions(+), 4 deletions(-)

diff --git a/drivers/spi/spi_imx.c b/drivers/spi/spi_imx.c
index 7972e90..8d9c9da 100644
--- a/drivers/spi/spi_imx.c
+++ b/drivers/spi/spi_imx.c
@@ -155,6 +155,120 @@ static unsigned int spi_imx_clkdiv_2(unsigned int fin,
 	return 7;
 }
 
+/* MX51 eCSPI post divider */
+static unsigned int spi_imx_clkdiv_3(unsigned int fin,
+		unsigned int fspi)
+{
+	int i, div = 1;
+
+	for (i = 0; i < 15; i++) {
+		if (fspi * div >= fin)
+			return i;
+		div <<= 1;
+	}
+
+	return 15;
+}
+
+#define MX51_INTREG_TEEN		(1 << 0)
+#define MX51_INTREG_RREN		(1 << 3)
+
+#define MX51_CSPICTRL_ENABLE		(1 << 0)
+#define MX51_CSPICTRL_XCH		(1 << 2)
+
+#define MX51_CSPICTRL_BL_SHIFT		20
+#define MX51_CSPICTRL_CS_SHIFT		18
+#define MX51_CSPICTRL_DR_SHIFT		8
+#define MX51_CSPICTRL_MODE_SHIFT	4
+#define MX51_CSPICONF_PHA_SHIFT		0
+#define MX51_CSPICONF_POL_SHIFT		4
+#define MX51_CSPICONF_SSPOL_SHIFT	12
+#define MX51_CSPICONF_SSCTL_SHIFT	8
+
+#define MX51_CSPICTRL_CSMASK		0x3
+#define MX51_CSPIINT			0x10
+#define MX51_CSPICONF			0xC
+#define MX51_CSPISTATUS			0x18
+#define MX51_STATUS_RR			(1 << 3)
+
+#define MAX_CHIPSELECT_NUM 4
+
+static int get_chipselect(struct spi_imx_data *spi_imx,
+			  struct spi_imx_config *config)
+{
+	int i;
+
+	for (i = 0; i < MAX_CHIPSELECT_NUM; i++) {
+		if (config->cs == spi_imx->chipselect[i])
+			return i;
+	}
+
+	return -EINVAL;
+}
+static void mx51_intctrl(struct spi_imx_data *spi_imx, int enable)
+{
+	unsigned int val = 0;
+
+	if (enable & MXC_INT_TE)
+		val |= MX51_INTREG_TEEN;
+	if (enable & MXC_INT_RR)
+		val |= MX51_INTREG_RREN;
+
+	writel(val, spi_imx->base + MX51_CSPIINT);
+}
+
+static void mx51_trigger(struct spi_imx_data *spi_imx)
+{
+	unsigned int reg;
+
+	reg = readl(spi_imx->base + MXC_CSPICTRL);
+	reg |= MX51_CSPICTRL_XCH;
+	writel(reg, spi_imx->base + MXC_CSPICTRL);
+}
+
+static int mx51_config(struct spi_imx_data *spi_imx,
+		struct spi_imx_config *config)
+{
+	unsigned int config_reg = 0;
+	unsigned int ctrl_reg = MX51_CSPICTRL_ENABLE;
+	int chan;
+
+	chan = get_chipselect(spi_imx, config);
+	if (chan < 0)
+		return chan;
+	ctrl_reg |= (chan & MX51_CSPICTRL_CSMASK) << MX51_CSPICTRL_CS_SHIFT;
+	ctrl_reg |= (1 << (chan & MX51_CSPICTRL_CSMASK)) <<
+		MX51_CSPICTRL_MODE_SHIFT;
+	ctrl_reg |= spi_imx_clkdiv_3(spi_imx->spi_clk, config->speed_hz) <<
+		MX51_CSPICTRL_DR_SHIFT;
+
+	ctrl_reg |= (config->bpw - 1) << MX51_CSPICTRL_BL_SHIFT;
+
+
+	if (config->mode & SPI_CPHA)
+		config_reg |= (1 << (chan & MX51_CSPICTRL_CSMASK)) <<
+			MX51_CSPICONF_PHA_SHIFT;
+	if (config->mode & SPI_CPOL)
+		config_reg |= (1 << (chan & MX51_CSPICTRL_CSMASK)) <<
+			MX51_CSPICONF_POL_SHIFT;
+	if (config->mode & SPI_CS_HIGH)
+		config_reg |= (1 << (chan & MX51_CSPICTRL_CSMASK)) <<
+			MX51_CSPICONF_SSPOL_SHIFT;
+
+	config_reg |= (1 << (chan & MX51_CSPICTRL_CSMASK)) <<
+		MX51_CSPICONF_SSCTL_SHIFT;
+
+	writel(ctrl_reg, spi_imx->base + MXC_CSPICTRL);
+	writel(config_reg, spi_imx->base + MX51_CSPICONF);
+
+	return 0;
+}
+
+static int mx51_rx_available(struct spi_imx_data *spi_imx)
+{
+	return readl(spi_imx->base + MX51_CSPISTATUS) & MX51_STATUS_RR;
+}
+
 #define MX31_INTREG_TEEN	(1 << 0)
 #define MX31_INTREG_RREN	(1 << 3)
 
@@ -209,7 +323,7 @@ static int mx31_config(struct spi_imx_data *spi_imx,
 
 	if (cpu_is_mx31())
 		reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
-	else if (cpu_is_mx25() || cpu_is_mx35()) {
+	else if (cpu_is_mx25() || cpu_is_mx35() || cpu_is_mx51()) {
 		reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
 		reg |= MX31_CSPICTRL_SSCTL;
 	}
@@ -223,7 +337,7 @@ static int mx31_config(struct spi_imx_data *spi_imx,
 	if (config->cs < 0) {
 		if (cpu_is_mx31())
 			reg |= (config->cs + 32) << MX31_CSPICTRL_CS_SHIFT;
-		else if (cpu_is_mx25() || cpu_is_mx35())
+		else if (cpu_is_mx25() || cpu_is_mx35() || cpu_is_mx51())
 			reg |= (config->cs + 32) << MX35_CSPICTRL_CS_SHIFT;
 	}
 
@@ -567,7 +681,14 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
 		goto out_iounmap;
 	}
 
-	if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35()) {
+	/* i.MX51 has two eCSPI and one CSPI controllers, eCSPI controllers are
+	 * not compatible with existing SPI controllers on other i.MX platforms,
+	 * while CSPI controller is 100% compatible with the one on the i.MX35.
+	 * We set the platform device id to 2 for this CSPI at i.MX51 board init
+	 * level to distinguish it from two eCSPI controllers.
+	 */
+	if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35() ||
+	    (cpu_is_mx51() && (pdev->id == 2))) {
 		spi_imx->intctrl = mx31_intctrl;
 		spi_imx->config = mx31_config;
 		spi_imx->trigger = mx31_trigger;
@@ -582,6 +703,11 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
 		spi_imx->config = mx1_config;
 		spi_imx->trigger = mx1_trigger;
 		spi_imx->rx_available = mx1_rx_available;
+	} else if (cpu_is_mx51()) {
+		spi_imx->intctrl = mx51_intctrl;
+		spi_imx->config = mx51_config;
+		spi_imx->trigger = mx51_trigger;
+		spi_imx->rx_available = mx51_rx_available;
 	} else
 		BUG();
 
@@ -599,7 +725,8 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
 		writel(1, spi_imx->base + MXC_RESET);
 
 	/* drain receive buffer */
-	if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35())
+	if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35() ||
+	    (cpu_is_mx51() && (pdev->id == 2)))
 		while (readl(spi_imx->base + MX3_CSPISTAT) & MX3_CSPISTAT_RR)
 			readl(spi_imx->base + MXC_CSPIRXDATA);
 
-- 
1.5.6.5

[PATCH 2/6] i.MX5/clock: add eCSPI and CSPI clock definitions

[Jason Wang]

i.MX51 has two eCSPI and one CSPI controllers, now add clock
definitions and registrations for these controllers.

Signed-off-by: Jason Wang <jason77.wang@gmail.com>
---
 arch/arm/mach-mx5/clock-mx51.c |   79 ++++++++++++++++++++++++++++++++++++++++
 1 files changed, 79 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c
index 6af69de..217c3f3 100644
--- a/arch/arm/mach-mx5/clock-mx51.c
+++ b/arch/arm/mach-mx5/clock-mx51.c
@@ -38,6 +38,7 @@ static struct clk periph_apm_clk;
 static struct clk ahb_clk;
 static struct clk ipg_clk;
 static struct clk usboh3_clk;
+static struct clk spba_clk;
 
 #define MAX_DPLL_WAIT_TRIES	1000 /* 1000 * udelay(1) = 1ms */
 
@@ -52,6 +53,18 @@ static int _clk_ccgr_enable(struct clk *clk)
 	return 0;
 }
 
+static int _clk_ccgr_enable_inrun(struct clk *clk)
+{
+	u32 reg;
+
+	reg = __raw_readl(clk->enable_reg);
+	reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
+	reg |= MXC_CCM_CCGRx_MOD_IDLE << clk->enable_shift;
+	__raw_writel(reg, clk->enable_reg);
+
+	return 0;
+}
+
 static void _clk_ccgr_disable(struct clk *clk)
 {
 	u32 reg;
@@ -762,6 +775,61 @@ static struct clk kpp_clk = {
 	.id = 0,
 };
 
+/* eCSPI */
+static unsigned long _clk_ecspi_getrate(struct clk *clk)
+{
+	u32 reg, prediv, podf;
+	unsigned long ret;
+
+	reg = __raw_readl(MXC_CCM_CSCDR2);
+	prediv = ((reg & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) >>
+		  MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET) + 1;
+	if (prediv == 1)
+		BUG();
+	podf = ((reg & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) >>
+		MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET) + 1;
+
+	ret = clk_get_rate(clk->parent) / (prediv * podf);
+	return ret;
+}
+
+static int _clk_ecspi_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg, mux;
+
+	mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
+		       &lp_apm_clk);
+	reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK;
+	reg |= mux << MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
+	__raw_writel(reg, MXC_CCM_CSCMR1);
+
+	return 0;
+}
+
+static struct clk ecspi_main_clk = {
+	.parent = &pll3_sw_clk,
+	.get_rate = _clk_ecspi_getrate,
+	.set_parent = _clk_ecspi_set_parent,
+};
+
+static struct clk ecspi1_ipg_clk = {
+	.parent = &ipg_clk,
+	.secondary = &spba_clk,
+	.enable_reg = MXC_CCM_CCGR4,
+	.enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
+	.enable = _clk_ccgr_enable_inrun,
+	.disable = _clk_ccgr_disable,
+};
+
+static struct clk ecspi2_ipg_clk = {
+	.parent = &ipg_clk,
+	.secondary = &aips_tz2_clk,
+	.enable_reg = MXC_CCM_CCGR4,
+	.enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
+	.enable = _clk_ccgr_enable_inrun,
+	.disable = _clk_ccgr_disable,
+};
+
 #define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s)	\
 	static struct clk name = {			\
 		.id		= i,			\
@@ -814,6 +882,14 @@ DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
 DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
 	NULL,  NULL, &ipg_clk, NULL);
 
+/* eCSPI & CSPI */
+DEFINE_CLOCK(cspi1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG10_OFFSET,
+	NULL, NULL, &ecspi_main_clk, &ecspi1_ipg_clk);
+DEFINE_CLOCK(cspi2_clk, 1, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG12_OFFSET,
+	NULL, NULL, &ecspi_main_clk, &ecspi2_ipg_clk);
+DEFINE_CLOCK(cspi3_clk, 2, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG13_OFFSET,
+	NULL, NULL, &ipg_clk, NULL);
+
 #define _REGISTER_CLOCK(d, n, c) \
        { \
 		.dev_id = d, \
@@ -837,6 +913,9 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
 	_REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
 	_REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk)
+	_REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
+	_REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
+	_REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk)
 };
 
 static void clk_tree_init(void)
-- 
1.5.6.5

[PATCH 3/6] mx5: add support to dynamically register spi_imx devices (imx51 3ds)

[Jason Wang]

Signed-off-by: Jason Wang <jason77.wang@gmail.com>
---
 arch/arm/mach-mx5/Kconfig         |    1 +
 arch/arm/mach-mx5/devices-imx51.h |   20 ++++++++++++++++++++
 2 files changed, 21 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-mx5/devices-imx51.h

diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index 0848db5..898fb47 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -18,6 +18,7 @@ config MACH_MX51_BABBAGE
 config MACH_MX51_3DS
 	bool "Support MX51PDK (3DS)"
 	select MXC_DEBUG_BOARD
+	select IMX_HAVE_PLATFORM_SPI_IMX
 	help
 	  Include support for MX51PDK (3DS) platform. This includes specific
 	  configurations for the board and its peripherals.
diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h
new file mode 100644
index 0000000..d04c7eb
--- /dev/null
+++ b/arch/arm/mach-mx5/devices-imx51.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (C) 2010 Jason Wang <jason77.wang@gmail.com>
+ *
+ * based on mach-mx3/devices-imx35.h which is
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx51.h>
+#include <mach/devices-common.h>
+
+#define imx51_add_spi_imx0(pdata)	\
+	imx_add_spi_imx(0, MX51_CSPI1_BASE_ADDR, SZ_4K, MX51_MXC_INT_CSPI1, pdata)
+#define imx51_add_spi_imx1(pdata)	\
+	imx_add_spi_imx(1, MX51_CSPI2_BASE_ADDR, SZ_4K, MX51_MXC_INT_CSPI2, pdata)
+#define imx51_add_spi_imx2(pdata)	\
+	imx_add_spi_imx(1, MX51_CSPI3_BASE_ADDR, SZ_4K, MX51_MXC_INT_CSPI, pdata)
-- 
1.5.6.5

[PATCH 4/6] mx5/iomux: add iomux definitions for eCSPI2 on the imx51_3ds board

[Jason Wang]

On the imx51_3ds board, eCSPI2 is connected to a SPI NOR flash,
now add iomux definitions for those used pins.

Signed-off-by: Jason Wang <jason77.wang@gmail.com>
---
 arch/arm/plat-mxc/include/mach/iomux-mx51.h |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index 0d77be3..d0ef881 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -45,6 +45,8 @@ typedef enum iomux_config {
 				PAD_CTL_PKE | PAD_CTL_HYS)
 #define MX51_GPIO_PAD_CTRL		(PAD_CTL_DSE_HIGH | PAD_CTL_PKE | \
 				PAD_CTL_SRE_FAST)
+#define MX51_ECSPI_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
+				PAD_CTL_SRE_FAST)
 
 #define MX51_PAD_CTRL_1	(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
 					PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_HYS)
@@ -139,8 +141,10 @@ typedef enum iomux_config {
 #define MX51_PAD_NANDF_RB0__GPIO_3_8            IOMUX_PAD(0x4F8, 0x11C, 3, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_RB1__GPIO_3_9            IOMUX_PAD(0x4FC, 0x120, 3, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_RB2__GPIO_3_10           IOMUX_PAD(0x500, 0x124, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK         IOMUX_PAD(0x500, 0x124, 2, 0x0,   0, MX51_ECSPI_PAD_CTRL)
 #define MX51_PAD_NANDF_RB2__FEC_COL		IOMUX_PAD(0x500, 0x124, 1, 0x0,   0, MX51_PAD_CTRL_2)
 #define MX51_PAD_NANDF_RB3__GPIO_3_11           IOMUX_PAD(0x504, 0x128, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB3__ECSPI2_MISO         IOMUX_PAD(0x504, 0x128, 2, 0x0,   0, MX51_ECSPI_PAD_CTRL)
 #define MX51_PAD_NANDF_RB3__FEC_RXCLK		IOMUX_PAD(0x504, 0x128, 1, 0x0,   0, MX51_PAD_CTRL_2)
 #define MX51_PAD_NANDF_RB6__FEC_RDAT0		IOMUX_PAD(0x5DC, 0x134, 1, 0x0,   0, MX51_PAD_CTRL_4)
 #define MX51_PAD_NANDF_RB7__FEC_TDAT0		IOMUX_PAD(0x5E0, 0x138, 1, 0x0,   0, MX51_PAD_CTRL_5)
@@ -162,6 +166,7 @@ typedef enum iomux_config {
 #define MX51_PAD_NANDF_RDY_INT__GPIO_3_24       IOMUX_PAD(0x538, 0x150, 3, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK	IOMUX_PAD(0x538, 0x150, 1, 0x0,   0, MX51_PAD_CTRL_4)
 #define MX51_PAD_NANDF_D15__GPIO_3_25           IOMUX_PAD(0x53C, 0x154, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D15__ECSPI2_MOSI         IOMUX_PAD(0x53C, 0x154, 2, 0x0,   0, MX51_ECSPI_PAD_CTRL)
 #define MX51_PAD_NANDF_D14__GPIO_3_26           IOMUX_PAD(0x540, 0x158, 3, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_D13__GPIO_3_27           IOMUX_PAD(0x544, 0x15C, 3, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_D12__GPIO_3_28           IOMUX_PAD(0x548, 0x160, 3, 0x0,   0, NO_PAD_CTRL)
-- 
1.5.6.5

[PATCH 5/6] mx51_3ds: add eCSPI2 support on the imx51_3ds board

[Jason Wang]

Add platform data for eCSPI2 and register it through spi_imx dynamical
register interface.

Signed-off-by: Jason Wang <jason77.wang@gmail.com>
---
 arch/arm/mach-mx5/board-mx51_3ds.c |   20 ++++++++++++++++++++
 1 files changed, 20 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
index f95c2fd..0cf4e14 100644
--- a/arch/arm/mach-mx5/board-mx51_3ds.c
+++ b/arch/arm/mach-mx5/board-mx51_3ds.c
@@ -24,9 +24,11 @@
 #include <mach/imx-uart.h>
 #include <mach/3ds_debugboard.h>
 
+#include "devices-imx51.h"
 #include "devices.h"
 
 #define EXPIO_PARENT_INT	(MXC_INTERNAL_IRQS + GPIO_PORTA + 6)
+#define MX51_3DS_ECSPI2_CS	(GPIO_PORTC + 28)
 
 static struct pad_desc mx51_3ds_pads[] = {
 	/* UART1 */
@@ -61,6 +63,12 @@ static struct pad_desc mx51_3ds_pads[] = {
 	MX51_PAD_KEY_COL3__KEY_COL3,
 	MX51_PAD_KEY_COL4__KEY_COL4,
 	MX51_PAD_KEY_COL5__KEY_COL5,
+
+	/* eCSPI2 */
+	MX51_PAD_NANDF_RB2__ECSPI2_SCLK,
+	MX51_PAD_NANDF_RB3__ECSPI2_MISO,
+	MX51_PAD_NANDF_D15__ECSPI2_MOSI,
+	MX51_PAD_NANDF_D12__GPIO_3_28,
 };
 
 /* Serial ports */
@@ -127,6 +135,16 @@ static inline void mxc_init_keypad(void)
 }
 #endif
 
+static int mx51_3ds_spi2_cs[] = {
+	MXC_SPI_CS(0),
+	MX51_3DS_ECSPI2_CS,
+};
+
+static struct spi_imx_master mx51_3ds_spi2_pdata = {
+	.chipselect	= mx51_3ds_spi2_cs,
+	.num_chipselect	= ARRAY_SIZE(mx51_3ds_spi2_cs),
+};
+
 /*
  * Board specific initialization.
  */
@@ -136,6 +154,8 @@ static void __init mxc_board_init(void)
 					ARRAY_SIZE(mx51_3ds_pads));
 	mxc_init_imx_uart();
 
+	imx51_add_spi_imx1(&mx51_3ds_spi2_pdata);
+
 	if (mxc_expio_init(MX51_CS5_BASE_ADDR, EXPIO_PARENT_INT))
 		printk(KERN_WARNING "Init of the debugboard failed, all "
 				    "devices on the board are unusable.\n");
-- 
1.5.6.5

[PATCH 6/6] mx51_3ds: add SPI NOR flash in the board init stage

[Jason Wang]

A 2M bytes SPI NOR flash(sst25vf016b) is soldered on the mx51_3ds
board, Now add registration for it in the board init stage.

Signed-off-by: Jason Wang <jason77.wang@gmail.com>
---
 arch/arm/mach-mx5/board-mx51_3ds.c |   13 +++++++++++++
 1 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
index 0cf4e14..8f1631d 100644
--- a/arch/arm/mach-mx5/board-mx51_3ds.c
+++ b/arch/arm/mach-mx5/board-mx51_3ds.c
@@ -13,6 +13,7 @@
 #include <linux/irq.h>
 #include <linux/platform_device.h>
 #include <linux/input/matrix_keypad.h>
+#include <linux/spi/spi.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -145,6 +146,16 @@ static struct spi_imx_master mx51_3ds_spi2_pdata = {
 	.num_chipselect	= ARRAY_SIZE(mx51_3ds_spi2_cs),
 };
 
+static struct spi_board_info mx51_3ds_spi_nor_device[] = {
+	{
+	 .modalias = "m25p80",
+	 .max_speed_hz = 25000000,	/* max spi clock (SCK) speed in HZ */
+	 .bus_num = 1,
+	 .chip_select = 1,
+	 .mode = SPI_MODE_0,
+	 .platform_data = NULL,},
+};
+
 /*
  * Board specific initialization.
  */
@@ -155,6 +166,8 @@ static void __init mxc_board_init(void)
 	mxc_init_imx_uart();
 
 	imx51_add_spi_imx1(&mx51_3ds_spi2_pdata);
+	spi_register_board_info(mx51_3ds_spi_nor_device,
+				ARRAY_SIZE(mx51_3ds_spi_nor_device));
 
 	if (mxc_expio_init(MX51_CS5_BASE_ADDR, EXPIO_PARENT_INT))
 		printk(KERN_WARNING "Init of the debugboard failed, all "
-- 
1.5.6.5

Re: [PATCH 5/6] mx51_3ds: add eCSPI2 support on the imx51_3ds board

[Uwe Kleine-König]

Hi Jason,

On Thu, Sep 02, 2010 at 03:52:03PM +0800, Jason Wang wrote:
> Add platform data for eCSPI2 and register it through spi_imx dynamical
> register interface.
> 
> Signed-off-by: Jason Wang <jason77.wang@gmail.com>
> ---
>  arch/arm/mach-mx5/board-mx51_3ds.c |   20 ++++++++++++++++++++
>  1 files changed, 20 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
> index f95c2fd..0cf4e14 100644
> --- a/arch/arm/mach-mx5/board-mx51_3ds.c
> +++ b/arch/arm/mach-mx5/board-mx51_3ds.c
> @@ -24,9 +24,11 @@
>  #include <mach/imx-uart.h>
>  #include <mach/3ds_debugboard.h>
>  
> +#include "devices-imx51.h"
>  #include "devices.h"
>  
>  #define EXPIO_PARENT_INT	(MXC_INTERNAL_IRQS + GPIO_PORTA + 6)
> +#define MX51_3DS_ECSPI2_CS	(GPIO_PORTC + 28)
>  
>  static struct pad_desc mx51_3ds_pads[] = {
>  	/* UART1 */
> @@ -61,6 +63,12 @@ static struct pad_desc mx51_3ds_pads[] = {
>  	MX51_PAD_KEY_COL3__KEY_COL3,
>  	MX51_PAD_KEY_COL4__KEY_COL4,
>  	MX51_PAD_KEY_COL5__KEY_COL5,
> +
> +	/* eCSPI2 */
> +	MX51_PAD_NANDF_RB2__ECSPI2_SCLK,
> +	MX51_PAD_NANDF_RB3__ECSPI2_MISO,
> +	MX51_PAD_NANDF_D15__ECSPI2_MOSI,
> +	MX51_PAD_NANDF_D12__GPIO_3_28,
>  };
>  
>  /* Serial ports */
> @@ -127,6 +135,16 @@ static inline void mxc_init_keypad(void)
>  }
>  #endif
>  
> +static int mx51_3ds_spi2_cs[] = {
> +	MXC_SPI_CS(0),
> +	MX51_3DS_ECSPI2_CS,
> +};
> +
> +static struct spi_imx_master mx51_3ds_spi2_pdata = {
> +	.chipselect	= mx51_3ds_spi2_cs,
> +	.num_chipselect	= ARRAY_SIZE(mx51_3ds_spi2_cs),
> +};
maybe better call it mx51_3ds_ecspi2_pdata?  This should be const
__initconst.

>  /*
>   * Board specific initialization.
>   */
> @@ -136,6 +154,8 @@ static void __init mxc_board_init(void)
>  					ARRAY_SIZE(mx51_3ds_pads));
>  	mxc_init_imx_uart();
>  
> +	imx51_add_spi_imx1(&mx51_3ds_spi2_pdata);
> +
>  	if (mxc_expio_init(MX51_CS5_BASE_ADDR, EXPIO_PARENT_INT))
>  		printk(KERN_WARNING "Init of the debugboard failed, all "
>  				    "devices on the board are unusable.\n");
> -- 
> 1.5.6.5
> 
> 

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

Re: [PATCH 5/6] mx51_3ds: add eCSPI2 support on the imx51_3ds board

[Jason Wang]

Uwe Kleine-König wrote:
> Hi Jason,
>
> On Thu, Sep 02, 2010 at 03:52:03PM +0800, Jason Wang wrote:
>   
>> Add platform data for eCSPI2 and register it through spi_imx dynamical
>> register interface.
>>
>> Signed-off-by: Jason Wang <jason77.wang@gmail.com>
>> ---
>>  arch/arm/mach-mx5/board-mx51_3ds.c |   20 ++++++++++++++++++++
>>  1 files changed, 20 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
>> index f95c2fd..0cf4e14 100644
>> --- a/arch/arm/mach-mx5/board-mx51_3ds.c
>> +++ b/arch/arm/mach-mx5/board-mx51_3ds.c
>> @@ -24,9 +24,11 @@
>>  #include <mach/imx-uart.h>
>>  #include <mach/3ds_debugboard.h>
>>  
>> +#include "devices-imx51.h"
>>  #include "devices.h"
>>  
>>  #define EXPIO_PARENT_INT	(MXC_INTERNAL_IRQS + GPIO_PORTA + 6)
>> +#define MX51_3DS_ECSPI2_CS	(GPIO_PORTC + 28)
>>  
>>  static struct pad_desc mx51_3ds_pads[] = {
>>  	/* UART1 */
>> @@ -61,6 +63,12 @@ static struct pad_desc mx51_3ds_pads[] = {
>>  	MX51_PAD_KEY_COL3__KEY_COL3,
>>  	MX51_PAD_KEY_COL4__KEY_COL4,
>>  	MX51_PAD_KEY_COL5__KEY_COL5,
>> +
>> +	/* eCSPI2 */
>> +	MX51_PAD_NANDF_RB2__ECSPI2_SCLK,
>> +	MX51_PAD_NANDF_RB3__ECSPI2_MISO,
>> +	MX51_PAD_NANDF_D15__ECSPI2_MOSI,
>> +	MX51_PAD_NANDF_D12__GPIO_3_28,
>>  };
>>  
>>  /* Serial ports */
>> @@ -127,6 +135,16 @@ static inline void mxc_init_keypad(void)
>>  }
>>  #endif
>>  
>> +static int mx51_3ds_spi2_cs[] = {
>> +	MXC_SPI_CS(0),
>> +	MX51_3DS_ECSPI2_CS,
>> +};
>> +
>> +static struct spi_imx_master mx51_3ds_spi2_pdata = {
>> +	.chipselect	= mx51_3ds_spi2_cs,
>> +	.num_chipselect	= ARRAY_SIZE(mx51_3ds_spi2_cs),
>> +};
>>     
> maybe better call it mx51_3ds_ecspi2_pdata?  This should be const
> __initconst.
>
>   
OK, i will modify it.
>>  /*
>>   * Board specific initialization.
>>   */
>> @@ -136,6 +154,8 @@ static void __init mxc_board_init(void)
>>  					ARRAY_SIZE(mx51_3ds_pads));
>>  	mxc_init_imx_uart();
>>  
>> +	imx51_add_spi_imx1(&mx51_3ds_spi2_pdata);
>> +
>>  	if (mxc_expio_init(MX51_CS5_BASE_ADDR, EXPIO_PARENT_INT))
>>  		printk(KERN_WARNING "Init of the debugboard failed, all "
>>  				    "devices on the board are unusable.\n");
>> -- 
>> 1.5.6.5
>>
>>
>>     
>
>   

Re: [PATCH 3/6] mx5: add support to dynamically register spi_imx devices (imx51 3ds)

[Uwe Kleine-König]

Hi Jason,

On Thu, Sep 02, 2010 at 03:52:01PM +0800, Jason Wang wrote:
> Signed-off-by: Jason Wang <jason77.wang@gmail.com>
> ---
>  arch/arm/mach-mx5/Kconfig         |    1 +
>  arch/arm/mach-mx5/devices-imx51.h |   20 ++++++++++++++++++++
>  2 files changed, 21 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/mach-mx5/devices-imx51.h
> 
> diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
> index 0848db5..898fb47 100644
> --- a/arch/arm/mach-mx5/Kconfig
> +++ b/arch/arm/mach-mx5/Kconfig
> @@ -18,6 +18,7 @@ config MACH_MX51_BABBAGE
>  config MACH_MX51_3DS
>  	bool "Support MX51PDK (3DS)"
>  	select MXC_DEBUG_BOARD
> +	select IMX_HAVE_PLATFORM_SPI_IMX
>  	help
>  	  Include support for MX51PDK (3DS) platform. This includes specific
>  	  configurations for the board and its peripherals.
> diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h
> new file mode 100644
> index 0000000..d04c7eb
> --- /dev/null
> +++ b/arch/arm/mach-mx5/devices-imx51.h
> @@ -0,0 +1,20 @@
> +/*
> + * Copyright (C) 2010 Jason Wang <jason77.wang@gmail.com>
> + *
> + * based on mach-mx3/devices-imx35.h which is
> + * Copyright (C) 2010 Pengutronix
> + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
> + *
> + * This program is free software; you can redistribute it and/or modify it under
> + * the terms of the GNU General Public License version 2 as published by the
> + * Free Software Foundation.
> + */
> +#include <mach/mx51.h>
> +#include <mach/devices-common.h>
> +
> +#define imx51_add_spi_imx0(pdata)	\
> +	imx_add_spi_imx(0, MX51_CSPI1_BASE_ADDR, SZ_4K, MX51_MXC_INT_CSPI1, pdata)
> +#define imx51_add_spi_imx1(pdata)	\
> +	imx_add_spi_imx(1, MX51_CSPI2_BASE_ADDR, SZ_4K, MX51_MXC_INT_CSPI2, pdata)
> +#define imx51_add_spi_imx2(pdata)	\
> +	imx_add_spi_imx(1, MX51_CSPI3_BASE_ADDR, SZ_4K, MX51_MXC_INT_CSPI, pdata)
I like my new approach better.  See my patch 3.

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

Re: [PATCH 3/6] mx5: add support to dynamically register spi_imx devices (imx51 3ds)

[Jason Wang]

Uwe Kleine-König wrote:
> Hi Jason,
>
> On Thu, Sep 02, 2010 at 03:52:01PM +0800, Jason Wang wrote:
>   
>> Signed-off-by: Jason Wang <jason77.wang@gmail.com>
>> ---
>>  arch/arm/mach-mx5/Kconfig         |    1 +
>>  arch/arm/mach-mx5/devices-imx51.h |   20 ++++++++++++++++++++
>>  2 files changed, 21 insertions(+), 0 deletions(-)
>>  create mode 100644 arch/arm/mach-mx5/devices-imx51.h
>>
>> diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
>> index 0848db5..898fb47 100644
>> --- a/arch/arm/mach-mx5/Kconfig
>> +++ b/arch/arm/mach-mx5/Kconfig
>> @@ -18,6 +18,7 @@ config MACH_MX51_BABBAGE
>>  config MACH_MX51_3DS
>>  	bool "Support MX51PDK (3DS)"
>>  	select MXC_DEBUG_BOARD
>> +	select IMX_HAVE_PLATFORM_SPI_IMX
>>  	help
>>  	  Include support for MX51PDK (3DS) platform. This includes specific
>>  	  configurations for the board and its peripherals.
>> diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h
>> new file mode 100644
>> index 0000000..d04c7eb
>> --- /dev/null
>> +++ b/arch/arm/mach-mx5/devices-imx51.h
>> @@ -0,0 +1,20 @@
>> +/*
>> + * Copyright (C) 2010 Jason Wang <jason77.wang@gmail.com>
>> + *
>> + * based on mach-mx3/devices-imx35.h which is
>> + * Copyright (C) 2010 Pengutronix
>> + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
>> + *
>> + * This program is free software; you can redistribute it and/or modify it under
>> + * the terms of the GNU General Public License version 2 as published by the
>> + * Free Software Foundation.
>> + */
>> +#include <mach/mx51.h>
>> +#include <mach/devices-common.h>
>> +
>> +#define imx51_add_spi_imx0(pdata)	\
>> +	imx_add_spi_imx(0, MX51_CSPI1_BASE_ADDR, SZ_4K, MX51_MXC_INT_CSPI1, pdata)
>> +#define imx51_add_spi_imx1(pdata)	\
>> +	imx_add_spi_imx(1, MX51_CSPI2_BASE_ADDR, SZ_4K, MX51_MXC_INT_CSPI2, pdata)
>> +#define imx51_add_spi_imx2(pdata)	\
>> +	imx_add_spi_imx(1, MX51_CSPI3_BASE_ADDR, SZ_4K, MX51_MXC_INT_CSPI, pdata)
>>     
> I like my new approach better.  See my patch 3.
>
>   
OK, i will drop this patch.

Re: [PATCH 2/6] i.MX5/clock: add eCSPI and CSPI clock definitions

[Uwe Kleine-König]

On Thu, Sep 02, 2010 at 03:52:00PM +0800, Jason Wang wrote:
> i.MX51 has two eCSPI and one CSPI controllers, now add clock
> definitions and registrations for these controllers.
> 
> Signed-off-by: Jason Wang <jason77.wang@gmail.com>
> ---
>  arch/arm/mach-mx5/clock-mx51.c |   79 ++++++++++++++++++++++++++++++++++++++++
>  1 files changed, 79 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c
> index 6af69de..217c3f3 100644
> --- a/arch/arm/mach-mx5/clock-mx51.c
> +++ b/arch/arm/mach-mx5/clock-mx51.c
> @@ -38,6 +38,7 @@ static struct clk periph_apm_clk;
>  static struct clk ahb_clk;
>  static struct clk ipg_clk;
>  static struct clk usboh3_clk;
> +static struct clk spba_clk;
>  
>  #define MAX_DPLL_WAIT_TRIES	1000 /* 1000 * udelay(1) = 1ms */
>  
> @@ -52,6 +53,18 @@ static int _clk_ccgr_enable(struct clk *clk)
>  	return 0;
>  }
>  
> +static int _clk_ccgr_enable_inrun(struct clk *clk)
> +{
> +	u32 reg;
> +
> +	reg = __raw_readl(clk->enable_reg);
> +	reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
> +	reg |= MXC_CCM_CCGRx_MOD_IDLE << clk->enable_shift;
> +	__raw_writel(reg, clk->enable_reg);
> +
> +	return 0;
> +}
> +
imho this should be consolidated in something like:

static int _clk_ccgr_setclk(struct clk *clk, unsigned mode)
{
	...
}

#define _clk_ccgr_enable(clk) _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_ON)
#define _clk_ccgr_disable(clk) _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_OFF)
#define _clk_ccgr_enable_inrun(clk) _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE)

>  static void _clk_ccgr_disable(struct clk *clk)
>  {
>  	u32 reg;
> @@ -762,6 +775,61 @@ static struct clk kpp_clk = {
>  	.id = 0,
>  };
>  
> +/* eCSPI */
> +static unsigned long _clk_ecspi_getrate(struct clk *clk)
> +{
> +	u32 reg, prediv, podf;
> +	unsigned long ret;
> +
> +	reg = __raw_readl(MXC_CCM_CSCDR2);
> +	prediv = ((reg & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) >>
> +		  MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET) + 1;
> +	if (prediv == 1)
> +		BUG();
> +	podf = ((reg & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) >>
> +		MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET) + 1;
> +
> +	ret = clk_get_rate(clk->parent) / (prediv * podf);
> +	return ret;
> +}
> +
> +static int _clk_ecspi_set_parent(struct clk *clk, struct clk *parent)
> +{
> +	u32 reg, mux;
> +
> +	mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
> +		       &lp_apm_clk);
> +	reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK;
> +	reg |= mux << MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
> +	__raw_writel(reg, MXC_CCM_CSCMR1);
> +
> +	return 0;
> +}
> +
> +static struct clk ecspi_main_clk = {
> +	.parent = &pll3_sw_clk,
> +	.get_rate = _clk_ecspi_getrate,
> +	.set_parent = _clk_ecspi_set_parent,
Sascha didn't implement set_parent

> +};
> +
> +static struct clk ecspi1_ipg_clk = {
> +	.parent = &ipg_clk,
> +	.secondary = &spba_clk,
> +	.enable_reg = MXC_CCM_CCGR4,
> +	.enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
> +	.enable = _clk_ccgr_enable_inrun,
> +	.disable = _clk_ccgr_disable,
> +};
> +
> +static struct clk ecspi2_ipg_clk = {
> +	.parent = &ipg_clk,
> +	.secondary = &aips_tz2_clk,
> +	.enable_reg = MXC_CCM_CCGR4,
> +	.enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
> +	.enable = _clk_ccgr_enable_inrun,
> +	.disable = _clk_ccgr_disable,
> +};
> +
>  #define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s)	\
>  	static struct clk name = {			\
>  		.id		= i,			\
> @@ -814,6 +882,14 @@ DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
>  DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
>  	NULL,  NULL, &ipg_clk, NULL);
>  
> +/* eCSPI & CSPI */
> +DEFINE_CLOCK(cspi1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG10_OFFSET,
> +	NULL, NULL, &ecspi_main_clk, &ecspi1_ipg_clk);
> +DEFINE_CLOCK(cspi2_clk, 1, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG12_OFFSET,
> +	NULL, NULL, &ecspi_main_clk, &ecspi2_ipg_clk);
> +DEFINE_CLOCK(cspi3_clk, 2, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG13_OFFSET,
> +	NULL, NULL, &ipg_clk, NULL);
> +
Maybe use ecspi1_clk, cspi2_clk, cspi_clk here?  I thought about this,
too, for our code, couldn't really decide.  What do you think?

>  #define _REGISTER_CLOCK(d, n, c) \
>         { \
>  		.dev_id = d, \
> @@ -837,6 +913,9 @@ static struct clk_lookup lookups[] = {
>  	_REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
>  	_REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
>  	_REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk)
> +	_REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
> +	_REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
> +	_REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk)
>  };
>  

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

Re: [PATCH 2/6] i.MX5/clock: add eCSPI and CSPI clock definitions

[Jason Wang]

Uwe Kleine-König wrote:
> On Thu, Sep 02, 2010 at 03:52:00PM +0800, Jason Wang wrote:
>   
>> i.MX51 has two eCSPI and one CSPI controllers, now add clock
>> definitions and registrations for these controllers.
>>
>> Signed-off-by: Jason Wang <jason77.wang@gmail.com>
>> ---
>>  arch/arm/mach-mx5/clock-mx51.c |   79 ++++++++++++++++++++++++++++++++++++++++
>>  1 files changed, 79 insertions(+), 0 deletions(-)
>>
>> diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c
>> index 6af69de..217c3f3 100644
>> --- a/arch/arm/mach-mx5/clock-mx51.c
>> +++ b/arch/arm/mach-mx5/clock-mx51.c
>> @@ -38,6 +38,7 @@ static struct clk periph_apm_clk;
>>  static struct clk ahb_clk;
>>  static struct clk ipg_clk;
>>  static struct clk usboh3_clk;
>> +static struct clk spba_clk;
>>  
>>  #define MAX_DPLL_WAIT_TRIES	1000 /* 1000 * udelay(1) = 1ms */
>>  
>> @@ -52,6 +53,18 @@ static int _clk_ccgr_enable(struct clk *clk)
>>  	return 0;
>>  }
>>  
>> +static int _clk_ccgr_enable_inrun(struct clk *clk)
>> +{
>> +	u32 reg;
>> +
>> +	reg = __raw_readl(clk->enable_reg);
>> +	reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
>> +	reg |= MXC_CCM_CCGRx_MOD_IDLE << clk->enable_shift;
>> +	__raw_writel(reg, clk->enable_reg);
>> +
>> +	return 0;
>> +}
>> +
>>     
> imho this should be consolidated in something like:
>
> static int _clk_ccgr_setclk(struct clk *clk, unsigned mode)
> {
> 	...
> }
>
> #define _clk_ccgr_enable(clk) _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_ON)
> #define _clk_ccgr_disable(clk) _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_OFF)
> #define _clk_ccgr_enable_inrun(clk) _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE)
>
>   
It makes  code more concise. On the other hand, too many macros will
add troubles when we use kgdb to perform sourcecode-level debug.

Anyway, i agree your suggestion.
>>  static void _clk_ccgr_disable(struct clk *clk)
>>  {
>>  	u32 reg;
>> @@ -762,6 +775,61 @@ static struct clk kpp_clk = {
>>  	.id = 0,
>>  };
>>  
>> +/* eCSPI */
>> +static unsigned long _clk_ecspi_getrate(struct clk *clk)
>> +{
>> +	u32 reg, prediv, podf;
>> +	unsigned long ret;
>> +
>> +	reg = __raw_readl(MXC_CCM_CSCDR2);
>> +	prediv = ((reg & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) >>
>> +		  MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET) + 1;
>> +	if (prediv == 1)
>> +		BUG();
>> +	podf = ((reg & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) >>
>> +		MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET) + 1;
>> +
>> +	ret = clk_get_rate(clk->parent) / (prediv * podf);
>> +	return ret;
>> +}
>> +
>> +static int _clk_ecspi_set_parent(struct clk *clk, struct clk *parent)
>> +{
>> +	u32 reg, mux;
>> +
>> +	mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
>> +		       &lp_apm_clk);
>> +	reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK;
>> +	reg |= mux << MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
>> +	__raw_writel(reg, MXC_CCM_CSCMR1);
>> +
>> +	return 0;
>> +}
>> +
>> +static struct clk ecspi_main_clk = {
>> +	.parent = &pll3_sw_clk,
>> +	.get_rate = _clk_ecspi_getrate,
>> +	.set_parent = _clk_ecspi_set_parent,
>>     
> Sascha didn't implement set_parent
>
>   
ecspi really can change parent root clock.
>> +};
>> +
>> +static struct clk ecspi1_ipg_clk = {
>> +	.parent = &ipg_clk,
>> +	.secondary = &spba_clk,
>> +	.enable_reg = MXC_CCM_CCGR4,
>> +	.enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
>> +	.enable = _clk_ccgr_enable_inrun,
>> +	.disable = _clk_ccgr_disable,
>> +};
>> +
>> +static struct clk ecspi2_ipg_clk = {
>> +	.parent = &ipg_clk,
>> +	.secondary = &aips_tz2_clk,
>> +	.enable_reg = MXC_CCM_CCGR4,
>> +	.enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
>> +	.enable = _clk_ccgr_enable_inrun,
>> +	.disable = _clk_ccgr_disable,
>> +};
>> +
>>  #define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s)	\
>>  	static struct clk name = {			\
>>  		.id		= i,			\
>> @@ -814,6 +882,14 @@ DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
>>  DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
>>  	NULL,  NULL, &ipg_clk, NULL);
>>  
>> +/* eCSPI & CSPI */
>> +DEFINE_CLOCK(cspi1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG10_OFFSET,
>> +	NULL, NULL, &ecspi_main_clk, &ecspi1_ipg_clk);
>> +DEFINE_CLOCK(cspi2_clk, 1, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG12_OFFSET,
>> +	NULL, NULL, &ecspi_main_clk, &ecspi2_ipg_clk);
>> +DEFINE_CLOCK(cspi3_clk, 2, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG13_OFFSET,
>> +	NULL, NULL, &ipg_clk, NULL);
>> +
>>     
> Maybe use ecspi1_clk, cspi2_clk, cspi_clk here?  I thought about this,
> too, for our code, couldn't really decide.  What do you think?
>
>   
Agree.
>>  #define _REGISTER_CLOCK(d, n, c) \
>>         { \
>>  		.dev_id = d, \
>> @@ -837,6 +913,9 @@ static struct clk_lookup lookups[] = {
>>  	_REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
>>  	_REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
>>  	_REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk)
>> +	_REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
>> +	_REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
>> +	_REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk)
>>  };
>>  
>>     
>
> Best regards
> Uwe
>
>   

Re: [PATCH 2/6] i.MX5/clock: add eCSPI and CSPI clock definitions

[Uwe Kleine-König]

Hello Jason,

I currently merge your and our patch set.  Will follow up with the
result hopefully later today.

On Fri, Sep 03, 2010 at 02:22:08PM +0800, Jason Wang wrote:
>>>  @@ -52,6 +53,18 @@ static int _clk_ccgr_enable(struct clk *clk)
>>>  	return 0;
>>>  }
>>>  +static int _clk_ccgr_enable_inrun(struct clk *clk)
>>> +{
>>> +	u32 reg;
>>> +
>>> +	reg = __raw_readl(clk->enable_reg);
>>> +	reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
>>> +	reg |= MXC_CCM_CCGRx_MOD_IDLE << clk->enable_shift;
>>> +	__raw_writel(reg, clk->enable_reg);
>>> +
>>> +	return 0;
>>> +}
>>> +
>>>     
>> imho this should be consolidated in something like:
>>
>> static int _clk_ccgr_setclk(struct clk *clk, unsigned mode)
>> {
>> 	...
>> }
>>
>> #define _clk_ccgr_enable(clk) _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_ON)
>> #define _clk_ccgr_disable(clk) _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_OFF)
>> #define _clk_ccgr_enable_inrun(clk) _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE)
>>
>>   
> It makes  code more concise. On the other hand, too many macros will
> add troubles when we use kgdb to perform sourcecode-level debug.
Using macros doesn't work here, as they are used as callbacks.  Still
made it with functions.  Then (apart from the return value)
_clk_ccgr_enable_inrun and _clk_ccgr_disable_inwait are identically.
I wonder if this is intended?

> Anyway, i agree your suggestion.
>>>  static void _clk_ccgr_disable(struct clk *clk)
>>>  {
>>>  	u32 reg;
>>> @@ -762,6 +775,61 @@ static struct clk kpp_clk = {
>>>  	.id = 0,
>>>  };
>>>  +/* eCSPI */
>>> +static unsigned long _clk_ecspi_getrate(struct clk *clk)
>>> +{
>>> +	u32 reg, prediv, podf;
>>> +	unsigned long ret;
>>> +
>>> +	reg = __raw_readl(MXC_CCM_CSCDR2);
>>> +	prediv = ((reg & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) >>
>>> +		  MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET) + 1;
>>> +	if (prediv == 1)
>>> +		BUG();
>>> +	podf = ((reg & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) >>
>>> +		MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET) + 1;
>>> +
>>> +	ret = clk_get_rate(clk->parent) / (prediv * podf);
>>> +	return ret;
>>> +}
>>> +
>>> +static int _clk_ecspi_set_parent(struct clk *clk, struct clk *parent)
>>> +{
>>> +	u32 reg, mux;
>>> +
>>> +	mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
>>> +		       &lp_apm_clk);
>>> +	reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK;
>>> +	reg |= mux << MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
>>> +	__raw_writel(reg, MXC_CCM_CSCMR1);
>>> +
>>> +	return 0;
>>> +}
>>> +
>>> +static struct clk ecspi_main_clk = {
>>> +	.parent = &pll3_sw_clk,
>>> +	.get_rate = _clk_ecspi_getrate,
>>> +	.set_parent = _clk_ecspi_set_parent,
>>>     
>> Sascha didn't implement set_parent
>>
>>   
> ecspi really can change parent root clock.
>>> +};
>>> +
>>> +static struct clk ecspi1_ipg_clk = {
>>> +	.parent = &ipg_clk,
>>> +	.secondary = &spba_clk,
>>> +	.enable_reg = MXC_CCM_CCGR4,
>>> +	.enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
>>> +	.enable = _clk_ccgr_enable_inrun,
>>> +	.disable = _clk_ccgr_disable,
>>> +};
>>> +
>>> +static struct clk ecspi2_ipg_clk = {
>>> +	.parent = &ipg_clk,
>>> +	.secondary = &aips_tz2_clk,
>>> +	.enable_reg = MXC_CCM_CCGR4,
>>> +	.enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
>>> +	.enable = _clk_ccgr_enable_inrun,
>>> +	.disable = _clk_ccgr_disable,
>>> +};
aips_tz2_clk is wrong here, no?  Sascha used spba_clk here, too.  I
didn't found out yet how to read that out of the reference manual.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

Re: [PATCH 2/6] i.MX5/clock: add eCSPI and CSPI clock definitions

[Lothar Waßmann]

Hi,

Uwe Kleine-König writes:
> >>> +static struct clk ecspi2_ipg_clk = {
> >>> +	.parent = &ipg_clk,
> >>> +	.secondary = &aips_tz2_clk,
> >>> +	.enable_reg = MXC_CCM_CCGR4,
> >>> +	.enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
> >>> +	.enable = _clk_ccgr_enable_inrun,
> >>> +	.disable = _clk_ccgr_disable,
> >>> +};
> aips_tz2_clk is wrong here, no?  Sascha used spba_clk here, too.  I
> didn't found out yet how to read that out of the reference manual.
> 
The Freescale BSP used aips_tz2_clk (and spba for cspi1). They should
know what's right. Maybe a copy/paste error from Sascha?


Lothar Waßmann
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Re: [PATCH 2/6] i.MX5/clock: add eCSPI and CSPI clock definitions

[Jason Wang]

Uwe Kleine-König wrote:
> Hello Jason,
>
> I currently merge your and our patch set.  Will follow up with the
> result hopefully later today.
>
> On Fri, Sep 03, 2010 at 02:22:08PM +0800, Jason Wang wrote:
>   
>>>>  @@ -52,6 +53,18 @@ static int _clk_ccgr_enable(struct clk *clk)
>>>>  	return 0;
>>>>  }
>>>>  +static int _clk_ccgr_enable_inrun(struct clk *clk)
>>>> +{
>>>> +	u32 reg;
>>>> +
>>>> +	reg = __raw_readl(clk->enable_reg);
>>>> +	reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
>>>> +	reg |= MXC_CCM_CCGRx_MOD_IDLE << clk->enable_shift;
>>>> +	__raw_writel(reg, clk->enable_reg);
>>>> +
>>>> +	return 0;
>>>> +}
>>>> +
>>>>     
>>>>         
>>> imho this should be consolidated in something like:
>>>
>>> static int _clk_ccgr_setclk(struct clk *clk, unsigned mode)
>>> {
>>> 	...
>>> }
>>>
>>> #define _clk_ccgr_enable(clk) _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_ON)
>>> #define _clk_ccgr_disable(clk) _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_OFF)
>>> #define _clk_ccgr_enable_inrun(clk) _clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE)
>>>
>>>   
>>>       
>> It makes  code more concise. On the other hand, too many macros will
>> add troubles when we use kgdb to perform sourcecode-level debug.
>>     
> Using macros doesn't work here, as they are used as callbacks.  Still
> made it with functions.  Then (apart from the return value)
> _clk_ccgr_enable_inrun and _clk_ccgr_disable_inwait are identically.
> I wonder if this is intended?
>
>   
This is from Freescale's original design.

enalble_inrun = disable_inwait  = paritial enable = partial disable.
(clock is enable in free run mode, while is disable in wait/stop mode.)

This function can be both an enable callback and a disable callback.
I guess that assign this function two names just for logic clear.
>> Anyway, i agree your suggestion.
>>     
>>>>  static void _clk_ccgr_disable(struct clk *clk)
>>>>  {
>>>>  	u32 reg;
>>>> @@ -762,6 +775,61 @@ static struct clk kpp_clk = {
>>>>  	.id = 0,
>>>>  };
>>>>  +/* eCSPI */
>>>> +static unsigned long _clk_ecspi_getrate(struct clk *clk)
>>>> +{
>>>> +	u32 reg, prediv, podf;
>>>> +	unsigned long ret;
>>>> +
>>>> +	reg = __raw_readl(MXC_CCM_CSCDR2);
>>>> +	prediv = ((reg & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) >>
>>>> +		  MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET) + 1;
>>>> +	if (prediv == 1)
>>>> +		BUG();
>>>> +	podf = ((reg & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) >>
>>>> +		MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET) + 1;
>>>> +
>>>> +	ret = clk_get_rate(clk->parent) / (prediv * podf);
>>>> +	return ret;
>>>> +}
>>>> +
>>>> +static int _clk_ecspi_set_parent(struct clk *clk, struct clk *parent)
>>>> +{
>>>> +	u32 reg, mux;
>>>> +
>>>> +	mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
>>>> +		       &lp_apm_clk);
>>>> +	reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK;
>>>> +	reg |= mux << MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
>>>> +	__raw_writel(reg, MXC_CCM_CSCMR1);
>>>> +
>>>> +	return 0;
>>>> +}
>>>> +
>>>> +static struct clk ecspi_main_clk = {
>>>> +	.parent = &pll3_sw_clk,
>>>> +	.get_rate = _clk_ecspi_getrate,
>>>> +	.set_parent = _clk_ecspi_set_parent,
>>>>     
>>>>         
>>> Sascha didn't implement set_parent
>>>
>>>   
>>>       
>> ecspi really can change parent root clock.
>>     
>>>> +};
>>>> +
>>>> +static struct clk ecspi1_ipg_clk = {
>>>> +	.parent = &ipg_clk,
>>>> +	.secondary = &spba_clk,
>>>> +	.enable_reg = MXC_CCM_CCGR4,
>>>> +	.enable_shift = MXC_CCM_CCGRx_CG9_OFFSET,
>>>> +	.enable = _clk_ccgr_enable_inrun,
>>>> +	.disable = _clk_ccgr_disable,
>>>> +};
>>>> +
>>>> +static struct clk ecspi2_ipg_clk = {
>>>> +	.parent = &ipg_clk,
>>>> +	.secondary = &aips_tz2_clk,
>>>> +	.enable_reg = MXC_CCM_CCGR4,
>>>> +	.enable_shift = MXC_CCM_CCGRx_CG11_OFFSET,
>>>> +	.enable = _clk_ccgr_enable_inrun,
>>>> +	.disable = _clk_ccgr_disable,
>>>> +};
>>>>         
> aips_tz2_clk is wrong here, no?  Sascha used spba_clk here, too.  I
> didn't found out yet how to read that out of the reference manual.
>
>   
Just guess from Freescale original design and "charpter 2 Memory Map" of
MCIMX51RM.pdf.

eCSPI1 is in the AIPS_TZ1(spba) ip module, while eCSPI2 is in the AIPS_TZ2
ip module, so they have different "secondary ipg parent clock".

Thanks,
Jason.
> Best regards
> Uwe
>
>   

Re: [PATCH 1/6] spi-imx: add CSPI and eCSPI support for i.MX51 MCU

[Uwe Kleine-König]

Hello Jason,

On Thu, Sep 02, 2010 at 03:51:59PM +0800, Jason Wang wrote:
> There are 3 SPI controllers on i.MX51, one is called CSPI and is
> 100% compatible with the one on i.MX35, the other two are called
> eCSPI and are not compatible with existing controllers on other
> i.MX platforms, here we add support of these three controllers in
> the imx spi driver.
> 
> Signed-off-by: Jason Wang <jason77.wang@gmail.com>
> ---
>  drivers/spi/spi_imx.c |  135 +++++++++++++++++++++++++++++++++++++++++++++++--
>  1 files changed, 131 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/spi/spi_imx.c b/drivers/spi/spi_imx.c
> index 7972e90..8d9c9da 100644
> --- a/drivers/spi/spi_imx.c
> +++ b/drivers/spi/spi_imx.c
> @@ -155,6 +155,120 @@ static unsigned int spi_imx_clkdiv_2(unsigned int fin,
>  	return 7;
>  }
>  
> +/* MX51 eCSPI post divider */
> +static unsigned int spi_imx_clkdiv_3(unsigned int fin,
> +		unsigned int fspi)
> +{
> +	int i, div = 1;
> +
> +	for (i = 0; i < 15; i++) {
> +		if (fspi * div >= fin)
> +			return i;
> +		div <<= 1;
> +	}
> +
> +	return 15;
> +}
This is different in Sascha's patch.  Didn't try yet to understand the
difference.

> +
> +#define MX51_INTREG_TEEN		(1 << 0)
> +#define MX51_INTREG_RREN		(1 << 3)
> +
> +#define MX51_CSPICTRL_ENABLE		(1 << 0)
> +#define MX51_CSPICTRL_XCH		(1 << 2)
> +
> +#define MX51_CSPICTRL_BL_SHIFT		20
> +#define MX51_CSPICTRL_CS_SHIFT		18
> +#define MX51_CSPICTRL_DR_SHIFT		8
> +#define MX51_CSPICTRL_MODE_SHIFT	4
> +#define MX51_CSPICONF_PHA_SHIFT		0
> +#define MX51_CSPICONF_POL_SHIFT		4
> +#define MX51_CSPICONF_SSPOL_SHIFT	12
> +#define MX51_CSPICONF_SSCTL_SHIFT	8
> +
> +#define MX51_CSPICTRL_CSMASK		0x3
> +#define MX51_CSPIINT			0x10
> +#define MX51_CSPICONF			0xC
> +#define MX51_CSPISTATUS			0x18
> +#define MX51_STATUS_RR			(1 << 3)
> +
> +#define MAX_CHIPSELECT_NUM 4
> +
> +static int get_chipselect(struct spi_imx_data *spi_imx,
> +			  struct spi_imx_config *config)
> +{
> +	int i;
> +
> +	for (i = 0; i < MAX_CHIPSELECT_NUM; i++) {
> +		if (config->cs == spi_imx->chipselect[i])
> +			return i;
> +	}
> +
> +	return -EINVAL;
> +}
> +static void mx51_intctrl(struct spi_imx_data *spi_imx, int enable)
> +{
> +	unsigned int val = 0;
> +
> +	if (enable & MXC_INT_TE)
> +		val |= MX51_INTREG_TEEN;
> +	if (enable & MXC_INT_RR)
> +		val |= MX51_INTREG_RREN;
> +
> +	writel(val, spi_imx->base + MX51_CSPIINT);
> +}
> +
> +static void mx51_trigger(struct spi_imx_data *spi_imx)
> +{
> +	unsigned int reg;
> +
> +	reg = readl(spi_imx->base + MXC_CSPICTRL);
> +	reg |= MX51_CSPICTRL_XCH;
> +	writel(reg, spi_imx->base + MXC_CSPICTRL);
> +}
> +
> +static int mx51_config(struct spi_imx_data *spi_imx,
> +		struct spi_imx_config *config)
> +{
> +	unsigned int config_reg = 0;
> +	unsigned int ctrl_reg = MX51_CSPICTRL_ENABLE;
> +	int chan;
> +
> +	chan = get_chipselect(spi_imx, config);
> +	if (chan < 0)
> +		return chan;
can this happen?  Does that have to do with using a GPIO for CS?

> +	ctrl_reg |= (chan & MX51_CSPICTRL_CSMASK) << MX51_CSPICTRL_CS_SHIFT;
> +	ctrl_reg |= (1 << (chan & MX51_CSPICTRL_CSMASK)) <<
> +		MX51_CSPICTRL_MODE_SHIFT;
> +	ctrl_reg |= spi_imx_clkdiv_3(spi_imx->spi_clk, config->speed_hz) <<
> +		MX51_CSPICTRL_DR_SHIFT;
> +
> +	ctrl_reg |= (config->bpw - 1) << MX51_CSPICTRL_BL_SHIFT;
> +
> +
duplicated empty line

> +	if (config->mode & SPI_CPHA)
> +		config_reg |= (1 << (chan & MX51_CSPICTRL_CSMASK)) <<
> +			MX51_CSPICONF_PHA_SHIFT;
> +	if (config->mode & SPI_CPOL)
> +		config_reg |= (1 << (chan & MX51_CSPICTRL_CSMASK)) <<
> +			MX51_CSPICONF_POL_SHIFT;
> +	if (config->mode & SPI_CS_HIGH)
> +		config_reg |= (1 << (chan & MX51_CSPICTRL_CSMASK)) <<
> +			MX51_CSPICONF_SSPOL_SHIFT;
> +
> +	config_reg |= (1 << (chan & MX51_CSPICTRL_CSMASK)) <<
> +		MX51_CSPICONF_SSCTL_SHIFT;
> +
> +	writel(ctrl_reg, spi_imx->base + MXC_CSPICTRL);
> +	writel(config_reg, spi_imx->base + MX51_CSPICONF);
> +
> +	return 0;
> +}
> +
> +static int mx51_rx_available(struct spi_imx_data *spi_imx)
> +{
> +	return readl(spi_imx->base + MX51_CSPISTATUS) & MX51_STATUS_RR;
> +}
> +
>  #define MX31_INTREG_TEEN	(1 << 0)
>  #define MX31_INTREG_RREN	(1 << 3)
>  
> @@ -209,7 +323,7 @@ static int mx31_config(struct spi_imx_data *spi_imx,
>  
>  	if (cpu_is_mx31())
>  		reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
> -	else if (cpu_is_mx25() || cpu_is_mx35()) {
> +	else if (cpu_is_mx25() || cpu_is_mx35() || cpu_is_mx51()) {
>  		reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
>  		reg |= MX31_CSPICTRL_SSCTL;
>  	}
> @@ -223,7 +337,7 @@ static int mx31_config(struct spi_imx_data *spi_imx,
>  	if (config->cs < 0) {
>  		if (cpu_is_mx31())
>  			reg |= (config->cs + 32) << MX31_CSPICTRL_CS_SHIFT;
> -		else if (cpu_is_mx25() || cpu_is_mx35())
> +		else if (cpu_is_mx25() || cpu_is_mx35() || cpu_is_mx51())
>  			reg |= (config->cs + 32) << MX35_CSPICTRL_CS_SHIFT;
>  	}
>  
> @@ -567,7 +681,14 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
>  		goto out_iounmap;
>  	}
>  
> -	if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35()) {
> +	/* i.MX51 has two eCSPI and one CSPI controllers, eCSPI controllers are
> +	 * not compatible with existing SPI controllers on other i.MX platforms,
> +	 * while CSPI controller is 100% compatible with the one on the i.MX35.
> +	 * We set the platform device id to 2 for this CSPI at i.MX51 board init
> +	 * level to distinguish it from two eCSPI controllers.
> +	 */
This comment is missing in Sascha's driver.  I like it.
BTW, I'd like to make use of platform ids in this driver.  This would
make this ugly "on imx51 id2 is a cspi" distinction unnecessary.

> +	if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35() ||
> +	    (cpu_is_mx51() && (pdev->id == 2))) {
>  		spi_imx->intctrl = mx31_intctrl;
>  		spi_imx->config = mx31_config;
>  		spi_imx->trigger = mx31_trigger;
> @@ -582,6 +703,11 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
>  		spi_imx->config = mx1_config;
>  		spi_imx->trigger = mx1_trigger;
>  		spi_imx->rx_available = mx1_rx_available;
> +	} else if (cpu_is_mx51()) {
> +		spi_imx->intctrl = mx51_intctrl;
> +		spi_imx->config = mx51_config;
> +		spi_imx->trigger = mx51_trigger;
> +		spi_imx->rx_available = mx51_rx_available;
>  	} else
>  		BUG();
>  
> @@ -599,7 +725,8 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
>  		writel(1, spi_imx->base + MXC_RESET);
>  
>  	/* drain receive buffer */
> -	if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35())
> +	if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35() ||
> +	    (cpu_is_mx51() && (pdev->id == 2)))
>  		while (readl(spi_imx->base + MX3_CSPISTAT) & MX3_CSPISTAT_RR)
>  			readl(spi_imx->base + MXC_CSPIRXDATA);
Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

Re: [PATCH 1/6] spi-imx: add CSPI and eCSPI support for i.MX51 MCU

[Lothar Waßmann]

Hi,

> > -	if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35()) {
> > +	/* i.MX51 has two eCSPI and one CSPI controllers, eCSPI controllers are
> > +	 * not compatible with existing SPI controllers on other i.MX platforms,
> > +	 * while CSPI controller is 100% compatible with the one on the i.MX35.
> > +	 * We set the platform device id to 2 for this CSPI at i.MX51 board init
> > +	 * level to distinguish it from two eCSPI controllers.
> > +	 */
> This comment is missing in Sascha's driver.  I like it.
> BTW, I'd like to make use of platform ids in this driver.  This would
> make this ugly "on imx51 id2 is a cspi" distinction unnecessary.
> 
> > +	if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35() ||
> > +	    (cpu_is_mx51() && (pdev->id == 2))) {
I'd prefer a flag in the platform_data that tells the driver to act as
an eCSPI driver. This way the information about eCSPI or not would be
where it belongs (in the arch specific code).


Lothar Waßmann
-- 
___________________________________________________________

Ka-Ro electronics GmbH | Pascalstraße 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Geschäftsführer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996

www.karo-electronics.de | info@karo-electronics.de
___________________________________________________________

Re: [PATCH 1/6] spi-imx: add CSPI and eCSPI support for i.MX51 MCU

[Baruch Siach]

Hi Lothar,

On Thu, Sep 02, 2010 at 05:11:56PM +0200, Lothar Waßmann wrote:
> > > -	if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35()) {
> > > +	/* i.MX51 has two eCSPI and one CSPI controllers, eCSPI controllers are
> > > +	 * not compatible with existing SPI controllers on other i.MX platforms,
> > > +	 * while CSPI controller is 100% compatible with the one on the i.MX35.
> > > +	 * We set the platform device id to 2 for this CSPI at i.MX51 board init
> > > +	 * level to distinguish it from two eCSPI controllers.
> > > +	 */
> > This comment is missing in Sascha's driver.  I like it.
> > BTW, I'd like to make use of platform ids in this driver.  This would
> > make this ugly "on imx51 id2 is a cspi" distinction unnecessary.
> > 
> > > +	if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35() ||
> > > +	    (cpu_is_mx51() && (pdev->id == 2))) {
> I'd prefer a flag in the platform_data that tells the driver to act as
> an eCSPI driver. This way the information about eCSPI or not would be
> where it belongs (in the arch specific code).

But this also increases the size of driver code, since the compiler can 
resolve cpu_is_* at compile time, and drop the dead code. Maybe an is_ecspi 
macro will make the above code clearer.

baruch

-- 
                                                     ~. .~   Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
   - baruch@tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -

Re: [PATCH 1/6] spi-imx: add CSPI and eCSPI support for i.MX51 MCU

[Uwe Kleine-König]

Hello,

On Thu, Sep 02, 2010 at 08:29:09PM +0300, Baruch Siach wrote:
> Hi Lothar,
> 
> On Thu, Sep 02, 2010 at 05:11:56PM +0200, Lothar Waßmann wrote:
> > > > -	if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35()) {
> > > > +	/* i.MX51 has two eCSPI and one CSPI controllers, eCSPI controllers are
> > > > +	 * not compatible with existing SPI controllers on other i.MX platforms,
> > > > +	 * while CSPI controller is 100% compatible with the one on the i.MX35.
> > > > +	 * We set the platform device id to 2 for this CSPI at i.MX51 board init
> > > > +	 * level to distinguish it from two eCSPI controllers.
> > > > +	 */
> > > This comment is missing in Sascha's driver.  I like it.
> > > BTW, I'd like to make use of platform ids in this driver.  This would
> > > make this ugly "on imx51 id2 is a cspi" distinction unnecessary.
> > > 
> > > > +	if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35() ||
> > > > +	    (cpu_is_mx51() && (pdev->id == 2))) {
> > I'd prefer a flag in the platform_data that tells the driver to act as
> > an eCSPI driver. This way the information about eCSPI or not would be
> > where it belongs (in the arch specific code).
> 
> But this also increases the size of driver code, since the compiler can 
> resolve cpu_is_* at compile time, and drop the dead code. Maybe an is_ecspi 
> macro will make the above code clearer.
If you ask me the cleanest approach is using platform ids.  That is the
devices on mx51 could be called:

	imx51-ecspi.0
	imx51-ecspi.1
	imx51-cspi.0

I don't know what the implications on driver code size is, but I can
imagine that if done carefully the driver doesn't need to be bigger.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

Re: [PATCH 1/6] spi-imx: add CSPI and eCSPI support for i.MX51 MCU

[Lothar Waßmann]

Hi,

> On Thu, Sep 02, 2010 at 05:11:56PM +0200, Lothar Waßmann wrote:
> > > > -	if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35()) {
> > > > +	/* i.MX51 has two eCSPI and one CSPI controllers, eCSPI controllers are
> > > > +	 * not compatible with existing SPI controllers on other i.MX platforms,
> > > > +	 * while CSPI controller is 100% compatible with the one on the i.MX35.
> > > > +	 * We set the platform device id to 2 for this CSPI at i.MX51 board init
> > > > +	 * level to distinguish it from two eCSPI controllers.
> > > > +	 */
> > > This comment is missing in Sascha's driver.  I like it.
> > > BTW, I'd like to make use of platform ids in this driver.  This would
> > > make this ugly "on imx51 id2 is a cspi" distinction unnecessary.
> > > 
> > > > +	if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35() ||
> > > > +	    (cpu_is_mx51() && (pdev->id == 2))) {
> > I'd prefer a flag in the platform_data that tells the driver to act as
> > an eCSPI driver. This way the information about eCSPI or not would be
> > where it belongs (in the arch specific code).
> 
> But this also increases the size of driver code, since the compiler can 
> resolve cpu_is_* at compile time, and drop the dead code. Maybe an is_ecspi 
> macro will make the above code clearer.
> 
I did not mean to remove the cpu_is_* macros, but use the explicit
ecspi flag instead of the comparison with pdev->id.


Lothar Waßmann
-- 
___________________________________________________________

Ka-Ro electronics GmbH | Pascalstraße 22 | D - 52076 Aachen
Phone: +49 2408 1402-0 | Fax: +49 2408 1402-10
Geschäftsführer: Matthias Kaussen
Handelsregistereintrag: Amtsgericht Aachen, HRB 4996

www.karo-electronics.de | info@karo-electronics.de
___________________________________________________________

Re: [PATCH 1/6] spi-imx: add CSPI and eCSPI support for i.MX51 MCU

[Jason Wang]

Uwe Kleine-König wrote:
> Hello Jason,
>
> On Thu, Sep 02, 2010 at 03:51:59PM +0800, Jason Wang wrote:
>   
>> There are 3 SPI controllers on i.MX51, one is called CSPI and is
>> 100% compatible with the one on i.MX35, the other two are called
>> eCSPI and are not compatible with existing controllers on other
>> i.MX platforms, here we add support of these three controllers in
>> the imx spi driver.
>>
>> Signed-off-by: Jason Wang <jason77.wang@gmail.com>
>> ---
>>  drivers/spi/spi_imx.c |  135 +++++++++++++++++++++++++++++++++++++++++++++++--
>>  1 files changed, 131 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/spi/spi_imx.c b/drivers/spi/spi_imx.c
>> index 7972e90..8d9c9da 100644
>> --- a/drivers/spi/spi_imx.c
>> +++ b/drivers/spi/spi_imx.c
>> @@ -155,6 +155,120 @@ static unsigned int spi_imx_clkdiv_2(unsigned int fin,
>>  	return 7;
>>  }
>>  
>> +/* MX51 eCSPI post divider */
>> +static unsigned int spi_imx_clkdiv_3(unsigned int fin,
>> +		unsigned int fspi)
>> +{
>> +	int i, div = 1;
>> +
>> +	for (i = 0; i < 15; i++) {
>> +		if (fspi * div >= fin)
>> +			return i;
>> +		div <<= 1;
>> +	}
>> +
>> +	return 15;
>> +}
>>     
> This is different in Sascha's patch.  Didn't try yet to understand the
> difference.
>
>   
To change the spi clock frequency, we can set pre-divider and post-divider,
here, to be simple, i only change post-divider(set pre-divider to 1), while
sascha handle both pre-divider and post-divider.
>> +
>> +#define MX51_INTREG_TEEN		(1 << 0)
>> +#define MX51_INTREG_RREN		(1 << 3)
>> +
>> +#define MX51_CSPICTRL_ENABLE		(1 << 0)
>> +#define MX51_CSPICTRL_XCH		(1 << 2)
>> +
>> +#define MX51_CSPICTRL_BL_SHIFT		20
>> +#define MX51_CSPICTRL_CS_SHIFT		18
>> +#define MX51_CSPICTRL_DR_SHIFT		8
>> +#define MX51_CSPICTRL_MODE_SHIFT	4
>> +#define MX51_CSPICONF_PHA_SHIFT		0
>> +#define MX51_CSPICONF_POL_SHIFT		4
>> +#define MX51_CSPICONF_SSPOL_SHIFT	12
>> +#define MX51_CSPICONF_SSCTL_SHIFT	8
>> +
>> +#define MX51_CSPICTRL_CSMASK		0x3
>> +#define MX51_CSPIINT			0x10
>> +#define MX51_CSPICONF			0xC
>> +#define MX51_CSPISTATUS			0x18
>> +#define MX51_STATUS_RR			(1 << 3)
>> +
>> +#define MAX_CHIPSELECT_NUM 4
>> +
>> +static int get_chipselect(struct spi_imx_data *spi_imx,
>> +			  struct spi_imx_config *config)
>> +{
>> +	int i;
>> +
>> +	for (i = 0; i < MAX_CHIPSELECT_NUM; i++) {
>> +		if (config->cs == spi_imx->chipselect[i])
>> +			return i;
>> +	}
>> +
>> +	return -EINVAL;
>> +}
>> +static void mx51_intctrl(struct spi_imx_data *spi_imx, int enable)
>> +{
>> +	unsigned int val = 0;
>> +
>> +	if (enable & MXC_INT_TE)
>> +		val |= MX51_INTREG_TEEN;
>> +	if (enable & MXC_INT_RR)
>> +		val |= MX51_INTREG_RREN;
>> +
>> +	writel(val, spi_imx->base + MX51_CSPIINT);
>> +}
>> +
>> +static void mx51_trigger(struct spi_imx_data *spi_imx)
>> +{
>> +	unsigned int reg;
>> +
>> +	reg = readl(spi_imx->base + MXC_CSPICTRL);
>> +	reg |= MX51_CSPICTRL_XCH;
>> +	writel(reg, spi_imx->base + MXC_CSPICTRL);
>> +}
>> +
>> +static int mx51_config(struct spi_imx_data *spi_imx,
>> +		struct spi_imx_config *config)
>> +{
>> +	unsigned int config_reg = 0;
>> +	unsigned int ctrl_reg = MX51_CSPICTRL_ENABLE;
>> +	int chan;
>> +
>> +	chan = get_chipselect(spi_imx, config);
>> +	if (chan < 0)
>> +		return chan;
>>     
> can this happen?  Does that have to do with using a GPIO for CS?
>   
If we use 4 GPIOs for 4 SPI client devices, we can assign each to a 
separate channel.
each channel has its own transfer mode(like clk edge...).
>   
>> +	ctrl_reg |= (chan & MX51_CSPICTRL_CSMASK) << MX51_CSPICTRL_CS_SHIFT;
>> +	ctrl_reg |= (1 << (chan & MX51_CSPICTRL_CSMASK)) <<
>> +		MX51_CSPICTRL_MODE_SHIFT;
>> +	ctrl_reg |= spi_imx_clkdiv_3(spi_imx->spi_clk, config->speed_hz) <<
>> +		MX51_CSPICTRL_DR_SHIFT;
>> +
>> +	ctrl_reg |= (config->bpw - 1) << MX51_CSPICTRL_BL_SHIFT;
>> +
>> +
>>     
> duplicated empty line
>
>   
OK.
>> +	if (config->mode & SPI_CPHA)
>> +		config_reg |= (1 << (chan & MX51_CSPICTRL_CSMASK)) <<
>> +			MX51_CSPICONF_PHA_SHIFT;
>> +	if (config->mode & SPI_CPOL)
>> +		config_reg |= (1 << (chan & MX51_CSPICTRL_CSMASK)) <<
>> +			MX51_CSPICONF_POL_SHIFT;
>> +	if (config->mode & SPI_CS_HIGH)
>> +		config_reg |= (1 << (chan & MX51_CSPICTRL_CSMASK)) <<
>> +			MX51_CSPICONF_SSPOL_SHIFT;
>> +
>> +	config_reg |= (1 << (chan & MX51_CSPICTRL_CSMASK)) <<
>> +		MX51_CSPICONF_SSCTL_SHIFT;
>> +
>> +	writel(ctrl_reg, spi_imx->base + MXC_CSPICTRL);
>> +	writel(config_reg, spi_imx->base + MX51_CSPICONF);
>> +
>> +	return 0;
>> +}
>> +
>> +static int mx51_rx_available(struct spi_imx_data *spi_imx)
>> +{
>> +	return readl(spi_imx->base + MX51_CSPISTATUS) & MX51_STATUS_RR;
>> +}
>> +
>>  #define MX31_INTREG_TEEN	(1 << 0)
>>  #define MX31_INTREG_RREN	(1 << 3)
>>  
>> @@ -209,7 +323,7 @@ static int mx31_config(struct spi_imx_data *spi_imx,
>>  
>>  	if (cpu_is_mx31())
>>  		reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
>> -	else if (cpu_is_mx25() || cpu_is_mx35()) {
>> +	else if (cpu_is_mx25() || cpu_is_mx35() || cpu_is_mx51()) {
>>  		reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
>>  		reg |= MX31_CSPICTRL_SSCTL;
>>  	}
>> @@ -223,7 +337,7 @@ static int mx31_config(struct spi_imx_data *spi_imx,
>>  	if (config->cs < 0) {
>>  		if (cpu_is_mx31())
>>  			reg |= (config->cs + 32) << MX31_CSPICTRL_CS_SHIFT;
>> -		else if (cpu_is_mx25() || cpu_is_mx35())
>> +		else if (cpu_is_mx25() || cpu_is_mx35() || cpu_is_mx51())
>>  			reg |= (config->cs + 32) << MX35_CSPICTRL_CS_SHIFT;
>>  	}
>>  
>> @@ -567,7 +681,14 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
>>  		goto out_iounmap;
>>  	}
>>  
>> -	if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35()) {
>> +	/* i.MX51 has two eCSPI and one CSPI controllers, eCSPI controllers are
>> +	 * not compatible with existing SPI controllers on other i.MX platforms,
>> +	 * while CSPI controller is 100% compatible with the one on the i.MX35.
>> +	 * We set the platform device id to 2 for this CSPI at i.MX51 board init
>> +	 * level to distinguish it from two eCSPI controllers.
>> +	 */
>>     
> This comment is missing in Sascha's driver.  I like it.
> BTW, I'd like to make use of platform ids in this driver.  This would
> make this ugly "on imx51 id2 is a cspi" distinction unnecessary.
>
>   
agree, i like both your and lothar's solution.
Either platform ids or flags in platform_data.

>> +	if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35() ||
>> +	    (cpu_is_mx51() && (pdev->id == 2))) {
>>  		spi_imx->intctrl = mx31_intctrl;
>>  		spi_imx->config = mx31_config;
>>  		spi_imx->trigger = mx31_trigger;
>> @@ -582,6 +703,11 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
>>  		spi_imx->config = mx1_config;
>>  		spi_imx->trigger = mx1_trigger;
>>  		spi_imx->rx_available = mx1_rx_available;
>> +	} else if (cpu_is_mx51()) {
>> +		spi_imx->intctrl = mx51_intctrl;
>> +		spi_imx->config = mx51_config;
>> +		spi_imx->trigger = mx51_trigger;
>> +		spi_imx->rx_available = mx51_rx_available;
>>  	} else
>>  		BUG();
>>  
>> @@ -599,7 +725,8 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
>>  		writel(1, spi_imx->base + MXC_RESET);
>>  
>>  	/* drain receive buffer */
>> -	if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35())
>> +	if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35() ||
>> +	    (cpu_is_mx51() && (pdev->id == 2)))
>>  		while (readl(spi_imx->base + MX3_CSPISTAT) & MX3_CSPISTAT_RR)
>>  			readl(spi_imx->base + MXC_CSPIRXDATA);
>>     
> Best regards
> Uwe
>
>   

Re: [PATCH 1/6] spi-imx: add CSPI and eCSPI support for i.MX51 MCU

[Uwe Kleine-König]

Hello,

On Fri, Sep 03, 2010 at 02:16:11PM +0800, Jason Wang wrote:
>>>  -	if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35()) {
>>> +	/* i.MX51 has two eCSPI and one CSPI controllers, eCSPI controllers are
>>> +	 * not compatible with existing SPI controllers on other i.MX platforms,
>>> +	 * while CSPI controller is 100% compatible with the one on the i.MX35.
>>> +	 * We set the platform device id to 2 for this CSPI at i.MX51 board init
>>> +	 * level to distinguish it from two eCSPI controllers.
>>> +	 */
>>>     
>> This comment is missing in Sascha's driver.  I like it.
>> BTW, I'd like to make use of platform ids in this driver.  This would
>> make this ugly "on imx51 id2 is a cspi" distinction unnecessary.
>>
>>   
> agree, i like both your and lothar's solution.
> Either platform ids or flags in platform_data.
I suggest to do the cleanup later.  Doing it before adding mx51 support
would make only more work for little benefit.  And then the cleanup
bases on a working version.  I'm willing to implement the platform id
thingy and evaluate it.  But currently I have no time for that.  So I
suggest we choose a mix between your and Sascha's patch for now and I
will check where the cleanup fits in my planning.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

Re: [PATCH 0/6] add spi support for i.MX51 in the existing spi_imx driver

[Uwe Kleine-König]

Hello Jason,

On Thu, Sep 02, 2010 at 03:51:58PM +0800, Jason Wang wrote:
> Some explanations:
> 
> This patchset is to add SPI support in the existing spi_imx driver for
> i.MX51 and add SPI relating stuffs for mx51_3ds board level.
> 
> i.MX51 has two eCSPI controllers and one CSPI controller, CSPI
> controller is 100% compatible with the one of i.MX35, so we don't need
> to add new functions for this CSPI, only bind it with i.MX35 together,
> while eCSPI isn't compatible with existing controllers of i.MX
> platforms, so i add new functions for these two eCSPIs in the existing
> spi_imx driver.
> 
> If these patches pass review, the first patch 0001-xxx.patch should be
> merged by Grant.likely; other patches(0002-0006) are based off
> imx-for-2.6.37 and should be handled by Sascha.

Unfortunately we (=Pengutronix) have some patches pending to add
mx51-spi support, too.  And there are some other patches that will
conflict with your series (e.g. I renamed some symbols used by you:

-#define MX51_CSPI1_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x10000)
+#define MX51_ECSPI1_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x10000)
-#define MX51_CSPI2_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xac000)
+#define MX51_ECSPI2_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xac000)
-#define MX51_CSPI3_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xc0000)
+#define MX51_CSPI_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xc0000)
-#define MX51_MXC_INT_CSPI1		36
-#define MX51_MXC_INT_CSPI2		37
-#define MX51_MXC_INT_CSPI		38
+#define MX51_INT_ECSPI1			36
+#define MX51_INT_ECSPI2			37
+#define MX51_INT_CSPI			38
)

Actually I would prefer our patches, but of course I'm biased :-)

I don't know how we should handle this.  And Sascha is on vacation this
and next week.  I will investigate if our patches are already free to be
posted.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

Re: [PATCH 0/6] add spi support for i.MX51 in the existing spi_imx driver

[Jason Wang]

Uwe Kleine-König wrote:
> Hello Jason,
>
> On Thu, Sep 02, 2010 at 03:51:58PM +0800, Jason Wang wrote:
>   
>> Some explanations:
>>
>> This patchset is to add SPI support in the existing spi_imx driver for
>> i.MX51 and add SPI relating stuffs for mx51_3ds board level.
>>
>> i.MX51 has two eCSPI controllers and one CSPI controller, CSPI
>> controller is 100% compatible with the one of i.MX35, so we don't need
>> to add new functions for this CSPI, only bind it with i.MX35 together,
>> while eCSPI isn't compatible with existing controllers of i.MX
>> platforms, so i add new functions for these two eCSPIs in the existing
>> spi_imx driver.
>>
>> If these patches pass review, the first patch 0001-xxx.patch should be
>> merged by Grant.likely; other patches(0002-0006) are based off
>> imx-for-2.6.37 and should be handled by Sascha.
>>     
>
> Unfortunately we (=Pengutronix) have some patches pending to add
> mx51-spi support, too.  And there are some other patches that will
> conflict with your series (e.g. I renamed some symbols used by you:
>
> -#define MX51_CSPI1_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x10000)
> +#define MX51_ECSPI1_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x10000)
> -#define MX51_CSPI2_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xac000)
> +#define MX51_ECSPI2_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xac000)
> -#define MX51_CSPI3_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xc0000)
> +#define MX51_CSPI_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xc0000)
> -#define MX51_MXC_INT_CSPI1		36
> -#define MX51_MXC_INT_CSPI2		37
> -#define MX51_MXC_INT_CSPI		38
> +#define MX51_INT_ECSPI1			36
> +#define MX51_INT_ECSPI2			37
> +#define MX51_INT_CSPI			38
> )
>
> Actually I would prefer our patches, but of course I'm biased :-)
>
> I don't know how we should handle this.  And Sascha is on vacation this
> and next week.  I will investigate if our patches are already free to be
> posted.
>
>   
OK, for conflicting parts, i will wait for new patches to be posted out,
and rebase my conflicting patches off that.

If it is possible, please review other parts first.

Thanks,
Jason.

> Best regards
> Uwe
>
>   

Re: [PATCH 0/6] add spi support for i.MX51 in the existing spi_imx driver

[Uwe Kleine-König]

Hello Jason,

>> Actually I would prefer our patches, but of course I'm biased :-)
>>
>> I don't know how we should handle this.  And Sascha is on vacation this
>> and next week.  I will investigate if our patches are already free to be
>> posted.
OK, I can post our patches.  I think the driver part is quite similar,
the platform part is not.  But look for yourself, I'll post them in reply to
this mail.  Hopefully we can join forces to get the best out of the two
approaches.

BTW, we're working on nand (David merged an early patch series by
Sascha, we have some fixes pending), mc19892 and ipuv3, too.  Just to
notice the possibility for more cooperation early. :-)

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

[PATCH 1/6] ARM: mx51: clean up mx51 header

[Uwe Kleine-König]

This makes the header more look like the other ones, i.e.

 - sort #defines by value
 - use lowercase hex constants
 - use a consistently named header guard

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
 arch/arm/plat-mxc/include/mach/mx51.h |  608 ++++++++++++++++-----------------
 1 files changed, 300 insertions(+), 308 deletions(-)

diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
index 5aad344..92b39f7 100644
--- a/arch/arm/plat-mxc/include/mach/mx51.h
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_ARCH_MXC_MX51_H__
-#define __ASM_ARCH_MXC_MX51_H__
+#ifndef __MACH_MX51_H__
+#define __MACH_MX51_H__
 
 /*
  * MX51 memory map:
@@ -7,24 +7,23 @@
  *
  * Virt		Phys		Size	What
  * ---------------------------------------------------------------------------
- * FA3E0000	1FFE0000	128K	IRAM (SCCv2 RAM)
+ * fa3e0000	1ffe0000	128K	IRAM (SCCv2 RAM)
  *         	30000000	256M	GPU
  *         	40000000	512M	IPU
- * FA200000	60000000	1M	DEBUG
- * FB100000	70000000	1M	SPBA 0
- * FB000000	73F00000	1M	AIPS 1
- * FB200000	83F00000	1M	AIPS 2
- *		8FFFC000	16K	TZIC (interrupt controller)
+ * fa200000	60000000	1M	DEBUG
+ * fb100000	70000000	1M	SPBA 0
+ * fb000000	73f00000	1M	AIPS 1
+ * fb200000	83f00000	1M	AIPS 2
+ *		8fffc000	16K	TZIC (interrupt controller)
  *         	90000000	256M	CSD0 SDRAM/DDR
- *         	A0000000	256M	CSD1 SDRAM/DDR
- *         	B0000000	128M	CS0 Flash
- *         	B8000000	128M	CS1 Flash
- *         	C0000000	128M	CS2 Flash
- *         	C8000000	64M	CS3 Flash
- *         	CC000000	32M	CS4 SRAM
- *         	CE000000	32M	CS5 SRAM
- *		CFFF0000	64K	NFC (NAND Flash AXI)
- *
+ *         	a0000000	256M	CSD1 SDRAM/DDR
+ *         	b0000000	128M	CS0 Flash
+ *         	b8000000	128M	CS1 Flash
+ *         	c0000000	128M	CS2 Flash
+ *         	c8000000	64M	CS3 Flash
+ *         	cc000000	32M	CS4 SRAM
+ *         	ce000000	32M	CS5 SRAM
+ *		cfff0000	64K	NFC (NAND Flash AXI)
  */
 
 /*
@@ -36,65 +35,140 @@
 /*
  * IRAM
  */
-#define MX51_IRAM_BASE_ADDR		0x1FFE0000	/* internal ram */
-#define MX51_IRAM_BASE_ADDR_VIRT	0xFA3E0000
+#define MX51_IRAM_BASE_ADDR		0x1ffe0000	/* internal ram */
+#define MX51_IRAM_BASE_ADDR_VIRT	0xfa3e0000
 #define MX51_IRAM_PARTITIONS		16
-#define MX51_IRAM_PARTITIONS_TO1	12
 #define MX51_IRAM_SIZE		(MX51_IRAM_PARTITIONS * SZ_8K)	/* 128KB */
 
+#define MX51_GPU_BASE_ADDR		0x20000000
+#define MX51_GPU_CTRL_BASE_ADDR		0x30000000
+#define MX51_IPU_CTRL_BASE_ADDR		0x40000000
+
+#define MX51_DEBUG_BASE_ADDR		0x60000000
+#define MX51_DEBUG_BASE_ADDR_VIRT	0xfa200000
+#define MX51_DEBUG_SIZE			SZ_1M
+
+#define MX51_ETB_BASE_ADDR		(MX51_DEBUG_BASE_ADDR + 0x01000)
+#define MX51_ETM_BASE_ADDR		(MX51_DEBUG_BASE_ADDR + 0x02000)
+#define MX51_TPIU_BASE_ADDR		(MX51_DEBUG_BASE_ADDR + 0x03000)
+#define MX51_CTI0_BASE_ADDR		(MX51_DEBUG_BASE_ADDR + 0x04000)
+#define MX51_CTI1_BASE_ADDR		(MX51_DEBUG_BASE_ADDR + 0x05000)
+#define MX51_CTI2_BASE_ADDR		(MX51_DEBUG_BASE_ADDR + 0x06000)
+#define MX51_CTI3_BASE_ADDR		(MX51_DEBUG_BASE_ADDR + 0x07000)
+#define MX51_CORTEX_DBG_BASE_ADDR	(MX51_DEBUG_BASE_ADDR + 0x08000)
+
 /*
- * NFC
+ * SPBA global module enabled #0
  */
-#define MX51_NFC_AXI_BASE_ADDR		0xCFFF0000	/* NAND flash AXI */
-#define MX51_NFC_AXI_SIZE		SZ_64K
+#define MX51_SPBA0_BASE_ADDR		0x70000000
+#define MX51_SPBA0_BASE_ADDR_VIRT	0xfb100000
+#define MX51_SPBA0_SIZE			SZ_1M
+
+#define MX51_MMC_SDHC1_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x04000)
+#define MX51_MMC_SDHC2_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x08000)
+#define MX51_UART3_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x0c000)
+#define MX51_CSPI1_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x10000)
+#define MX51_SSI2_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x14000)
+#define MX51_MMC_SDHC3_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x20000)
+#define MX51_MMC_SDHC4_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x24000)
+#define MX51_SPDIF_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x28000)
+#define MX51_ATA_DMA_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x30000)
+#define MX51_SLIM_DMA_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x34000)
+#define MX51_HSI2C_DMA_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x38000)
+#define MX51_SPBA_CTRL_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x3c000)
 
 /*
- * Graphics Memory of GPU
+ * AIPS 1
  */
-#define MX51_GPU_BASE_ADDR		0x20000000
-#define MX51_GPU2D_BASE_ADDR		0xD0000000
+#define MX51_AIPS1_BASE_ADDR		0x73f00000
+#define MX51_AIPS1_BASE_ADDR_VIRT	0xfb000000
+#define MX51_AIPS1_SIZE			SZ_1M
+
+#define MX51_OTG_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0x80000)
+#define MX51_GPIO1_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0x84000)
+#define MX51_GPIO2_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0x88000)
+#define MX51_GPIO3_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0x8c000)
+#define MX51_GPIO4_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0x90000)
+#define MX51_KPP_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0x94000)
+#define MX51_WDOG_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0x98000)
+#define MX51_WDOG2_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0x9c000)
+#define MX51_GPT1_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0xa0000)
+#define MX51_SRTC_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0xa4000)
+#define MX51_IOMUXC_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0xa8000)
+#define MX51_EPIT1_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0xac000)
+#define MX51_EPIT2_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0xb0000)
+#define MX51_PWM1_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0xb4000)
+#define MX51_PWM2_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0xb8000)
+#define MX51_UART1_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0xbc000)
+#define MX51_UART2_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0xc0000)
+#define MX51_SRC_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0xd0000)
+#define MX51_CCM_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0xd4000)
+#define MX51_GPC_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0xd8000)
 
-#define MX51_TZIC_BASE_ADDR_TO1		0x8FFFC000
-#define MX51_TZIC_BASE_ADDR		0xE0000000
+/*
+ * AIPS 2
+ */
+#define MX51_AIPS2_BASE_ADDR		0x83f00000
+#define MX51_AIPS2_BASE_ADDR_VIRT	0xfb200000
+#define MX51_AIPS2_SIZE			SZ_1M
 
-#define MX51_DEBUG_BASE_ADDR		0x60000000
-#define MX51_DEBUG_BASE_ADDR_VIRT	0xFA200000
-#define MX51_DEBUG_SIZE			SZ_1M
-#define MX51_ETB_BASE_ADDR		(MX51_DEBUG_BASE_ADDR + 0x00001000)
-#define MX51_ETM_BASE_ADDR		(MX51_DEBUG_BASE_ADDR + 0x00002000)
-#define MX51_TPIU_BASE_ADDR		(MX51_DEBUG_BASE_ADDR + 0x00003000)
-#define MX51_CTI0_BASE_ADDR		(MX51_DEBUG_BASE_ADDR + 0x00004000)
-#define MX51_CTI1_BASE_ADDR		(MX51_DEBUG_BASE_ADDR + 0x00005000)
-#define MX51_CTI2_BASE_ADDR		(MX51_DEBUG_BASE_ADDR + 0x00006000)
-#define MX51_CTI3_BASE_ADDR		(MX51_DEBUG_BASE_ADDR + 0x00007000)
-#define MX51_CORTEX_DBG_BASE_ADDR	(MX51_DEBUG_BASE_ADDR + 0x00008000)
+#define MX51_PLL1_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0x80000)
+#define MX51_PLL2_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0x84000)
+#define MX51_PLL3_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0x88000)
+#define MX51_AHBMAX_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0x94000)
+#define MX51_IIM_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0x98000)
+#define MX51_CSU_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0x9c000)
+#define MX51_ARM_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xa0000)
+#define MX51_OWIRE_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xa4000)
+#define MX51_FIRI_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xa8000)
+#define MX51_CSPI2_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xac000)
+#define MX51_SDMA_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xb0000)
+#define MX51_SCC_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xb4000)
+#define MX51_ROMCP_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xb8000)
+#define MX51_RTIC_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xbc000)
+#define MX51_CSPI3_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xc0000)
+#define MX51_I2C2_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xc4000)
+#define MX51_I2C1_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xc8000)
+#define MX51_SSI1_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xcc000)
+#define MX51_AUDMUX_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xd0000)
+#define MX51_M4IF_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xd8000)
+#define MX51_ESDCTL_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xd9000)
+#define MX51_WEIM_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xda000)
+#define MX51_NFC_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xdb000)
+#define MX51_EMI_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xdbf00)
+#define MX51_MIPI_HSC_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xdc000)
+#define MX51_ATA_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xe0000)
+#define MX51_SIM_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xe4000)
+#define MX51_SSI3BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xe8000)
+#define MX51_MXC_FEC_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xec000)
+#define MX51_TVE_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xf0000)
+#define MX51_VPU_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xf4000)
+#define MX51_SAHARA_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xf8000)
+
+#define MX51_CSD0_BASE_ADDR		0x90000000
+#define MX51_CSD1_BASE_ADDR		0xa0000000
+#define MX51_CS0_BASE_ADDR		0xb0000000
+#define MX51_CS1_BASE_ADDR		0xb8000000
+#define MX51_CS2_BASE_ADDR		0xc0000000
+#define MX51_CS3_BASE_ADDR		0xc8000000
+#define MX51_CS4_BASE_ADDR		0xcc000000
+#define MX51_CS5_BASE_ADDR		0xce000000
 
 /*
- * SPBA global module enabled #0
+ * NFC
  */
-#define MX51_SPBA0_BASE_ADDR 		0x70000000
-#define MX51_SPBA0_BASE_ADDR_VIRT	0xFB100000
-#define MX51_SPBA0_SIZE			SZ_1M
+#define MX51_NFC_AXI_BASE_ADDR		0xcfff0000	/* NAND flash AXI */
+#define MX51_NFC_AXI_SIZE		SZ_64K
 
-#define MX51_MMC_SDHC1_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x00004000)
-#define MX51_MMC_SDHC2_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x00008000)
-#define MX51_UART3_BASE_ADDR 		(MX51_SPBA0_BASE_ADDR + 0x0000C000)
-#define MX51_CSPI1_BASE_ADDR 		(MX51_SPBA0_BASE_ADDR + 0x00010000)
-#define MX51_SSI2_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x00014000)
-#define MX51_MMC_SDHC3_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x00020000)
-#define MX51_MMC_SDHC4_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x00024000)
-#define MX51_SPDIF_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x00028000)
-#define MX51_ATA_DMA_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x00030000)
-#define MX51_SLIM_DMA_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x00034000)
-#define MX51_HSI2C_DMA_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x00038000)
-#define MX51_SPBA_CTRL_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x0003C000)
+#define MX51_GPU2D_BASE_ADDR		0xd0000000
+#define MX51_TZIC_BASE_ADDR		0xe0000000
 
 /*
  * defines for SPBA modules
  */
 #define MX51_SPBA_SDHC1	0x04
 #define MX51_SPBA_SDHC2	0x08
-#define MX51_SPBA_UART3	0x0C
+#define MX51_SPBA_UART3	0x0c
 #define MX51_SPBA_CSPI1	0x10
 #define MX51_SPBA_SSI2	0x14
 #define MX51_SPBA_SDHC3	0x20
@@ -103,35 +177,7 @@
 #define MX51_SPBA_ATA	0x30
 #define MX51_SPBA_SLIM	0x34
 #define MX51_SPBA_HSI2C	0x38
-#define MX51_SPBA_CTRL	0x3C
-
-/*
- * AIPS 1
- */
-#define MX51_AIPS1_BASE_ADDR 	0x73F00000
-#define MX51_AIPS1_BASE_ADDR_VIRT	0xFB000000
-#define MX51_AIPS1_SIZE		SZ_1M
-
-#define MX51_OTG_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x00080000)
-#define MX51_GPIO1_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x00084000)
-#define MX51_GPIO2_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x00088000)
-#define MX51_GPIO3_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x0008C000)
-#define MX51_GPIO4_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x00090000)
-#define MX51_KPP_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x00094000)
-#define MX51_WDOG_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x00098000)
-#define MX51_WDOG2_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x0009C000)
-#define MX51_GPT1_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000A0000)
-#define MX51_SRTC_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000A4000)
-#define MX51_IOMUXC_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000A8000)
-#define MX51_EPIT1_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000AC000)
-#define MX51_EPIT2_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000B0000)
-#define MX51_PWM1_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000B4000)
-#define MX51_PWM2_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000B8000)
-#define MX51_UART1_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000BC000)
-#define MX51_UART2_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000C0000)
-#define MX51_SRC_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000D0000)
-#define MX51_CCM_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000D4000)
-#define MX51_GPC_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000D8000)
+#define MX51_SPBA_CTRL	0x3c
 
 /*
  * Defines for modules using static and dynamic DMA channels
@@ -164,60 +210,6 @@
 #define MX51_MXC_DMA_CHANNEL_ATA_TX	MXC_DMA_DYNAMIC_CHANNEL
 #define MX51_MXC_DMA_CHANNEL_MEMORY	MXC_DMA_DYNAMIC_CHANNEL
 
-/*
- * AIPS 2
- */
-#define MX51_AIPS2_BASE_ADDR		0x83F00000
-#define MX51_AIPS2_BASE_ADDR_VIRT	0xFB200000
-#define MX51_AIPS2_SIZE			SZ_1M
-
-#define MX51_PLL1_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x00080000)
-#define MX51_PLL2_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x00084000)
-#define MX51_PLL3_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x00088000)
-#define MX51_AHBMAX_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x00094000)
-#define MX51_IIM_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x00098000)
-#define MX51_CSU_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x0009C000)
-#define MX51_ARM_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000A0000)
-#define MX51_OWIRE_BASE_ADDR 	(MX51_AIPS2_BASE_ADDR + 0x000A4000)
-#define MX51_FIRI_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000A8000)
-#define MX51_CSPI2_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000AC000)
-#define MX51_SDMA_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000B0000)
-#define MX51_SCC_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000B4000)
-#define MX51_ROMCP_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000B8000)
-#define MX51_RTIC_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000BC000)
-#define MX51_CSPI3_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000C0000)
-#define MX51_I2C2_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000C4000)
-#define MX51_I2C1_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000C8000)
-#define MX51_SSI1_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000CC000)
-#define MX51_AUDMUX_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000D0000)
-#define MX51_M4IF_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000D8000)
-#define MX51_ESDCTL_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000D9000)
-#define MX51_WEIM_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000DA000)
-#define MX51_NFC_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000DB000)
-#define MX51_EMI_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000DBF00)
-#define MX51_MIPI_HSC_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000DC000)
-#define MX51_ATA_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000E0000)
-#define MX51_SIM_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000E4000)
-#define MX51_SSI3BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000E8000)
-#define MX51_MXC_FEC_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000EC000)
-#define MX51_TVE_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000F0000)
-#define MX51_VPU_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000F4000)
-#define MX51_SAHARA_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000F8000)
-
-/*
- * Memory regions and CS
- */
-#define MX51_GPU_CTRL_BASE_ADDR		0x30000000
-#define MX51_IPU_CTRL_BASE_ADDR		0x40000000
-#define MX51_CSD0_BASE_ADDR		0x90000000
-#define MX51_CSD1_BASE_ADDR		0xA0000000
-#define MX51_CS0_BASE_ADDR		0xB0000000
-#define MX51_CS1_BASE_ADDR		0xB8000000
-#define MX51_CS2_BASE_ADDR		0xC0000000
-#define MX51_CS3_BASE_ADDR		0xC8000000
-#define MX51_CS4_BASE_ADDR		0xCC000000
-#define MX51_CS5_BASE_ADDR		0xCE000000
-
 /* Does given address belongs to the specified memory region? */
 #define ADDRESS_IN_REGION(addr, start, size)			\
 	(((addr) >= (start)) && ((addr) < (start)+(size)))
@@ -230,7 +222,7 @@
  * This macro defines the physical to virtual address mapping for all the
  * peripheral modules. It is used by passing in the physical address as x
  * and returning the virtual address. If the physical address is not mapped,
- * it returns 0xDEADBEEF
+ * it returns 0xdeadbeef
  */
 
 #define MX51_IO_ADDRESS(x)					\
@@ -240,7 +232,7 @@
 	MX51_IS_MODULE(x, SPBA0) ? MX51_SPBA0_IO_ADDRESS(x) :	\
 	MX51_IS_MODULE(x, AIPS1) ? MX51_AIPS1_IO_ADDRESS(x) :	\
 	MX51_IS_MODULE(x, AIPS2) ? MX51_AIPS2_IO_ADDRESS(x) : \
-	0xDEADBEEF)
+	0xdeadbeef)
 
 /*
  * define the address mapping macros: in physical address order
@@ -265,181 +257,181 @@
 /*
  * DMA request assignments
  */
-#define MX51_DMA_REQ_SSI3_TX1	47
-#define MX51_DMA_REQ_SSI3_RX1	46
-#define MX51_DMA_REQ_SPDIF	45
-#define MX51_DMA_REQ_UART3_TX	44
-#define MX51_DMA_REQ_UART3_RX	43
-#define MX51_DMA_REQ_SLIM_B_TX	42
-#define MX51_DMA_REQ_SDHC4	41
-#define MX51_DMA_REQ_SDHC3	40
-#define MX51_DMA_REQ_CSPI_TX	39
-#define MX51_DMA_REQ_CSPI_RX	38
-#define MX51_DMA_REQ_SSI3_TX2	37
-#define MX51_DMA_REQ_IPU	36
-#define MX51_DMA_REQ_SSI3_RX2	35
-#define MX51_DMA_REQ_EPIT2	34
-#define MX51_DMA_REQ_CTI2_1	33
-#define MX51_DMA_REQ_EMI_WR	32
-#define MX51_DMA_REQ_CTI2_0	31
-#define MX51_DMA_REQ_EMI_RD	30
-#define MX51_DMA_REQ_SSI1_TX1	29
-#define MX51_DMA_REQ_SSI1_RX1	28
-#define MX51_DMA_REQ_SSI1_TX2	27
-#define MX51_DMA_REQ_SSI1_RX2	26
-#define MX51_DMA_REQ_SSI2_TX1	25
-#define MX51_DMA_REQ_SSI2_RX1	24
-#define MX51_DMA_REQ_SSI2_TX2	23
-#define MX51_DMA_REQ_SSI2_RX2	22
-#define MX51_DMA_REQ_SDHC2	21
-#define MX51_DMA_REQ_SDHC1	20
-#define MX51_DMA_REQ_UART1_TX	19
-#define MX51_DMA_REQ_UART1_RX	18
-#define MX51_DMA_REQ_UART2_TX	17
-#define MX51_DMA_REQ_UART2_RX	16
-#define MX51_DMA_REQ_GPU	15
-#define MX51_DMA_REQ_EXTREQ1	14
-#define MX51_DMA_REQ_FIRI_TX	13
-#define MX51_DMA_REQ_FIRI_RX	12
-#define MX51_DMA_REQ_HS_I2C_RX	11
-#define MX51_DMA_REQ_HS_I2C_TX	10
-#define MX51_DMA_REQ_CSPI2_TX	9
-#define MX51_DMA_REQ_CSPI2_RX	8
-#define MX51_DMA_REQ_CSPI1_TX	7
-#define MX51_DMA_REQ_CSPI1_RX	6
-#define MX51_DMA_REQ_SLIM_B	5
-#define MX51_DMA_REQ_ATA_TX_END	4
-#define MX51_DMA_REQ_ATA_TX	3
-#define MX51_DMA_REQ_ATA_RX	2
-#define MX51_DMA_REQ_GPC	1
-#define MX51_DMA_REQ_VPU	0
+#define MX51_DMA_REQ_VPU		0
+#define MX51_DMA_REQ_GPC		1
+#define MX51_DMA_REQ_ATA_RX		2
+#define MX51_DMA_REQ_ATA_TX		3
+#define MX51_DMA_REQ_ATA_TX_END		4
+#define MX51_DMA_REQ_SLIM_B		5
+#define MX51_DMA_REQ_CSPI1_RX		6
+#define MX51_DMA_REQ_CSPI1_TX		7
+#define MX51_DMA_REQ_CSPI2_RX		8
+#define MX51_DMA_REQ_CSPI2_TX		9
+#define MX51_DMA_REQ_HS_I2C_TX		10
+#define MX51_DMA_REQ_HS_I2C_RX		11
+#define MX51_DMA_REQ_FIRI_RX		12
+#define MX51_DMA_REQ_FIRI_TX		13
+#define MX51_DMA_REQ_EXTREQ1		14
+#define MX51_DMA_REQ_GPU		15
+#define MX51_DMA_REQ_UART2_RX		16
+#define MX51_DMA_REQ_UART2_TX		17
+#define MX51_DMA_REQ_UART1_RX		18
+#define MX51_DMA_REQ_UART1_TX		19
+#define MX51_DMA_REQ_SDHC1		20
+#define MX51_DMA_REQ_SDHC2		21
+#define MX51_DMA_REQ_SSI2_RX2		22
+#define MX51_DMA_REQ_SSI2_TX2		23
+#define MX51_DMA_REQ_SSI2_RX1		24
+#define MX51_DMA_REQ_SSI2_TX1		25
+#define MX51_DMA_REQ_SSI1_RX2		26
+#define MX51_DMA_REQ_SSI1_TX2		27
+#define MX51_DMA_REQ_SSI1_RX1		28
+#define MX51_DMA_REQ_SSI1_TX1		29
+#define MX51_DMA_REQ_EMI_RD		30
+#define MX51_DMA_REQ_CTI2_0		31
+#define MX51_DMA_REQ_EMI_WR		32
+#define MX51_DMA_REQ_CTI2_1		33
+#define MX51_DMA_REQ_EPIT2		34
+#define MX51_DMA_REQ_SSI3_RX2		35
+#define MX51_DMA_REQ_IPU		36
+#define MX51_DMA_REQ_SSI3_TX2		37
+#define MX51_DMA_REQ_CSPI_RX		38
+#define MX51_DMA_REQ_CSPI_TX		39
+#define MX51_DMA_REQ_SDHC3		40
+#define MX51_DMA_REQ_SDHC4		41
+#define MX51_DMA_REQ_SLIM_B_TX		42
+#define MX51_DMA_REQ_UART3_RX		43
+#define MX51_DMA_REQ_UART3_TX		44
+#define MX51_DMA_REQ_SPDIF		45
+#define MX51_DMA_REQ_SSI3_RX1		46
+#define MX51_DMA_REQ_SSI3_TX1		47
 
 /*
  * Interrupt numbers
  */
-#define MX51_MXC_INT_BASE	0
-#define MX51_MXC_INT_RESV0	0
-#define MX51_MXC_INT_MMC_SDHC1	1
-#define MX51_MXC_INT_MMC_SDHC2	2
-#define MX51_MXC_INT_MMC_SDHC3	3
-#define MX51_MXC_INT_MMC_SDHC4	4
-#define MX51_MXC_INT_RESV5	5
-#define MX51_MXC_INT_SDMA	6
-#define MX51_MXC_INT_IOMUX	7
-#define MX51_MXC_INT_NFC	8
-#define MX51_MXC_INT_VPU	9
-#define MX51_MXC_INT_IPU_ERR	10
-#define MX51_MXC_INT_IPU_SYN	11
-#define MX51_MXC_INT_GPU	12
-#define MX51_MXC_INT_RESV13	13
-#define MX51_MXC_INT_USB_H1	14
-#define MX51_MXC_INT_EMI	15
-#define MX51_MXC_INT_USB_H2	16
-#define MX51_MXC_INT_USB_H3	17
-#define MX51_MXC_INT_USB_OTG	18
-#define MX51_MXC_INT_SAHARA_H0	19
-#define MX51_MXC_INT_SAHARA_H1	20
-#define MX51_MXC_INT_SCC_SMN	21
-#define MX51_MXC_INT_SCC_STZ	22
-#define MX51_MXC_INT_SCC_SCM	23
-#define MX51_MXC_INT_SRTC_NTZ	24
-#define MX51_MXC_INT_SRTC_TZ	25
-#define MX51_MXC_INT_RTIC	26
-#define MX51_MXC_INT_CSU	27
-#define MX51_MXC_INT_SLIM_B	28
-#define MX51_MXC_INT_SSI1	29
-#define MX51_MXC_INT_SSI2	30
-#define MX51_MXC_INT_UART1	31
-#define MX51_MXC_INT_UART2	32
-#define MX51_MXC_INT_UART3	33
-#define MX51_MXC_INT_RESV34	34
-#define MX51_MXC_INT_RESV35	35
-#define MX51_MXC_INT_CSPI1	36
-#define MX51_MXC_INT_CSPI2	37
-#define MX51_MXC_INT_CSPI	38
-#define MX51_MXC_INT_GPT	39
-#define MX51_MXC_INT_EPIT1	40
-#define MX51_MXC_INT_EPIT2	41
-#define MX51_MXC_INT_GPIO1_INT7	42
-#define MX51_MXC_INT_GPIO1_INT6	43
-#define MX51_MXC_INT_GPIO1_INT5	44
-#define MX51_MXC_INT_GPIO1_INT4	45
-#define MX51_MXC_INT_GPIO1_INT3	46
-#define MX51_MXC_INT_GPIO1_INT2	47
-#define MX51_MXC_INT_GPIO1_INT1	48
-#define MX51_MXC_INT_GPIO1_INT0	49
-#define MX51_MXC_INT_GPIO1_LOW	50
-#define MX51_MXC_INT_GPIO1_HIGH	51
-#define MX51_MXC_INT_GPIO2_LOW	52
-#define MX51_MXC_INT_GPIO2_HIGH	53
-#define MX51_MXC_INT_GPIO3_LOW	54
-#define MX51_MXC_INT_GPIO3_HIGH	55
-#define MX51_MXC_INT_GPIO4_LOW	56
-#define MX51_MXC_INT_GPIO4_HIGH	57
-#define MX51_MXC_INT_WDOG1	58
-#define MX51_MXC_INT_WDOG2	59
-#define MX51_MXC_INT_KPP	60
-#define MX51_MXC_INT_PWM1	61
-#define MX51_MXC_INT_I2C1	62
-#define MX51_MXC_INT_I2C2	63
-#define MX51_MXC_INT_HS_I2C	64
-#define MX51_MXC_INT_RESV65	65
-#define MX51_MXC_INT_RESV66	66
-#define MX51_MXC_INT_SIM_IPB	67
-#define MX51_MXC_INT_SIM_DAT	68
-#define MX51_MXC_INT_IIM	69
-#define MX51_MXC_INT_ATA	70
-#define MX51_MXC_INT_CCM1	71
-#define MX51_MXC_INT_CCM2	72
-#define MX51_MXC_INT_GPC1	73
-#define MX51_MXC_INT_GPC2	74
-#define MX51_MXC_INT_SRC	75
-#define MX51_MXC_INT_NM		76
-#define MX51_MXC_INT_PMU	77
-#define MX51_MXC_INT_CTI_IRQ	78
-#define MX51_MXC_INT_CTI1_TG0	79
-#define MX51_MXC_INT_CTI1_TG1	80
-#define MX51_MXC_INT_MCG_ERR	81
-#define MX51_MXC_INT_MCG_TMR	82
-#define MX51_MXC_INT_MCG_FUNC	83
-#define MX51_MXC_INT_GPU2_IRQ	84
-#define MX51_MXC_INT_GPU2_BUSY	85
-#define MX51_MXC_INT_RESV86	86
-#define MX51_MXC_INT_FEC	87
-#define MX51_MXC_INT_OWIRE	88
-#define MX51_MXC_INT_CTI1_TG2	89
-#define MX51_MXC_INT_SJC	90
-#define MX51_MXC_INT_SPDIF	91
-#define MX51_MXC_INT_TVE	92
-#define MX51_MXC_INT_FIRI	93
-#define MX51_MXC_INT_PWM2	94
-#define MX51_MXC_INT_SLIM_EXP	95
-#define MX51_MXC_INT_SSI3	96
-#define MX51_MXC_INT_EMI_BOOT	97
-#define MX51_MXC_INT_CTI1_TG3	98
-#define MX51_MXC_INT_SMC_RX	99
-#define MX51_MXC_INT_VPU_IDLE	100
-#define MX51_MXC_INT_EMI_NFC	101
-#define MX51_MXC_INT_GPU_IDLE	102
+#define MX51_MXC_INT_BASE		0
+#define MX51_MXC_INT_RESV0		0
+#define MX51_MXC_INT_MMC_SDHC1		1
+#define MX51_MXC_INT_MMC_SDHC2		2
+#define MX51_MXC_INT_MMC_SDHC3		3
+#define MX51_MXC_INT_MMC_SDHC4		4
+#define MX51_MXC_INT_RESV5		5
+#define MX51_MXC_INT_SDMA		6
+#define MX51_MXC_INT_IOMUX		7
+#define MX51_MXC_INT_NFC		8
+#define MX51_MXC_INT_VPU		9
+#define MX51_MXC_INT_IPU_ERR		10
+#define MX51_MXC_INT_IPU_SYN		11
+#define MX51_MXC_INT_GPU		12
+#define MX51_MXC_INT_RESV13		13
+#define MX51_MXC_INT_USB_H1		14
+#define MX51_MXC_INT_EMI		15
+#define MX51_MXC_INT_USB_H2		16
+#define MX51_MXC_INT_USB_H3		17
+#define MX51_MXC_INT_USB_OTG		18
+#define MX51_MXC_INT_SAHARA_H0		19
+#define MX51_MXC_INT_SAHARA_H1		20
+#define MX51_MXC_INT_SCC_SMN		21
+#define MX51_MXC_INT_SCC_STZ		22
+#define MX51_MXC_INT_SCC_SCM		23
+#define MX51_MXC_INT_SRTC_NTZ		24
+#define MX51_MXC_INT_SRTC_TZ		25
+#define MX51_MXC_INT_RTIC		26
+#define MX51_MXC_INT_CSU		27
+#define MX51_MXC_INT_SLIM_B		28
+#define MX51_MXC_INT_SSI1		29
+#define MX51_MXC_INT_SSI2		30
+#define MX51_MXC_INT_UART1		31
+#define MX51_MXC_INT_UART2		32
+#define MX51_MXC_INT_UART3		33
+#define MX51_MXC_INT_RESV34		34
+#define MX51_MXC_INT_RESV35		35
+#define MX51_MXC_INT_CSPI1		36
+#define MX51_MXC_INT_CSPI2		37
+#define MX51_MXC_INT_CSPI		38
+#define MX51_MXC_INT_GPT		39
+#define MX51_MXC_INT_EPIT1		40
+#define MX51_MXC_INT_EPIT2		41
+#define MX51_MXC_INT_GPIO1_INT7		42
+#define MX51_MXC_INT_GPIO1_INT6		43
+#define MX51_MXC_INT_GPIO1_INT5		44
+#define MX51_MXC_INT_GPIO1_INT4		45
+#define MX51_MXC_INT_GPIO1_INT3		46
+#define MX51_MXC_INT_GPIO1_INT2		47
+#define MX51_MXC_INT_GPIO1_INT1		48
+#define MX51_MXC_INT_GPIO1_INT0		49
+#define MX51_MXC_INT_GPIO1_LOW		50
+#define MX51_MXC_INT_GPIO1_HIGH		51
+#define MX51_MXC_INT_GPIO2_LOW		52
+#define MX51_MXC_INT_GPIO2_HIGH		53
+#define MX51_MXC_INT_GPIO3_LOW		54
+#define MX51_MXC_INT_GPIO3_HIGH		55
+#define MX51_MXC_INT_GPIO4_LOW		56
+#define MX51_MXC_INT_GPIO4_HIGH		57
+#define MX51_MXC_INT_WDOG1		58
+#define MX51_MXC_INT_WDOG2		59
+#define MX51_MXC_INT_KPP		60
+#define MX51_MXC_INT_PWM1		61
+#define MX51_MXC_INT_I2C1		62
+#define MX51_MXC_INT_I2C2		63
+#define MX51_MXC_INT_HS_I2C		64
+#define MX51_MXC_INT_RESV65		65
+#define MX51_MXC_INT_RESV66		66
+#define MX51_MXC_INT_SIM_IPB		67
+#define MX51_MXC_INT_SIM_DAT		68
+#define MX51_MXC_INT_IIM		69
+#define MX51_MXC_INT_ATA		70
+#define MX51_MXC_INT_CCM1		71
+#define MX51_MXC_INT_CCM2		72
+#define MX51_MXC_INT_GPC1		73
+#define MX51_MXC_INT_GPC2		74
+#define MX51_MXC_INT_SRC		75
+#define MX51_MXC_INT_NM			76
+#define MX51_MXC_INT_PMU		77
+#define MX51_MXC_INT_CTI_IRQ		78
+#define MX51_MXC_INT_CTI1_TG0		79
+#define MX51_MXC_INT_CTI1_TG1		80
+#define MX51_MXC_INT_MCG_ERR		81
+#define MX51_MXC_INT_MCG_TMR		82
+#define MX51_MXC_INT_MCG_FUNC		83
+#define MX51_MXC_INT_GPU2_IRQ		84
+#define MX51_MXC_INT_GPU2_BUSY		85
+#define MX51_MXC_INT_RESV86		86
+#define MX51_MXC_INT_FEC		87
+#define MX51_MXC_INT_OWIRE		88
+#define MX51_MXC_INT_CTI1_TG2		89
+#define MX51_MXC_INT_SJC		90
+#define MX51_MXC_INT_SPDIF		91
+#define MX51_MXC_INT_TVE		92
+#define MX51_MXC_INT_FIRI		93
+#define MX51_MXC_INT_PWM2		94
+#define MX51_MXC_INT_SLIM_EXP		95
+#define MX51_MXC_INT_SSI3		96
+#define MX51_MXC_INT_EMI_BOOT		97
+#define MX51_MXC_INT_CTI1_TG3		98
+#define MX51_MXC_INT_SMC_RX		99
+#define MX51_MXC_INT_VPU_IDLE		100
+#define MX51_MXC_INT_EMI_NFC		101
+#define MX51_MXC_INT_GPU_IDLE		102
 
 /* silicon revisions specific to i.MX51 */
-#define MX51_CHIP_REV_1_0	0x10
-#define MX51_CHIP_REV_1_1	0x11
-#define MX51_CHIP_REV_1_2	0x12
-#define MX51_CHIP_REV_1_3	0x13
-#define MX51_CHIP_REV_2_0	0x20
-#define MX51_CHIP_REV_2_1	0x21
-#define MX51_CHIP_REV_2_2	0x22
-#define MX51_CHIP_REV_2_3	0x23
-#define MX51_CHIP_REV_3_0	0x30
-#define MX51_CHIP_REV_3_1	0x31
-#define MX51_CHIP_REV_3_2	0x32
-
-/* Mandatory defines used globally */
+#define MX51_CHIP_REV_1_0		0x10
+#define MX51_CHIP_REV_1_1		0x11
+#define MX51_CHIP_REV_1_2		0x12
+#define MX51_CHIP_REV_1_3		0x13
+#define MX51_CHIP_REV_2_0		0x20
+#define MX51_CHIP_REV_2_1		0x21
+#define MX51_CHIP_REV_2_2		0x22
+#define MX51_CHIP_REV_2_3		0x23
+#define MX51_CHIP_REV_3_0		0x30
+#define MX51_CHIP_REV_3_1		0x31
+#define MX51_CHIP_REV_3_2		0x32
 
 #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
-
 extern int mx51_revision(void);
 #endif
 
-#endif	/*  __ASM_ARCH_MXC_MX51_H__ */
+/* tape-out 1 defines */
+#define MX51_TZIC_BASE_ADDR_TO1		0x8fffc000
+
+#endif	/* ifndef __MACH_MX51_H__ */
-- 
1.7.1


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[PATCH 2/6] ARM: mx51: fix naming of spi related defines

[Uwe Kleine-König]

The names used now match the processor's reference manual.  Also remove
MXC from the interrupt defines to match the other imx platforms.

Acked-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
 arch/arm/plat-mxc/include/mach/mx51.h |   12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
index 92b39f7..d0fda39 100644
--- a/arch/arm/plat-mxc/include/mach/mx51.h
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -67,7 +67,7 @@
 #define MX51_MMC_SDHC1_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x04000)
 #define MX51_MMC_SDHC2_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x08000)
 #define MX51_UART3_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x0c000)
-#define MX51_CSPI1_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x10000)
+#define MX51_ECSPI1_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x10000)
 #define MX51_SSI2_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x14000)
 #define MX51_MMC_SDHC3_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x20000)
 #define MX51_MMC_SDHC4_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x24000)
@@ -121,12 +121,12 @@
 #define MX51_ARM_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xa0000)
 #define MX51_OWIRE_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xa4000)
 #define MX51_FIRI_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xa8000)
-#define MX51_CSPI2_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xac000)
+#define MX51_ECSPI2_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xac000)
 #define MX51_SDMA_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xb0000)
 #define MX51_SCC_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xb4000)
 #define MX51_ROMCP_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xb8000)
 #define MX51_RTIC_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xbc000)
-#define MX51_CSPI3_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xc0000)
+#define MX51_CSPI_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xc0000)
 #define MX51_I2C2_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xc4000)
 #define MX51_I2C1_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xc8000)
 #define MX51_SSI1_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xcc000)
@@ -346,9 +346,9 @@
 #define MX51_MXC_INT_UART3		33
 #define MX51_MXC_INT_RESV34		34
 #define MX51_MXC_INT_RESV35		35
-#define MX51_MXC_INT_CSPI1		36
-#define MX51_MXC_INT_CSPI2		37
-#define MX51_MXC_INT_CSPI		38
+#define MX51_INT_ECSPI1			36
+#define MX51_INT_ECSPI2			37
+#define MX51_INT_CSPI			38
 #define MX51_MXC_INT_GPT		39
 #define MX51_MXC_INT_EPIT1		40
 #define MX51_MXC_INT_EPIT2		41
-- 
1.7.1


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[PATCH 3/6] ARM: imx: change the way spi-imx devices are registered

[Uwe Kleine-König]

Similar to the change done earlier for imx-uart devices group soc specific
data in a global struct instead of repeating it for each call to
imxXX_add_spi_imxX.

Acked-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
 arch/arm/mach-imx/devices-imx21.h               |    9 ++-
 arch/arm/mach-imx/devices-imx27.h               |   12 ++--
 arch/arm/mach-mx25/devices-imx25.h              |   12 ++--
 arch/arm/mach-mx3/devices-imx31.h               |   12 ++--
 arch/arm/mach-mx3/devices-imx35.h               |    9 ++-
 arch/arm/plat-mxc/devices/platform-spi_imx.c    |   76 ++++++++++++++++++++---
 arch/arm/plat-mxc/include/mach/devices-common.h |   10 +++-
 7 files changed, 103 insertions(+), 37 deletions(-)

diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h
index 42788e9..5cd991a 100644
--- a/arch/arm/mach-imx/devices-imx21.h
+++ b/arch/arm/mach-imx/devices-imx21.h
@@ -24,7 +24,8 @@
 #define imx21_add_mxc_nand(pdata)	\
 	imx_add_mxc_nand_v1(MX21_NFC_BASE_ADDR, MX21_INT_NANDFC, pdata)
 
-#define imx21_add_spi_imx0(pdata)	\
-	imx_add_spi_imx(0, MX21_CSPI1_BASE_ADDR, SZ_4K, MX21_INT_CSPI1, pdata)
-#define imx21_add_spi_imx1(pdata)	\
-	imx_add_spi_imx(1, MX21_CSPI2_BASE_ADDR, SZ_4K, MX21_INT_CSPI2, pdata)
+extern const struct imx_spi_imx_data imx21_spi_imx_data[] __initconst;
+#define imx21_add_spi_imx(id, pdata)	\
+	imx_add_spi_imx(&imx21_spi_imx_data[id], pdata)
+#define imx21_add_spi_imx0(pdata)	imx21_add_spi_imx(0, pdata)
+#define imx21_add_spi_imx1(pdata)	imx21_add_spi_imx(1, pdata)
diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h
index 65e7bb7..ed37afd 100644
--- a/arch/arm/mach-imx/devices-imx27.h
+++ b/arch/arm/mach-imx/devices-imx27.h
@@ -30,9 +30,9 @@
 #define imx27_add_mxc_nand(pdata)	\
 	imx_add_mxc_nand_v1(MX27_NFC_BASE_ADDR, MX27_INT_NANDFC, pdata)
 
-#define imx27_add_spi_imx0(pdata)	\
-	imx_add_spi_imx(0, MX27_CSPI1_BASE_ADDR, SZ_4K, MX27_INT_CSPI1, pdata)
-#define imx27_add_spi_imx1(pdata)	\
-	imx_add_spi_imx(1, MX27_CSPI2_BASE_ADDR, SZ_4K, MX27_INT_CSPI2, pdata)
-#define imx27_add_spi_imx2(pdata)	\
-	imx_add_spi_imx(2, MX27_CSPI3_BASE_ADDR, SZ_4K, MX27_INT_CSPI3, pdata)
+extern const struct imx_spi_imx_data imx27_spi_imx_data[] __initconst;
+#define imx27_add_spi_imx(id, pdata)	\
+	imx_add_spi_imx(&imx27_spi_imx_data[id], pdata)
+#define imx27_add_spi_imx0(pdata)	imx27_add_spi_imx(0, pdata)
+#define imx27_add_spi_imx1(pdata)	imx27_add_spi_imx(1, pdata)
+#define imx27_add_spi_imx2(pdata)	imx27_add_spi_imx(2, pdata)
diff --git a/arch/arm/mach-mx25/devices-imx25.h b/arch/arm/mach-mx25/devices-imx25.h
index d86a7c3..34a7061 100644
--- a/arch/arm/mach-mx25/devices-imx25.h
+++ b/arch/arm/mach-mx25/devices-imx25.h
@@ -35,9 +35,9 @@
 #define imx25_add_mxc_nand(pdata)	\
 	imx_add_mxc_nand_v21(MX25_NFC_BASE_ADDR, MX25_INT_NANDFC, pdata)
 
-#define imx25_add_spi_imx0(pdata)	\
-	imx_add_spi_imx(0, MX25_CSPI1_BASE_ADDR, SZ_16K, MX25_INT_CSPI1, pdata)
-#define imx25_add_spi_imx1(pdata)	\
-	imx_add_spi_imx(1, MX25_CSPI2_BASE_ADDR, SZ_16K, MX25_INT_CSPI2, pdata)
-#define imx25_add_spi_imx2(pdata)	\
-	imx_add_spi_imx(2, MX25_CSPI3_BASE_ADDR, SZ_16K, MX25_INT_CSPI3, pdata)
+extern const struct imx_spi_imx_data imx25_spi_imx_data[] __initconst;
+#define imx25_add_spi_imx(id, pdata)	\
+	imx_add_spi_imx(&imx25_spi_imx_data[id], pdata)
+#define imx25_add_spi_imx0(pdata)	imx25_add_spi_imx(0, pdata)
+#define imx25_add_spi_imx1(pdata)	imx25_add_spi_imx(1, pdata)
+#define imx25_add_spi_imx2(pdata)	imx25_add_spi_imx(2, pdata)
diff --git a/arch/arm/mach-mx3/devices-imx31.h b/arch/arm/mach-mx3/devices-imx31.h
index 3b1a44a..9fe00b2 100644
--- a/arch/arm/mach-mx3/devices-imx31.h
+++ b/arch/arm/mach-mx3/devices-imx31.h
@@ -30,9 +30,9 @@
 #define imx31_add_mxc_nand(pdata)	\
 	imx_add_mxc_nand_v1(MX31_NFC_BASE_ADDR, MX31_INT_NANDFC, pdata)
 
-#define imx31_add_spi_imx0(pdata)	\
-	imx_add_spi_imx(0, MX31_CSPI1_BASE_ADDR, SZ_4K, MX31_INT_CSPI1, pdata)
-#define imx31_add_spi_imx1(pdata)	\
-	imx_add_spi_imx(1, MX31_CSPI2_BASE_ADDR, SZ_4K, MX31_INT_CSPI2, pdata)
-#define imx31_add_spi_imx2(pdata)	\
-	imx_add_spi_imx(2, MX31_CSPI3_BASE_ADDR, SZ_4K, MX31_INT_CSPI3, pdata)
+extern const struct imx_spi_imx_data imx31_spi_imx_data[] __initconst;
+#define imx31_add_spi_imx(id, pdata)	\
+	imx_add_spi_imx(&imx31_spi_imx_data[id], pdata)
+#define imx31_add_spi_imx0(pdata)	imx31_add_spi_imx(0, pdata)
+#define imx31_add_spi_imx1(pdata)	imx31_add_spi_imx(1, pdata)
+#define imx31_add_spi_imx2(pdata)	imx31_add_spi_imx(2, pdata)
diff --git a/arch/arm/mach-mx3/devices-imx35.h b/arch/arm/mach-mx3/devices-imx35.h
index f6a431a..9972ffc 100644
--- a/arch/arm/mach-mx3/devices-imx35.h
+++ b/arch/arm/mach-mx3/devices-imx35.h
@@ -31,7 +31,8 @@
 #define imx35_add_mxc_nand(pdata)	\
 	imx_add_mxc_nand_v21(MX35_NFC_BASE_ADDR, MX35_INT_NANDFC, pdata)
 
-#define imx35_add_spi_imx0(pdata)	\
-	imx_add_spi_imx(0, MX35_CSPI1_BASE_ADDR, SZ_4K, MX35_INT_CSPI1, pdata)
-#define imx35_add_spi_imx1(pdata)	\
-	imx_add_spi_imx(1, MX35_CSPI2_BASE_ADDR, SZ_4K, MX35_INT_CSPI2, pdata)
+extern const struct imx_spi_imx_data imx35_spi_imx_data[] __initconst;
+#define imx35_add_spi_imx(id, pdata)	\
+	imx_add_spi_imx(&imx35_spi_imx_data[id], pdata)
+#define imx35_add_spi_imx0(pdata)	imx35_add_spi_imx(0, pdata)
+#define imx35_add_spi_imx1(pdata)	imx35_add_spi_imx(1, pdata)
diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c
index 2831a6d..7b7b005 100644
--- a/arch/arm/plat-mxc/devices/platform-spi_imx.c
+++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c
@@ -6,25 +6,83 @@
  * the terms of the GNU General Public License version 2 as published by the
  * Free Software Foundation.
  */
-#include <asm/sizes.h>
+#include <mach/hardware.h>
 #include <mach/devices-common.h>
 
-struct platform_device *__init imx_add_spi_imx(int id,
-		resource_size_t iobase, resource_size_t iosize, int irq,
+#define imx_spi_imx_data_entry_single(soc, type, _name, _id, _hwid, _size) \
+	{								\
+		.id = _id,						\
+		.iobase = soc ## _ ## type ## _hwid ## _BASE_ADDR,	\
+		.iosize = _size,					\
+		.irq = soc ## _INT_ ## type ## _hwid,			\
+	}
+
+#define imx_spi_imx_data_entry(soc, type, name, _id, _hwid, _size)	\
+	[_id] = imx_spi_imx_data_entry_single(soc, type, _name, _id, _hwid, _size)
+
+#ifdef CONFIG_SOC_IMX21
+const struct imx_spi_imx_data imx21_spi_imx_data[] __initconst = {
+#define imx21_spi_imx_data_entry(_id, _hwid)                            \
+	imx_spi_imx_data_entry(MX21, CSPI, "imx21-cspi", _id, _hwid, SZ_4K)
+	imx21_spi_imx_data_entry(0, 1),
+	imx21_spi_imx_data_entry(1, 2),
+#endif
+
+#ifdef CONFIG_ARCH_MX25
+const struct imx_spi_imx_data imx25_spi_imx_data[] __initconst = {
+#define imx25_spi_imx_data_entry(_id, _hwid)				\
+	imx_spi_imx_data_entry(MX25, CSPI, "imx25-cspi", _id, _hwid, SZ_16K)
+	imx25_spi_imx_data_entry(0, 1),
+	imx25_spi_imx_data_entry(1, 2),
+	imx25_spi_imx_data_entry(2, 3),
+};
+#endif /* ifdef CONFIG_ARCH_MX25 */
+
+#ifdef CONFIG_SOC_IMX27
+const struct imx_spi_imx_data imx27_spi_imx_data[] __initconst = {
+#define imx27_spi_imx_data_entry(_id, _hwid)				\
+	imx_spi_imx_data_entry(MX27, CSPI, "imx27-cspi", _id, _hwid, SZ_4K)
+	imx27_spi_imx_data_entry(0, 1),
+	imx27_spi_imx_data_entry(1, 2),
+	imx27_spi_imx_data_entry(2, 3),
+};
+#endif /* ifdef CONFIG_SOC_IMX27 */
+
+#ifdef CONFIG_ARCH_MX31
+const struct imx_spi_imx_data imx31_spi_imx_data[] __initconst = {
+#define imx31_spi_imx_data_entry(_id, _hwid)				\
+	imx_spi_imx_data_entry(MX31, CSPI, "imx31-cspi", _id, _hwid, SZ_4K)
+	imx31_spi_imx_data_entry(0, 1),
+	imx31_spi_imx_data_entry(1, 2),
+	imx31_spi_imx_data_entry(2, 3),
+};
+#endif /* ifdef CONFIG_ARCH_MX31 */
+
+#ifdef CONFIG_ARCH_MX35
+const struct imx_spi_imx_data imx35_spi_imx_data[] __initconst = {
+#define imx35_spi_imx_data_entry(_id, _hwid)                           \
+	imx_spi_imx_data_entry(MX35, CSPI, "imx35-cspi", _id, _hwid, SZ_4K)
+	imx35_spi_imx_data_entry(0, 1),
+	imx35_spi_imx_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_ARCH_MX35 */
+
+struct platform_device *__init imx_add_spi_imx(
+		const struct imx_spi_imx_data *data,
 		const struct spi_imx_master *pdata)
 {
 	struct resource res[] = {
 		{
-			.start = iobase,
-			.end = iobase + iosize - 1,
+			.start = data->iobase,
+			.end = data->iobase + data->iosize - 1,
 			.flags = IORESOURCE_MEM,
 		}, {
-			.start = irq,
-			.end = irq,
+			.start = data->irq,
+			.end = data->irq,
 			.flags = IORESOURCE_IRQ,
 		},
 	};
 
-	return imx_add_platform_device("spi_imx", id, res, ARRAY_SIZE(res),
-			pdata, sizeof(*pdata));
+	return imx_add_platform_device("spi_imx", data->id,
+			res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
 }
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index c5f68c5..abe12c2 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -55,6 +55,12 @@ struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase,
 		int irq, const struct mxc_nand_platform_data *pdata);
 
 #include <mach/spi.h>
-struct platform_device *__init imx_add_spi_imx(int id,
-		resource_size_t iobase, resource_size_t iosize, int irq,
+struct imx_spi_imx_data {
+	int id;
+	resource_size_t iobase;
+	resource_size_t iosize;
+	int irq;
+};
+struct platform_device *__init imx_add_spi_imx(
+		const struct imx_spi_imx_data *data,
 		const struct spi_imx_master *pdata);
-- 
1.7.1


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[PATCH 4/6] ARM: mx51: Add spi clock and spi_imx device registration

[Uwe Kleine-König]

From: Sascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
 arch/arm/mach-mx5/clock-mx51.c               |   42 ++++++++++++++++++++++++++
 arch/arm/mach-mx5/devices-imx51.h            |   18 +++++++++++
 arch/arm/plat-mxc/devices/platform-spi_imx.c |   17 ++++++++++
 3 files changed, 77 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-mx5/devices-imx51.h

diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c
index 6af69de..9ab4d17 100644
--- a/arch/arm/mach-mx5/clock-mx51.c
+++ b/arch/arm/mach-mx5/clock-mx51.c
@@ -762,6 +762,29 @@ static struct clk kpp_clk = {
 	.id = 0,
 };
 
+static unsigned long clk_cspi_get_rate(struct clk *clk)
+{
+	u32 reg, prediv, podf;
+	unsigned long rate;
+
+	reg = __raw_readl(MXC_CCM_CSCDR2);
+	prediv = ((reg & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) >>
+		  MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET) + 1;
+	if (prediv == 1)
+		BUG();
+	podf = ((reg & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) >>
+		MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET) + 1;
+
+	rate = clk_get_rate(clk->parent) / (prediv * podf);
+
+	return rate;
+}
+
+static struct clk cspi_main_clk = {
+	.parent = &pll3_sw_clk,
+	.get_rate = clk_cspi_get_rate,
+};
+
 #define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s)	\
 	static struct clk name = {			\
 		.id		= i,			\
@@ -810,6 +833,22 @@ DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG10_OFFSET,
 DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
 	NULL, NULL, &ipg_clk, NULL);
 
+/* SPI */
+DEFINE_CLOCK(cspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
+	NULL, NULL, &ipg_clk, &spba_clk);
+DEFINE_CLOCK(cspi1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG10_OFFSET,
+	NULL, NULL, &cspi_main_clk, &cspi1_ipg_clk);
+
+DEFINE_CLOCK(cspi2_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG11_OFFSET,
+	NULL, NULL, &ipg_clk, &spba_clk);
+DEFINE_CLOCK(cspi2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG12_OFFSET,
+	NULL, NULL, &cspi_main_clk, &cspi2_ipg_clk);
+
+DEFINE_CLOCK(cspi3_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
+	NULL, NULL, &ipg_clk, &aips_tz2_clk);
+DEFINE_CLOCK(cspi3_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG13_OFFSET,
+	NULL, NULL, &cspi_main_clk, &cspi3_ipg_clk);
+
 /* FEC */
 DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
 	NULL,  NULL, &ipg_clk, NULL);
@@ -837,6 +876,9 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
 	_REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
 	_REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk)
+	_REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
+	_REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
+	_REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk)
 };
 
 static void clk_tree_init(void)
diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h
new file mode 100644
index 0000000..3901f59
--- /dev/null
+++ b/arch/arm/mach-mx5/devices-imx51.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx51.h>
+#include <mach/devices-common.h>
+
+extern const struct imx_spi_imx_data imx51_cspi_imx_data __initconst;
+#define imx51_add_cspi_imx(pdata)	\
+	imx_add_spi_imx(&imx51_cspi_imx_data, pdata)
+
+extern struct imx_spi_imx_data imx51_ecspi_imx_data[] __initconst;
+#define imx51_add_ecspi_imx(id, pdata)	\
+	imx_add_spi_imx(&imx51_ecspi_imx_data[id], pdata)
diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c
index 7b7b005..077f936 100644
--- a/arch/arm/plat-mxc/devices/platform-spi_imx.c
+++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c
@@ -67,6 +67,23 @@ const struct imx_spi_imx_data imx35_spi_imx_data[] __initconst = {
 };
 #endif /* ifdef CONFIG_ARCH_MX35 */
 
+#ifdef CONFIG_ARCH_MX51
+/*
+ * until the imx-spi supports platform-ids, the cspi device has to use a
+ * different id than the ecspi devices above.  The driver currently hardcodes 2
+ * for the cspi device.
+ */
+const struct imx_spi_imx_data imx51_cspi_imx_data __initconst =
+	imx_spi_imx_data_entry_single(MX51, CSPI, "imx51-cspi", 2, , SZ_4K);
+
+const struct imx_spi_imx_data imx51_ecspi_imx_data[] __initconst = {
+#define imx51_ecspi_imx_data_entry(_id, _hwid)				\
+	imx_spi_imx_data_entry(MX51, ECSPI, "imx51-ecspi", _id, _hwid, SZ_4K)
+	imx51_ecspi_imx_data_entry(0, 1),
+	imx51_ecspi_imx_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_ARCH_MX51 */
+
 struct platform_device *__init imx_add_spi_imx(
 		const struct imx_spi_imx_data *data,
 		const struct spi_imx_master *pdata)
-- 
1.7.1


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Re: [PATCH 4/6] ARM: mx51: Add spi clock and spi_imx device registration

[Jason Wang]

Uwe Kleine-König wrote:
> From: Sascha Hauer <s.hauer@pengutronix.de>
>
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
> ---
>  arch/arm/mach-mx5/clock-mx51.c               |   42 ++++++++++++++++++++++++++
>  arch/arm/mach-mx5/devices-imx51.h            |   18 +++++++++++
>  arch/arm/plat-mxc/devices/platform-spi_imx.c |   17 ++++++++++
>  3 files changed, 77 insertions(+), 0 deletions(-)
>  create mode 100644 arch/arm/mach-mx5/devices-imx51.h
>
> diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c
> index 6af69de..9ab4d17 100644
> --- a/arch/arm/mach-mx5/clock-mx51.c
> +++ b/arch/arm/mach-mx5/clock-mx51.c
> @@ -762,6 +762,29 @@ static struct clk kpp_clk = {
>  	.id = 0,
>  };
>  
> +static unsigned long clk_cspi_get_rate(struct clk *clk)
> +{
> +	u32 reg, prediv, podf;
> +	unsigned long rate;
> +
> +	reg = __raw_readl(MXC_CCM_CSCDR2);
> +	prediv = ((reg & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) >>
> +		  MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET) + 1;
> +	if (prediv == 1)
> +		BUG();
> +	podf = ((reg & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) >>
> +		MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET) + 1;
> +
> +	rate = clk_get_rate(clk->parent) / (prediv * podf);
> +
> +	return rate;
> +}
> +
> +static struct clk cspi_main_clk = {
> +	.parent = &pll3_sw_clk,
> +	.get_rate = clk_cspi_get_rate,
> +};
> +
>  #define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s)	\
>  	static struct clk name = {			\
>  		.id		= i,			\
> @@ -810,6 +833,22 @@ DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG10_OFFSET,
>  DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
>  	NULL, NULL, &ipg_clk, NULL);
>  
> +/* SPI */
> +DEFINE_CLOCK(cspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
> +	NULL, NULL, &ipg_clk, &spba_clk);
> +DEFINE_CLOCK(cspi1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG10_OFFSET,
> +	NULL, NULL, &cspi_main_clk, &cspi1_ipg_clk);
> +
> +DEFINE_CLOCK(cspi2_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG11_OFFSET,
> +	NULL, NULL, &ipg_clk, &spba_clk);
> +DEFINE_CLOCK(cspi2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG12_OFFSET,
> +	NULL, NULL, &cspi_main_clk, &cspi2_ipg_clk);
> +
> +DEFINE_CLOCK(cspi3_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
> +	NULL, NULL, &ipg_clk, &aips_tz2_clk);
> +DEFINE_CLOCK(cspi3_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG13_OFFSET,
> +	NULL, NULL, &cspi_main_clk, &cspi3_ipg_clk);
> +
>   
Here, from "MCIMX51RM Rev. 0 11/2009, chapter 7", the CSPI's direct 
parent clock seems to be
ipg_clk instead of cspi_main_clk.

>  /* FEC */
>  DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
>  	NULL,  NULL, &ipg_clk, NULL);
> @@ -837,6 +876,9 @@ static struct clk_lookup lookups[] = {
>  	_REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
>  	_REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
>  	_REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk)
> +	_REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
> +	_REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
> +	_REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk)
>  };
>  
>  static void clk_tree_init(void)
> diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h
> new file mode 100644
> index 0000000..3901f59
> --- /dev/null
> +++ b/arch/arm/mach-mx5/devices-imx51.h
> @@ -0,0 +1,18 @@
> +/*
> + * Copyright (C) 2010 Pengutronix
> + * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
> + *
> + * This program is free software; you can redistribute it and/or modify it under
> + * the terms of the GNU General Public License version 2 as published by the
> + * Free Software Foundation.
> + */
> +#include <mach/mx51.h>
> +#include <mach/devices-common.h>
> +
> +extern const struct imx_spi_imx_data imx51_cspi_imx_data __initconst;
> +#define imx51_add_cspi_imx(pdata)	\
> +	imx_add_spi_imx(&imx51_cspi_imx_data, pdata)
> +
> +extern struct imx_spi_imx_data imx51_ecspi_imx_data[] __initconst;
> +#define imx51_add_ecspi_imx(id, pdata)	\
> +	imx_add_spi_imx(&imx51_ecspi_imx_data[id], pdata)
> diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c
> index 7b7b005..077f936 100644
> --- a/arch/arm/plat-mxc/devices/platform-spi_imx.c
> +++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c
> @@ -67,6 +67,23 @@ const struct imx_spi_imx_data imx35_spi_imx_data[] __initconst = {
>  };
>  #endif /* ifdef CONFIG_ARCH_MX35 */
>  
> +#ifdef CONFIG_ARCH_MX51
> +/*
> + * until the imx-spi supports platform-ids, the cspi device has to use a
> + * different id than the ecspi devices above.  The driver currently hardcodes 2
> + * for the cspi device.
> + */
> +const struct imx_spi_imx_data imx51_cspi_imx_data __initconst =
> +	imx_spi_imx_data_entry_single(MX51, CSPI, "imx51-cspi", 2, , SZ_4K);
> +
> +const struct imx_spi_imx_data imx51_ecspi_imx_data[] __initconst = {
> +#define imx51_ecspi_imx_data_entry(_id, _hwid)				\
> +	imx_spi_imx_data_entry(MX51, ECSPI, "imx51-ecspi", _id, _hwid, SZ_4K)
> +	imx51_ecspi_imx_data_entry(0, 1),
> +	imx51_ecspi_imx_data_entry(1, 2),
> +};
> +#endif /* ifdef CONFIG_ARCH_MX51 */
> +
>  struct platform_device *__init imx_add_spi_imx(
>  		const struct imx_spi_imx_data *data,
>  		const struct spi_imx_master *pdata)
>   


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[PATCH 5/6] spi-imx: Add i.MX51 support

[Uwe Kleine-König]

From: Sascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/spi/spi_imx.c |  123 +++++++++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 120 insertions(+), 3 deletions(-)

diff --git a/drivers/spi/spi_imx.c b/drivers/spi/spi_imx.c
index 7972e90..5ee2699 100644
--- a/drivers/spi/spi_imx.c
+++ b/drivers/spi/spi_imx.c
@@ -155,6 +155,117 @@ static unsigned int spi_imx_clkdiv_2(unsigned int fin,
 	return 7;
 }
 
+/* MX51 */
+static unsigned int spi_imx_clkdiv_3(unsigned int fin,
+		unsigned int fspi)
+{
+	unsigned int div = 4, post = 0, pre = 0, res;
+
+	div = fin / fspi;
+
+	res = fin;
+	while (res > (fspi * 16)) {
+		post++;
+		res = fin / (1 << post);
+	}
+
+	pre = fin / (1 << post) / fspi;
+
+	return (post & 0xf) | ((pre & 0xf) << 4);
+}
+
+#define MX51_CSPIRXDATA		0x00
+#define MX51_CSPITXDATA		0x04
+#define MX51_CSPICTRL		0x08
+#define MX51_CSPICONFIG		0x0c
+#define MX51_CSPIINT		0x10
+#define MX51_CSPIDMA		0x14
+#define MX51_CSPISTATUS		0x18
+#define MX51_CSPIPERIOD		0x1c
+#define MX51_CSPITEST		0x20
+
+#define MX51_INTREG_TEEN	(1 << 0)
+#define MX51_INTREG_RREN	(1 << 3)
+
+#define MX51_CSPICTRL_ENABLE	(1 << 0)
+#define MX51_CSPICTRL_XCH	(1 << 2)
+#define MX51_CSPICTRL_DIV_SHIFT	8
+#define MX51_CSPICTRL_MASTER(cs)	((1 << (cs)) << 4)
+#define MX51_CSPICTRL_BL_SHIFT	20
+#define MX51_CSPICTRL_CS(cs)	((cs) << 18)
+
+#define MX51_CSPICONFIG_PHA(cs)		((1 << (cs)) << 0)
+#define MX51_CSPICONFIG_POL(cs)		((1 << (cs)) << 4)
+#define MX51_CSPICONFIG_SSBCTRL(cs)	((1 << (cs)) << 8)
+#define MX51_CSPICONFIG_SSBPOL(cs)	((1 << (cs)) << 12)
+#define MX51_CSPICONFIG_DATACTRL(cs)	((1 << (cs)) << 16)
+#define MX51_CSPICONFIG_SCLKCTRL(cs)	((1 << (cs)) << 20)
+
+#define MX51_STATUS_RR		(1 << 3)
+
+#define MX51_CSPITEST_LBC	(1 << 31)
+
+static void mx51_intctrl(struct spi_imx_data *spi_imx, int enable)
+{
+	unsigned int val = 0;
+
+	if (enable & MXC_INT_TE)
+		val |= MX51_INTREG_TEEN;
+	if (enable & MXC_INT_RR)
+		val |= MX51_INTREG_RREN;
+
+	writel(val, spi_imx->base + MX51_CSPIINT);
+}
+
+static void mx51_trigger(struct spi_imx_data *spi_imx)
+{
+	unsigned int reg;
+
+	reg = readl(spi_imx->base + MXC_CSPICTRL);
+	reg |= MX51_CSPICTRL_XCH;
+	writel(reg, spi_imx->base + MXC_CSPICTRL);
+}
+
+static int mx51_config(struct spi_imx_data *spi_imx,
+		struct spi_imx_config *config)
+{
+	int cs;
+	u32 ctrl;
+	u32 cfg = 0;
+
+#ifdef INTERNAL_LOOPBACK
+	writel(MX51_CSPITEST_LBC, spi_imx->base + MX51_CSPITEST);
+#endif
+	if (config->cs < 0)
+		cs = config->cs + 32;
+	else
+		cs = 0;
+
+	ctrl = MX51_CSPICTRL_MASTER(cs) | MX51_CSPICTRL_ENABLE;
+	ctrl |= spi_imx_clkdiv_3(spi_imx->spi_clk, config->speed_hz) <<
+		MX51_CSPICTRL_DIV_SHIFT;
+
+	ctrl |= (config->bpw - 1) << MX51_CSPICTRL_BL_SHIFT;
+	cfg |= MX51_CSPICONFIG_SSBCTRL(cs);
+	if (config->mode & SPI_CPHA)
+		cfg |= MX51_CSPICONFIG_PHA(cs);
+	if (config->mode & SPI_CPOL)
+		cfg |= MX51_CSPICONFIG_POL(cs) | MX51_CSPICONFIG_SCLKCTRL(cs);
+	if (config->mode & SPI_CS_HIGH)
+		cfg |= MX51_CSPICONFIG_SSBPOL(cs);
+	ctrl |= MX51_CSPICTRL_CS(cs);
+
+	writel(ctrl, spi_imx->base + MX51_CSPICTRL);
+	writel(cfg, spi_imx->base + MX51_CSPICONFIG);
+
+	return 0;
+}
+
+static int mx51_rx_available(struct spi_imx_data *spi_imx)
+{
+	return readl(spi_imx->base + MX51_CSPISTATUS) & MX51_STATUS_RR;
+}
+
 #define MX31_INTREG_TEEN	(1 << 0)
 #define MX31_INTREG_RREN	(1 << 3)
 
@@ -209,7 +320,7 @@ static int mx31_config(struct spi_imx_data *spi_imx,
 
 	if (cpu_is_mx31())
 		reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
-	else if (cpu_is_mx25() || cpu_is_mx35()) {
+	else if (cpu_is_mx25() || cpu_is_mx35() || cpu_is_mx51()) {
 		reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
 		reg |= MX31_CSPICTRL_SSCTL;
 	}
@@ -223,7 +334,7 @@ static int mx31_config(struct spi_imx_data *spi_imx,
 	if (config->cs < 0) {
 		if (cpu_is_mx31())
 			reg |= (config->cs + 32) << MX31_CSPICTRL_CS_SHIFT;
-		else if (cpu_is_mx25() || cpu_is_mx35())
+		else if (cpu_is_mx25() || cpu_is_mx35() || cpu_is_mx51())
 			reg |= (config->cs + 32) << MX35_CSPICTRL_CS_SHIFT;
 	}
 
@@ -567,7 +678,8 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
 		goto out_iounmap;
 	}
 
-	if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35()) {
+	if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35() ||
+			(cpu_is_mx51() && pdev->id == 2)) {
 		spi_imx->intctrl = mx31_intctrl;
 		spi_imx->config = mx31_config;
 		spi_imx->trigger = mx31_trigger;
@@ -582,6 +694,11 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
 		spi_imx->config = mx1_config;
 		spi_imx->trigger = mx1_trigger;
 		spi_imx->rx_available = mx1_rx_available;
+	} else if (cpu_is_mx51()) {
+		spi_imx->intctrl = mx51_intctrl;
+		spi_imx->config = mx51_config;
+		spi_imx->trigger = mx51_trigger;
+		spi_imx->rx_available = mx51_rx_available;
 	} else
 		BUG();
 
-- 
1.7.1

Re: [PATCH 5/6] spi-imx: Add i.MX51 support

[Grant Likely]

Hi Uwe,

On Thu, Sep 02, 2010 at 04:42:02PM +0200, Uwe Kleine-König wrote:
> From: Sascha Hauer <s.hauer@pengutronix.de>
> 

A description of what is required to add imx51 support would be
appreciated by us poor patch reviewers.

> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>  drivers/spi/spi_imx.c |  123 +++++++++++++++++++++++++++++++++++++++++++++++-
>  1 files changed, 120 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/spi/spi_imx.c b/drivers/spi/spi_imx.c
> index 7972e90..5ee2699 100644
> --- a/drivers/spi/spi_imx.c
> +++ b/drivers/spi/spi_imx.c
> @@ -155,6 +155,117 @@ static unsigned int spi_imx_clkdiv_2(unsigned int fin,
>  	return 7;
>  }
>  
> +/* MX51 */
> +static unsigned int spi_imx_clkdiv_3(unsigned int fin,
> +		unsigned int fspi)
> +{
> +	unsigned int div = 4, post = 0, pre = 0, res;
> +
> +	div = fin / fspi;
> +
> +	res = fin;
> +	while (res > (fspi * 16)) {
> +		post++;
> +		res = fin / (1 << post);
> +	}
> +
> +	pre = fin / (1 << post) / fspi;
> +
> +	return (post & 0xf) | ((pre & 0xf) << 4);
> +}
> +
> +#define MX51_CSPIRXDATA		0x00
> +#define MX51_CSPITXDATA		0x04
> +#define MX51_CSPICTRL		0x08
> +#define MX51_CSPICONFIG		0x0c
> +#define MX51_CSPIINT		0x10
> +#define MX51_CSPIDMA		0x14
> +#define MX51_CSPISTATUS		0x18
> +#define MX51_CSPIPERIOD		0x1c
> +#define MX51_CSPITEST		0x20
> +
> +#define MX51_INTREG_TEEN	(1 << 0)
> +#define MX51_INTREG_RREN	(1 << 3)
> +
> +#define MX51_CSPICTRL_ENABLE	(1 << 0)
> +#define MX51_CSPICTRL_XCH	(1 << 2)
> +#define MX51_CSPICTRL_DIV_SHIFT	8
> +#define MX51_CSPICTRL_MASTER(cs)	((1 << (cs)) << 4)
> +#define MX51_CSPICTRL_BL_SHIFT	20
> +#define MX51_CSPICTRL_CS(cs)	((cs) << 18)
> +
> +#define MX51_CSPICONFIG_PHA(cs)		((1 << (cs)) << 0)
> +#define MX51_CSPICONFIG_POL(cs)		((1 << (cs)) << 4)
> +#define MX51_CSPICONFIG_SSBCTRL(cs)	((1 << (cs)) << 8)
> +#define MX51_CSPICONFIG_SSBPOL(cs)	((1 << (cs)) << 12)
> +#define MX51_CSPICONFIG_DATACTRL(cs)	((1 << (cs)) << 16)
> +#define MX51_CSPICONFIG_SCLKCTRL(cs)	((1 << (cs)) << 20)
> +
> +#define MX51_STATUS_RR		(1 << 3)
> +
> +#define MX51_CSPITEST_LBC	(1 << 31)
> +
> +static void mx51_intctrl(struct spi_imx_data *spi_imx, int enable)
> +{
> +	unsigned int val = 0;
> +
> +	if (enable & MXC_INT_TE)
> +		val |= MX51_INTREG_TEEN;
> +	if (enable & MXC_INT_RR)
> +		val |= MX51_INTREG_RREN;
> +
> +	writel(val, spi_imx->base + MX51_CSPIINT);
> +}
> +
> +static void mx51_trigger(struct spi_imx_data *spi_imx)
> +{
> +	unsigned int reg;
> +
> +	reg = readl(spi_imx->base + MXC_CSPICTRL);
> +	reg |= MX51_CSPICTRL_XCH;
> +	writel(reg, spi_imx->base + MXC_CSPICTRL);
> +}
> +
> +static int mx51_config(struct spi_imx_data *spi_imx,
> +		struct spi_imx_config *config)
> +{
> +	int cs;
> +	u32 ctrl;
> +	u32 cfg = 0;
> +
> +#ifdef INTERNAL_LOOPBACK
> +	writel(MX51_CSPITEST_LBC, spi_imx->base + MX51_CSPITEST);
> +#endif
> +	if (config->cs < 0)
> +		cs = config->cs + 32;
> +	else
> +		cs = 0;
> +
> +	ctrl = MX51_CSPICTRL_MASTER(cs) | MX51_CSPICTRL_ENABLE;
> +	ctrl |= spi_imx_clkdiv_3(spi_imx->spi_clk, config->speed_hz) <<
> +		MX51_CSPICTRL_DIV_SHIFT;
> +
> +	ctrl |= (config->bpw - 1) << MX51_CSPICTRL_BL_SHIFT;
> +	cfg |= MX51_CSPICONFIG_SSBCTRL(cs);
> +	if (config->mode & SPI_CPHA)
> +		cfg |= MX51_CSPICONFIG_PHA(cs);
> +	if (config->mode & SPI_CPOL)
> +		cfg |= MX51_CSPICONFIG_POL(cs) | MX51_CSPICONFIG_SCLKCTRL(cs);
> +	if (config->mode & SPI_CS_HIGH)
> +		cfg |= MX51_CSPICONFIG_SSBPOL(cs);
> +	ctrl |= MX51_CSPICTRL_CS(cs);
> +
> +	writel(ctrl, spi_imx->base + MX51_CSPICTRL);
> +	writel(cfg, spi_imx->base + MX51_CSPICONFIG);
> +
> +	return 0;
> +}
> +
> +static int mx51_rx_available(struct spi_imx_data *spi_imx)
> +{
> +	return readl(spi_imx->base + MX51_CSPISTATUS) & MX51_STATUS_RR;
> +}
> +
>  #define MX31_INTREG_TEEN	(1 << 0)
>  #define MX31_INTREG_RREN	(1 << 3)
>  
> @@ -209,7 +320,7 @@ static int mx31_config(struct spi_imx_data *spi_imx,
>  
>  	if (cpu_is_mx31())
>  		reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
> -	else if (cpu_is_mx25() || cpu_is_mx35()) {
> +	else if (cpu_is_mx25() || cpu_is_mx35() || cpu_is_mx51()) {
>  		reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
>  		reg |= MX31_CSPICTRL_SSCTL;
>  	}
> @@ -223,7 +334,7 @@ static int mx31_config(struct spi_imx_data *spi_imx,
>  	if (config->cs < 0) {
>  		if (cpu_is_mx31())
>  			reg |= (config->cs + 32) << MX31_CSPICTRL_CS_SHIFT;
> -		else if (cpu_is_mx25() || cpu_is_mx35())
> +		else if (cpu_is_mx25() || cpu_is_mx35() || cpu_is_mx51())
>  			reg |= (config->cs + 32) << MX35_CSPICTRL_CS_SHIFT;
>  	}
>  
> @@ -567,7 +678,8 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
>  		goto out_iounmap;
>  	}
>  
> -	if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35()) {
> +	if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35() ||
> +			(cpu_is_mx51() && pdev->id == 2)) {

These lists are getting a bit silly.  There's got to be a better way.

Otherwise, looks okay.  Reply with an appropriate patch description
and I'll pick it up.

>  		spi_imx->intctrl = mx31_intctrl;
>  		spi_imx->config = mx31_config;
>  		spi_imx->trigger = mx31_trigger;
> @@ -582,6 +694,11 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
>  		spi_imx->config = mx1_config;
>  		spi_imx->trigger = mx1_trigger;
>  		spi_imx->rx_available = mx1_rx_available;
> +	} else if (cpu_is_mx51()) {
> +		spi_imx->intctrl = mx51_intctrl;
> +		spi_imx->config = mx51_config;
> +		spi_imx->trigger = mx51_trigger;
> +		spi_imx->rx_available = mx51_rx_available;
>  	} else
>  		BUG();
>  
> -- 
> 1.7.1
> 

Re: [PATCH 5/6] spi-imx: Add i.MX51 support

[Uwe Kleine-König]

Hi Grant,

On Wed, Sep 08, 2010 at 11:33:16PM -0600, Grant Likely wrote:
> A description of what is required to add imx51 support would be
> appreciated by us poor patch reviewers.
Currently there are two different patches for adding imx51 support, one
by Sascha (sent by me) and one by Jason Wang.

I'll try to pick the best our of both and come back to you, of course
with a nice commit log :-)

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

[PATCH 6/6] ARM: mx5/mx51_babbage: Add spi support

[Uwe Kleine-König]

From: Sascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm/mach-mx5/Kconfig              |    1 +
 arch/arm/mach-mx5/board-mx51_babbage.c |   31 +++++++++++++++++++++++++++++++
 2 files changed, 32 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index 0848db5..f55b0f5 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -10,6 +10,7 @@ comment "MX5 platforms:"
 
 config MACH_MX51_BABBAGE
 	bool "Support MX51 BABBAGE platforms"
+	select IMX_HAVE_PLATFORM_SPI_IMX
 	help
 	  Include support for MX51 Babbage platform, also known as MX51EVK in
 	  u-boot. This includes specific configurations for the board and its
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index 6e384d9..4ed0a9a 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -17,6 +17,7 @@
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/fsl_devices.h>
+#include <linux/spi/spi.h>
 
 #include <mach/common.h>
 #include <mach/hardware.h>
@@ -31,6 +32,7 @@
 #include <asm/mach/arch.h>
 #include <asm/mach/time.h>
 
+#include "devices-imx51.h"
 #include "devices.h"
 
 #define BABBAGE_USB_HUB_RESET	(0*32 + 7)	/* GPIO_1_7 */
@@ -240,6 +242,31 @@ static int __init babbage_otg_mode(char *options)
 }
 __setup("otg_mode=", babbage_otg_mode);
 
+#define BABBAGE_ECSPI1_CS0	(3 * 32 + 24)
+#define BABBAGE_ECSPI1_CS1	(3 * 32 + 25)
+
+static const struct spi_board_info mx51_babbage_spi_board_info[] __initconst = {
+	{
+		/* mc13892 */
+		.modalias = "spidev",
+		.max_speed_hz = 300000,
+		.bus_num = 0,
+		.chip_select = 0,
+	}, {
+		.modalias = "spidev",
+		.max_speed_hz = 300000,
+		.bus_num = 0,
+		.chip_select = 1,
+	},
+};
+
+static int mx51_babbage_ecspi0_cs[] = {BABBAGE_ECSPI1_CS0, BABBAGE_ECSPI1_CS1};
+
+static const struct spi_imx_master mx51_babbage_ecspi0_data __initconst = {
+	.chipselect = mx51_babbage_ecspi0_cs,
+	.num_chipselect = ARRAY_SIZE(mx51_babbage_ecspi0_cs),
+};
+
 /*
  * Board specific initialization.
  */
@@ -268,6 +295,10 @@ static void __init mxc_board_init(void)
 	/* setback USBH1_STP to be function */
 	mxc_iomux_v3_setup_pad(&usbh1stp);
 	babbage_usbhub_reset();
+
+	spi_register_board_info(mx51_babbage_spi_board_info,
+			ARRAY_SIZE(mx51_babbage_spi_board_info));
+	imx51_add_ecspi_imx(0, &mx51_babbage_ecspi0_data);
 }
 
 static void __init mx51_babbage_timer_init(void)
-- 
1.7.1

Re: [PATCH 0/6] add spi support for i.MX51 in the existing spi_imx driver

[Jason Wang]

Uwe Kleine-König wrote:
> Hello Jason,
>
>   
>>> Actually I would prefer our patches, but of course I'm biased :-)
>>>
>>> I don't know how we should handle this.  And Sascha is on vacation this
>>> and next week.  I will investigate if our patches are already free to be
>>> posted.
>>>       
> OK, I can post our patches.  I think the driver part is quite similar,
> the platform part is not.  But look for yourself, I'll post them in reply to
> this mail.  Hopefully we can join forces to get the best out of the two
> approaches.
>   
OK, glad to see the refine of platform header files.
> BTW, we're working on nand (David merged an early patch series by
> Sascha, we have some fixes pending), mc19892 and ipuv3, too.  Just to
> notice the possibility for more cooperation early. :-)
>
>   
Good news, after add sdma, mc13892 and ipuv3, the i.MX51 will
be like a real useful platform. :-)
> Best regards
> Uwe
>
>   

Re: [PATCH 0/6] add spi support for i.MX51 in the existing spi_imx driver

[Amit Kucheria]

On 10 Sep 03, Jason Wang wrote:
> Uwe Kleine-König wrote:
> >Hello Jason,
> >
> >>>Actually I would prefer our patches, but of course I'm biased :-)
> >>>
> >>>I don't know how we should handle this.  And Sascha is on vacation this
> >>>and next week.  I will investigate if our patches are already free to be
> >>>posted.
> >OK, I can post our patches.  I think the driver part is quite similar,
> >the platform part is not.  But look for yourself, I'll post them in reply to
> >this mail.  Hopefully we can join forces to get the best out of the two
> >approaches.
> OK, glad to see the refine of platform header files.
> >BTW, we're working on nand (David merged an early patch series by
> >Sascha, we have some fixes pending), mc19892 and ipuv3, too.  Just to
> >notice the possibility for more cooperation early. :-)
> >
> Good news, after add sdma, mc13892 and ipuv3, the i.MX51 will
> be like a real useful platform. :-)

Jason, Uwe,

Can we put up a wiki page of what drivers are being worked on by who so we
don't work on the same drivers?

We are planning to look at the power management aspects of the i.MX51 at Linaro.

/Amit

-- 
----------------------------------------------------------------------
Amit Kucheria, Kernel Engineer || amit.kucheria@canonical.com
----------------------------------------------------------------------

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Re: [PATCH 0/6] add spi support for i.MX51 in the existing spi_imx driver

[Robert Schwebel]

On Fri, Sep 03, 2010 at 09:41:04AM +0300, Amit Kucheria wrote:
> Can we put up a wiki page of what drivers are being worked on by who so we
> don't work on the same drivers?
> 
> We are planning to look at the power management aspects of the i.MX51 at Linaro.

Something like this: http://www.elinux.org/I.MX
Feel free to optimize the format, it's just a first raw cut.

rsc
-- 
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

Re: [PATCH 0/6] add spi support for i.MX51 in the existing spi_imx driver

[Uwe Kleine-König]

Hello,

On Thu, Sep 02, 2010 at 04:39:08PM +0200, Uwe Kleine-König wrote:
> Hello Jason,
> 
> >> Actually I would prefer our patches, but of course I'm biased :-)
> >>
> >> I don't know how we should handle this.  And Sascha is on vacation this
> >> and next week.  I will investigate if our patches are already free to be
> >> posted.
> OK, I can post our patches.  I think the driver part is quite similar,
> the platform part is not.  But look for yourself, I'll post them in reply to
> this mail.  Hopefully we can join forces to get the best out of the two
> approaches.
I now made the effort to try doing this.  I hope this is OK though it
feels strage that no commit is attributed to Sascha.

The following changes since commit 5b1caa2452a2cf09417ab657ae3a2275ebd78103:

  ARM: mx5/mx51_babbage: Add FEC support (2010-09-13 11:31:22 +0200)

are available in the git repository at:
  git://git.pengutronix.de/git/ukl/linux-2.6.git spi-imx51

(5b1caa2452a2cf09417ab657ae3a2275ebd78103 is the result of rebasing
Sascha's for-2.6.37 branch on top of 2.6.36-rc4---done mainly to contain
the for-2.6.36 branch)

Jason Wang (4):
      ARM: mx5/clock-mx51: add spi clocks
      ARM: mx5/iomux-mx51: add iomux definitions for eCSPI2 on the imx51_3ds board
      ARM: mx5/mx51_3ds: add eCSPI2 support on the imx51_3ds board
      ARM: mx5/mx51_3ds: add SPI NOR flash in the board init stage

Uwe Kleine-König (12):
      spi/imx: default to m on platforms that have such devices
      spi/imx: convert driver to use platform ids
      spi/imx: get rid of more ifs depending on the used cpu
      spi/imx: save the spi chip select in config struct, not the gpio to use
      spi/imx: add support for imx51's eCSPI and CSPI
      ARM: imx: change the way spi-imx devices are registered
      ARM: imx: use platform ids for spi_imx devices
      ARM: mx51: clean up mx51 header
      ARM: mx51: fix naming of spi related defines
      ARM: mx5: add spi_imx device registration
      ARM: mx5/clock-mx51: refactor ccgr callbacks to use common code
      ARM: mx5/clock-mx51: new macro that defines a clk with all members

 arch/arm/mach-imx/clock-imx1.c                  |    2 +-
 arch/arm/mach-imx/clock-imx21.c                 |    6 +-
 arch/arm/mach-imx/clock-imx27.c                 |    6 +-
 arch/arm/mach-imx/devices-imx21.h               |    9 +-
 arch/arm/mach-imx/devices-imx27.h               |   12 +-
 arch/arm/mach-mx25/clock.c                      |    6 +-
 arch/arm/mach-mx25/devices-imx25.h              |   12 +-
 arch/arm/mach-mx3/clock-imx31.c                 |    6 +-
 arch/arm/mach-mx3/clock-imx35.c                 |    4 +-
 arch/arm/mach-mx3/devices-imx31.h               |   12 +-
 arch/arm/mach-mx3/devices-imx35.h               |    9 +-
 arch/arm/mach-mx5/Kconfig                       |    1 +
 arch/arm/mach-mx5/board-mx51_3ds.c              |   33 ++
 arch/arm/mach-mx5/clock-mx51.c                  |  113 ++++-
 arch/arm/mach-mx5/devices-imx51.h               |   18 +
 arch/arm/plat-mxc/devices/platform-spi_imx.c    |   89 +++-
 arch/arm/plat-mxc/include/mach/devices-common.h |   11 +-
 arch/arm/plat-mxc/include/mach/iomux-mx51.h     |    5 +
 arch/arm/plat-mxc/include/mach/mx51.h           |  608 +++++++++++------------
 drivers/spi/Kconfig                             |   16 +
 drivers/spi/spi_imx.c                           |  394 ++++++++++++---
 21 files changed, 919 insertions(+), 453 deletions(-)
 create mode 100644 arch/arm/mach-mx5/devices-imx51.h

Thanks
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

[PATCH 01/16] spi/imx: default to m on platforms that have such devices

[Uwe Kleine-König]

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
 drivers/spi/Kconfig |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 91c2f4f..30aea6d 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -147,6 +147,7 @@ config SPI_IMX
 	tristate "Freescale i.MX SPI controllers"
 	depends on ARCH_MXC
 	select SPI_BITBANG
+	default m if IMX_HAVE_PLATFORM_SPI_IMX
 	help
 	  This enables using the Freescale i.MX SPI controllers in master
 	  mode.
-- 
1.7.2.3


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[PATCH 03/16] spi/imx: get rid of more ifs depending on the used cpu

[Uwe Kleine-König]

Nearly everything that is needed is provided by the version of the SPI IP.
Now the only checks left using cpu_is_... are clk divider tuning on mx21/mx27
and autodetection (which will die soon).

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
 drivers/spi/spi_imx.c |   73 +++++++++++++++++++++++++++++++++++-------------
 1 files changed, 53 insertions(+), 20 deletions(-)

diff --git a/drivers/spi/spi_imx.c b/drivers/spi/spi_imx.c
index 20cdee3..60a52d1 100644
--- a/drivers/spi/spi_imx.c
+++ b/drivers/spi/spi_imx.c
@@ -75,6 +75,7 @@ struct spi_imx_devtype_data {
 	int (*config)(struct spi_imx_data *, struct spi_imx_config *);
 	void (*trigger)(struct spi_imx_data *);
 	int (*rx_available)(struct spi_imx_data *);
+	void (*reset)(struct spi_imx_data *);
 };
 
 struct spi_imx_data {
@@ -213,7 +214,7 @@ static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx)
 	writel(reg, spi_imx->base + MXC_CSPICTRL);
 }
 
-static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx,
+static int __maybe_unused spi_imx0_4_config(struct spi_imx_data *spi_imx,
 		struct spi_imx_config *config)
 {
 	unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
@@ -221,12 +222,7 @@ static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx,
 	reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
 		MX31_CSPICTRL_DR_SHIFT;
 
-	if (cpu_is_mx31())
-		reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
-	else if (cpu_is_mx25() || cpu_is_mx35()) {
-		reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
-		reg |= MX31_CSPICTRL_SSCTL;
-	}
+	reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
 
 	if (config->mode & SPI_CPHA)
 		reg |= MX31_CSPICTRL_PHA;
@@ -235,10 +231,7 @@ static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx,
 	if (config->mode & SPI_CS_HIGH)
 		reg |= MX31_CSPICTRL_SSPOL;
 	if (config->cs < 0) {
-		if (cpu_is_mx31())
-			reg |= (config->cs + 32) << MX31_CSPICTRL_CS_SHIFT;
-		else if (cpu_is_mx25() || cpu_is_mx35())
-			reg |= (config->cs + 32) << MX35_CSPICTRL_CS_SHIFT;
+		reg |= (config->cs + 32) << MX31_CSPICTRL_CS_SHIFT;
 	}
 
 	writel(reg, spi_imx->base + MXC_CSPICTRL);
@@ -246,11 +239,43 @@ static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx,
 	return 0;
 }
 
+static int __maybe_unused spi_imx0_7_config(struct spi_imx_data *spi_imx,
+		struct spi_imx_config *config)
+{
+	unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
+
+	reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
+		MX31_CSPICTRL_DR_SHIFT;
+
+	reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
+	reg |= MX31_CSPICTRL_SSCTL;
+
+	if (config->mode & SPI_CPHA)
+		reg |= MX31_CSPICTRL_PHA;
+	if (config->mode & SPI_CPOL)
+		reg |= MX31_CSPICTRL_POL;
+	if (config->mode & SPI_CS_HIGH)
+		reg |= MX31_CSPICTRL_SSPOL;
+	if (config->cs < 0)
+		reg |= (config->cs + 32) << MX35_CSPICTRL_CS_SHIFT;
+
+	writel(reg, spi_imx->base + MXC_CSPICTRL);
+
+	return 0;
+}
+
 static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx)
 {
 	return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
 }
 
+static void __maybe_unused spi_imx0_4_reset(struct spi_imx_data *spi_imx)
+{
+	/* drain receive buffer */
+	while (readl(spi_imx->base + MX3_CSPISTAT) & MX3_CSPISTAT_RR)
+		readl(spi_imx->base + MXC_CSPIRXDATA);
+}
+
 #define MX27_INTREG_RR		(1 << 4)
 #define MX27_INTREG_TEEN	(1 << 9)
 #define MX27_INTREG_RREN	(1 << 13)
@@ -313,6 +338,11 @@ static int __maybe_unused mx27_rx_available(struct spi_imx_data *spi_imx)
 	return readl(spi_imx->base + MXC_CSPIINT) & MX27_INTREG_RR;
 }
 
+static void __maybe_unused spi_imx0_0_reset(struct spi_imx_data *spi_imx)
+{
+	writel(1, spi_imx->base + MXC_RESET);
+}
+
 #define MX1_INTREG_RR		(1 << 3)
 #define MX1_INTREG_TEEN		(1 << 8)
 #define MX1_INTREG_RREN		(1 << 11)
@@ -369,6 +399,11 @@ static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx)
 	return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
 }
 
+static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx)
+{
+	writel(1, spi_imx->base + MXC_RESET);
+}
+
 /*
  * These version numbers are taken from the Freescale driver.  Unfortunately it
  * doesn't support i.MX1, so this entry doesn't match the scheme. :-(
@@ -380,6 +415,7 @@ static struct spi_imx_devtype_data spi_imx_devtype_data[] __devinitdata = {
 		.config = mx1_config,
 		.trigger = mx1_trigger,
 		.rx_available = mx1_rx_available,
+		.reset = mx1_reset,
 	},
 #endif
 #ifdef CONFIG_SPI_IMX_VER_0_0
@@ -388,22 +424,25 @@ static struct spi_imx_devtype_data spi_imx_devtype_data[] __devinitdata = {
 		.config = mx27_config,
 		.trigger = mx27_trigger,
 		.rx_available = mx27_rx_available,
+		.reset = spi_imx0_0_reset,
 	},
 #endif
 #ifdef CONFIG_SPI_IMX_VER_0_4
 	[SPI_IMX_VER_0_4] = {
 		.intctrl = mx31_intctrl,
-		.config = mx31_config,
+		.config = spi_imx0_4_config,
 		.trigger = mx31_trigger,
 		.rx_available = mx31_rx_available,
+		.reset = spi_imx0_4_reset,
 	},
 #endif
 #ifdef CONFIG_SPI_IMX_VER_0_7
 	[SPI_IMX_VER_0_7] = {
 		.intctrl = mx31_intctrl,
-		.config = mx31_config,
+		.config = spi_imx0_7_config,
 		.trigger = mx31_trigger,
 		.rx_available = mx31_rx_available,
+		.reset = spi_imx0_4_reset,
 	},
 #endif
 };
@@ -683,13 +722,7 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
 	clk_enable(spi_imx->clk);
 	spi_imx->spi_clk = clk_get_rate(spi_imx->clk);
 
-	if (cpu_is_mx1() || cpu_is_mx21() || cpu_is_mx27())
-		writel(1, spi_imx->base + MXC_RESET);
-
-	/* drain receive buffer */
-	if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35())
-		while (readl(spi_imx->base + MX3_CSPISTAT) & MX3_CSPISTAT_RR)
-			readl(spi_imx->base + MXC_CSPIRXDATA);
+	spi_imx->devtype_data.reset(spi_imx);
 
 	spi_imx->devtype_data.intctrl(spi_imx, 0);
 
-- 
1.7.2.3


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[PATCH 12/16] ARM: mx5/clock-mx51: new macro that defines a clk with all members

[Uwe Kleine-König]

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
 arch/arm/mach-mx5/clock-mx51.c |   26 +++++++++++++-------------
 1 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c
index fe658bf..0e39698 100644
--- a/arch/arm/mach-mx5/clock-mx51.c
+++ b/arch/arm/mach-mx5/clock-mx51.c
@@ -764,21 +764,21 @@ static struct clk kpp_clk = {
 	.id = 0,
 };
 
-#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s)	\
-	static struct clk name = {			\
-		.id		= i,			\
-		.enable_reg	= er,			\
-		.enable_shift	= es,			\
-		.get_rate	= gr,			\
-		.set_rate	= sr,			\
-		.enable		= _clk_ccgr_enable,	\
-		.disable	= _clk_ccgr_disable,	\
-		.parent		= p,			\
-		.secondary	= s,			\
+#define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s)		\
+	static struct clk name = {					\
+		.id		= i,					\
+		.enable_reg	= er,					\
+		.enable_shift	= es,					\
+		.get_rate	= gr,					\
+		.set_rate	= sr,					\
+		.enable		= e,					\
+		.disable	= d,					\
+		.parent		= p,					\
+		.secondary	= s,					\
 	}
 
-/* DEFINE_CLOCK(name, id, enable_reg, enable_shift,
-   get_rate, set_rate, parent, secondary); */
+#define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s)			\
+	DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, _clk_ccgr_enable, _clk_ccgr_disable, p, s)
 
 /* Shared peripheral bus arbiter */
 DEFINE_CLOCK(spba_clk, 0, MXC_CCM_CCGR5, MXC_CCM_CCGRx_CG0_OFFSET,
-- 
1.7.2.3


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[PATCH 02/16] spi/imx: convert driver to use platform ids

[Uwe Kleine-König]

This has the advantage not to need to much cpu_is_... macros.  Still more
when imx51 support is added which has two different spi interfaces which
would introduce additional checks on the device id.

With this setup it's not possible for the compiler anymore to detect the
unused functions, so four additional kconfig symbols are introduced to
ifdef out the unneeded functions in the callback array and all these
functions are marked with __maybe_unused to suppress the corresponding
gcc warnings.

Comparing the driver footprint with and without the patch for a mx27
kernel yields:

add/remove: 2/0 grow/shrink: 2/0 up/down: 280/0 (280)
function                                     old     new   delta
spi_imx_devtype                                -     192    +192
spi_imx_probe                                980    1032     +52
spi_imx_devtype_data                           -      32     +32
spi_imx_setupxfer                            276     280      +4

Later when the platform code is updated to use the platform ids, the
autodetection can be removed which will make the driver a bit smaller
again.  (~60 Bytes in my test.)

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
 drivers/spi/Kconfig   |   12 ++++
 drivers/spi/spi_imx.c |  173 +++++++++++++++++++++++++++++++++++++------------
 2 files changed, 143 insertions(+), 42 deletions(-)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 30aea6d..4e9d77b 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -143,6 +143,18 @@ config SPI_GPIO
 	  GPIO operations, you should be able to leverage that for better
 	  speed with a custom version of this driver; see the source code.
 
+config SPI_IMX_VER_IMX1
+	def_bool y if SOC_IMX1
+
+config SPI_IMX_VER_0_0
+	def_bool y if SOC_IMX21 || SOC_IMX27
+
+config SPI_IMX_VER_0_4
+	def_bool y if ARCH_MX31
+
+config SPI_IMX_VER_0_7
+	def_bool y if ARCH_MX25 || ARCH_MX35
+
 config SPI_IMX
 	tristate "Freescale i.MX SPI controllers"
 	depends on ARCH_MXC
diff --git a/drivers/spi/spi_imx.c b/drivers/spi/spi_imx.c
index 7972e90..20cdee3 100644
--- a/drivers/spi/spi_imx.c
+++ b/drivers/spi/spi_imx.c
@@ -59,6 +59,24 @@ struct spi_imx_config {
 	int cs;
 };
 
+enum spi_imx_devtype {
+	SPI_IMX_VER_IMX1,
+	SPI_IMX_VER_0_0,
+	SPI_IMX_VER_0_4,
+	SPI_IMX_VER_0_5,
+	SPI_IMX_VER_0_7,
+	SPI_IMX_VER_AUTODETECT,
+};
+
+struct spi_imx_data;
+
+struct spi_imx_devtype_data {
+	void (*intctrl)(struct spi_imx_data *, int);
+	int (*config)(struct spi_imx_data *, struct spi_imx_config *);
+	void (*trigger)(struct spi_imx_data *);
+	int (*rx_available)(struct spi_imx_data *);
+};
+
 struct spi_imx_data {
 	struct spi_bitbang bitbang;
 
@@ -76,11 +94,7 @@ struct spi_imx_data {
 	const void *tx_buf;
 	unsigned int txfifo; /* number of words pushed in tx FIFO */
 
-	/* SoC specific functions */
-	void (*intctrl)(struct spi_imx_data *, int);
-	int (*config)(struct spi_imx_data *, struct spi_imx_config *);
-	void (*trigger)(struct spi_imx_data *);
-	int (*rx_available)(struct spi_imx_data *);
+	struct spi_imx_devtype_data devtype_data;
 };
 
 #define MXC_SPI_BUF_RX(type)						\
@@ -178,7 +192,7 @@ static unsigned int spi_imx_clkdiv_2(unsigned int fin,
  * the i.MX35 has a slightly different register layout for bits
  * we do not use here.
  */
-static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
+static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
 {
 	unsigned int val = 0;
 
@@ -190,7 +204,7 @@ static void mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
 	writel(val, spi_imx->base + MXC_CSPIINT);
 }
 
-static void mx31_trigger(struct spi_imx_data *spi_imx)
+static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx)
 {
 	unsigned int reg;
 
@@ -199,7 +213,7 @@ static void mx31_trigger(struct spi_imx_data *spi_imx)
 	writel(reg, spi_imx->base + MXC_CSPICTRL);
 }
 
-static int mx31_config(struct spi_imx_data *spi_imx,
+static int __maybe_unused mx31_config(struct spi_imx_data *spi_imx,
 		struct spi_imx_config *config)
 {
 	unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
@@ -232,7 +246,7 @@ static int mx31_config(struct spi_imx_data *spi_imx,
 	return 0;
 }
 
-static int mx31_rx_available(struct spi_imx_data *spi_imx)
+static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx)
 {
 	return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
 }
@@ -250,7 +264,7 @@ static int mx31_rx_available(struct spi_imx_data *spi_imx)
 #define MX27_CSPICTRL_DR_SHIFT	14
 #define MX27_CSPICTRL_CS_SHIFT	19
 
-static void mx27_intctrl(struct spi_imx_data *spi_imx, int enable)
+static void __maybe_unused mx27_intctrl(struct spi_imx_data *spi_imx, int enable)
 {
 	unsigned int val = 0;
 
@@ -262,7 +276,7 @@ static void mx27_intctrl(struct spi_imx_data *spi_imx, int enable)
 	writel(val, spi_imx->base + MXC_CSPIINT);
 }
 
-static void mx27_trigger(struct spi_imx_data *spi_imx)
+static void __maybe_unused mx27_trigger(struct spi_imx_data *spi_imx)
 {
 	unsigned int reg;
 
@@ -271,7 +285,7 @@ static void mx27_trigger(struct spi_imx_data *spi_imx)
 	writel(reg, spi_imx->base + MXC_CSPICTRL);
 }
 
-static int mx27_config(struct spi_imx_data *spi_imx,
+static int __maybe_unused mx27_config(struct spi_imx_data *spi_imx,
 		struct spi_imx_config *config)
 {
 	unsigned int reg = MX27_CSPICTRL_ENABLE | MX27_CSPICTRL_MASTER;
@@ -294,7 +308,7 @@ static int mx27_config(struct spi_imx_data *spi_imx,
 	return 0;
 }
 
-static int mx27_rx_available(struct spi_imx_data *spi_imx)
+static int __maybe_unused mx27_rx_available(struct spi_imx_data *spi_imx)
 {
 	return readl(spi_imx->base + MXC_CSPIINT) & MX27_INTREG_RR;
 }
@@ -310,7 +324,7 @@ static int mx27_rx_available(struct spi_imx_data *spi_imx)
 #define MX1_CSPICTRL_MASTER	(1 << 10)
 #define MX1_CSPICTRL_DR_SHIFT	13
 
-static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
+static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
 {
 	unsigned int val = 0;
 
@@ -322,7 +336,7 @@ static void mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
 	writel(val, spi_imx->base + MXC_CSPIINT);
 }
 
-static void mx1_trigger(struct spi_imx_data *spi_imx)
+static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx)
 {
 	unsigned int reg;
 
@@ -331,7 +345,7 @@ static void mx1_trigger(struct spi_imx_data *spi_imx)
 	writel(reg, spi_imx->base + MXC_CSPICTRL);
 }
 
-static int mx1_config(struct spi_imx_data *spi_imx,
+static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx,
 		struct spi_imx_config *config)
 {
 	unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
@@ -350,11 +364,50 @@ static int mx1_config(struct spi_imx_data *spi_imx,
 	return 0;
 }
 
-static int mx1_rx_available(struct spi_imx_data *spi_imx)
+static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx)
 {
 	return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
 }
 
+/*
+ * These version numbers are taken from the Freescale driver.  Unfortunately it
+ * doesn't support i.MX1, so this entry doesn't match the scheme. :-(
+ */
+static struct spi_imx_devtype_data spi_imx_devtype_data[] __devinitdata = {
+#ifdef CONFIG_SPI_IMX_VER_IMX1
+	[SPI_IMX_VER_IMX1] = {
+		.intctrl = mx1_intctrl,
+		.config = mx1_config,
+		.trigger = mx1_trigger,
+		.rx_available = mx1_rx_available,
+	},
+#endif
+#ifdef CONFIG_SPI_IMX_VER_0_0
+	[SPI_IMX_VER_0_0] = {
+		.intctrl = mx27_intctrl,
+		.config = mx27_config,
+		.trigger = mx27_trigger,
+		.rx_available = mx27_rx_available,
+	},
+#endif
+#ifdef CONFIG_SPI_IMX_VER_0_4
+	[SPI_IMX_VER_0_4] = {
+		.intctrl = mx31_intctrl,
+		.config = mx31_config,
+		.trigger = mx31_trigger,
+		.rx_available = mx31_rx_available,
+	},
+#endif
+#ifdef CONFIG_SPI_IMX_VER_0_7
+	[SPI_IMX_VER_0_7] = {
+		.intctrl = mx31_intctrl,
+		.config = mx31_config,
+		.trigger = mx31_trigger,
+		.rx_available = mx31_rx_available,
+	},
+#endif
+};
+
 static void spi_imx_chipselect(struct spi_device *spi, int is_active)
 {
 	struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
@@ -377,14 +430,14 @@ static void spi_imx_push(struct spi_imx_data *spi_imx)
 		spi_imx->txfifo++;
 	}
 
-	spi_imx->trigger(spi_imx);
+	spi_imx->devtype_data.trigger(spi_imx);
 }
 
 static irqreturn_t spi_imx_isr(int irq, void *dev_id)
 {
 	struct spi_imx_data *spi_imx = dev_id;
 
-	while (spi_imx->rx_available(spi_imx)) {
+	while (spi_imx->devtype_data.rx_available(spi_imx)) {
 		spi_imx->rx(spi_imx);
 		spi_imx->txfifo--;
 	}
@@ -398,11 +451,12 @@ static irqreturn_t spi_imx_isr(int irq, void *dev_id)
 		/* No data left to push, but still waiting for rx data,
 		 * enable receive data available interrupt.
 		 */
-		spi_imx->intctrl(spi_imx, MXC_INT_RR);
+		spi_imx->devtype_data.intctrl(
+				spi_imx, MXC_INT_RR);
 		return IRQ_HANDLED;
 	}
 
-	spi_imx->intctrl(spi_imx, 0);
+	spi_imx->devtype_data.intctrl(spi_imx, 0);
 	complete(&spi_imx->xfer_done);
 
 	return IRQ_HANDLED;
@@ -439,7 +493,7 @@ static int spi_imx_setupxfer(struct spi_device *spi,
 	} else
 		BUG();
 
-	spi_imx->config(spi_imx, &config);
+	spi_imx->devtype_data.config(spi_imx, &config);
 
 	return 0;
 }
@@ -458,7 +512,7 @@ static int spi_imx_transfer(struct spi_device *spi,
 
 	spi_imx_push(spi_imx);
 
-	spi_imx->intctrl(spi_imx, MXC_INT_TE);
+	spi_imx->devtype_data.intctrl(spi_imx, MXC_INT_TE);
 
 	wait_for_completion(&spi_imx->xfer_done);
 
@@ -485,6 +539,33 @@ static void spi_imx_cleanup(struct spi_device *spi)
 {
 }
 
+static struct platform_device_id spi_imx_devtype[] = {
+	{
+		.name = DRIVER_NAME,
+		.driver_data = SPI_IMX_VER_AUTODETECT,
+	}, {
+		.name = "imx1-cspi",
+		.driver_data = SPI_IMX_VER_IMX1,
+	}, {
+		.name = "imx21-cspi",
+		.driver_data = SPI_IMX_VER_0_0,
+	}, {
+		.name = "imx25-cspi",
+		.driver_data = SPI_IMX_VER_0_7,
+	}, {
+		.name = "imx27-cspi",
+		.driver_data = SPI_IMX_VER_0_0,
+	}, {
+		.name = "imx31-cspi",
+		.driver_data = SPI_IMX_VER_0_4,
+	}, {
+		.name = "imx35-cspi",
+		.driver_data = SPI_IMX_VER_0_7,
+	}, {
+		/* sentinel */
+	}
+};
+
 static int __devinit spi_imx_probe(struct platform_device *pdev)
 {
 	struct spi_imx_master *mxc_platform_info;
@@ -536,6 +617,31 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
 
 	init_completion(&spi_imx->xfer_done);
 
+	if (pdev->id_entry->driver_data == SPI_IMX_VER_AUTODETECT) {
+		if (cpu_is_mx25() || cpu_is_mx35())
+			spi_imx->devtype_data =
+				spi_imx_devtype_data[SPI_IMX_VER_0_7];
+		else if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35())
+			spi_imx->devtype_data =
+				spi_imx_devtype_data[SPI_IMX_VER_0_4];
+		else if (cpu_is_mx27() || cpu_is_mx21())
+			spi_imx->devtype_data =
+				spi_imx_devtype_data[SPI_IMX_VER_0_0];
+		else if (cpu_is_mx1())
+			spi_imx->devtype_data =
+				spi_imx_devtype_data[SPI_IMX_VER_IMX1];
+		else
+			BUG();
+	} else
+		spi_imx->devtype_data =
+			spi_imx_devtype_data[pdev->id_entry->driver_data];
+
+	if (!spi_imx->devtype_data.intctrl) {
+		dev_err(&pdev->dev, "no support for this device compiled in\n");
+		ret = -ENODEV;
+		goto out_gpio_free;
+	}
+
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	if (!res) {
 		dev_err(&pdev->dev, "can't get platform resource\n");
@@ -567,24 +673,6 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
 		goto out_iounmap;
 	}
 
-	if (cpu_is_mx25() || cpu_is_mx31() || cpu_is_mx35()) {
-		spi_imx->intctrl = mx31_intctrl;
-		spi_imx->config = mx31_config;
-		spi_imx->trigger = mx31_trigger;
-		spi_imx->rx_available = mx31_rx_available;
-	} else  if (cpu_is_mx27() || cpu_is_mx21()) {
-		spi_imx->intctrl = mx27_intctrl;
-		spi_imx->config = mx27_config;
-		spi_imx->trigger = mx27_trigger;
-		spi_imx->rx_available = mx27_rx_available;
-	} else if (cpu_is_mx1()) {
-		spi_imx->intctrl = mx1_intctrl;
-		spi_imx->config = mx1_config;
-		spi_imx->trigger = mx1_trigger;
-		spi_imx->rx_available = mx1_rx_available;
-	} else
-		BUG();
-
 	spi_imx->clk = clk_get(&pdev->dev, NULL);
 	if (IS_ERR(spi_imx->clk)) {
 		dev_err(&pdev->dev, "unable to get clock\n");
@@ -603,7 +691,7 @@ static int __devinit spi_imx_probe(struct platform_device *pdev)
 		while (readl(spi_imx->base + MX3_CSPISTAT) & MX3_CSPISTAT_RR)
 			readl(spi_imx->base + MXC_CSPIRXDATA);
 
-	spi_imx->intctrl(spi_imx, 0);
+	spi_imx->devtype_data.intctrl(spi_imx, 0);
 
 	ret = spi_bitbang_start(&spi_imx->bitbang);
 	if (ret) {
@@ -668,6 +756,7 @@ static struct platform_driver spi_imx_driver = {
 		   .name = DRIVER_NAME,
 		   .owner = THIS_MODULE,
 		   },
+	.id_table = spi_imx_devtype,
 	.probe = spi_imx_probe,
 	.remove = __devexit_p(spi_imx_remove),
 };
-- 
1.7.2.3


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[PATCH 04/16] spi/imx: save the spi chip select in config struct, not the gpio to use

[Uwe Kleine-König]

This prepares adding support for imx51's eCSPI.  This IP has seperate
control and config bits for all four supported chip selects, so the
config routine needs to know which chip select is being used even if
the chipselect is realized by a gpio.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
 drivers/spi/spi_imx.c |   20 +++++++++++---------
 1 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/drivers/spi/spi_imx.c b/drivers/spi/spi_imx.c
index 60a52d1..23db984 100644
--- a/drivers/spi/spi_imx.c
+++ b/drivers/spi/spi_imx.c
@@ -56,7 +56,7 @@ struct spi_imx_config {
 	unsigned int speed_hz;
 	unsigned int bpw;
 	unsigned int mode;
-	int cs;
+	u8 cs;
 };
 
 enum spi_imx_devtype {
@@ -218,6 +218,7 @@ static int __maybe_unused spi_imx0_4_config(struct spi_imx_data *spi_imx,
 		struct spi_imx_config *config)
 {
 	unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
+	int cs = spi_imx->chipselect[config->cs];
 
 	reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
 		MX31_CSPICTRL_DR_SHIFT;
@@ -230,9 +231,8 @@ static int __maybe_unused spi_imx0_4_config(struct spi_imx_data *spi_imx,
 		reg |= MX31_CSPICTRL_POL;
 	if (config->mode & SPI_CS_HIGH)
 		reg |= MX31_CSPICTRL_SSPOL;
-	if (config->cs < 0) {
-		reg |= (config->cs + 32) << MX31_CSPICTRL_CS_SHIFT;
-	}
+	if (cs < 0)
+		reg |= (cs + 32) << MX31_CSPICTRL_CS_SHIFT;
 
 	writel(reg, spi_imx->base + MXC_CSPICTRL);
 
@@ -243,6 +243,7 @@ static int __maybe_unused spi_imx0_7_config(struct spi_imx_data *spi_imx,
 		struct spi_imx_config *config)
 {
 	unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
+	int cs = spi_imx->chipselect[config->cs];
 
 	reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
 		MX31_CSPICTRL_DR_SHIFT;
@@ -256,8 +257,8 @@ static int __maybe_unused spi_imx0_7_config(struct spi_imx_data *spi_imx,
 		reg |= MX31_CSPICTRL_POL;
 	if (config->mode & SPI_CS_HIGH)
 		reg |= MX31_CSPICTRL_SSPOL;
-	if (config->cs < 0)
-		reg |= (config->cs + 32) << MX35_CSPICTRL_CS_SHIFT;
+	if (cs < 0)
+		reg |= (cs + 32) << MX35_CSPICTRL_CS_SHIFT;
 
 	writel(reg, spi_imx->base + MXC_CSPICTRL);
 
@@ -314,6 +315,7 @@ static int __maybe_unused mx27_config(struct spi_imx_data *spi_imx,
 		struct spi_imx_config *config)
 {
 	unsigned int reg = MX27_CSPICTRL_ENABLE | MX27_CSPICTRL_MASTER;
+	int cs = spi_imx->chipselect[config->cs];
 
 	reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz) <<
 		MX27_CSPICTRL_DR_SHIFT;
@@ -325,8 +327,8 @@ static int __maybe_unused mx27_config(struct spi_imx_data *spi_imx,
 		reg |= MX27_CSPICTRL_POL;
 	if (config->mode & SPI_CS_HIGH)
 		reg |= MX27_CSPICTRL_SSPOL;
-	if (config->cs < 0)
-		reg |= (config->cs + 32) << MX27_CSPICTRL_CS_SHIFT;
+	if (cs < 0)
+		reg |= (cs + 32) << MX27_CSPICTRL_CS_SHIFT;
 
 	writel(reg, spi_imx->base + MXC_CSPICTRL);
 
@@ -510,7 +512,7 @@ static int spi_imx_setupxfer(struct spi_device *spi,
 	config.bpw = t ? t->bits_per_word : spi->bits_per_word;
 	config.speed_hz  = t ? t->speed_hz : spi->max_speed_hz;
 	config.mode = spi->mode;
-	config.cs = spi_imx->chipselect[spi->chip_select];
+	config.cs = spi->chip_select;
 
 	if (!config.speed_hz)
 		config.speed_hz = spi->max_speed_hz;
-- 
1.7.2.3


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Re: [PATCH 04/16] spi/imx: save the spi chip select in config struct, not the gpio to use

[Lothar Waßmann]

Hi,

> diff --git a/drivers/spi/spi_imx.c b/drivers/spi/spi_imx.c
> index 60a52d1..23db984 100644
> --- a/drivers/spi/spi_imx.c
> +++ b/drivers/spi/spi_imx.c
> @@ -56,7 +56,7 @@ struct spi_imx_config {
>  	unsigned int speed_hz;
>  	unsigned int bpw;
>  	unsigned int mode;
> -	int cs;
> +	u8 cs;
        ^^^^^^
>  };
>  
>  enum spi_imx_devtype {
> @@ -218,6 +218,7 @@ static int __maybe_unused spi_imx0_4_config(struct spi_imx_data *spi_imx,
>  		struct spi_imx_config *config)
>  {
>  	unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
> +	int cs = spi_imx->chipselect[config->cs];
>  
>  	reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
>  		MX31_CSPICTRL_DR_SHIFT;
> @@ -230,9 +231,8 @@ static int __maybe_unused spi_imx0_4_config(struct spi_imx_data *spi_imx,
>  		reg |= MX31_CSPICTRL_POL;
>  	if (config->mode & SPI_CS_HIGH)
>  		reg |= MX31_CSPICTRL_SSPOL;
> -	if (config->cs < 0) {
> -		reg |= (config->cs + 32) << MX31_CSPICTRL_CS_SHIFT;
> -	}
> +	if (cs < 0)
>
This can never be true, since an 'int' promoted from 'u8' will always
be positive!


Lothar Waßmann
-- 
___________________________________________________________

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___________________________________________________________

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Re: [PATCH 04/16] spi/imx: save the spi chip select in config struct, not the gpio to use

[Russell King - ARM Linux]

On Fri, Sep 17, 2010 at 01:11:14PM +0200, Lothar Waßmann wrote:
> Hi,
> 
> > diff --git a/drivers/spi/spi_imx.c b/drivers/spi/spi_imx.c
> > index 60a52d1..23db984 100644
> > --- a/drivers/spi/spi_imx.c
> > +++ b/drivers/spi/spi_imx.c
> > @@ -56,7 +56,7 @@ struct spi_imx_config {
> >  	unsigned int speed_hz;
> >  	unsigned int bpw;
> >  	unsigned int mode;
> > -	int cs;
> > +	u8 cs;
>         ^^^^^^

u8 cs in spi_imx_config.

> >  };
> >  
> >  enum spi_imx_devtype {
> > @@ -218,6 +218,7 @@ static int __maybe_unused spi_imx0_4_config(struct spi_imx_data *spi_imx,
> >  		struct spi_imx_config *config)
> >  {
> >  	unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
> > +	int cs = spi_imx->chipselect[config->cs];

which is used as an index to this array (which presumably is an array of
ints.)  Let's hope that it is 256 entries long (maybe it should be
checked before use?)

> >  
> >  	reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
> >  		MX31_CSPICTRL_DR_SHIFT;
> > @@ -230,9 +231,8 @@ static int __maybe_unused spi_imx0_4_config(struct spi_imx_data *spi_imx,
> >  		reg |= MX31_CSPICTRL_POL;
> >  	if (config->mode & SPI_CS_HIGH)
> >  		reg |= MX31_CSPICTRL_SSPOL;
> > -	if (config->cs < 0) {
> > -		reg |= (config->cs + 32) << MX31_CSPICTRL_CS_SHIFT;
> > -	}
> > +	if (cs < 0)
> >
> This can never be true, since an 'int' promoted from 'u8' will always
> be positive!

This is the value of chipselect[config->cs] not of the u8 config->cs.

Re: [PATCH 04/16] spi/imx: save the spi chip select in config struct, not the gpio to use

[Jason Wang]

Russell King - ARM Linux wrote:
> On Fri, Sep 17, 2010 at 01:11:14PM +0200, Lothar Waßmann wrote:
>   
>> Hi,
>>
>>     
>>> diff --git a/drivers/spi/spi_imx.c b/drivers/spi/spi_imx.c
>>> index 60a52d1..23db984 100644
>>> --- a/drivers/spi/spi_imx.c
>>> +++ b/drivers/spi/spi_imx.c
>>> @@ -56,7 +56,7 @@ struct spi_imx_config {
>>>  	unsigned int speed_hz;
>>>  	unsigned int bpw;
>>>  	unsigned int mode;
>>> -	int cs;
>>> +	u8 cs;
>>>       
>>         ^^^^^^
>>     
>
> u8 cs in spi_imx_config.
>
>   
>>>  };
>>>  
>>>  enum spi_imx_devtype {
>>> @@ -218,6 +218,7 @@ static int __maybe_unused spi_imx0_4_config(struct spi_imx_data *spi_imx,
>>>  		struct spi_imx_config *config)
>>>  {
>>>  	unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
>>> +	int cs = spi_imx->chipselect[config->cs];
>>>       
>
> which is used as an index to this array (which presumably is an array of
> ints.)  Let's hope that it is 256 entries long (maybe it should be
> checked before use?)
>
>   
>>>  
>>>  	reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
>>>  		MX31_CSPICTRL_DR_SHIFT;
>>> @@ -230,9 +231,8 @@ static int __maybe_unused spi_imx0_4_config(struct spi_imx_data *spi_imx,
>>>  		reg |= MX31_CSPICTRL_POL;
>>>  	if (config->mode & SPI_CS_HIGH)
>>>  		reg |= MX31_CSPICTRL_SSPOL;
>>> -	if (config->cs < 0) {
>>> -		reg |= (config->cs + 32) << MX31_CSPICTRL_CS_SHIFT;
>>> -	}
>>> +	if (cs < 0)
>>>
>>>       
>> This can never be true, since an 'int' promoted from 'u8' will always
>> be positive!
>>     
>
> This is the value of chipselect[config->cs] not of the u8 config->cs.
>
>   
Yes, here (cs < 0) means a SPI dedicate internal CS pin, while (cs >= 0)
means a GPIO act as a SPI CS pin.

Thanks,
Jason.

[PATCH 05/16] spi/imx: add support for imx51's eCSPI and CSPI

[Uwe Kleine-König]

i.MX51 comes with two eCSPI interfaces (that are quite different from
what was known before---the tried and tested Freescale way) and a CSPI
interface that is identical to the devices found on i.MX25 and i.MX35.

This patch is a merge of two very similar patches (by Jason Wang and Sascha
Hauer resp.) plus a (now hopefully correct) reimplementation of the
clock calculation.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
 drivers/spi/Kconfig   |    5 ++-
 drivers/spi/spi_imx.c |  140 ++++++++++++++++++++++++++++++++++++++++++++++++-
 2 files changed, 143 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 4e9d77b..7e631fa 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -153,7 +153,10 @@ config SPI_IMX_VER_0_4
 	def_bool y if ARCH_MX31
 
 config SPI_IMX_VER_0_7
-	def_bool y if ARCH_MX25 || ARCH_MX35
+	def_bool y if ARCH_MX25 || ARCH_MX35 || ARCH_MX51
+
+config SPI_IMX_VER_2_3
+	def_bool y if ARCH_MX51
 
 config SPI_IMX
 	tristate "Freescale i.MX SPI controllers"
diff --git a/drivers/spi/spi_imx.c b/drivers/spi/spi_imx.c
index 23db984..6bab2cf 100644
--- a/drivers/spi/spi_imx.c
+++ b/drivers/spi/spi_imx.c
@@ -65,6 +65,7 @@ enum spi_imx_devtype {
 	SPI_IMX_VER_0_4,
 	SPI_IMX_VER_0_5,
 	SPI_IMX_VER_0_7,
+	SPI_IMX_VER_2_3,
 	SPI_IMX_VER_AUTODETECT,
 };
 
@@ -155,7 +156,7 @@ static unsigned int spi_imx_clkdiv_1(unsigned int fin,
 	return max;
 }
 
-/* MX1, MX31, MX35 */
+/* MX1, MX31, MX35, MX51 CSPI */
 static unsigned int spi_imx_clkdiv_2(unsigned int fin,
 		unsigned int fspi)
 {
@@ -170,6 +171,128 @@ static unsigned int spi_imx_clkdiv_2(unsigned int fin,
 	return 7;
 }
 
+#define SPI_IMX2_3_CTRL		0x08
+#define SPI_IMX2_3_CTRL_ENABLE		(1 <<  0)
+#define SPI_IMX2_3_CTRL_XCH		(1 <<  2)
+#define SPI_IMX2_3_CTRL_MODE(cs)	(1 << ((cs) +  4))
+#define SPI_IMX2_3_CTRL_POSTDIV_OFFSET	8
+#define SPI_IMX2_3_CTRL_PREDIV_OFFSET	12
+#define SPI_IMX2_3_CTRL_CS(cs)		((cs) << 18)
+#define SPI_IMX2_3_CTRL_BL_OFFSET	20
+
+#define SPI_IMX2_3_CONFIG	0x0c
+#define SPI_IMX2_3_CONFIG_SCLKPHA(cs)	(1 << ((cs) +  0))
+#define SPI_IMX2_3_CONFIG_SCLKPOL(cs)	(1 << ((cs) +  4))
+#define SPI_IMX2_3_CONFIG_SBBCTRL(cs)	(1 << ((cs) +  8))
+#define SPI_IMX2_3_CONFIG_SSBPOL(cs)	(1 << ((cs) + 12))
+
+#define SPI_IMX2_3_INT		0x10
+#define SPI_IMX2_3_INT_TEEN		(1 <<  0)
+#define SPI_IMX2_3_INT_RREN		(1 <<  3)
+
+#define SPI_IMX2_3_STAT		0x18
+#define SPI_IMX2_3_STAT_RR		(1 <<  3)
+
+/* MX51 eCSPI */
+static unsigned int spi_imx2_3_clkdiv(unsigned int fin, unsigned int fspi)
+{
+	/*
+	 * there are two 4-bit dividers, the pre-divider divides by
+	 * $pre, the post-divider by 2^$post
+	 */
+	unsigned int pre, post;
+
+	if (unlikely(fspi > fin))
+		return 0;
+
+	post = fls(fin) - fls(fspi);
+	if (fin > fspi << post)
+		post++;
+
+	/* now we have: (fin <= fspi << post) with post being minimal */
+
+	post = max(4U, post) - 4;
+	if (unlikely(post > 0xf)) {
+		pr_err("%s: cannot set clock freq: %u (base freq: %u)\n",
+				__func__, fspi, fin);
+		return 0xff;
+	}
+
+	pre = DIV_ROUND_UP(fin, fspi << post) - 1;
+
+	pr_debug("%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
+			__func__, fin, fspi, post, pre);
+	return (pre << SPI_IMX2_3_CTRL_PREDIV_OFFSET) |
+		(post << SPI_IMX2_3_CTRL_POSTDIV_OFFSET);
+}
+
+static void __maybe_unused spi_imx2_3_intctrl(struct spi_imx_data *spi_imx, int enable)
+{
+	unsigned val = 0;
+
+	if (enable & MXC_INT_TE)
+		val |= SPI_IMX2_3_INT_TEEN;
+
+	if (enable & MXC_INT_RR)
+		val |= SPI_IMX2_3_INT_RREN;
+
+	writel(val, spi_imx->base + SPI_IMX2_3_INT);
+}
+
+static void __maybe_unused spi_imx2_3_trigger(struct spi_imx_data *spi_imx)
+{
+	u32 reg;
+
+	reg = readl(spi_imx->base + SPI_IMX2_3_CTRL);
+	reg |= SPI_IMX2_3_CTRL_XCH;
+	writel(reg, spi_imx->base + SPI_IMX2_3_CTRL);
+}
+
+static int __maybe_unused spi_imx2_3_config(struct spi_imx_data *spi_imx,
+		struct spi_imx_config *config)
+{
+	u32 ctrl = SPI_IMX2_3_CTRL_ENABLE, cfg = 0;
+
+	/* set master mode */
+	ctrl |= SPI_IMX2_3_CTRL_MODE(config->cs);
+
+	/* set clock speed */
+	ctrl |= spi_imx2_3_clkdiv(spi_imx->spi_clk, config->speed_hz);
+
+	/* set chip select to use */
+	ctrl |= SPI_IMX2_3_CTRL_CS(config->cs);
+
+	ctrl |= (config->bpw - 1) << SPI_IMX2_3_CTRL_BL_OFFSET;
+
+	cfg |= SPI_IMX2_3_CONFIG_SBBCTRL(config->cs);
+
+	if (config->mode & SPI_CPHA)
+		cfg |= SPI_IMX2_3_CONFIG_SCLKPHA(config->cs);
+
+	if (config->mode & SPI_CPOL)
+		cfg |= SPI_IMX2_3_CONFIG_SCLKPOL(config->cs);
+
+	if (config->mode & SPI_CS_HIGH)
+		cfg |= SPI_IMX2_3_CONFIG_SSBPOL(config->cs);
+
+	writel(ctrl, spi_imx->base + SPI_IMX2_3_CTRL);
+	writel(cfg, spi_imx->base + SPI_IMX2_3_CONFIG);
+
+	return 0;
+}
+
+static int __maybe_unused spi_imx2_3_rx_available(struct spi_imx_data *spi_imx)
+{
+	return readl(spi_imx->base + SPI_IMX2_3_STAT) & SPI_IMX2_3_STAT_RR;
+}
+
+static void __maybe_unused spi_imx2_3_reset(struct spi_imx_data *spi_imx)
+{
+	/* drain receive buffer */
+	while (spi_imx2_3_rx_available(spi_imx))
+		readl(spi_imx->base + MXC_CSPIRXDATA);
+}
+
 #define MX31_INTREG_TEEN	(1 << 0)
 #define MX31_INTREG_RREN	(1 << 3)
 
@@ -447,6 +570,15 @@ static struct spi_imx_devtype_data spi_imx_devtype_data[] __devinitdata = {
 		.reset = spi_imx0_4_reset,
 	},
 #endif
+#ifdef CONFIG_SPI_IMX_VER_2_3
+	[SPI_IMX_VER_2_3] = {
+		.intctrl = spi_imx2_3_intctrl,
+		.config = spi_imx2_3_config,
+		.trigger = spi_imx2_3_trigger,
+		.rx_available = spi_imx2_3_rx_available,
+		.reset = spi_imx2_3_reset,
+	},
+#endif
 };
 
 static void spi_imx_chipselect(struct spi_device *spi, int is_active)
@@ -603,6 +735,12 @@ static struct platform_device_id spi_imx_devtype[] = {
 		.name = "imx35-cspi",
 		.driver_data = SPI_IMX_VER_0_7,
 	}, {
+		.name = "imx51-cspi",
+		.driver_data = SPI_IMX_VER_0_7,
+	}, {
+		.name = "imx51-ecspi",
+		.driver_data = SPI_IMX_VER_2_3,
+	}, {
 		/* sentinel */
 	}
 };
-- 
1.7.2.3


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[PATCH 06/16] ARM: imx: change the way spi-imx devices are registered

[Uwe Kleine-König]

Group soc specific data in a global struct instead of repeating it for
each call to imxXX_add_spi_imxX.  The structs holding the actual data
are placed in .init.constdata and so don't do much harm.  Compared to
the previous approach this reduces code size to call imx_add_spi_imx.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
 arch/arm/mach-imx/devices-imx21.h               |    9 ++-
 arch/arm/mach-imx/devices-imx27.h               |   12 ++--
 arch/arm/mach-mx25/devices-imx25.h              |   12 ++--
 arch/arm/mach-mx3/devices-imx31.h               |   12 ++--
 arch/arm/mach-mx3/devices-imx35.h               |    9 ++-
 arch/arm/plat-mxc/devices/platform-spi_imx.c    |   76 ++++++++++++++++++++---
 arch/arm/plat-mxc/include/mach/devices-common.h |   10 +++-
 7 files changed, 103 insertions(+), 37 deletions(-)

diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h
index 42788e9..2b45d33 100644
--- a/arch/arm/mach-imx/devices-imx21.h
+++ b/arch/arm/mach-imx/devices-imx21.h
@@ -24,7 +24,8 @@
 #define imx21_add_mxc_nand(pdata)	\
 	imx_add_mxc_nand_v1(MX21_NFC_BASE_ADDR, MX21_INT_NANDFC, pdata)
 
-#define imx21_add_spi_imx0(pdata)	\
-	imx_add_spi_imx(0, MX21_CSPI1_BASE_ADDR, SZ_4K, MX21_INT_CSPI1, pdata)
-#define imx21_add_spi_imx1(pdata)	\
-	imx_add_spi_imx(1, MX21_CSPI2_BASE_ADDR, SZ_4K, MX21_INT_CSPI2, pdata)
+extern const struct imx_spi_imx_data imx21_cspi_data[] __initconst;
+#define imx21_add_cspi(id, pdata)	\
+	imx_add_spi_imx(&imx21_cspi_data[id], pdata)
+#define imx21_add_spi_imx0(pdata)	imx21_add_cspi(0, pdata)
+#define imx21_add_spi_imx1(pdata)	imx21_add_cspi(1, pdata)
diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h
index 65e7bb7..04bfcf0 100644
--- a/arch/arm/mach-imx/devices-imx27.h
+++ b/arch/arm/mach-imx/devices-imx27.h
@@ -30,9 +30,9 @@
 #define imx27_add_mxc_nand(pdata)	\
 	imx_add_mxc_nand_v1(MX27_NFC_BASE_ADDR, MX27_INT_NANDFC, pdata)
 
-#define imx27_add_spi_imx0(pdata)	\
-	imx_add_spi_imx(0, MX27_CSPI1_BASE_ADDR, SZ_4K, MX27_INT_CSPI1, pdata)
-#define imx27_add_spi_imx1(pdata)	\
-	imx_add_spi_imx(1, MX27_CSPI2_BASE_ADDR, SZ_4K, MX27_INT_CSPI2, pdata)
-#define imx27_add_spi_imx2(pdata)	\
-	imx_add_spi_imx(2, MX27_CSPI3_BASE_ADDR, SZ_4K, MX27_INT_CSPI3, pdata)
+extern const struct imx_spi_imx_data imx27_cspi_data[] __initconst;
+#define imx27_add_cspi(id, pdata)	\
+	imx_add_spi_imx(&imx27_cspi_data[id], pdata)
+#define imx27_add_spi_imx0(pdata)	imx27_add_cspi(0, pdata)
+#define imx27_add_spi_imx1(pdata)	imx27_add_cspi(1, pdata)
+#define imx27_add_spi_imx2(pdata)	imx27_add_cspi(2, pdata)
diff --git a/arch/arm/mach-mx25/devices-imx25.h b/arch/arm/mach-mx25/devices-imx25.h
index d86a7c3..34a7061 100644
--- a/arch/arm/mach-mx25/devices-imx25.h
+++ b/arch/arm/mach-mx25/devices-imx25.h
@@ -35,9 +35,9 @@
 #define imx25_add_mxc_nand(pdata)	\
 	imx_add_mxc_nand_v21(MX25_NFC_BASE_ADDR, MX25_INT_NANDFC, pdata)
 
-#define imx25_add_spi_imx0(pdata)	\
-	imx_add_spi_imx(0, MX25_CSPI1_BASE_ADDR, SZ_16K, MX25_INT_CSPI1, pdata)
-#define imx25_add_spi_imx1(pdata)	\
-	imx_add_spi_imx(1, MX25_CSPI2_BASE_ADDR, SZ_16K, MX25_INT_CSPI2, pdata)
-#define imx25_add_spi_imx2(pdata)	\
-	imx_add_spi_imx(2, MX25_CSPI3_BASE_ADDR, SZ_16K, MX25_INT_CSPI3, pdata)
+extern const struct imx_spi_imx_data imx25_spi_imx_data[] __initconst;
+#define imx25_add_spi_imx(id, pdata)	\
+	imx_add_spi_imx(&imx25_spi_imx_data[id], pdata)
+#define imx25_add_spi_imx0(pdata)	imx25_add_spi_imx(0, pdata)
+#define imx25_add_spi_imx1(pdata)	imx25_add_spi_imx(1, pdata)
+#define imx25_add_spi_imx2(pdata)	imx25_add_spi_imx(2, pdata)
diff --git a/arch/arm/mach-mx3/devices-imx31.h b/arch/arm/mach-mx3/devices-imx31.h
index 3b1a44a..7b4d022 100644
--- a/arch/arm/mach-mx3/devices-imx31.h
+++ b/arch/arm/mach-mx3/devices-imx31.h
@@ -30,9 +30,9 @@
 #define imx31_add_mxc_nand(pdata)	\
 	imx_add_mxc_nand_v1(MX31_NFC_BASE_ADDR, MX31_INT_NANDFC, pdata)
 
-#define imx31_add_spi_imx0(pdata)	\
-	imx_add_spi_imx(0, MX31_CSPI1_BASE_ADDR, SZ_4K, MX31_INT_CSPI1, pdata)
-#define imx31_add_spi_imx1(pdata)	\
-	imx_add_spi_imx(1, MX31_CSPI2_BASE_ADDR, SZ_4K, MX31_INT_CSPI2, pdata)
-#define imx31_add_spi_imx2(pdata)	\
-	imx_add_spi_imx(2, MX31_CSPI3_BASE_ADDR, SZ_4K, MX31_INT_CSPI3, pdata)
+extern const struct imx_spi_imx_data imx31_cspi_data[] __initconst;
+#define imx31_add_cspi(id, pdata)	\
+	imx_add_spi_imx(&imx31_cspi_data[id], pdata)
+#define imx31_add_spi_imx0(pdata)	imx31_add_cspi(0, pdata)
+#define imx31_add_spi_imx1(pdata)	imx31_add_cspi(1, pdata)
+#define imx31_add_spi_imx2(pdata)	imx31_add_cspi(2, pdata)
diff --git a/arch/arm/mach-mx3/devices-imx35.h b/arch/arm/mach-mx3/devices-imx35.h
index f6a431a..af0bc1f 100644
--- a/arch/arm/mach-mx3/devices-imx35.h
+++ b/arch/arm/mach-mx3/devices-imx35.h
@@ -31,7 +31,8 @@
 #define imx35_add_mxc_nand(pdata)	\
 	imx_add_mxc_nand_v21(MX35_NFC_BASE_ADDR, MX35_INT_NANDFC, pdata)
 
-#define imx35_add_spi_imx0(pdata)	\
-	imx_add_spi_imx(0, MX35_CSPI1_BASE_ADDR, SZ_4K, MX35_INT_CSPI1, pdata)
-#define imx35_add_spi_imx1(pdata)	\
-	imx_add_spi_imx(1, MX35_CSPI2_BASE_ADDR, SZ_4K, MX35_INT_CSPI2, pdata)
+extern const struct imx_spi_imx_data imx35_cspi_data[] __initconst;
+#define imx35_add_cspi(id, pdata)	\
+	imx_add_spi_imx(&imx35_cspi_data[id], pdata)
+#define imx35_add_spi_imx0(pdata)	imx35_add_cspi(0, pdata)
+#define imx35_add_spi_imx1(pdata)	imx35_add_cspi(1, pdata)
diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c
index 2831a6d..412a81f 100644
--- a/arch/arm/plat-mxc/devices/platform-spi_imx.c
+++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c
@@ -6,25 +6,83 @@
  * the terms of the GNU General Public License version 2 as published by the
  * Free Software Foundation.
  */
-#include <asm/sizes.h>
+#include <mach/hardware.h>
 #include <mach/devices-common.h>
 
-struct platform_device *__init imx_add_spi_imx(int id,
-		resource_size_t iobase, resource_size_t iosize, int irq,
+#define imx_spi_imx_data_entry_single(soc, type, _devid, _id, hwid, _size) \
+	{								\
+		.id = _id,						\
+		.iobase = soc ## _ ## type ## hwid ## _BASE_ADDR,	\
+		.iosize = _size,					\
+		.irq = soc ## _INT_ ## type ## hwid,			\
+	}
+
+#define imx_spi_imx_data_entry(soc, type, devid, id, hwid, size)	\
+	[id] = imx_spi_imx_data_entry_single(soc, type, devid, id, hwid, size)
+
+#ifdef CONFIG_SOC_IMX21
+const struct imx_spi_imx_data imx21_cspi_data[] __initconst = {
+#define imx21_cspi_data_entry(_id, _hwid)                            \
+	imx_spi_imx_data_entry(MX21, CSPI, "imx21-cspi", _id, _hwid, SZ_4K)
+	imx21_cspi_data_entry(0, 1),
+	imx21_cspi_data_entry(1, 2),
+#endif
+
+#ifdef CONFIG_ARCH_MX25
+const struct imx_spi_imx_data imx25_cspi_data[] __initconst = {
+#define imx25_cspi_data_entry(_id, _hwid)				\
+	imx_spi_imx_data_entry(MX25, CSPI, "imx25-cspi", _id, _hwid, SZ_16K)
+	imx25_cspi_data_entry(0, 1),
+	imx25_cspi_data_entry(1, 2),
+	imx25_cspi_data_entry(2, 3),
+};
+#endif /* ifdef CONFIG_ARCH_MX25 */
+
+#ifdef CONFIG_SOC_IMX27
+const struct imx_spi_imx_data imx27_cspi_data[] __initconst = {
+#define imx27_cspi_data_entry(_id, _hwid)				\
+	imx_spi_imx_data_entry(MX27, CSPI, "imx27-cspi", _id, _hwid, SZ_4K)
+	imx27_cspi_data_entry(0, 1),
+	imx27_cspi_data_entry(1, 2),
+	imx27_cspi_data_entry(2, 3),
+};
+#endif /* ifdef CONFIG_SOC_IMX27 */
+
+#ifdef CONFIG_ARCH_MX31
+const struct imx_spi_imx_data imx31_cspi_data[] __initconst = {
+#define imx31_cspi_data_entry(_id, _hwid)				\
+	imx_spi_imx_data_entry(MX31, CSPI, "imx31-cspi", _id, _hwid, SZ_4K)
+	imx31_cspi_data_entry(0, 1),
+	imx31_cspi_data_entry(1, 2),
+	imx31_cspi_data_entry(2, 3),
+};
+#endif /* ifdef CONFIG_ARCH_MX31 */
+
+#ifdef CONFIG_ARCH_MX35
+const struct imx_spi_imx_data imx35_cspi_data[] __initconst = {
+#define imx35_cspi_data_entry(_id, _hwid)                           \
+	imx_spi_imx_data_entry(MX35, CSPI, "imx35-cspi", _id, _hwid, SZ_4K)
+	imx35_cspi_data_entry(0, 1),
+	imx35_cspi_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_ARCH_MX35 */
+
+struct platform_device *__init imx_add_spi_imx(
+		const struct imx_spi_imx_data *data,
 		const struct spi_imx_master *pdata)
 {
 	struct resource res[] = {
 		{
-			.start = iobase,
-			.end = iobase + iosize - 1,
+			.start = data->iobase,
+			.end = data->iobase + data->iosize - 1,
 			.flags = IORESOURCE_MEM,
 		}, {
-			.start = irq,
-			.end = irq,
+			.start = data->irq,
+			.end = data->irq,
 			.flags = IORESOURCE_IRQ,
 		},
 	};
 
-	return imx_add_platform_device("spi_imx", id, res, ARRAY_SIZE(res),
-			pdata, sizeof(*pdata));
+	return imx_add_platform_device("spi_imx", data->id,
+			res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
 }
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index c5f68c5..abe12c29 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -55,6 +55,12 @@ struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase,
 		int irq, const struct mxc_nand_platform_data *pdata);
 
 #include <mach/spi.h>
-struct platform_device *__init imx_add_spi_imx(int id,
-		resource_size_t iobase, resource_size_t iosize, int irq,
+struct imx_spi_imx_data {
+	int id;
+	resource_size_t iobase;
+	resource_size_t iosize;
+	int irq;
+};
+struct platform_device *__init imx_add_spi_imx(
+		const struct imx_spi_imx_data *data,
 		const struct spi_imx_master *pdata);
-- 
1.7.2.3


------------------------------------------------------------------------------
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and start using them to simplify application deployment and
accelerate your shift to cloud computing.
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[PATCH 07/16] ARM: imx: use platform ids for spi_imx devices

[Uwe Kleine-König]

The driver recently learned to handle platform ids.  Make use of this
new feature.  The up side is that the driver needs less knowledge about
the spi interfaces used on different SoCs.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
 arch/arm/mach-imx/clock-imx1.c                  |    2 +-
 arch/arm/mach-imx/clock-imx21.c                 |    6 +++---
 arch/arm/mach-imx/clock-imx27.c                 |    6 +++---
 arch/arm/mach-mx25/clock.c                      |    6 +++---
 arch/arm/mach-mx3/clock-imx31.c                 |    6 +++---
 arch/arm/mach-mx3/clock-imx35.c                 |    4 ++--
 arch/arm/plat-mxc/devices/platform-spi_imx.c    |    3 ++-
 arch/arm/plat-mxc/include/mach/devices-common.h |    1 +
 8 files changed, 18 insertions(+), 16 deletions(-)

diff --git a/arch/arm/mach-imx/clock-imx1.c b/arch/arm/mach-imx/clock-imx1.c
index c05096c..daca30b 100644
--- a/arch/arm/mach-imx/clock-imx1.c
+++ b/arch/arm/mach-imx/clock-imx1.c
@@ -592,7 +592,7 @@ static struct clk_lookup lookups[] __initdata = {
 	_REGISTER_CLOCK("imx-uart.1", NULL, uart_clk)
 	_REGISTER_CLOCK("imx-uart.2", NULL, uart_clk)
 	_REGISTER_CLOCK("imx-i2c.0", NULL, i2c_clk)
-	_REGISTER_CLOCK("spi_imx.0", NULL, spi_clk)
+	_REGISTER_CLOCK("imx1-cspi.0", NULL, spi_clk)
 	_REGISTER_CLOCK("imx-mmc.0", NULL, sdhc_clk)
 	_REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
 	_REGISTER_CLOCK(NULL, "mshc", mshc_clk)
diff --git a/arch/arm/mach-imx/clock-imx21.c b/arch/arm/mach-imx/clock-imx21.c
index bb419ef..cf15ea5 100644
--- a/arch/arm/mach-imx/clock-imx21.c
+++ b/arch/arm/mach-imx/clock-imx21.c
@@ -1172,9 +1172,9 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK(NULL, "pwm", pwm_clk[0])
 	_REGISTER_CLOCK(NULL, "sdhc1", sdhc_clk[0])
 	_REGISTER_CLOCK(NULL, "sdhc2", sdhc_clk[1])
-	_REGISTER_CLOCK(NULL, "cspi1", cspi_clk[0])
-	_REGISTER_CLOCK(NULL, "cspi2", cspi_clk[1])
-	_REGISTER_CLOCK(NULL, "cspi3", cspi_clk[2])
+	_REGISTER_CLOCK("imx21-cspi.0", NULL, cspi_clk[0])
+	_REGISTER_CLOCK("imx21-cspi.1", NULL, cspi_clk[1])
+	_REGISTER_CLOCK("imx21-cspi.2", NULL, cspi_clk[2])
 	_REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk[0])
 	_REGISTER_CLOCK(NULL, "csi", csi_clk[0])
 	_REGISTER_CLOCK("imx21-hcd.0", NULL, usb_clk[0])
diff --git a/arch/arm/mach-imx/clock-imx27.c b/arch/arm/mach-imx/clock-imx27.c
index 5a1aa15..07bf315 100644
--- a/arch/arm/mach-imx/clock-imx27.c
+++ b/arch/arm/mach-imx/clock-imx27.c
@@ -640,9 +640,9 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk)
 	_REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk)
 	_REGISTER_CLOCK("mxc-mmc.2", NULL, sdhc3_clk)
-	_REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
-	_REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
-	_REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk)
+	_REGISTER_CLOCK("imx27-cspi.0", NULL, cspi1_clk)
+	_REGISTER_CLOCK("imx27-cspi.1", NULL, cspi2_clk)
+	_REGISTER_CLOCK("imx27-cspi.2", NULL, cspi3_clk)
 	_REGISTER_CLOCK("imx-fb.0", NULL, lcdc_clk)
 	_REGISTER_CLOCK("mx2-camera.0", NULL, csi_clk)
 	_REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk)
diff --git a/arch/arm/mach-mx25/clock.c b/arch/arm/mach-mx25/clock.c
index 40c7cc4..039464a 100644
--- a/arch/arm/mach-mx25/clock.c
+++ b/arch/arm/mach-mx25/clock.c
@@ -261,9 +261,9 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
 	_REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
 	_REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
-	_REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
-	_REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
-	_REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk)
+	_REGISTER_CLOCK("imx25-cspi.0", NULL, cspi1_clk)
+	_REGISTER_CLOCK("imx25-cspi.1", NULL, cspi2_clk)
+	_REGISTER_CLOCK("imx25-cspi.2", NULL, cspi3_clk)
 	_REGISTER_CLOCK("mxc_pwm.0", NULL, pwm1_clk)
 	_REGISTER_CLOCK("mxc_pwm.1", NULL, pwm2_clk)
 	_REGISTER_CLOCK("mxc_pwm.2", NULL, pwm3_clk)
diff --git a/arch/arm/mach-mx3/clock-imx31.c b/arch/arm/mach-mx3/clock-imx31.c
index 9a9eb6d..18e98f1 100644
--- a/arch/arm/mach-mx3/clock-imx31.c
+++ b/arch/arm/mach-mx3/clock-imx31.c
@@ -525,9 +525,9 @@ DEFINE_CLOCK(ipg_clk,     0, NULL,          0, ipg_get_rate, NULL, &ahb_clk);
 
 static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK(NULL, "emi", emi_clk)
-	_REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
-	_REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
-	_REGISTER_CLOCK("spi_imx.2", NULL, cspi3_clk)
+	_REGISTER_CLOCK("imx31-cspi.0", NULL, cspi1_clk)
+	_REGISTER_CLOCK("imx31-cspi.1", NULL, cspi2_clk)
+	_REGISTER_CLOCK("imx31-cspi.2", NULL, cspi3_clk)
 	_REGISTER_CLOCK(NULL, "gpt", gpt_clk)
 	_REGISTER_CLOCK(NULL, "pwm", pwm_clk)
 	_REGISTER_CLOCK("imx-wdt.0", NULL, wdog_clk)
diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c
index f11ef99..708c2b3 100644
--- a/arch/arm/mach-mx3/clock-imx35.c
+++ b/arch/arm/mach-mx3/clock-imx35.c
@@ -451,8 +451,8 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK(NULL, "ata", ata_clk)
 	_REGISTER_CLOCK("flexcan.0", NULL, can1_clk)
 	_REGISTER_CLOCK("flexcan.1", NULL, can2_clk)
-	_REGISTER_CLOCK("spi_imx.0", NULL, cspi1_clk)
-	_REGISTER_CLOCK("spi_imx.1", NULL, cspi2_clk)
+	_REGISTER_CLOCK("imx35-cspi.0", NULL, cspi1_clk)
+	_REGISTER_CLOCK("imx35-cspi.1", NULL, cspi2_clk)
 	_REGISTER_CLOCK(NULL, "ect", ect_clk)
 	_REGISTER_CLOCK(NULL, "edio", edio_clk)
 	_REGISTER_CLOCK(NULL, "emi", emi_clk)
diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c
index 412a81f..bd30d4b 100644
--- a/arch/arm/plat-mxc/devices/platform-spi_imx.c
+++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c
@@ -11,6 +11,7 @@
 
 #define imx_spi_imx_data_entry_single(soc, type, _devid, _id, hwid, _size) \
 	{								\
+		.devid = _devid,					\
 		.id = _id,						\
 		.iobase = soc ## _ ## type ## hwid ## _BASE_ADDR,	\
 		.iosize = _size,					\
@@ -83,6 +84,6 @@ struct platform_device *__init imx_add_spi_imx(
 		},
 	};
 
-	return imx_add_platform_device("spi_imx", data->id,
+	return imx_add_platform_device(data->devid, data->id,
 			res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
 }
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index abe12c29..dbb9b47 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -56,6 +56,7 @@ struct platform_device *__init imx_add_mxc_nand_v21(resource_size_t iobase,
 
 #include <mach/spi.h>
 struct imx_spi_imx_data {
+	const char *devid;
 	int id;
 	resource_size_t iobase;
 	resource_size_t iosize;
-- 
1.7.2.3


------------------------------------------------------------------------------
Start uncovering the many advantages of virtual appliances
and start using them to simplify application deployment and
accelerate your shift to cloud computing.
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_______________________________________________
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[PATCH 08/16] ARM: mx51: clean up mx51 header

[Uwe Kleine-König]

This makes the header more look like the other ones, i.e.

 - sort #defines by value
 - use lowercase hex constants
 - use a consistently named header guard

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
 arch/arm/plat-mxc/include/mach/mx51.h |  608 ++++++++++++++++-----------------
 1 files changed, 300 insertions(+), 308 deletions(-)

diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
index 5aad344..92b39f7 100644
--- a/arch/arm/plat-mxc/include/mach/mx51.h
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_ARCH_MXC_MX51_H__
-#define __ASM_ARCH_MXC_MX51_H__
+#ifndef __MACH_MX51_H__
+#define __MACH_MX51_H__
 
 /*
  * MX51 memory map:
@@ -7,24 +7,23 @@
  *
  * Virt		Phys		Size	What
  * ---------------------------------------------------------------------------
- * FA3E0000	1FFE0000	128K	IRAM (SCCv2 RAM)
+ * fa3e0000	1ffe0000	128K	IRAM (SCCv2 RAM)
  *         	30000000	256M	GPU
  *         	40000000	512M	IPU
- * FA200000	60000000	1M	DEBUG
- * FB100000	70000000	1M	SPBA 0
- * FB000000	73F00000	1M	AIPS 1
- * FB200000	83F00000	1M	AIPS 2
- *		8FFFC000	16K	TZIC (interrupt controller)
+ * fa200000	60000000	1M	DEBUG
+ * fb100000	70000000	1M	SPBA 0
+ * fb000000	73f00000	1M	AIPS 1
+ * fb200000	83f00000	1M	AIPS 2
+ *		8fffc000	16K	TZIC (interrupt controller)
  *         	90000000	256M	CSD0 SDRAM/DDR
- *         	A0000000	256M	CSD1 SDRAM/DDR
- *         	B0000000	128M	CS0 Flash
- *         	B8000000	128M	CS1 Flash
- *         	C0000000	128M	CS2 Flash
- *         	C8000000	64M	CS3 Flash
- *         	CC000000	32M	CS4 SRAM
- *         	CE000000	32M	CS5 SRAM
- *		CFFF0000	64K	NFC (NAND Flash AXI)
- *
+ *         	a0000000	256M	CSD1 SDRAM/DDR
+ *         	b0000000	128M	CS0 Flash
+ *         	b8000000	128M	CS1 Flash
+ *         	c0000000	128M	CS2 Flash
+ *         	c8000000	64M	CS3 Flash
+ *         	cc000000	32M	CS4 SRAM
+ *         	ce000000	32M	CS5 SRAM
+ *		cfff0000	64K	NFC (NAND Flash AXI)
  */
 
 /*
@@ -36,65 +35,140 @@
 /*
  * IRAM
  */
-#define MX51_IRAM_BASE_ADDR		0x1FFE0000	/* internal ram */
-#define MX51_IRAM_BASE_ADDR_VIRT	0xFA3E0000
+#define MX51_IRAM_BASE_ADDR		0x1ffe0000	/* internal ram */
+#define MX51_IRAM_BASE_ADDR_VIRT	0xfa3e0000
 #define MX51_IRAM_PARTITIONS		16
-#define MX51_IRAM_PARTITIONS_TO1	12
 #define MX51_IRAM_SIZE		(MX51_IRAM_PARTITIONS * SZ_8K)	/* 128KB */
 
+#define MX51_GPU_BASE_ADDR		0x20000000
+#define MX51_GPU_CTRL_BASE_ADDR		0x30000000
+#define MX51_IPU_CTRL_BASE_ADDR		0x40000000
+
+#define MX51_DEBUG_BASE_ADDR		0x60000000
+#define MX51_DEBUG_BASE_ADDR_VIRT	0xfa200000
+#define MX51_DEBUG_SIZE			SZ_1M
+
+#define MX51_ETB_BASE_ADDR		(MX51_DEBUG_BASE_ADDR + 0x01000)
+#define MX51_ETM_BASE_ADDR		(MX51_DEBUG_BASE_ADDR + 0x02000)
+#define MX51_TPIU_BASE_ADDR		(MX51_DEBUG_BASE_ADDR + 0x03000)
+#define MX51_CTI0_BASE_ADDR		(MX51_DEBUG_BASE_ADDR + 0x04000)
+#define MX51_CTI1_BASE_ADDR		(MX51_DEBUG_BASE_ADDR + 0x05000)
+#define MX51_CTI2_BASE_ADDR		(MX51_DEBUG_BASE_ADDR + 0x06000)
+#define MX51_CTI3_BASE_ADDR		(MX51_DEBUG_BASE_ADDR + 0x07000)
+#define MX51_CORTEX_DBG_BASE_ADDR	(MX51_DEBUG_BASE_ADDR + 0x08000)
+
 /*
- * NFC
+ * SPBA global module enabled #0
  */
-#define MX51_NFC_AXI_BASE_ADDR		0xCFFF0000	/* NAND flash AXI */
-#define MX51_NFC_AXI_SIZE		SZ_64K
+#define MX51_SPBA0_BASE_ADDR		0x70000000
+#define MX51_SPBA0_BASE_ADDR_VIRT	0xfb100000
+#define MX51_SPBA0_SIZE			SZ_1M
+
+#define MX51_MMC_SDHC1_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x04000)
+#define MX51_MMC_SDHC2_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x08000)
+#define MX51_UART3_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x0c000)
+#define MX51_CSPI1_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x10000)
+#define MX51_SSI2_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x14000)
+#define MX51_MMC_SDHC3_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x20000)
+#define MX51_MMC_SDHC4_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x24000)
+#define MX51_SPDIF_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x28000)
+#define MX51_ATA_DMA_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x30000)
+#define MX51_SLIM_DMA_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x34000)
+#define MX51_HSI2C_DMA_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x38000)
+#define MX51_SPBA_CTRL_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x3c000)
 
 /*
- * Graphics Memory of GPU
+ * AIPS 1
  */
-#define MX51_GPU_BASE_ADDR		0x20000000
-#define MX51_GPU2D_BASE_ADDR		0xD0000000
+#define MX51_AIPS1_BASE_ADDR		0x73f00000
+#define MX51_AIPS1_BASE_ADDR_VIRT	0xfb000000
+#define MX51_AIPS1_SIZE			SZ_1M
+
+#define MX51_OTG_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0x80000)
+#define MX51_GPIO1_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0x84000)
+#define MX51_GPIO2_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0x88000)
+#define MX51_GPIO3_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0x8c000)
+#define MX51_GPIO4_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0x90000)
+#define MX51_KPP_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0x94000)
+#define MX51_WDOG_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0x98000)
+#define MX51_WDOG2_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0x9c000)
+#define MX51_GPT1_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0xa0000)
+#define MX51_SRTC_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0xa4000)
+#define MX51_IOMUXC_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0xa8000)
+#define MX51_EPIT1_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0xac000)
+#define MX51_EPIT2_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0xb0000)
+#define MX51_PWM1_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0xb4000)
+#define MX51_PWM2_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0xb8000)
+#define MX51_UART1_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0xbc000)
+#define MX51_UART2_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0xc0000)
+#define MX51_SRC_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0xd0000)
+#define MX51_CCM_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0xd4000)
+#define MX51_GPC_BASE_ADDR		(MX51_AIPS1_BASE_ADDR + 0xd8000)
 
-#define MX51_TZIC_BASE_ADDR_TO1		0x8FFFC000
-#define MX51_TZIC_BASE_ADDR		0xE0000000
+/*
+ * AIPS 2
+ */
+#define MX51_AIPS2_BASE_ADDR		0x83f00000
+#define MX51_AIPS2_BASE_ADDR_VIRT	0xfb200000
+#define MX51_AIPS2_SIZE			SZ_1M
 
-#define MX51_DEBUG_BASE_ADDR		0x60000000
-#define MX51_DEBUG_BASE_ADDR_VIRT	0xFA200000
-#define MX51_DEBUG_SIZE			SZ_1M
-#define MX51_ETB_BASE_ADDR		(MX51_DEBUG_BASE_ADDR + 0x00001000)
-#define MX51_ETM_BASE_ADDR		(MX51_DEBUG_BASE_ADDR + 0x00002000)
-#define MX51_TPIU_BASE_ADDR		(MX51_DEBUG_BASE_ADDR + 0x00003000)
-#define MX51_CTI0_BASE_ADDR		(MX51_DEBUG_BASE_ADDR + 0x00004000)
-#define MX51_CTI1_BASE_ADDR		(MX51_DEBUG_BASE_ADDR + 0x00005000)
-#define MX51_CTI2_BASE_ADDR		(MX51_DEBUG_BASE_ADDR + 0x00006000)
-#define MX51_CTI3_BASE_ADDR		(MX51_DEBUG_BASE_ADDR + 0x00007000)
-#define MX51_CORTEX_DBG_BASE_ADDR	(MX51_DEBUG_BASE_ADDR + 0x00008000)
+#define MX51_PLL1_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0x80000)
+#define MX51_PLL2_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0x84000)
+#define MX51_PLL3_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0x88000)
+#define MX51_AHBMAX_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0x94000)
+#define MX51_IIM_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0x98000)
+#define MX51_CSU_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0x9c000)
+#define MX51_ARM_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xa0000)
+#define MX51_OWIRE_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xa4000)
+#define MX51_FIRI_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xa8000)
+#define MX51_CSPI2_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xac000)
+#define MX51_SDMA_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xb0000)
+#define MX51_SCC_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xb4000)
+#define MX51_ROMCP_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xb8000)
+#define MX51_RTIC_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xbc000)
+#define MX51_CSPI3_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xc0000)
+#define MX51_I2C2_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xc4000)
+#define MX51_I2C1_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xc8000)
+#define MX51_SSI1_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xcc000)
+#define MX51_AUDMUX_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xd0000)
+#define MX51_M4IF_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xd8000)
+#define MX51_ESDCTL_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xd9000)
+#define MX51_WEIM_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xda000)
+#define MX51_NFC_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xdb000)
+#define MX51_EMI_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xdbf00)
+#define MX51_MIPI_HSC_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xdc000)
+#define MX51_ATA_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xe0000)
+#define MX51_SIM_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xe4000)
+#define MX51_SSI3BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xe8000)
+#define MX51_MXC_FEC_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xec000)
+#define MX51_TVE_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xf0000)
+#define MX51_VPU_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xf4000)
+#define MX51_SAHARA_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xf8000)
+
+#define MX51_CSD0_BASE_ADDR		0x90000000
+#define MX51_CSD1_BASE_ADDR		0xa0000000
+#define MX51_CS0_BASE_ADDR		0xb0000000
+#define MX51_CS1_BASE_ADDR		0xb8000000
+#define MX51_CS2_BASE_ADDR		0xc0000000
+#define MX51_CS3_BASE_ADDR		0xc8000000
+#define MX51_CS4_BASE_ADDR		0xcc000000
+#define MX51_CS5_BASE_ADDR		0xce000000
 
 /*
- * SPBA global module enabled #0
+ * NFC
  */
-#define MX51_SPBA0_BASE_ADDR 		0x70000000
-#define MX51_SPBA0_BASE_ADDR_VIRT	0xFB100000
-#define MX51_SPBA0_SIZE			SZ_1M
+#define MX51_NFC_AXI_BASE_ADDR		0xcfff0000	/* NAND flash AXI */
+#define MX51_NFC_AXI_SIZE		SZ_64K
 
-#define MX51_MMC_SDHC1_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x00004000)
-#define MX51_MMC_SDHC2_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x00008000)
-#define MX51_UART3_BASE_ADDR 		(MX51_SPBA0_BASE_ADDR + 0x0000C000)
-#define MX51_CSPI1_BASE_ADDR 		(MX51_SPBA0_BASE_ADDR + 0x00010000)
-#define MX51_SSI2_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x00014000)
-#define MX51_MMC_SDHC3_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x00020000)
-#define MX51_MMC_SDHC4_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x00024000)
-#define MX51_SPDIF_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x00028000)
-#define MX51_ATA_DMA_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x00030000)
-#define MX51_SLIM_DMA_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x00034000)
-#define MX51_HSI2C_DMA_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x00038000)
-#define MX51_SPBA_CTRL_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x0003C000)
+#define MX51_GPU2D_BASE_ADDR		0xd0000000
+#define MX51_TZIC_BASE_ADDR		0xe0000000
 
 /*
  * defines for SPBA modules
  */
 #define MX51_SPBA_SDHC1	0x04
 #define MX51_SPBA_SDHC2	0x08
-#define MX51_SPBA_UART3	0x0C
+#define MX51_SPBA_UART3	0x0c
 #define MX51_SPBA_CSPI1	0x10
 #define MX51_SPBA_SSI2	0x14
 #define MX51_SPBA_SDHC3	0x20
@@ -103,35 +177,7 @@
 #define MX51_SPBA_ATA	0x30
 #define MX51_SPBA_SLIM	0x34
 #define MX51_SPBA_HSI2C	0x38
-#define MX51_SPBA_CTRL	0x3C
-
-/*
- * AIPS 1
- */
-#define MX51_AIPS1_BASE_ADDR 	0x73F00000
-#define MX51_AIPS1_BASE_ADDR_VIRT	0xFB000000
-#define MX51_AIPS1_SIZE		SZ_1M
-
-#define MX51_OTG_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x00080000)
-#define MX51_GPIO1_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x00084000)
-#define MX51_GPIO2_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x00088000)
-#define MX51_GPIO3_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x0008C000)
-#define MX51_GPIO4_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x00090000)
-#define MX51_KPP_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x00094000)
-#define MX51_WDOG_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x00098000)
-#define MX51_WDOG2_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x0009C000)
-#define MX51_GPT1_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000A0000)
-#define MX51_SRTC_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000A4000)
-#define MX51_IOMUXC_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000A8000)
-#define MX51_EPIT1_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000AC000)
-#define MX51_EPIT2_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000B0000)
-#define MX51_PWM1_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000B4000)
-#define MX51_PWM2_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000B8000)
-#define MX51_UART1_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000BC000)
-#define MX51_UART2_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000C0000)
-#define MX51_SRC_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000D0000)
-#define MX51_CCM_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000D4000)
-#define MX51_GPC_BASE_ADDR	(MX51_AIPS1_BASE_ADDR + 0x000D8000)
+#define MX51_SPBA_CTRL	0x3c
 
 /*
  * Defines for modules using static and dynamic DMA channels
@@ -164,60 +210,6 @@
 #define MX51_MXC_DMA_CHANNEL_ATA_TX	MXC_DMA_DYNAMIC_CHANNEL
 #define MX51_MXC_DMA_CHANNEL_MEMORY	MXC_DMA_DYNAMIC_CHANNEL
 
-/*
- * AIPS 2
- */
-#define MX51_AIPS2_BASE_ADDR		0x83F00000
-#define MX51_AIPS2_BASE_ADDR_VIRT	0xFB200000
-#define MX51_AIPS2_SIZE			SZ_1M
-
-#define MX51_PLL1_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x00080000)
-#define MX51_PLL2_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x00084000)
-#define MX51_PLL3_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x00088000)
-#define MX51_AHBMAX_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x00094000)
-#define MX51_IIM_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x00098000)
-#define MX51_CSU_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x0009C000)
-#define MX51_ARM_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000A0000)
-#define MX51_OWIRE_BASE_ADDR 	(MX51_AIPS2_BASE_ADDR + 0x000A4000)
-#define MX51_FIRI_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000A8000)
-#define MX51_CSPI2_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000AC000)
-#define MX51_SDMA_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000B0000)
-#define MX51_SCC_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000B4000)
-#define MX51_ROMCP_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000B8000)
-#define MX51_RTIC_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000BC000)
-#define MX51_CSPI3_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000C0000)
-#define MX51_I2C2_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000C4000)
-#define MX51_I2C1_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000C8000)
-#define MX51_SSI1_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000CC000)
-#define MX51_AUDMUX_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000D0000)
-#define MX51_M4IF_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000D8000)
-#define MX51_ESDCTL_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000D9000)
-#define MX51_WEIM_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000DA000)
-#define MX51_NFC_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000DB000)
-#define MX51_EMI_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000DBF00)
-#define MX51_MIPI_HSC_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000DC000)
-#define MX51_ATA_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000E0000)
-#define MX51_SIM_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000E4000)
-#define MX51_SSI3BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000E8000)
-#define MX51_MXC_FEC_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000EC000)
-#define MX51_TVE_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000F0000)
-#define MX51_VPU_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000F4000)
-#define MX51_SAHARA_BASE_ADDR	(MX51_AIPS2_BASE_ADDR + 0x000F8000)
-
-/*
- * Memory regions and CS
- */
-#define MX51_GPU_CTRL_BASE_ADDR		0x30000000
-#define MX51_IPU_CTRL_BASE_ADDR		0x40000000
-#define MX51_CSD0_BASE_ADDR		0x90000000
-#define MX51_CSD1_BASE_ADDR		0xA0000000
-#define MX51_CS0_BASE_ADDR		0xB0000000
-#define MX51_CS1_BASE_ADDR		0xB8000000
-#define MX51_CS2_BASE_ADDR		0xC0000000
-#define MX51_CS3_BASE_ADDR		0xC8000000
-#define MX51_CS4_BASE_ADDR		0xCC000000
-#define MX51_CS5_BASE_ADDR		0xCE000000
-
 /* Does given address belongs to the specified memory region? */
 #define ADDRESS_IN_REGION(addr, start, size)			\
 	(((addr) >= (start)) && ((addr) < (start)+(size)))
@@ -230,7 +222,7 @@
  * This macro defines the physical to virtual address mapping for all the
  * peripheral modules. It is used by passing in the physical address as x
  * and returning the virtual address. If the physical address is not mapped,
- * it returns 0xDEADBEEF
+ * it returns 0xdeadbeef
  */
 
 #define MX51_IO_ADDRESS(x)					\
@@ -240,7 +232,7 @@
 	MX51_IS_MODULE(x, SPBA0) ? MX51_SPBA0_IO_ADDRESS(x) :	\
 	MX51_IS_MODULE(x, AIPS1) ? MX51_AIPS1_IO_ADDRESS(x) :	\
 	MX51_IS_MODULE(x, AIPS2) ? MX51_AIPS2_IO_ADDRESS(x) : \
-	0xDEADBEEF)
+	0xdeadbeef)
 
 /*
  * define the address mapping macros: in physical address order
@@ -265,181 +257,181 @@
 /*
  * DMA request assignments
  */
-#define MX51_DMA_REQ_SSI3_TX1	47
-#define MX51_DMA_REQ_SSI3_RX1	46
-#define MX51_DMA_REQ_SPDIF	45
-#define MX51_DMA_REQ_UART3_TX	44
-#define MX51_DMA_REQ_UART3_RX	43
-#define MX51_DMA_REQ_SLIM_B_TX	42
-#define MX51_DMA_REQ_SDHC4	41
-#define MX51_DMA_REQ_SDHC3	40
-#define MX51_DMA_REQ_CSPI_TX	39
-#define MX51_DMA_REQ_CSPI_RX	38
-#define MX51_DMA_REQ_SSI3_TX2	37
-#define MX51_DMA_REQ_IPU	36
-#define MX51_DMA_REQ_SSI3_RX2	35
-#define MX51_DMA_REQ_EPIT2	34
-#define MX51_DMA_REQ_CTI2_1	33
-#define MX51_DMA_REQ_EMI_WR	32
-#define MX51_DMA_REQ_CTI2_0	31
-#define MX51_DMA_REQ_EMI_RD	30
-#define MX51_DMA_REQ_SSI1_TX1	29
-#define MX51_DMA_REQ_SSI1_RX1	28
-#define MX51_DMA_REQ_SSI1_TX2	27
-#define MX51_DMA_REQ_SSI1_RX2	26
-#define MX51_DMA_REQ_SSI2_TX1	25
-#define MX51_DMA_REQ_SSI2_RX1	24
-#define MX51_DMA_REQ_SSI2_TX2	23
-#define MX51_DMA_REQ_SSI2_RX2	22
-#define MX51_DMA_REQ_SDHC2	21
-#define MX51_DMA_REQ_SDHC1	20
-#define MX51_DMA_REQ_UART1_TX	19
-#define MX51_DMA_REQ_UART1_RX	18
-#define MX51_DMA_REQ_UART2_TX	17
-#define MX51_DMA_REQ_UART2_RX	16
-#define MX51_DMA_REQ_GPU	15
-#define MX51_DMA_REQ_EXTREQ1	14
-#define MX51_DMA_REQ_FIRI_TX	13
-#define MX51_DMA_REQ_FIRI_RX	12
-#define MX51_DMA_REQ_HS_I2C_RX	11
-#define MX51_DMA_REQ_HS_I2C_TX	10
-#define MX51_DMA_REQ_CSPI2_TX	9
-#define MX51_DMA_REQ_CSPI2_RX	8
-#define MX51_DMA_REQ_CSPI1_TX	7
-#define MX51_DMA_REQ_CSPI1_RX	6
-#define MX51_DMA_REQ_SLIM_B	5
-#define MX51_DMA_REQ_ATA_TX_END	4
-#define MX51_DMA_REQ_ATA_TX	3
-#define MX51_DMA_REQ_ATA_RX	2
-#define MX51_DMA_REQ_GPC	1
-#define MX51_DMA_REQ_VPU	0
+#define MX51_DMA_REQ_VPU		0
+#define MX51_DMA_REQ_GPC		1
+#define MX51_DMA_REQ_ATA_RX		2
+#define MX51_DMA_REQ_ATA_TX		3
+#define MX51_DMA_REQ_ATA_TX_END		4
+#define MX51_DMA_REQ_SLIM_B		5
+#define MX51_DMA_REQ_CSPI1_RX		6
+#define MX51_DMA_REQ_CSPI1_TX		7
+#define MX51_DMA_REQ_CSPI2_RX		8
+#define MX51_DMA_REQ_CSPI2_TX		9
+#define MX51_DMA_REQ_HS_I2C_TX		10
+#define MX51_DMA_REQ_HS_I2C_RX		11
+#define MX51_DMA_REQ_FIRI_RX		12
+#define MX51_DMA_REQ_FIRI_TX		13
+#define MX51_DMA_REQ_EXTREQ1		14
+#define MX51_DMA_REQ_GPU		15
+#define MX51_DMA_REQ_UART2_RX		16
+#define MX51_DMA_REQ_UART2_TX		17
+#define MX51_DMA_REQ_UART1_RX		18
+#define MX51_DMA_REQ_UART1_TX		19
+#define MX51_DMA_REQ_SDHC1		20
+#define MX51_DMA_REQ_SDHC2		21
+#define MX51_DMA_REQ_SSI2_RX2		22
+#define MX51_DMA_REQ_SSI2_TX2		23
+#define MX51_DMA_REQ_SSI2_RX1		24
+#define MX51_DMA_REQ_SSI2_TX1		25
+#define MX51_DMA_REQ_SSI1_RX2		26
+#define MX51_DMA_REQ_SSI1_TX2		27
+#define MX51_DMA_REQ_SSI1_RX1		28
+#define MX51_DMA_REQ_SSI1_TX1		29
+#define MX51_DMA_REQ_EMI_RD		30
+#define MX51_DMA_REQ_CTI2_0		31
+#define MX51_DMA_REQ_EMI_WR		32
+#define MX51_DMA_REQ_CTI2_1		33
+#define MX51_DMA_REQ_EPIT2		34
+#define MX51_DMA_REQ_SSI3_RX2		35
+#define MX51_DMA_REQ_IPU		36
+#define MX51_DMA_REQ_SSI3_TX2		37
+#define MX51_DMA_REQ_CSPI_RX		38
+#define MX51_DMA_REQ_CSPI_TX		39
+#define MX51_DMA_REQ_SDHC3		40
+#define MX51_DMA_REQ_SDHC4		41
+#define MX51_DMA_REQ_SLIM_B_TX		42
+#define MX51_DMA_REQ_UART3_RX		43
+#define MX51_DMA_REQ_UART3_TX		44
+#define MX51_DMA_REQ_SPDIF		45
+#define MX51_DMA_REQ_SSI3_RX1		46
+#define MX51_DMA_REQ_SSI3_TX1		47
 
 /*
  * Interrupt numbers
  */
-#define MX51_MXC_INT_BASE	0
-#define MX51_MXC_INT_RESV0	0
-#define MX51_MXC_INT_MMC_SDHC1	1
-#define MX51_MXC_INT_MMC_SDHC2	2
-#define MX51_MXC_INT_MMC_SDHC3	3
-#define MX51_MXC_INT_MMC_SDHC4	4
-#define MX51_MXC_INT_RESV5	5
-#define MX51_MXC_INT_SDMA	6
-#define MX51_MXC_INT_IOMUX	7
-#define MX51_MXC_INT_NFC	8
-#define MX51_MXC_INT_VPU	9
-#define MX51_MXC_INT_IPU_ERR	10
-#define MX51_MXC_INT_IPU_SYN	11
-#define MX51_MXC_INT_GPU	12
-#define MX51_MXC_INT_RESV13	13
-#define MX51_MXC_INT_USB_H1	14
-#define MX51_MXC_INT_EMI	15
-#define MX51_MXC_INT_USB_H2	16
-#define MX51_MXC_INT_USB_H3	17
-#define MX51_MXC_INT_USB_OTG	18
-#define MX51_MXC_INT_SAHARA_H0	19
-#define MX51_MXC_INT_SAHARA_H1	20
-#define MX51_MXC_INT_SCC_SMN	21
-#define MX51_MXC_INT_SCC_STZ	22
-#define MX51_MXC_INT_SCC_SCM	23
-#define MX51_MXC_INT_SRTC_NTZ	24
-#define MX51_MXC_INT_SRTC_TZ	25
-#define MX51_MXC_INT_RTIC	26
-#define MX51_MXC_INT_CSU	27
-#define MX51_MXC_INT_SLIM_B	28
-#define MX51_MXC_INT_SSI1	29
-#define MX51_MXC_INT_SSI2	30
-#define MX51_MXC_INT_UART1	31
-#define MX51_MXC_INT_UART2	32
-#define MX51_MXC_INT_UART3	33
-#define MX51_MXC_INT_RESV34	34
-#define MX51_MXC_INT_RESV35	35
-#define MX51_MXC_INT_CSPI1	36
-#define MX51_MXC_INT_CSPI2	37
-#define MX51_MXC_INT_CSPI	38
-#define MX51_MXC_INT_GPT	39
-#define MX51_MXC_INT_EPIT1	40
-#define MX51_MXC_INT_EPIT2	41
-#define MX51_MXC_INT_GPIO1_INT7	42
-#define MX51_MXC_INT_GPIO1_INT6	43
-#define MX51_MXC_INT_GPIO1_INT5	44
-#define MX51_MXC_INT_GPIO1_INT4	45
-#define MX51_MXC_INT_GPIO1_INT3	46
-#define MX51_MXC_INT_GPIO1_INT2	47
-#define MX51_MXC_INT_GPIO1_INT1	48
-#define MX51_MXC_INT_GPIO1_INT0	49
-#define MX51_MXC_INT_GPIO1_LOW	50
-#define MX51_MXC_INT_GPIO1_HIGH	51
-#define MX51_MXC_INT_GPIO2_LOW	52
-#define MX51_MXC_INT_GPIO2_HIGH	53
-#define MX51_MXC_INT_GPIO3_LOW	54
-#define MX51_MXC_INT_GPIO3_HIGH	55
-#define MX51_MXC_INT_GPIO4_LOW	56
-#define MX51_MXC_INT_GPIO4_HIGH	57
-#define MX51_MXC_INT_WDOG1	58
-#define MX51_MXC_INT_WDOG2	59
-#define MX51_MXC_INT_KPP	60
-#define MX51_MXC_INT_PWM1	61
-#define MX51_MXC_INT_I2C1	62
-#define MX51_MXC_INT_I2C2	63
-#define MX51_MXC_INT_HS_I2C	64
-#define MX51_MXC_INT_RESV65	65
-#define MX51_MXC_INT_RESV66	66
-#define MX51_MXC_INT_SIM_IPB	67
-#define MX51_MXC_INT_SIM_DAT	68
-#define MX51_MXC_INT_IIM	69
-#define MX51_MXC_INT_ATA	70
-#define MX51_MXC_INT_CCM1	71
-#define MX51_MXC_INT_CCM2	72
-#define MX51_MXC_INT_GPC1	73
-#define MX51_MXC_INT_GPC2	74
-#define MX51_MXC_INT_SRC	75
-#define MX51_MXC_INT_NM		76
-#define MX51_MXC_INT_PMU	77
-#define MX51_MXC_INT_CTI_IRQ	78
-#define MX51_MXC_INT_CTI1_TG0	79
-#define MX51_MXC_INT_CTI1_TG1	80
-#define MX51_MXC_INT_MCG_ERR	81
-#define MX51_MXC_INT_MCG_TMR	82
-#define MX51_MXC_INT_MCG_FUNC	83
-#define MX51_MXC_INT_GPU2_IRQ	84
-#define MX51_MXC_INT_GPU2_BUSY	85
-#define MX51_MXC_INT_RESV86	86
-#define MX51_MXC_INT_FEC	87
-#define MX51_MXC_INT_OWIRE	88
-#define MX51_MXC_INT_CTI1_TG2	89
-#define MX51_MXC_INT_SJC	90
-#define MX51_MXC_INT_SPDIF	91
-#define MX51_MXC_INT_TVE	92
-#define MX51_MXC_INT_FIRI	93
-#define MX51_MXC_INT_PWM2	94
-#define MX51_MXC_INT_SLIM_EXP	95
-#define MX51_MXC_INT_SSI3	96
-#define MX51_MXC_INT_EMI_BOOT	97
-#define MX51_MXC_INT_CTI1_TG3	98
-#define MX51_MXC_INT_SMC_RX	99
-#define MX51_MXC_INT_VPU_IDLE	100
-#define MX51_MXC_INT_EMI_NFC	101
-#define MX51_MXC_INT_GPU_IDLE	102
+#define MX51_MXC_INT_BASE		0
+#define MX51_MXC_INT_RESV0		0
+#define MX51_MXC_INT_MMC_SDHC1		1
+#define MX51_MXC_INT_MMC_SDHC2		2
+#define MX51_MXC_INT_MMC_SDHC3		3
+#define MX51_MXC_INT_MMC_SDHC4		4
+#define MX51_MXC_INT_RESV5		5
+#define MX51_MXC_INT_SDMA		6
+#define MX51_MXC_INT_IOMUX		7
+#define MX51_MXC_INT_NFC		8
+#define MX51_MXC_INT_VPU		9
+#define MX51_MXC_INT_IPU_ERR		10
+#define MX51_MXC_INT_IPU_SYN		11
+#define MX51_MXC_INT_GPU		12
+#define MX51_MXC_INT_RESV13		13
+#define MX51_MXC_INT_USB_H1		14
+#define MX51_MXC_INT_EMI		15
+#define MX51_MXC_INT_USB_H2		16
+#define MX51_MXC_INT_USB_H3		17
+#define MX51_MXC_INT_USB_OTG		18
+#define MX51_MXC_INT_SAHARA_H0		19
+#define MX51_MXC_INT_SAHARA_H1		20
+#define MX51_MXC_INT_SCC_SMN		21
+#define MX51_MXC_INT_SCC_STZ		22
+#define MX51_MXC_INT_SCC_SCM		23
+#define MX51_MXC_INT_SRTC_NTZ		24
+#define MX51_MXC_INT_SRTC_TZ		25
+#define MX51_MXC_INT_RTIC		26
+#define MX51_MXC_INT_CSU		27
+#define MX51_MXC_INT_SLIM_B		28
+#define MX51_MXC_INT_SSI1		29
+#define MX51_MXC_INT_SSI2		30
+#define MX51_MXC_INT_UART1		31
+#define MX51_MXC_INT_UART2		32
+#define MX51_MXC_INT_UART3		33
+#define MX51_MXC_INT_RESV34		34
+#define MX51_MXC_INT_RESV35		35
+#define MX51_MXC_INT_CSPI1		36
+#define MX51_MXC_INT_CSPI2		37
+#define MX51_MXC_INT_CSPI		38
+#define MX51_MXC_INT_GPT		39
+#define MX51_MXC_INT_EPIT1		40
+#define MX51_MXC_INT_EPIT2		41
+#define MX51_MXC_INT_GPIO1_INT7		42
+#define MX51_MXC_INT_GPIO1_INT6		43
+#define MX51_MXC_INT_GPIO1_INT5		44
+#define MX51_MXC_INT_GPIO1_INT4		45
+#define MX51_MXC_INT_GPIO1_INT3		46
+#define MX51_MXC_INT_GPIO1_INT2		47
+#define MX51_MXC_INT_GPIO1_INT1		48
+#define MX51_MXC_INT_GPIO1_INT0		49
+#define MX51_MXC_INT_GPIO1_LOW		50
+#define MX51_MXC_INT_GPIO1_HIGH		51
+#define MX51_MXC_INT_GPIO2_LOW		52
+#define MX51_MXC_INT_GPIO2_HIGH		53
+#define MX51_MXC_INT_GPIO3_LOW		54
+#define MX51_MXC_INT_GPIO3_HIGH		55
+#define MX51_MXC_INT_GPIO4_LOW		56
+#define MX51_MXC_INT_GPIO4_HIGH		57
+#define MX51_MXC_INT_WDOG1		58
+#define MX51_MXC_INT_WDOG2		59
+#define MX51_MXC_INT_KPP		60
+#define MX51_MXC_INT_PWM1		61
+#define MX51_MXC_INT_I2C1		62
+#define MX51_MXC_INT_I2C2		63
+#define MX51_MXC_INT_HS_I2C		64
+#define MX51_MXC_INT_RESV65		65
+#define MX51_MXC_INT_RESV66		66
+#define MX51_MXC_INT_SIM_IPB		67
+#define MX51_MXC_INT_SIM_DAT		68
+#define MX51_MXC_INT_IIM		69
+#define MX51_MXC_INT_ATA		70
+#define MX51_MXC_INT_CCM1		71
+#define MX51_MXC_INT_CCM2		72
+#define MX51_MXC_INT_GPC1		73
+#define MX51_MXC_INT_GPC2		74
+#define MX51_MXC_INT_SRC		75
+#define MX51_MXC_INT_NM			76
+#define MX51_MXC_INT_PMU		77
+#define MX51_MXC_INT_CTI_IRQ		78
+#define MX51_MXC_INT_CTI1_TG0		79
+#define MX51_MXC_INT_CTI1_TG1		80
+#define MX51_MXC_INT_MCG_ERR		81
+#define MX51_MXC_INT_MCG_TMR		82
+#define MX51_MXC_INT_MCG_FUNC		83
+#define MX51_MXC_INT_GPU2_IRQ		84
+#define MX51_MXC_INT_GPU2_BUSY		85
+#define MX51_MXC_INT_RESV86		86
+#define MX51_MXC_INT_FEC		87
+#define MX51_MXC_INT_OWIRE		88
+#define MX51_MXC_INT_CTI1_TG2		89
+#define MX51_MXC_INT_SJC		90
+#define MX51_MXC_INT_SPDIF		91
+#define MX51_MXC_INT_TVE		92
+#define MX51_MXC_INT_FIRI		93
+#define MX51_MXC_INT_PWM2		94
+#define MX51_MXC_INT_SLIM_EXP		95
+#define MX51_MXC_INT_SSI3		96
+#define MX51_MXC_INT_EMI_BOOT		97
+#define MX51_MXC_INT_CTI1_TG3		98
+#define MX51_MXC_INT_SMC_RX		99
+#define MX51_MXC_INT_VPU_IDLE		100
+#define MX51_MXC_INT_EMI_NFC		101
+#define MX51_MXC_INT_GPU_IDLE		102
 
 /* silicon revisions specific to i.MX51 */
-#define MX51_CHIP_REV_1_0	0x10
-#define MX51_CHIP_REV_1_1	0x11
-#define MX51_CHIP_REV_1_2	0x12
-#define MX51_CHIP_REV_1_3	0x13
-#define MX51_CHIP_REV_2_0	0x20
-#define MX51_CHIP_REV_2_1	0x21
-#define MX51_CHIP_REV_2_2	0x22
-#define MX51_CHIP_REV_2_3	0x23
-#define MX51_CHIP_REV_3_0	0x30
-#define MX51_CHIP_REV_3_1	0x31
-#define MX51_CHIP_REV_3_2	0x32
-
-/* Mandatory defines used globally */
+#define MX51_CHIP_REV_1_0		0x10
+#define MX51_CHIP_REV_1_1		0x11
+#define MX51_CHIP_REV_1_2		0x12
+#define MX51_CHIP_REV_1_3		0x13
+#define MX51_CHIP_REV_2_0		0x20
+#define MX51_CHIP_REV_2_1		0x21
+#define MX51_CHIP_REV_2_2		0x22
+#define MX51_CHIP_REV_2_3		0x23
+#define MX51_CHIP_REV_3_0		0x30
+#define MX51_CHIP_REV_3_1		0x31
+#define MX51_CHIP_REV_3_2		0x32
 
 #if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
-
 extern int mx51_revision(void);
 #endif
 
-#endif	/*  __ASM_ARCH_MXC_MX51_H__ */
+/* tape-out 1 defines */
+#define MX51_TZIC_BASE_ADDR_TO1		0x8fffc000
+
+#endif	/* ifndef __MACH_MX51_H__ */
-- 
1.7.2.3


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[PATCH 09/16] ARM: mx51: fix naming of spi related defines

[Uwe Kleine-König]

The names used now match the processor's reference manual.  Also remove
MXC from the interrupt defines to match the other imx platforms.

Acked-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
 arch/arm/plat-mxc/include/mach/mx51.h |   12 ++++++------
 1 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/arm/plat-mxc/include/mach/mx51.h b/arch/arm/plat-mxc/include/mach/mx51.h
index 92b39f7..d0fda39 100644
--- a/arch/arm/plat-mxc/include/mach/mx51.h
+++ b/arch/arm/plat-mxc/include/mach/mx51.h
@@ -67,7 +67,7 @@
 #define MX51_MMC_SDHC1_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x04000)
 #define MX51_MMC_SDHC2_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x08000)
 #define MX51_UART3_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x0c000)
-#define MX51_CSPI1_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x10000)
+#define MX51_ECSPI1_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x10000)
 #define MX51_SSI2_BASE_ADDR		(MX51_SPBA0_BASE_ADDR + 0x14000)
 #define MX51_MMC_SDHC3_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x20000)
 #define MX51_MMC_SDHC4_BASE_ADDR	(MX51_SPBA0_BASE_ADDR + 0x24000)
@@ -121,12 +121,12 @@
 #define MX51_ARM_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xa0000)
 #define MX51_OWIRE_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xa4000)
 #define MX51_FIRI_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xa8000)
-#define MX51_CSPI2_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xac000)
+#define MX51_ECSPI2_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xac000)
 #define MX51_SDMA_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xb0000)
 #define MX51_SCC_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xb4000)
 #define MX51_ROMCP_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xb8000)
 #define MX51_RTIC_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xbc000)
-#define MX51_CSPI3_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xc0000)
+#define MX51_CSPI_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xc0000)
 #define MX51_I2C2_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xc4000)
 #define MX51_I2C1_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xc8000)
 #define MX51_SSI1_BASE_ADDR		(MX51_AIPS2_BASE_ADDR + 0xcc000)
@@ -346,9 +346,9 @@
 #define MX51_MXC_INT_UART3		33
 #define MX51_MXC_INT_RESV34		34
 #define MX51_MXC_INT_RESV35		35
-#define MX51_MXC_INT_CSPI1		36
-#define MX51_MXC_INT_CSPI2		37
-#define MX51_MXC_INT_CSPI		38
+#define MX51_INT_ECSPI1			36
+#define MX51_INT_ECSPI2			37
+#define MX51_INT_CSPI			38
 #define MX51_MXC_INT_GPT		39
 #define MX51_MXC_INT_EPIT1		40
 #define MX51_MXC_INT_EPIT2		41
-- 
1.7.2.3


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[PATCH 10/16] ARM: mx5: add spi_imx device registration

[Uwe Kleine-König]

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
 arch/arm/mach-mx5/devices-imx51.h            |   18 ++++++++++++++++++
 arch/arm/plat-mxc/devices/platform-spi_imx.c |   12 ++++++++++++
 2 files changed, 30 insertions(+), 0 deletions(-)
 create mode 100644 arch/arm/mach-mx5/devices-imx51.h

diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h
new file mode 100644
index 0000000..fe6c987
--- /dev/null
+++ b/arch/arm/mach-mx5/devices-imx51.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx51.h>
+#include <mach/devices-common.h>
+
+extern const struct imx_spi_imx_data imx51_cspi_data __initconst;
+#define imx51_add_cspi(pdata)      \
+	imx_add_spi_imx(&imx51_cspi_data, pdata)
+
+extern struct imx_spi_imx_data imx51_ecspi_data[] __initconst;
+#define imx51_add_ecspi(id, pdata) \
+	imx_add_spi_imx(&imx51_ecspi_data[id], pdata)
diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c
index bd30d4b..e48340e 100644
--- a/arch/arm/plat-mxc/devices/platform-spi_imx.c
+++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c
@@ -68,6 +68,18 @@ const struct imx_spi_imx_data imx35_cspi_data[] __initconst = {
 };
 #endif /* ifdef CONFIG_ARCH_MX35 */
 
+#ifdef CONFIG_ARCH_MX51
+const struct imx_spi_imx_data imx51_cspi_data __initconst =
+	imx_spi_imx_data_entry_single(MX51, CSPI, "imx51-cspi", 0, , SZ_4K);
+
+const struct imx_spi_imx_data imx51_ecspi_data[] __initconst = {
+#define imx51_ecspi_data_entry(_id, _hwid)				\
+	imx_spi_imx_data_entry(MX51, ECSPI, "imx51-ecspi", _id, _hwid, SZ_4K)
+	imx51_ecspi_data_entry(0, 1),
+	imx51_ecspi_data_entry(1, 2),
+};
+#endif /* ifdef CONFIG_ARCH_MX51 */
+
 struct platform_device *__init imx_add_spi_imx(
 		const struct imx_spi_imx_data *data,
 		const struct spi_imx_master *pdata)
-- 
1.7.2.3


------------------------------------------------------------------------------
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[PATCH 11/16] ARM: mx5/clock-mx51: refactor ccgr callbacks to use common code

[Uwe Kleine-König]

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
 arch/arm/mach-mx5/clock-mx51.c |   30 ++++++++++++++++--------------
 1 files changed, 16 insertions(+), 14 deletions(-)

diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c
index 57c10a9..fe658bf 100644
--- a/arch/arm/mach-mx5/clock-mx51.c
+++ b/arch/arm/mach-mx5/clock-mx51.c
@@ -41,34 +41,36 @@ static struct clk usboh3_clk;
 
 #define MAX_DPLL_WAIT_TRIES	1000 /* 1000 * udelay(1) = 1ms */
 
-static int _clk_ccgr_enable(struct clk *clk)
+static void _clk_ccgr_setclk(struct clk *clk, unsigned mode)
 {
-	u32 reg;
+	u32 reg = __raw_readl(clk->enable_reg);
+
+	reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
+	reg |= mode << clk->enable_shift;
 
-	reg = __raw_readl(clk->enable_reg);
-	reg |= MXC_CCM_CCGRx_MOD_ON << clk->enable_shift;
 	__raw_writel(reg, clk->enable_reg);
+}
 
+static int _clk_ccgr_enable(struct clk *clk)
+{
+	_clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_ON);
 	return 0;
 }
 
 static void _clk_ccgr_disable(struct clk *clk)
 {
-	u32 reg;
-	reg = __raw_readl(clk->enable_reg);
-	reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
-	__raw_writel(reg, clk->enable_reg);
+	_clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_OFF);
+}
 
+static int _clk_ccgr_enable_inrun(struct clk *clk)
+{
+	_clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE);
+	return 0;
 }
 
 static void _clk_ccgr_disable_inwait(struct clk *clk)
 {
-	u32 reg;
-
-	reg = __raw_readl(clk->enable_reg);
-	reg &= ~(MXC_CCM_CCGRx_CG_MASK << clk->enable_shift);
-	reg |= MXC_CCM_CCGRx_MOD_IDLE << clk->enable_shift;
-	__raw_writel(reg, clk->enable_reg);
+	_clk_ccgr_setclk(clk, MXC_CCM_CCGRx_MOD_IDLE);
 }
 
 /*
-- 
1.7.2.3


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[PATCH 13/16] ARM: mx5/clock-mx51: add spi clocks

[Uwe Kleine-König]

From: Jason Wang <jason77.wang@gmail.com>

Signed-off-by: Jason Wang <jason77.wang@gmail.com>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
 arch/arm/mach-mx5/clock-mx51.c |   57 ++++++++++++++++++++++++++++++++++++++++
 1 files changed, 57 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mx5/clock-mx51.c b/arch/arm/mach-mx5/clock-mx51.c
index 0e39698..68aef2d 100644
--- a/arch/arm/mach-mx5/clock-mx51.c
+++ b/arch/arm/mach-mx5/clock-mx51.c
@@ -764,6 +764,42 @@ static struct clk kpp_clk = {
 	.id = 0,
 };
 
+/* eCSPI */
+static unsigned long clk_ecspi_get_rate(struct clk *clk)
+{
+	u32 reg, pred, podf;
+
+	reg = __raw_readl(MXC_CCM_CSCDR2);
+
+	pred = (reg & MXC_CCM_CSCDR2_CSPI_CLK_PRED_MASK) >>
+			MXC_CCM_CSCDR2_CSPI_CLK_PRED_OFFSET;
+	podf = (reg & MXC_CCM_CSCDR2_CSPI_CLK_PODF_MASK) >>
+			MXC_CCM_CSCDR2_CSPI_CLK_PODF_OFFSET;
+
+	return DIV_ROUND_CLOSEST(clk_get_rate(clk->parent),
+			(pred + 1) * (podf + 1));
+}
+
+static int clk_ecspi_set_parent(struct clk *clk, struct clk *parent)
+{
+	u32 reg, mux;
+
+	mux = _get_mux(parent, &pll1_sw_clk, &pll2_sw_clk, &pll3_sw_clk,
+			&lp_apm_clk);
+
+	reg = __raw_readl(MXC_CCM_CSCMR1) & ~MXC_CCM_CSCMR1_CSPI_CLK_SEL_MASK;
+	reg |= mux << MXC_CCM_CSCMR1_CSPI_CLK_SEL_OFFSET;
+	__raw_writel(reg, MXC_CCM_CSCMR1);
+
+	return 0;
+}
+
+static struct clk ecspi_main_clk = {
+	.parent = &pll3_sw_clk,
+	.get_rate = clk_ecspi_get_rate,
+	.set_parent = clk_ecspi_set_parent,
+};
+
 #define DEFINE_CLOCK_FULL(name, i, er, es, gr, sr, e, d, p, s)		\
 	static struct clk name = {					\
 		.id		= i,					\
@@ -816,6 +852,24 @@ DEFINE_CLOCK(hsi2c_clk, 0, MXC_CCM_CCGR1, MXC_CCM_CCGRx_CG11_OFFSET,
 DEFINE_CLOCK(fec_clk, 0, MXC_CCM_CCGR2, MXC_CCM_CCGRx_CG12_OFFSET,
 	NULL,  NULL, &ipg_clk, NULL);
 
+/* eCSPI */
+DEFINE_CLOCK_FULL(ecspi1_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
+		NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable,
+		&ipg_clk, &spba_clk);
+DEFINE_CLOCK(ecspi1_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG10_OFFSET,
+		NULL, NULL, &ecspi_main_clk, &ecspi1_ipg_clk);
+DEFINE_CLOCK_FULL(ecspi2_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG11_OFFSET,
+		NULL, NULL, _clk_ccgr_enable_inrun, _clk_ccgr_disable,
+		&ipg_clk, &aips_tz2_clk);
+DEFINE_CLOCK(ecspi2_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG12_OFFSET,
+		NULL, NULL, &ecspi_main_clk, &ecspi2_ipg_clk);
+
+/* CSPI */
+DEFINE_CLOCK(cspi_ipg_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG9_OFFSET,
+		NULL, NULL, &ipg_clk, &aips_tz2_clk);
+DEFINE_CLOCK(cspi_clk, 0, MXC_CCM_CCGR4, MXC_CCM_CCGRx_CG13_OFFSET,
+		NULL, NULL, &ipg_clk, &cspi_ipg_clk);
+
 #define _REGISTER_CLOCK(d, n, c) \
        { \
 		.dev_id = d, \
@@ -839,6 +893,9 @@ static struct clk_lookup lookups[] = {
 	_REGISTER_CLOCK("fsl-usb2-udc", "usb", usboh3_clk)
 	_REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", ahb_clk)
 	_REGISTER_CLOCK("imx-keypad.0", NULL, kpp_clk)
+	_REGISTER_CLOCK("imx51-ecspi.0", NULL, ecspi1_clk)
+	_REGISTER_CLOCK("imx51-ecspi.1", NULL, ecspi2_clk)
+	_REGISTER_CLOCK("imx51-cspi.0", NULL, cspi_clk)
 };
 
 static void clk_tree_init(void)
-- 
1.7.2.3


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[PATCH 14/16] ARM: mx5/iomux-mx51: add iomux definitions for eCSPI2 on the imx51_3ds board

[Uwe Kleine-König]

From: Jason Wang <jason77.wang@gmail.com>

On the imx51_3ds board, eCSPI2 is connected to a SPI NOR flash,
now add iomux definitions for those used pins.

Signed-off-by: Jason Wang <jason77.wang@gmail.com>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
 arch/arm/plat-mxc/include/mach/iomux-mx51.h |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx51.h b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
index 0d77be3..d0ef881 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx51.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx51.h
@@ -45,6 +45,8 @@ typedef enum iomux_config {
 				PAD_CTL_PKE | PAD_CTL_HYS)
 #define MX51_GPIO_PAD_CTRL		(PAD_CTL_DSE_HIGH | PAD_CTL_PKE | \
 				PAD_CTL_SRE_FAST)
+#define MX51_ECSPI_PAD_CTRL	(PAD_CTL_HYS | PAD_CTL_PKE | PAD_CTL_DSE_HIGH | \
+				PAD_CTL_SRE_FAST)
 
 #define MX51_PAD_CTRL_1	(PAD_CTL_SRE_FAST | PAD_CTL_DSE_HIGH | \
 					PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_HYS)
@@ -139,8 +141,10 @@ typedef enum iomux_config {
 #define MX51_PAD_NANDF_RB0__GPIO_3_8            IOMUX_PAD(0x4F8, 0x11C, 3, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_RB1__GPIO_3_9            IOMUX_PAD(0x4FC, 0x120, 3, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_RB2__GPIO_3_10           IOMUX_PAD(0x500, 0x124, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB2__ECSPI2_SCLK         IOMUX_PAD(0x500, 0x124, 2, 0x0,   0, MX51_ECSPI_PAD_CTRL)
 #define MX51_PAD_NANDF_RB2__FEC_COL		IOMUX_PAD(0x500, 0x124, 1, 0x0,   0, MX51_PAD_CTRL_2)
 #define MX51_PAD_NANDF_RB3__GPIO_3_11           IOMUX_PAD(0x504, 0x128, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_RB3__ECSPI2_MISO         IOMUX_PAD(0x504, 0x128, 2, 0x0,   0, MX51_ECSPI_PAD_CTRL)
 #define MX51_PAD_NANDF_RB3__FEC_RXCLK		IOMUX_PAD(0x504, 0x128, 1, 0x0,   0, MX51_PAD_CTRL_2)
 #define MX51_PAD_NANDF_RB6__FEC_RDAT0		IOMUX_PAD(0x5DC, 0x134, 1, 0x0,   0, MX51_PAD_CTRL_4)
 #define MX51_PAD_NANDF_RB7__FEC_TDAT0		IOMUX_PAD(0x5E0, 0x138, 1, 0x0,   0, MX51_PAD_CTRL_5)
@@ -162,6 +166,7 @@ typedef enum iomux_config {
 #define MX51_PAD_NANDF_RDY_INT__GPIO_3_24       IOMUX_PAD(0x538, 0x150, 3, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_RDY_INT__FEC_TX_CLK	IOMUX_PAD(0x538, 0x150, 1, 0x0,   0, MX51_PAD_CTRL_4)
 #define MX51_PAD_NANDF_D15__GPIO_3_25           IOMUX_PAD(0x53C, 0x154, 3, 0x0,   0, NO_PAD_CTRL)
+#define MX51_PAD_NANDF_D15__ECSPI2_MOSI         IOMUX_PAD(0x53C, 0x154, 2, 0x0,   0, MX51_ECSPI_PAD_CTRL)
 #define MX51_PAD_NANDF_D14__GPIO_3_26           IOMUX_PAD(0x540, 0x158, 3, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_D13__GPIO_3_27           IOMUX_PAD(0x544, 0x15C, 3, 0x0,   0, NO_PAD_CTRL)
 #define MX51_PAD_NANDF_D12__GPIO_3_28           IOMUX_PAD(0x548, 0x160, 3, 0x0,   0, NO_PAD_CTRL)
-- 
1.7.2.3


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[PATCH 15/16] ARM: mx5/mx51_3ds: add eCSPI2 support on the imx51_3ds board

[Uwe Kleine-König]

From: Jason Wang <jason77.wang@gmail.com>

Signed-off-by: Jason Wang <jason77.wang@gmail.com>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
 arch/arm/mach-mx5/Kconfig          |    1 +
 arch/arm/mach-mx5/board-mx51_3ds.c |   20 ++++++++++++++++++++
 2 files changed, 21 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index 0848db5..d4d5feb 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -17,6 +17,7 @@ config MACH_MX51_BABBAGE
 
 config MACH_MX51_3DS
 	bool "Support MX51PDK (3DS)"
+	select IMX_HAVE_PLATFORM_SPI_IMX
 	select MXC_DEBUG_BOARD
 	help
 	  Include support for MX51PDK (3DS) platform. This includes specific
diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
index f95c2fd..c9c4128 100644
--- a/arch/arm/mach-mx5/board-mx51_3ds.c
+++ b/arch/arm/mach-mx5/board-mx51_3ds.c
@@ -24,9 +24,11 @@
 #include <mach/imx-uart.h>
 #include <mach/3ds_debugboard.h>
 
+#include "devices-imx51.h"
 #include "devices.h"
 
 #define EXPIO_PARENT_INT	(MXC_INTERNAL_IRQS + GPIO_PORTA + 6)
+#define MX51_3DS_ECSPI2_CS	(GPIO_PORTC + 28)
 
 static struct pad_desc mx51_3ds_pads[] = {
 	/* UART1 */
@@ -61,6 +63,12 @@ static struct pad_desc mx51_3ds_pads[] = {
 	MX51_PAD_KEY_COL3__KEY_COL3,
 	MX51_PAD_KEY_COL4__KEY_COL4,
 	MX51_PAD_KEY_COL5__KEY_COL5,
+
+	/* eCSPI2 */
+	MX51_PAD_NANDF_RB2__ECSPI2_SCLK,
+	MX51_PAD_NANDF_RB3__ECSPI2_MISO,
+	MX51_PAD_NANDF_D15__ECSPI2_MOSI,
+	MX51_PAD_NANDF_D12__GPIO_3_28,
 };
 
 /* Serial ports */
@@ -127,6 +135,16 @@ static inline void mxc_init_keypad(void)
 }
 #endif
 
+static int mx51_3ds_spi2_cs[] = {
+	MXC_SPI_CS(0),
+	MX51_3DS_ECSPI2_CS,
+};
+
+static const struct spi_imx_master mx51_3ds_ecspi2_pdata __initconst = {
+	.chipselect	= mx51_3ds_spi2_cs,
+	.num_chipselect	= ARRAY_SIZE(mx51_3ds_spi2_cs),
+};
+
 /*
  * Board specific initialization.
  */
@@ -136,6 +154,8 @@ static void __init mxc_board_init(void)
 					ARRAY_SIZE(mx51_3ds_pads));
 	mxc_init_imx_uart();
 
+	imx51_add_ecspi(1, &mx51_3ds_ecspi2_pdata);
+
 	if (mxc_expio_init(MX51_CS5_BASE_ADDR, EXPIO_PARENT_INT))
 		printk(KERN_WARNING "Init of the debugboard failed, all "
 				    "devices on the board are unusable.\n");
-- 
1.7.2.3


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[PATCH 16/16] ARM: mx5/mx51_3ds: add SPI NOR flash in the board init stage

[Uwe Kleine-König]

From: Jason Wang <jason77.wang@gmail.com>

A 2M bytes SPI NOR flash(sst25vf016b) is soldered on the mx51_3ds
board.  So add the corresponding device for it.

Signed-off-by: Jason Wang <jason77.wang@gmail.com>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
 arch/arm/mach-mx5/board-mx51_3ds.c |   13 +++++++++++++
 1 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/arch/arm/mach-mx5/board-mx51_3ds.c b/arch/arm/mach-mx5/board-mx51_3ds.c
index c9c4128..b9d3331 100644
--- a/arch/arm/mach-mx5/board-mx51_3ds.c
+++ b/arch/arm/mach-mx5/board-mx51_3ds.c
@@ -13,6 +13,7 @@
 #include <linux/irq.h>
 #include <linux/platform_device.h>
 #include <linux/input/matrix_keypad.h>
+#include <linux/spi/spi.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -145,6 +146,16 @@ static const struct spi_imx_master mx51_3ds_ecspi2_pdata __initconst = {
 	.num_chipselect	= ARRAY_SIZE(mx51_3ds_spi2_cs),
 };
 
+static struct spi_board_info mx51_3ds_spi_nor_device[] = {
+	{
+	 .modalias = "m25p80",
+	 .max_speed_hz = 25000000,	/* max spi clock (SCK) speed in HZ */
+	 .bus_num = 1,
+	 .chip_select = 1,
+	 .mode = SPI_MODE_0,
+	 .platform_data = NULL,},
+};
+
 /*
  * Board specific initialization.
  */
@@ -155,6 +166,8 @@ static void __init mxc_board_init(void)
 	mxc_init_imx_uart();
 
 	imx51_add_ecspi(1, &mx51_3ds_ecspi2_pdata);
+	spi_register_board_info(mx51_3ds_spi_nor_device,
+				ARRAY_SIZE(mx51_3ds_spi_nor_device));
 
 	if (mxc_expio_init(MX51_CS5_BASE_ADDR, EXPIO_PARENT_INT))
 		printk(KERN_WARNING "Init of the debugboard failed, all "
-- 
1.7.2.3


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Re: [PATCH 0/6] add spi support for i.MX51 in the existing spi_imx driver

[Jason Wang]

Hi Uwe,

Uwe Kleine-König wrote:
> Hello,
>
> On Thu, Sep 02, 2010 at 04:39:08PM +0200, Uwe Kleine-König wrote:
>   
>> Hello Jason,
>>
>>     
>>>> Actually I would prefer our patches, but of course I'm biased :-)
>>>>
>>>> I don't know how we should handle this.  And Sascha is on vacation this
>>>> and next week.  I will investigate if our patches are already free to be
>>>> posted.
>>>>         
>> OK, I can post our patches.  I think the driver part is quite similar,
>> the platform part is not.  But look for yourself, I'll post them in reply to
>> this mail.  Hopefully we can join forces to get the best out of the two
>> approaches.
>>     
> I now made the effort to try doing this.  I hope this is OK though it
> feels strage that no commit is attributed to Sascha.
>
> The following changes since commit 5b1caa2452a2cf09417ab657ae3a2275ebd78103:
>
>   ARM: mx5/mx51_babbage: Add FEC support (2010-09-13 11:31:22 +0200)
>
> are available in the git repository at:
>   git://git.pengutronix.de/git/ukl/linux-2.6.git spi-imx51
>
> (5b1caa2452a2cf09417ab657ae3a2275ebd78103 is the result of rebasing
> Sascha's for-2.6.37 branch on top of 2.6.36-rc4---done mainly to contain
> the for-2.6.36 branch)
>
>   
I have performed a git pull for your repository based off 2.6.36-rc4, and
built and validated these patches  on imx51_3ds board, they worked fine.
The spi flash can be read without any problems.

And your patches looks pretty good to me. :-).

Thanks,
Jason.
> Jason Wang (4):
>       ARM: mx5/clock-mx51: add spi clocks
>       ARM: mx5/iomux-mx51: add iomux definitions for eCSPI2 on the imx51_3ds board
>       ARM: mx5/mx51_3ds: add eCSPI2 support on the imx51_3ds board
>       ARM: mx5/mx51_3ds: add SPI NOR flash in the board init stage
>
> Uwe Kleine-König (12):
>       spi/imx: default to m on platforms that have such devices
>       spi/imx: convert driver to use platform ids
>       spi/imx: get rid of more ifs depending on the used cpu
>       spi/imx: save the spi chip select in config struct, not the gpio to use
>       spi/imx: add support for imx51's eCSPI and CSPI
>       ARM: imx: change the way spi-imx devices are registered
>       ARM: imx: use platform ids for spi_imx devices
>       ARM: mx51: clean up mx51 header
>       ARM: mx51: fix naming of spi related defines
>       ARM: mx5: add spi_imx device registration
>       ARM: mx5/clock-mx51: refactor ccgr callbacks to use common code
>       ARM: mx5/clock-mx51: new macro that defines a clk with all members
>
>  arch/arm/mach-imx/clock-imx1.c                  |    2 +-
>  arch/arm/mach-imx/clock-imx21.c                 |    6 +-
>  arch/arm/mach-imx/clock-imx27.c                 |    6 +-
>  arch/arm/mach-imx/devices-imx21.h               |    9 +-
>  arch/arm/mach-imx/devices-imx27.h               |   12 +-
>  arch/arm/mach-mx25/clock.c                      |    6 +-
>  arch/arm/mach-mx25/devices-imx25.h              |   12 +-
>  arch/arm/mach-mx3/clock-imx31.c                 |    6 +-
>  arch/arm/mach-mx3/clock-imx35.c                 |    4 +-
>  arch/arm/mach-mx3/devices-imx31.h               |   12 +-
>  arch/arm/mach-mx3/devices-imx35.h               |    9 +-
>  arch/arm/mach-mx5/Kconfig                       |    1 +
>  arch/arm/mach-mx5/board-mx51_3ds.c              |   33 ++
>  arch/arm/mach-mx5/clock-mx51.c                  |  113 ++++-
>  arch/arm/mach-mx5/devices-imx51.h               |   18 +
>  arch/arm/plat-mxc/devices/platform-spi_imx.c    |   89 +++-
>  arch/arm/plat-mxc/include/mach/devices-common.h |   11 +-
>  arch/arm/plat-mxc/include/mach/iomux-mx51.h     |    5 +
>  arch/arm/plat-mxc/include/mach/mx51.h           |  608 +++++++++++------------
>  drivers/spi/Kconfig                             |   16 +
>  drivers/spi/spi_imx.c                           |  394 ++++++++++++---
>  21 files changed, 919 insertions(+), 453 deletions(-)
>  create mode 100644 arch/arm/mach-mx5/devices-imx51.h
>
> Thanks
> Uwe
>
>   

Re: [PATCH 0/6] add spi support for i.MX51 in the existing spi_imx driver

[Uwe Kleine-König]

Hi Jason,

> I have performed a git pull for your repository based off 2.6.36-rc4, and
> built and validated these patches  on imx51_3ds board, they worked fine.
> The spi flash can be read without any problems.
>
> And your patches looks pretty good to me. :-).
This is an ack for all patches in my series?

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

Re: [PATCH 0/6] add spi support for i.MX51 in the existing spi_imx driver

[Jason Wang]

Uwe Kleine-König wrote:
> Hi Jason,
>
>   
>> I have performed a git pull for your repository based off 2.6.36-rc4, and
>> built and validated these patches  on imx51_3ds board, they worked fine.
>> The spi flash can be read without any problems.
>>
>> And your patches looks pretty good to me. :-).
>>     
> This is an ack for all patches in my series?
>
>   
Yes, all patches look fine to me.

Thanks,
Jason.
> Best regards
> Uwe
>
>   

Re: [PATCH 0/6] add spi support for i.MX51 in the existing spi_imx driver

[Grant Likely]

2010/9/17 Uwe Kleine-König <u.kleine-koenig@pengutronix.de>:
> Hello,
>
> On Thu, Sep 02, 2010 at 04:39:08PM +0200, Uwe Kleine-König wrote:
>> Hello Jason,
>>
>> >> Actually I would prefer our patches, but of course I'm biased :-)
>> >>
>> >> I don't know how we should handle this.  And Sascha is on vacation this
>> >> and next week.  I will investigate if our patches are already free to be
>> >> posted.
>> OK, I can post our patches.  I think the driver part is quite similar,
>> the platform part is not.  But look for yourself, I'll post them in reply to
>> this mail.  Hopefully we can join forces to get the best out of the two
>> approaches.
> I now made the effort to try doing this.  I hope this is OK though it
> feels strage that no commit is attributed to Sascha.
>
> The following changes since commit 5b1caa2452a2cf09417ab657ae3a2275ebd78103:
>
>  ARM: mx5/mx51_babbage: Add FEC support (2010-09-13 11:31:22 +0200)
>
> are available in the git repository at:
>  git://git.pengutronix.de/git/ukl/linux-2.6.git spi-imx51
>
> (5b1caa2452a2cf09417ab657ae3a2275ebd78103 is the result of rebasing
> Sascha's for-2.6.37 branch on top of 2.6.36-rc4---done mainly to contain
> the for-2.6.36 branch)
>
> Jason Wang (4):
>      ARM: mx5/clock-mx51: add spi clocks
>      ARM: mx5/iomux-mx51: add iomux definitions for eCSPI2 on the imx51_3ds board
>      ARM: mx5/mx51_3ds: add eCSPI2 support on the imx51_3ds board
>      ARM: mx5/mx51_3ds: add SPI NOR flash in the board init stage
>
> Uwe Kleine-König (12):
>      spi/imx: default to m on platforms that have such devices
>      spi/imx: convert driver to use platform ids
>      spi/imx: get rid of more ifs depending on the used cpu
>      spi/imx: save the spi chip select in config struct, not the gpio to use
>      spi/imx: add support for imx51's eCSPI and CSPI
>      ARM: imx: change the way spi-imx devices are registered
>      ARM: imx: use platform ids for spi_imx devices
>      ARM: mx51: clean up mx51 header
>      ARM: mx51: fix naming of spi related defines
>      ARM: mx5: add spi_imx device registration
>      ARM: mx5/clock-mx51: refactor ccgr callbacks to use common code
>      ARM: mx5/clock-mx51: new macro that defines a clk with all members
>
>  arch/arm/mach-imx/clock-imx1.c                  |    2 +-
>  arch/arm/mach-imx/clock-imx21.c                 |    6 +-
>  arch/arm/mach-imx/clock-imx27.c                 |    6 +-
>  arch/arm/mach-imx/devices-imx21.h               |    9 +-
>  arch/arm/mach-imx/devices-imx27.h               |   12 +-
>  arch/arm/mach-mx25/clock.c                      |    6 +-
>  arch/arm/mach-mx25/devices-imx25.h              |   12 +-
>  arch/arm/mach-mx3/clock-imx31.c                 |    6 +-
>  arch/arm/mach-mx3/clock-imx35.c                 |    4 +-
>  arch/arm/mach-mx3/devices-imx31.h               |   12 +-
>  arch/arm/mach-mx3/devices-imx35.h               |    9 +-
>  arch/arm/mach-mx5/Kconfig                       |    1 +
>  arch/arm/mach-mx5/board-mx51_3ds.c              |   33 ++
>  arch/arm/mach-mx5/clock-mx51.c                  |  113 ++++-
>  arch/arm/mach-mx5/devices-imx51.h               |   18 +
>  arch/arm/plat-mxc/devices/platform-spi_imx.c    |   89 +++-
>  arch/arm/plat-mxc/include/mach/devices-common.h |   11 +-
>  arch/arm/plat-mxc/include/mach/iomux-mx51.h     |    5 +
>  arch/arm/plat-mxc/include/mach/mx51.h           |  608 +++++++++++------------
>  drivers/spi/Kconfig                             |   16 +
>  drivers/spi/spi_imx.c                           |  394 ++++++++++++---
>  21 files changed, 919 insertions(+), 453 deletions(-)
>  create mode 100644 arch/arm/mach-mx5/devices-imx51.h
>
> Thanks
> Uwe

I'm fine with this series.

Acked-by: Grant Likely <grant.likely@secretlab.ca>

What tree do you want to merge them through?

g.

Re: [PATCH 0/6] add spi support for i.MX51 in the existing spi_imx driver

[Uwe Kleine-König]

Hello Grant,

On Fri, Sep 24, 2010 at 01:00:14AM -0600, Grant Likely wrote:
> > Jason Wang (4):
> >      ARM: mx5/clock-mx51: add spi clocks
> >      ARM: mx5/iomux-mx51: add iomux definitions for eCSPI2 on the imx51_3ds board
> >      ARM: mx5/mx51_3ds: add eCSPI2 support on the imx51_3ds board
> >      ARM: mx5/mx51_3ds: add SPI NOR flash in the board init stage
> >
> > Uwe Kleine-König (12):
> >      spi/imx: default to m on platforms that have such devices
> >      spi/imx: convert driver to use platform ids
> >      spi/imx: get rid of more ifs depending on the used cpu
> >      spi/imx: save the spi chip select in config struct, not the gpio to use
> >      spi/imx: add support for imx51's eCSPI and CSPI
> >      ARM: imx: change the way spi-imx devices are registered
> >      ARM: imx: use platform ids for spi_imx devices
> >      ARM: mx51: clean up mx51 header
> >      ARM: mx51: fix naming of spi related defines
> >      ARM: mx5: add spi_imx device registration
> >      ARM: mx5/clock-mx51: refactor ccgr callbacks to use common code
> >      ARM: mx5/clock-mx51: new macro that defines a clk with all members
> >
> >  arch/arm/mach-imx/clock-imx1.c                  |    2 +-
> >  arch/arm/mach-imx/clock-imx21.c                 |    6 +-
> >  arch/arm/mach-imx/clock-imx27.c                 |    6 +-
> >  arch/arm/mach-imx/devices-imx21.h               |    9 +-
> >  arch/arm/mach-imx/devices-imx27.h               |   12 +-
> >  arch/arm/mach-mx25/clock.c                      |    6 +-
> >  arch/arm/mach-mx25/devices-imx25.h              |   12 +-
> >  arch/arm/mach-mx3/clock-imx31.c                 |    6 +-
> >  arch/arm/mach-mx3/clock-imx35.c                 |    4 +-
> >  arch/arm/mach-mx3/devices-imx31.h               |   12 +-
> >  arch/arm/mach-mx3/devices-imx35.h               |    9 +-
> >  arch/arm/mach-mx5/Kconfig                       |    1 +
> >  arch/arm/mach-mx5/board-mx51_3ds.c              |   33 ++
> >  arch/arm/mach-mx5/clock-mx51.c                  |  113 ++++-
> >  arch/arm/mach-mx5/devices-imx51.h               |   18 +
> >  arch/arm/plat-mxc/devices/platform-spi_imx.c    |   89 +++-
> >  arch/arm/plat-mxc/include/mach/devices-common.h |   11 +-
> >  arch/arm/plat-mxc/include/mach/iomux-mx51.h     |    5 +
> >  arch/arm/plat-mxc/include/mach/mx51.h           |  608 +++++++++++------------
> >  drivers/spi/Kconfig                             |   16 +
> >  drivers/spi/spi_imx.c                           |  394 ++++++++++++---
> >  21 files changed, 919 insertions(+), 453 deletions(-)
> >  create mode 100644 arch/arm/mach-mx5/devices-imx51.h
> 
> I'm fine with this series.
> 
> Acked-by: Grant Likely <grant.likely@secretlab.ca>
> 
> What tree do you want to merge them through?
I thought that the five patches touching drivers/spi should go via your
tree, the others via Sascha's.  Assuming this is OK for you, too, do you
prefer to pick the patches out here or should I prepare a branch with
these patches for you to pull?

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

Re: [PATCH 0/6] add spi support for i.MX51 in the existing spi_imx driver

[Grant Likely]

2010/9/24 Uwe Kleine-König <u.kleine-koenig@pengutronix.de>:
> Hello Grant,
>
> On Fri, Sep 24, 2010 at 01:00:14AM -0600, Grant Likely wrote:
>> > Jason Wang (4):
>> >      ARM: mx5/clock-mx51: add spi clocks
>> >      ARM: mx5/iomux-mx51: add iomux definitions for eCSPI2 on the imx51_3ds board
>> >      ARM: mx5/mx51_3ds: add eCSPI2 support on the imx51_3ds board
>> >      ARM: mx5/mx51_3ds: add SPI NOR flash in the board init stage
>> >
>> > Uwe Kleine-König (12):
>> >      spi/imx: default to m on platforms that have such devices
>> >      spi/imx: convert driver to use platform ids
>> >      spi/imx: get rid of more ifs depending on the used cpu
>> >      spi/imx: save the spi chip select in config struct, not the gpio to use
>> >      spi/imx: add support for imx51's eCSPI and CSPI
>> >      ARM: imx: change the way spi-imx devices are registered
>> >      ARM: imx: use platform ids for spi_imx devices
>> >      ARM: mx51: clean up mx51 header
>> >      ARM: mx51: fix naming of spi related defines
>> >      ARM: mx5: add spi_imx device registration
>> >      ARM: mx5/clock-mx51: refactor ccgr callbacks to use common code
>> >      ARM: mx5/clock-mx51: new macro that defines a clk with all members
>> >
>> >  arch/arm/mach-imx/clock-imx1.c                  |    2 +-
>> >  arch/arm/mach-imx/clock-imx21.c                 |    6 +-
>> >  arch/arm/mach-imx/clock-imx27.c                 |    6 +-
>> >  arch/arm/mach-imx/devices-imx21.h               |    9 +-
>> >  arch/arm/mach-imx/devices-imx27.h               |   12 +-
>> >  arch/arm/mach-mx25/clock.c                      |    6 +-
>> >  arch/arm/mach-mx25/devices-imx25.h              |   12 +-
>> >  arch/arm/mach-mx3/clock-imx31.c                 |    6 +-
>> >  arch/arm/mach-mx3/clock-imx35.c                 |    4 +-
>> >  arch/arm/mach-mx3/devices-imx31.h               |   12 +-
>> >  arch/arm/mach-mx3/devices-imx35.h               |    9 +-
>> >  arch/arm/mach-mx5/Kconfig                       |    1 +
>> >  arch/arm/mach-mx5/board-mx51_3ds.c              |   33 ++
>> >  arch/arm/mach-mx5/clock-mx51.c                  |  113 ++++-
>> >  arch/arm/mach-mx5/devices-imx51.h               |   18 +
>> >  arch/arm/plat-mxc/devices/platform-spi_imx.c    |   89 +++-
>> >  arch/arm/plat-mxc/include/mach/devices-common.h |   11 +-
>> >  arch/arm/plat-mxc/include/mach/iomux-mx51.h     |    5 +
>> >  arch/arm/plat-mxc/include/mach/mx51.h           |  608 +++++++++++------------
>> >  drivers/spi/Kconfig                             |   16 +
>> >  drivers/spi/spi_imx.c                           |  394 ++++++++++++---
>> >  21 files changed, 919 insertions(+), 453 deletions(-)
>> >  create mode 100644 arch/arm/mach-mx5/devices-imx51.h
>>
>> I'm fine with this series.
>>
>> Acked-by: Grant Likely <grant.likely@secretlab.ca>
>>
>> What tree do you want to merge them through?
> I thought that the five patches touching drivers/spi should go via your
> tree, the others via Sascha's.  Assuming this is OK for you, too, do you
> prefer to pick the patches out here or should I prepare a branch with
> these patches for you to pull?

You can just add my acked-by and take the whole series via Sascha.  No
sense breaking them up.

g.

Re: [PATCH 0/6] add spi support for i.MX51 in the existing spi_imx driver

[Uwe Kleine-König]

Hello Grant,

On Fri, Sep 24, 2010 at 10:12:47AM -0600, Grant Likely wrote:
> >> I'm fine with this series.
> >>
> >> Acked-by: Grant Likely <grant.likely@secretlab.ca>
> >>
> >> What tree do you want to merge them through?
> > I thought that the five patches touching drivers/spi should go via your
> > tree, the others via Sascha's.  Assuming this is OK for you, too, do you
> > prefer to pick the patches out here or should I prepare a branch with
> > these patches for you to pull?
> 
> You can just add my acked-by and take the whole series via Sascha.  No
> sense breaking them up.
OK, that makes it a bit easier for us.

Thanks
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

[PATCH 7/6] spi/imx: Support different fifo sizes

[Uwe Kleine-König]

From: David Jander <david@protonic.nl>

The i.MX51 ECSPI has a fifo size of 64 entries instead of 8 entries as
found on the other cspi bus devices.

Cc: Jason Wang <jason77.wang@gmail.com>
Signed-off-by: David Jander <david@protonic.nl>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
Hello,

this patch depends on patches already acked by Grant Likely and sitting
in Sascha Hauer's imx-for-2.6.37 branch.

Best regards
Uwe

 drivers/spi/spi_imx.c |    8 +++++++-
 1 files changed, 7 insertions(+), 1 deletions(-)

diff --git a/drivers/spi/spi_imx.c b/drivers/spi/spi_imx.c
index 6bab2cf..55a38e2 100644
--- a/drivers/spi/spi_imx.c
+++ b/drivers/spi/spi_imx.c
@@ -77,6 +77,7 @@ struct spi_imx_devtype_data {
 	void (*trigger)(struct spi_imx_data *);
 	int (*rx_available)(struct spi_imx_data *);
 	void (*reset)(struct spi_imx_data *);
+	unsigned int fifosize;
 };
 
 struct spi_imx_data {
@@ -541,6 +542,7 @@ static struct spi_imx_devtype_data spi_imx_devtype_data[] __devinitdata = {
 		.trigger = mx1_trigger,
 		.rx_available = mx1_rx_available,
 		.reset = mx1_reset,
+		.fifosize = 8,
 	},
 #endif
 #ifdef CONFIG_SPI_IMX_VER_0_0
@@ -550,6 +552,7 @@ static struct spi_imx_devtype_data spi_imx_devtype_data[] __devinitdata = {
 		.trigger = mx27_trigger,
 		.rx_available = mx27_rx_available,
 		.reset = spi_imx0_0_reset,
+		.fifosize = 8,
 	},
 #endif
 #ifdef CONFIG_SPI_IMX_VER_0_4
@@ -559,6 +562,7 @@ static struct spi_imx_devtype_data spi_imx_devtype_data[] __devinitdata = {
 		.trigger = mx31_trigger,
 		.rx_available = mx31_rx_available,
 		.reset = spi_imx0_4_reset,
+		.fifosize = 8,
 	},
 #endif
 #ifdef CONFIG_SPI_IMX_VER_0_7
@@ -568,6 +572,7 @@ static struct spi_imx_devtype_data spi_imx_devtype_data[] __devinitdata = {
 		.trigger = mx31_trigger,
 		.rx_available = mx31_rx_available,
 		.reset = spi_imx0_4_reset,
+		.fifosize = 8,
 	},
 #endif
 #ifdef CONFIG_SPI_IMX_VER_2_3
@@ -577,6 +582,7 @@ static struct spi_imx_devtype_data spi_imx_devtype_data[] __devinitdata = {
 		.trigger = spi_imx2_3_trigger,
 		.rx_available = spi_imx2_3_rx_available,
 		.reset = spi_imx2_3_reset,
+		.fifosize = 64,
 	},
 #endif
 };
@@ -596,7 +602,7 @@ static void spi_imx_chipselect(struct spi_device *spi, int is_active)
 
 static void spi_imx_push(struct spi_imx_data *spi_imx)
 {
-	while (spi_imx->txfifo < 8) {
+	while (spi_imx->txfifo < spi_imx->devtype_data.fifosize) {
 		if (!spi_imx->count)
 			break;
 		spi_imx->tx(spi_imx);
-- 
1.7.2.3


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Re: [PATCH 7/6] spi/imx: Support different fifo sizes

[Grant Likely]

On Fri, Oct 08, 2010 at 11:24:01AM +0200, Uwe Kleine-König wrote:
> From: David Jander <david-/Q/L1SwJa3aEVqv0pETR8A@public.gmane.org>
> 
> The i.MX51 ECSPI has a fifo size of 64 entries instead of 8 entries as
> found on the other cspi bus devices.
> 
> Cc: Jason Wang <jason77.wang-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Signed-off-by: David Jander <david-/Q/L1SwJa3aEVqv0pETR8A@public.gmane.org>
> Signed-off-by: Sascha Hauer <s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> Signed-off-by: Uwe Kleine-König <u.kleine-koenig-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>

Acked-by: Grant Likely <grant.likely-s3s/WqlpOiPyB63q8FvJNQ@public.gmane.org>

Please merge via Sascha's branch that already has the other patches.

g.

> ---
> Hello,
> 
> this patch depends on patches already acked by Grant Likely and sitting
> in Sascha Hauer's imx-for-2.6.37 branch.
> 
> Best regards
> Uwe
> 
>  drivers/spi/spi_imx.c |    8 +++++++-
>  1 files changed, 7 insertions(+), 1 deletions(-)
> 
> diff --git a/drivers/spi/spi_imx.c b/drivers/spi/spi_imx.c
> index 6bab2cf..55a38e2 100644
> --- a/drivers/spi/spi_imx.c
> +++ b/drivers/spi/spi_imx.c
> @@ -77,6 +77,7 @@ struct spi_imx_devtype_data {
>  	void (*trigger)(struct spi_imx_data *);
>  	int (*rx_available)(struct spi_imx_data *);
>  	void (*reset)(struct spi_imx_data *);
> +	unsigned int fifosize;
>  };
>  
>  struct spi_imx_data {
> @@ -541,6 +542,7 @@ static struct spi_imx_devtype_data spi_imx_devtype_data[] __devinitdata = {
>  		.trigger = mx1_trigger,
>  		.rx_available = mx1_rx_available,
>  		.reset = mx1_reset,
> +		.fifosize = 8,
>  	},
>  #endif
>  #ifdef CONFIG_SPI_IMX_VER_0_0
> @@ -550,6 +552,7 @@ static struct spi_imx_devtype_data spi_imx_devtype_data[] __devinitdata = {
>  		.trigger = mx27_trigger,
>  		.rx_available = mx27_rx_available,
>  		.reset = spi_imx0_0_reset,
> +		.fifosize = 8,
>  	},
>  #endif
>  #ifdef CONFIG_SPI_IMX_VER_0_4
> @@ -559,6 +562,7 @@ static struct spi_imx_devtype_data spi_imx_devtype_data[] __devinitdata = {
>  		.trigger = mx31_trigger,
>  		.rx_available = mx31_rx_available,
>  		.reset = spi_imx0_4_reset,
> +		.fifosize = 8,
>  	},
>  #endif
>  #ifdef CONFIG_SPI_IMX_VER_0_7
> @@ -568,6 +572,7 @@ static struct spi_imx_devtype_data spi_imx_devtype_data[] __devinitdata = {
>  		.trigger = mx31_trigger,
>  		.rx_available = mx31_rx_available,
>  		.reset = spi_imx0_4_reset,
> +		.fifosize = 8,
>  	},
>  #endif
>  #ifdef CONFIG_SPI_IMX_VER_2_3
> @@ -577,6 +582,7 @@ static struct spi_imx_devtype_data spi_imx_devtype_data[] __devinitdata = {
>  		.trigger = spi_imx2_3_trigger,
>  		.rx_available = spi_imx2_3_rx_available,
>  		.reset = spi_imx2_3_reset,
> +		.fifosize = 64,
>  	},
>  #endif
>  };
> @@ -596,7 +602,7 @@ static void spi_imx_chipselect(struct spi_device *spi, int is_active)
>  
>  static void spi_imx_push(struct spi_imx_data *spi_imx)
>  {
> -	while (spi_imx->txfifo < 8) {
> +	while (spi_imx->txfifo < spi_imx->devtype_data.fifosize) {
>  		if (!spi_imx->count)
>  			break;
>  		spi_imx->tx(spi_imx);
> -- 
> 1.7.2.3
> 

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