* [PATCH v2 02/17] spi: spi-geni-qcom: Use OPP API to set clk/perf state
[not found] <1587132279-27659-1-git-send-email-rnayak@codeaurora.org>
@ 2020-04-17 14:04 ` Rajendra Nayak
2020-04-17 14:04 ` [PATCH v2 15/17] spi: spi-qcom-qspi: " Rajendra Nayak
1 sibling, 0 replies; 2+ messages in thread
From: Rajendra Nayak @ 2020-04-17 14:04 UTC (permalink / raw)
To: viresh.kumar, sboyd, bjorn.andersson, agross
Cc: linux-arm-msm, devicetree, linux-kernel, mka, Rajendra Nayak,
Mark Brown, Alok Chauhan, Akash Asthana, linux-spi
geni spi needs to express a perforamnce state requirement on CX
depending on the frequency of the clock rates. Use OPP table from
DT to register with OPP framework and use dev_pm_opp_set_rate() to
set the clk/perf state.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: Alok Chauhan <alokc@codeaurora.org>
Cc: Akash Asthana <akashast@codeaurora.org>
Cc: linux-spi@vger.kernel.org
---
drivers/spi/spi-geni-qcom.c | 22 +++++++++++++++++++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c
index c397242..768b2fe 100644
--- a/drivers/spi/spi-geni-qcom.c
+++ b/drivers/spi/spi-geni-qcom.c
@@ -7,6 +7,7 @@
#include <linux/log2.h>
#include <linux/module.h>
#include <linux/platform_device.h>
+#include <linux/pm_opp.h>
#include <linux/pm_runtime.h>
#include <linux/qcom-geni-se.h>
#include <linux/spi/spi.h>
@@ -86,6 +87,7 @@ struct spi_geni_master {
spinlock_t lock;
enum spi_m_cmd_opcode cur_mcmd;
int irq;
+ bool opp_table;
};
static int get_spi_clk_cfg(unsigned int speed_hz,
@@ -95,7 +97,6 @@ static int get_spi_clk_cfg(unsigned int speed_hz,
{
unsigned long sclk_freq;
unsigned int actual_hz;
- struct geni_se *se = &mas->se;
int ret;
ret = geni_se_clk_freq_match(&mas->se,
@@ -112,9 +113,9 @@ static int get_spi_clk_cfg(unsigned int speed_hz,
dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz,
actual_hz, sclk_freq, *clk_idx, *clk_div);
- ret = clk_set_rate(se->clk, sclk_freq);
+ ret = dev_pm_opp_set_rate(mas->dev, sclk_freq);
if (ret)
- dev_err(mas->dev, "clk_set_rate failed %d\n", ret);
+ dev_err(mas->dev, "dev_pm_opp_set_rate failed %d\n", ret);
return ret;
}
@@ -561,6 +562,12 @@ static int spi_geni_probe(struct platform_device *pdev)
mas->se.wrapper = dev_get_drvdata(dev->parent);
mas->se.base = base;
mas->se.clk = clk;
+ mas->se.opp = dev_pm_opp_set_clkname(&pdev->dev, "se");
+ if (IS_ERR(mas->se.opp))
+ return PTR_ERR(mas->se.opp);
+ /* OPP table is optional */
+ if (!dev_pm_opp_of_add_table(&pdev->dev))
+ mas->opp_table = true;
spi->bus_num = -1;
spi->dev.of_node = dev->of_node;
@@ -596,6 +603,9 @@ static int spi_geni_probe(struct platform_device *pdev)
spi_geni_probe_runtime_disable:
pm_runtime_disable(dev);
spi_master_put(spi);
+ if (mas->opp_table)
+ dev_pm_opp_of_remove_table(&pdev->dev);
+ dev_pm_opp_put_clkname(mas->se.opp);
return ret;
}
@@ -604,6 +614,9 @@ static int spi_geni_remove(struct platform_device *pdev)
struct spi_master *spi = platform_get_drvdata(pdev);
struct spi_geni_master *mas = spi_master_get_devdata(spi);
+ if (mas->opp_table)
+ dev_pm_opp_of_remove_table(&pdev->dev);
+ dev_pm_opp_put_clkname(mas->se.opp);
/* Unregister _before_ disabling pm_runtime() so we stop transfers */
spi_unregister_master(spi);
@@ -617,6 +630,9 @@ static int __maybe_unused spi_geni_runtime_suspend(struct device *dev)
struct spi_master *spi = dev_get_drvdata(dev);
struct spi_geni_master *mas = spi_master_get_devdata(spi);
+ /* Drop the performance state vote */
+ dev_pm_opp_set_rate(dev, 0);
+
return geni_se_resources_off(&mas->se);
}
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [PATCH v2 15/17] spi: spi-qcom-qspi: Use OPP API to set clk/perf state
[not found] <1587132279-27659-1-git-send-email-rnayak@codeaurora.org>
2020-04-17 14:04 ` [PATCH v2 02/17] spi: spi-geni-qcom: Use OPP API to set clk/perf state Rajendra Nayak
@ 2020-04-17 14:04 ` Rajendra Nayak
1 sibling, 0 replies; 2+ messages in thread
From: Rajendra Nayak @ 2020-04-17 14:04 UTC (permalink / raw)
To: viresh.kumar, sboyd, bjorn.andersson, agross
Cc: linux-arm-msm, devicetree, linux-kernel, mka, Rajendra Nayak,
Mark Brown, Alok Chauhan, Akash Asthana, linux-spi
QSPI needs to vote on a performance state of a power domain depending on
the clock rate. Add support for it by specifying the perf state/clock rate
as an OPP table in device tree.
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Cc: Mark Brown <broonie@kernel.org>
Cc: Alok Chauhan <alokc@codeaurora.org>
Cc: Akash Asthana <akashast@codeaurora.org>
Cc: linux-spi@vger.kernel.org
---
drivers/spi/spi-qcom-qspi.c | 24 +++++++++++++++++++++++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-qcom-qspi.c b/drivers/spi/spi-qcom-qspi.c
index 3c4f83b..7c7bd18 100644
--- a/drivers/spi/spi-qcom-qspi.c
+++ b/drivers/spi/spi-qcom-qspi.c
@@ -8,6 +8,7 @@
#include <linux/of.h>
#include <linux/of_platform.h>
#include <linux/pm_runtime.h>
+#include <linux/pm_opp.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi-mem.h>
@@ -139,6 +140,8 @@ struct qcom_qspi {
struct device *dev;
struct clk_bulk_data *clks;
struct qspi_xfer xfer;
+ struct opp_table *opp;
+ bool opp_table;
/* Lock to protect xfer and IRQ accessed registers */
spinlock_t lock;
};
@@ -235,7 +238,7 @@ static int qcom_qspi_transfer_one(struct spi_master *master,
speed_hz = xfer->speed_hz;
/* In regular operation (SBL_EN=1) core must be 4x transfer clock */
- ret = clk_set_rate(ctrl->clks[QSPI_CLK_CORE].clk, speed_hz * 4);
+ ret = dev_pm_opp_set_rate(ctrl->dev, speed_hz * 4);
if (ret) {
dev_err(ctrl->dev, "Failed to set core clk %d\n", ret);
return ret;
@@ -481,6 +484,15 @@ static int qcom_qspi_probe(struct platform_device *pdev)
master->handle_err = qcom_qspi_handle_err;
master->auto_runtime_pm = true;
+ ctrl->opp = dev_pm_opp_set_clkname(&pdev->dev, "core");
+ if (IS_ERR(ctrl->opp)) {
+ ret = PTR_ERR(ctrl->opp);
+ goto exit_probe_master_put;
+ }
+ /* OPP table is optional */
+ if (!dev_pm_opp_of_add_table(&pdev->dev))
+ ctrl->opp_table = true;
+
pm_runtime_enable(dev);
ret = spi_register_master(master);
@@ -488,6 +500,9 @@ static int qcom_qspi_probe(struct platform_device *pdev)
return 0;
pm_runtime_disable(dev);
+ if (ctrl->opp_table)
+ dev_pm_opp_of_remove_table(&pdev->dev);
+ dev_pm_opp_put_clkname(ctrl->opp);
exit_probe_master_put:
spi_master_put(master);
@@ -498,6 +513,11 @@ static int qcom_qspi_probe(struct platform_device *pdev)
static int qcom_qspi_remove(struct platform_device *pdev)
{
struct spi_master *master = platform_get_drvdata(pdev);
+ struct qcom_qspi *ctrl = spi_master_get_devdata(master);
+
+ if (ctrl->opp_table)
+ dev_pm_opp_of_remove_table(&pdev->dev);
+ dev_pm_opp_put_clkname(ctrl->opp);
/* Unregister _before_ disabling pm_runtime() so we stop transfers */
spi_unregister_master(master);
@@ -512,6 +532,8 @@ static int __maybe_unused qcom_qspi_runtime_suspend(struct device *dev)
struct spi_master *master = dev_get_drvdata(dev);
struct qcom_qspi *ctrl = spi_master_get_devdata(master);
+ /* Drop the performance state vote */
+ dev_pm_opp_set_rate(dev, 0);
clk_bulk_disable_unprepare(QSPI_NUM_CLKS, ctrl->clks);
return 0;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
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2020-04-17 14:04 ` [PATCH v2 02/17] spi: spi-geni-qcom: Use OPP API to set clk/perf state Rajendra Nayak
2020-04-17 14:04 ` [PATCH v2 15/17] spi: spi-qcom-qspi: " Rajendra Nayak
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