* [PATCH v3 02/17] spi: spi-geni-qcom: Use OPP API to set clk/perf state [not found] <1588080785-6812-1-git-send-email-rnayak@codeaurora.org> @ 2020-04-28 13:32 ` Rajendra Nayak 2020-04-28 23:04 ` Matthias Kaehlcke 2020-04-28 13:33 ` [PATCH v3 15/17] spi: spi-qcom-qspi: " Rajendra Nayak 1 sibling, 1 reply; 5+ messages in thread From: Rajendra Nayak @ 2020-04-28 13:32 UTC (permalink / raw) To: viresh.kumar, sboyd, bjorn.andersson, agross Cc: linux-arm-msm, devicetree, linux-kernel, mka, Rajendra Nayak, Mark Brown, Alok Chauhan, Akash Asthana, linux-spi geni spi needs to express a perforamnce state requirement on CX depending on the frequency of the clock rates. Use OPP table from DT to register with OPP framework and use dev_pm_opp_set_rate() to set the clk/perf state. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Cc: Mark Brown <broonie@kernel.org> Cc: Alok Chauhan <alokc@codeaurora.org> Cc: Akash Asthana <akashast@codeaurora.org> Cc: linux-spi@vger.kernel.org --- This patch has a dependency on the 'PATCH 01/17' in this series, due to the changes in include/linux/qcom-geni-se.h Its ideal if this and the previous patch gets merged via the msm tree (once reviewed and ack'ed) Greg has already responded he is fine with it for serial. drivers/spi/spi-geni-qcom.c | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c index c397242..51186c3 100644 --- a/drivers/spi/spi-geni-qcom.c +++ b/drivers/spi/spi-geni-qcom.c @@ -7,6 +7,7 @@ #include <linux/log2.h> #include <linux/module.h> #include <linux/platform_device.h> +#include <linux/pm_opp.h> #include <linux/pm_runtime.h> #include <linux/qcom-geni-se.h> #include <linux/spi/spi.h> @@ -95,7 +96,6 @@ static int get_spi_clk_cfg(unsigned int speed_hz, { unsigned long sclk_freq; unsigned int actual_hz; - struct geni_se *se = &mas->se; int ret; ret = geni_se_clk_freq_match(&mas->se, @@ -112,9 +112,9 @@ static int get_spi_clk_cfg(unsigned int speed_hz, dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz, actual_hz, sclk_freq, *clk_idx, *clk_div); - ret = clk_set_rate(se->clk, sclk_freq); + ret = dev_pm_opp_set_rate(mas->dev, sclk_freq); if (ret) - dev_err(mas->dev, "clk_set_rate failed %d\n", ret); + dev_err(mas->dev, "dev_pm_opp_set_rate failed %d\n", ret); return ret; } @@ -561,6 +561,17 @@ static int spi_geni_probe(struct platform_device *pdev) mas->se.wrapper = dev_get_drvdata(dev->parent); mas->se.base = base; mas->se.clk = clk; + mas->se.opp_table = dev_pm_opp_set_clkname(&pdev->dev, "se"); + if (IS_ERR(mas->se.opp_table)) + return PTR_ERR(mas->se.opp_table); + /* OPP table is optional */ + ret = dev_pm_opp_of_add_table(&pdev->dev); + if (!ret) { + mas->se.has_opp_table = true; + } else if (ret != -ENODEV) { + dev_err(&pdev->dev, "Invalid OPP table in Device tree\n"); + return ret; + } spi->bus_num = -1; spi->dev.of_node = dev->of_node; @@ -596,6 +607,9 @@ static int spi_geni_probe(struct platform_device *pdev) spi_geni_probe_runtime_disable: pm_runtime_disable(dev); spi_master_put(spi); + if (mas->se.has_opp_table) + dev_pm_opp_of_remove_table(&pdev->dev); + dev_pm_opp_put_clkname(mas->se.opp_table); return ret; } @@ -604,6 +618,9 @@ static int spi_geni_remove(struct platform_device *pdev) struct spi_master *spi = platform_get_drvdata(pdev); struct spi_geni_master *mas = spi_master_get_devdata(spi); + if (mas->se.has_opp_table) + dev_pm_opp_of_remove_table(&pdev->dev); + dev_pm_opp_put_clkname(mas->se.opp_table); /* Unregister _before_ disabling pm_runtime() so we stop transfers */ spi_unregister_master(spi); @@ -617,6 +634,9 @@ static int __maybe_unused spi_geni_runtime_suspend(struct device *dev) struct spi_master *spi = dev_get_drvdata(dev); struct spi_geni_master *mas = spi_master_get_devdata(spi); + /* Drop the performance state vote */ + dev_pm_opp_set_rate(dev, 0); + return geni_se_resources_off(&mas->se); } -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v3 02/17] spi: spi-geni-qcom: Use OPP API to set clk/perf state 2020-04-28 13:32 ` [PATCH v3 02/17] spi: spi-geni-qcom: Use OPP API to set clk/perf state Rajendra Nayak @ 2020-04-28 23:04 ` Matthias Kaehlcke 0 siblings, 0 replies; 5+ messages in thread From: Matthias Kaehlcke @ 2020-04-28 23:04 UTC (permalink / raw) To: Rajendra Nayak Cc: viresh.kumar, sboyd, bjorn.andersson, agross, linux-arm-msm, devicetree, linux-kernel, Mark Brown, Alok Chauhan, Akash Asthana, linux-spi On Tue, Apr 28, 2020 at 07:02:50PM +0530, Rajendra Nayak wrote: > geni spi needs to express a perforamnce state requirement on CX > depending on the frequency of the clock rates. Use OPP table from > DT to register with OPP framework and use dev_pm_opp_set_rate() to > set the clk/perf state. > > Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> > Cc: Mark Brown <broonie@kernel.org> > Cc: Alok Chauhan <alokc@codeaurora.org> > Cc: Akash Asthana <akashast@codeaurora.org> > Cc: linux-spi@vger.kernel.org > --- > This patch has a dependency on the 'PATCH 01/17' in this series, > due to the changes in include/linux/qcom-geni-se.h > Its ideal if this and the previous patch gets merged via the > msm tree (once reviewed and ack'ed) > Greg has already responded he is fine with it for serial. > > drivers/spi/spi-geni-qcom.c | 26 +++++++++++++++++++++++--- > 1 file changed, 23 insertions(+), 3 deletions(-) > > diff --git a/drivers/spi/spi-geni-qcom.c b/drivers/spi/spi-geni-qcom.c > index c397242..51186c3 100644 > --- a/drivers/spi/spi-geni-qcom.c > +++ b/drivers/spi/spi-geni-qcom.c > @@ -7,6 +7,7 @@ > #include <linux/log2.h> > #include <linux/module.h> > #include <linux/platform_device.h> > +#include <linux/pm_opp.h> > #include <linux/pm_runtime.h> > #include <linux/qcom-geni-se.h> > #include <linux/spi/spi.h> > @@ -95,7 +96,6 @@ static int get_spi_clk_cfg(unsigned int speed_hz, > { > unsigned long sclk_freq; > unsigned int actual_hz; > - struct geni_se *se = &mas->se; > int ret; > > ret = geni_se_clk_freq_match(&mas->se, > @@ -112,9 +112,9 @@ static int get_spi_clk_cfg(unsigned int speed_hz, > > dev_dbg(mas->dev, "req %u=>%u sclk %lu, idx %d, div %d\n", speed_hz, > actual_hz, sclk_freq, *clk_idx, *clk_div); > - ret = clk_set_rate(se->clk, sclk_freq); > + ret = dev_pm_opp_set_rate(mas->dev, sclk_freq); > if (ret) > - dev_err(mas->dev, "clk_set_rate failed %d\n", ret); > + dev_err(mas->dev, "dev_pm_opp_set_rate failed %d\n", ret); > return ret; > } > > @@ -561,6 +561,17 @@ static int spi_geni_probe(struct platform_device *pdev) > mas->se.wrapper = dev_get_drvdata(dev->parent); > mas->se.base = base; > mas->se.clk = clk; > + mas->se.opp_table = dev_pm_opp_set_clkname(&pdev->dev, "se"); > + if (IS_ERR(mas->se.opp_table)) > + return PTR_ERR(mas->se.opp_table); > + /* OPP table is optional */ > + ret = dev_pm_opp_of_add_table(&pdev->dev); > + if (!ret) { > + mas->se.has_opp_table = true; > + } else if (ret != -ENODEV) { > + dev_err(&pdev->dev, "Invalid OPP table in Device tree\n"); > + return ret; > + } > > spi->bus_num = -1; > spi->dev.of_node = dev->of_node; > @@ -596,6 +607,9 @@ static int spi_geni_probe(struct platform_device *pdev) > spi_geni_probe_runtime_disable: > pm_runtime_disable(dev); > spi_master_put(spi); > + if (mas->se.has_opp_table) > + dev_pm_opp_of_remove_table(&pdev->dev); > + dev_pm_opp_put_clkname(mas->se.opp_table); > return ret; > } > > @@ -604,6 +618,9 @@ static int spi_geni_remove(struct platform_device *pdev) > struct spi_master *spi = platform_get_drvdata(pdev); > struct spi_geni_master *mas = spi_master_get_devdata(spi); > > + if (mas->se.has_opp_table) > + dev_pm_opp_of_remove_table(&pdev->dev); > + dev_pm_opp_put_clkname(mas->se.opp_table); > /* Unregister _before_ disabling pm_runtime() so we stop transfers */ > spi_unregister_master(spi); > > @@ -617,6 +634,9 @@ static int __maybe_unused spi_geni_runtime_suspend(struct device *dev) > struct spi_master *spi = dev_get_drvdata(dev); > struct spi_geni_master *mas = spi_master_get_devdata(spi); > > + /* Drop the performance state vote */ > + dev_pm_opp_set_rate(dev, 0); > + > return geni_se_resources_off(&mas->se); > } Reviewed-by: Matthias Kaehlcke <mka@chromium.org> ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v3 15/17] spi: spi-qcom-qspi: Use OPP API to set clk/perf state [not found] <1588080785-6812-1-git-send-email-rnayak@codeaurora.org> 2020-04-28 13:32 ` [PATCH v3 02/17] spi: spi-geni-qcom: Use OPP API to set clk/perf state Rajendra Nayak @ 2020-04-28 13:33 ` Rajendra Nayak 2020-04-29 0:49 ` Matthias Kaehlcke 1 sibling, 1 reply; 5+ messages in thread From: Rajendra Nayak @ 2020-04-28 13:33 UTC (permalink / raw) To: viresh.kumar, sboyd, bjorn.andersson, agross Cc: linux-arm-msm, devicetree, linux-kernel, mka, Rajendra Nayak, Mark Brown, Alok Chauhan, Akash Asthana, linux-spi QSPI needs to vote on a performance state of a power domain depending on the clock rate. Add support for it by specifying the perf state/clock rate as an OPP table in device tree. Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> Cc: Mark Brown <broonie@kernel.org> Cc: Alok Chauhan <alokc@codeaurora.org> Cc: Akash Asthana <akashast@codeaurora.org> Cc: linux-spi@vger.kernel.org --- drivers/spi/spi-qcom-qspi.c | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-qcom-qspi.c b/drivers/spi/spi-qcom-qspi.c index 3c4f83b..724a658 100644 --- a/drivers/spi/spi-qcom-qspi.c +++ b/drivers/spi/spi-qcom-qspi.c @@ -8,6 +8,7 @@ #include <linux/of.h> #include <linux/of_platform.h> #include <linux/pm_runtime.h> +#include <linux/pm_opp.h> #include <linux/spi/spi.h> #include <linux/spi/spi-mem.h> @@ -139,6 +140,8 @@ struct qcom_qspi { struct device *dev; struct clk_bulk_data *clks; struct qspi_xfer xfer; + struct opp_table *opp_table; + bool has_opp_table; /* Lock to protect xfer and IRQ accessed registers */ spinlock_t lock; }; @@ -235,7 +238,7 @@ static int qcom_qspi_transfer_one(struct spi_master *master, speed_hz = xfer->speed_hz; /* In regular operation (SBL_EN=1) core must be 4x transfer clock */ - ret = clk_set_rate(ctrl->clks[QSPI_CLK_CORE].clk, speed_hz * 4); + ret = dev_pm_opp_set_rate(ctrl->dev, speed_hz * 4); if (ret) { dev_err(ctrl->dev, "Failed to set core clk %d\n", ret); return ret; @@ -481,6 +484,20 @@ static int qcom_qspi_probe(struct platform_device *pdev) master->handle_err = qcom_qspi_handle_err; master->auto_runtime_pm = true; + ctrl->opp_table = dev_pm_opp_set_clkname(&pdev->dev, "core"); + if (IS_ERR(ctrl->opp_table)) { + ret = PTR_ERR(ctrl->opp_table); + goto exit_probe_master_put; + } + /* OPP table is optional */ + ret = dev_pm_opp_of_add_table(&pdev->dev); + if (!ret) { + ctrl->has_opp_table = true; + } else if (ret != -ENODEV) { + dev_err(&pdev->dev, "Invalid OPP table in Device tree\n"); + return ret; + } + pm_runtime_enable(dev); ret = spi_register_master(master); @@ -488,6 +505,9 @@ static int qcom_qspi_probe(struct platform_device *pdev) return 0; pm_runtime_disable(dev); + if (ctrl->has_opp_table) + dev_pm_opp_of_remove_table(&pdev->dev); + dev_pm_opp_put_clkname(ctrl->opp_table); exit_probe_master_put: spi_master_put(master); @@ -498,6 +518,11 @@ static int qcom_qspi_probe(struct platform_device *pdev) static int qcom_qspi_remove(struct platform_device *pdev) { struct spi_master *master = platform_get_drvdata(pdev); + struct qcom_qspi *ctrl = spi_master_get_devdata(master); + + if (ctrl->has_opp_table) + dev_pm_opp_of_remove_table(&pdev->dev); + dev_pm_opp_put_clkname(ctrl->opp_table); /* Unregister _before_ disabling pm_runtime() so we stop transfers */ spi_unregister_master(master); @@ -512,6 +537,8 @@ static int __maybe_unused qcom_qspi_runtime_suspend(struct device *dev) struct spi_master *master = dev_get_drvdata(dev); struct qcom_qspi *ctrl = spi_master_get_devdata(master); + /* Drop the performance state vote */ + dev_pm_opp_set_rate(dev, 0); clk_bulk_disable_unprepare(QSPI_NUM_CLKS, ctrl->clks); return 0; -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v3 15/17] spi: spi-qcom-qspi: Use OPP API to set clk/perf state 2020-04-28 13:33 ` [PATCH v3 15/17] spi: spi-qcom-qspi: " Rajendra Nayak @ 2020-04-29 0:49 ` Matthias Kaehlcke 2020-04-29 14:21 ` Rajendra Nayak 0 siblings, 1 reply; 5+ messages in thread From: Matthias Kaehlcke @ 2020-04-29 0:49 UTC (permalink / raw) To: Rajendra Nayak Cc: viresh.kumar, sboyd, bjorn.andersson, agross, linux-arm-msm, devicetree, linux-kernel, Mark Brown, Alok Chauhan, Akash Asthana, linux-spi Hi, On Tue, Apr 28, 2020 at 07:03:03PM +0530, Rajendra Nayak wrote: > QSPI needs to vote on a performance state of a power domain depending on > the clock rate. Add support for it by specifying the perf state/clock rate > as an OPP table in device tree. > > Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> > Cc: Mark Brown <broonie@kernel.org> > Cc: Alok Chauhan <alokc@codeaurora.org> > Cc: Akash Asthana <akashast@codeaurora.org> > Cc: linux-spi@vger.kernel.org > --- > drivers/spi/spi-qcom-qspi.c | 29 ++++++++++++++++++++++++++++- > 1 file changed, 28 insertions(+), 1 deletion(-) > > diff --git a/drivers/spi/spi-qcom-qspi.c b/drivers/spi/spi-qcom-qspi.c > index 3c4f83b..724a658 100644 > --- a/drivers/spi/spi-qcom-qspi.c > +++ b/drivers/spi/spi-qcom-qspi.c > @@ -8,6 +8,7 @@ > #include <linux/of.h> > #include <linux/of_platform.h> > #include <linux/pm_runtime.h> > +#include <linux/pm_opp.h> > #include <linux/spi/spi.h> > #include <linux/spi/spi-mem.h> > > @@ -139,6 +140,8 @@ struct qcom_qspi { > struct device *dev; > struct clk_bulk_data *clks; > struct qspi_xfer xfer; > + struct opp_table *opp_table; > + bool has_opp_table; > /* Lock to protect xfer and IRQ accessed registers */ > spinlock_t lock; > }; > @@ -235,7 +238,7 @@ static int qcom_qspi_transfer_one(struct spi_master *master, > speed_hz = xfer->speed_hz; > > /* In regular operation (SBL_EN=1) core must be 4x transfer clock */ > - ret = clk_set_rate(ctrl->clks[QSPI_CLK_CORE].clk, speed_hz * 4); > + ret = dev_pm_opp_set_rate(ctrl->dev, speed_hz * 4); > if (ret) { > dev_err(ctrl->dev, "Failed to set core clk %d\n", ret); > return ret; > @@ -481,6 +484,20 @@ static int qcom_qspi_probe(struct platform_device *pdev) > master->handle_err = qcom_qspi_handle_err; > master->auto_runtime_pm = true; > > + ctrl->opp_table = dev_pm_opp_set_clkname(&pdev->dev, "core"); > + if (IS_ERR(ctrl->opp_table)) { > + ret = PTR_ERR(ctrl->opp_table); > + goto exit_probe_master_put; > + } > + /* OPP table is optional */ > + ret = dev_pm_opp_of_add_table(&pdev->dev); > + if (!ret) { > + ctrl->has_opp_table = true; > + } else if (ret != -ENODEV) { > + dev_err(&pdev->dev, "Invalid OPP table in Device tree\n"); > + return ret; goto exit_probe_master_put; ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v3 15/17] spi: spi-qcom-qspi: Use OPP API to set clk/perf state 2020-04-29 0:49 ` Matthias Kaehlcke @ 2020-04-29 14:21 ` Rajendra Nayak 0 siblings, 0 replies; 5+ messages in thread From: Rajendra Nayak @ 2020-04-29 14:21 UTC (permalink / raw) To: Matthias Kaehlcke Cc: viresh.kumar, sboyd, bjorn.andersson, agross, linux-arm-msm, devicetree, linux-kernel, Mark Brown, Alok Chauhan, Akash Asthana, linux-spi On 4/29/2020 6:19 AM, Matthias Kaehlcke wrote: > Hi, > > On Tue, Apr 28, 2020 at 07:03:03PM +0530, Rajendra Nayak wrote: >> QSPI needs to vote on a performance state of a power domain depending on >> the clock rate. Add support for it by specifying the perf state/clock rate >> as an OPP table in device tree. >> >> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org> >> Cc: Mark Brown <broonie@kernel.org> >> Cc: Alok Chauhan <alokc@codeaurora.org> >> Cc: Akash Asthana <akashast@codeaurora.org> >> Cc: linux-spi@vger.kernel.org >> --- >> drivers/spi/spi-qcom-qspi.c | 29 ++++++++++++++++++++++++++++- >> 1 file changed, 28 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/spi/spi-qcom-qspi.c b/drivers/spi/spi-qcom-qspi.c >> index 3c4f83b..724a658 100644 >> --- a/drivers/spi/spi-qcom-qspi.c >> +++ b/drivers/spi/spi-qcom-qspi.c >> @@ -8,6 +8,7 @@ >> #include <linux/of.h> >> #include <linux/of_platform.h> >> #include <linux/pm_runtime.h> >> +#include <linux/pm_opp.h> >> #include <linux/spi/spi.h> >> #include <linux/spi/spi-mem.h> >> >> @@ -139,6 +140,8 @@ struct qcom_qspi { >> struct device *dev; >> struct clk_bulk_data *clks; >> struct qspi_xfer xfer; >> + struct opp_table *opp_table; >> + bool has_opp_table; >> /* Lock to protect xfer and IRQ accessed registers */ >> spinlock_t lock; >> }; >> @@ -235,7 +238,7 @@ static int qcom_qspi_transfer_one(struct spi_master *master, >> speed_hz = xfer->speed_hz; >> >> /* In regular operation (SBL_EN=1) core must be 4x transfer clock */ >> - ret = clk_set_rate(ctrl->clks[QSPI_CLK_CORE].clk, speed_hz * 4); >> + ret = dev_pm_opp_set_rate(ctrl->dev, speed_hz * 4); >> if (ret) { >> dev_err(ctrl->dev, "Failed to set core clk %d\n", ret); >> return ret; >> @@ -481,6 +484,20 @@ static int qcom_qspi_probe(struct platform_device *pdev) >> master->handle_err = qcom_qspi_handle_err; >> master->auto_runtime_pm = true; >> >> + ctrl->opp_table = dev_pm_opp_set_clkname(&pdev->dev, "core"); >> + if (IS_ERR(ctrl->opp_table)) { >> + ret = PTR_ERR(ctrl->opp_table); >> + goto exit_probe_master_put; >> + } >> + /* OPP table is optional */ >> + ret = dev_pm_opp_of_add_table(&pdev->dev); >> + if (!ret) { >> + ctrl->has_opp_table = true; >> + } else if (ret != -ENODEV) { >> + dev_err(&pdev->dev, "Invalid OPP table in Device tree\n"); >> + return ret; > > goto exit_probe_master_put; thanks for catching this. will fix and respin. -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-04-29 14:21 UTC | newest] Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- [not found] <1588080785-6812-1-git-send-email-rnayak@codeaurora.org> 2020-04-28 13:32 ` [PATCH v3 02/17] spi: spi-geni-qcom: Use OPP API to set clk/perf state Rajendra Nayak 2020-04-28 23:04 ` Matthias Kaehlcke 2020-04-28 13:33 ` [PATCH v3 15/17] spi: spi-qcom-qspi: " Rajendra Nayak 2020-04-29 0:49 ` Matthias Kaehlcke 2020-04-29 14:21 ` Rajendra Nayak
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