* [PATCH v3 01/15] dt-bindings: soc/microchip: update syscontroller compatibles
2022-01-14 15:17 [PATCH v3 00/15] Update the Icicle Kit device tree conor.dooley
@ 2022-01-14 15:17 ` conor.dooley
2022-01-14 16:18 ` conor dooley
2022-01-15 17:22 ` Rob Herring
2022-01-14 15:17 ` [PATCH v3 02/15] dt-bindings: soc/microchip: add services as children of sys ctrlr conor.dooley
` (13 subsequent siblings)
14 siblings, 2 replies; 27+ messages in thread
From: conor.dooley @ 2022-01-14 15:17 UTC (permalink / raw)
To: linus.walleij, bgolaszewski, robh+dt, jassisinghbrar,
paul.walmsley, palmer, aou, a.zummo, alexandre.belloni, broonie,
gregkh, thierry.reding, u.kleine-koenig, lee.jones, linux-gpio,
devicetree, linux-kernel, linux-i2c, linux-pwm, linux-riscv,
linux-crypto, linux-rtc, linux-spi, linux-usb
Cc: krzysztof.kozlowski, geert, bin.meng, heiko, lewis.hanly,
conor.dooley, daire.mcnamara, ivan.griffin, atishp
From: Conor Dooley <conor.dooley@microchip.com>
The Polarfire SoC is currently using two different compatible string
prefixes. Fix this by changing "polarfire-soc-*" strings to "mpfs-*" in
its system controller in order to match the compatible string used in
the soc binding and device tree
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
...larfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} | 6 +++---
...s-controller.yaml => microchip,mpfs-sys-controller.yaml} | 6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)
rename Documentation/devicetree/bindings/mailbox/{microchip,polarfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} (82%)
rename Documentation/devicetree/bindings/soc/microchip/{microchip,polarfire-soc-sys-controller.yaml => microchip,mpfs-sys-controller.yaml} (75%)
diff --git a/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
similarity index 82%
rename from Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml
rename to Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
index bbb173ea483c..9251c2218c68 100644
--- a/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml
+++ b/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/mailbox/microchip,polarfire-soc-mailbox.yaml#"
+$id: "http://devicetree.org/schemas/mailbox/microchip,mpfs-mailbox.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) mailbox controller
@@ -11,7 +11,7 @@ maintainers:
properties:
compatible:
- const: microchip,polarfire-soc-mailbox
+ const: microchip,mpfs-mailbox
reg:
items:
@@ -38,7 +38,7 @@ examples:
#address-cells = <2>;
#size-cells = <2>;
mbox: mailbox@37020000 {
- compatible = "microchip,polarfire-soc-mailbox";
+ compatible = "mpfs-mailbox";
reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318c 0x0 0x40>;
interrupt-parent = <&L1>;
interrupts = <96>;
diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
similarity index 75%
rename from Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
rename to Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
index 2cd3bc6bd8d6..f699772fedf3 100644
--- a/Documentation/devicetree/bindings/soc/microchip/microchip,polarfire-soc-sys-controller.yaml
+++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/soc/microchip/microchip,polarfire-soc-sys-controller.yaml#"
+$id: "http://devicetree.org/schemas/soc/microchip/microchip,mpfs-sys-controller.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) system controller
@@ -19,7 +19,7 @@ properties:
maxItems: 1
compatible:
- const: microchip,polarfire-soc-sys-controller
+ const: microchip,mpfs-sys-controller
required:
- compatible
@@ -30,6 +30,6 @@ additionalProperties: false
examples:
- |
syscontroller: syscontroller {
- compatible = "microchip,polarfire-soc-sys-controller";
+ compatible = "microchip,mpfs-sys-controller";
mboxes = <&mbox 0>;
};
--
2.32.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH v3 01/15] dt-bindings: soc/microchip: update syscontroller compatibles
2022-01-14 15:17 ` [PATCH v3 01/15] dt-bindings: soc/microchip: update syscontroller compatibles conor.dooley
@ 2022-01-14 16:18 ` conor dooley
2022-01-15 17:22 ` Rob Herring
1 sibling, 0 replies; 27+ messages in thread
From: conor dooley @ 2022-01-14 16:18 UTC (permalink / raw)
To: conor.dooley
Cc: linus.walleij, bgolaszewski, robh+dt, jassisinghbrar,
paul.walmsley, palmer, aou, a.zummo, alexandre.belloni, broonie,
gregkh, thierry.reding, u.kleine-koenig, lee.jones, linux-gpio,
devicetree, linux-kernel, linux-i2c, linux-pwm, linux-riscv,
linux-crypto, linux-rtc, linux-spi, linux-usb,
krzysztof.kozlowski, geert, bin.meng, heiko, lewis.hanly,
daire.mcnamara, ivan.griffin, atishp
> From: Conor Dooley <conor.dooley@microchip.com>
>
> The Polarfire SoC is currently using two different compatible string
> prefixes. Fix this by changing "polarfire-soc-*" strings to "mpfs-*" in
> its system controller in order to match the compatible string used in
> the soc binding and device tree
>
> Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> ...larfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} | 6 +++---
> ...s-controller.yaml => microchip,mpfs-sys-controller.yaml} | 6 +++---
> 2 files changed, 6 insertions(+), 6 deletions(-)
> rename Documentation/devicetree/bindings/mailbox/{microchip,polarfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} (82%)
> rename Documentation/devicetree/bindings/soc/microchip/{microchip,polarfire-soc-sys-controller.yaml => microchip,mpfs-sys-controller.yaml} (75%)
>
> diff --git a/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
> similarity index 82%
> rename from Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml
> rename to Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
> index bbb173ea483c..9251c2218c68 100644
> --- a/Documentation/devicetree/bindings/mailbox/microchip,polarfire-soc-mailbox.yaml
> +++ b/Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.yaml
> @@ -1,7 +1,7 @@
> # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> %YAML 1.2
> ---
> -$id: "http://devicetree.org/schemas/mailbox/microchip,polarfire-soc-mailbox.yaml#"
> +$id: "http://devicetree.org/schemas/mailbox/microchip,mpfs-mailbox.yaml#"
> $schema: "http://devicetree.org/meta-schemas/core.yaml#"
>
> title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) mailbox controller
> @@ -11,7 +11,7 @@ maintainers:
>
> properties:
> compatible:
> - const: microchip,polarfire-soc-mailbox
> + const: microchip,mpfs-mailbox
>
> reg:
> items:
> @@ -38,7 +38,7 @@ examples:
> #address-cells = <2>;
> #size-cells = <2>;
> mbox: mailbox@37020000 {
> - compatible = "microchip,polarfire-soc-mailbox";
> + compatible = "mpfs-mailbox";
Example is wrong, should read "microchip,mpfs-mailbox".
Will resubmit Monday.
> reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318c 0x0 0x40>;
> interrupt-parent = <&L1>;
> interrupts = <96>;
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 01/15] dt-bindings: soc/microchip: update syscontroller compatibles
2022-01-14 15:17 ` [PATCH v3 01/15] dt-bindings: soc/microchip: update syscontroller compatibles conor.dooley
2022-01-14 16:18 ` conor dooley
@ 2022-01-15 17:22 ` Rob Herring
1 sibling, 0 replies; 27+ messages in thread
From: Rob Herring @ 2022-01-15 17:22 UTC (permalink / raw)
To: conor.dooley
Cc: robh+dt, bgolaszewski, jassisinghbrar, linus.walleij, linux-i2c,
linux-gpio, paul.walmsley, linux-usb, lewis.hanly, lee.jones,
aou, daire.mcnamara, thierry.reding, linux-riscv, broonie,
linux-pwm, a.zummo, heiko, u.kleine-koenig, atishp, linux-spi,
alexandre.belloni, bin.meng, devicetree, geert, palmer,
linux-kernel, krzysztof.kozlowski, gregkh, linux-rtc,
ivan.griffin, linux-crypto
On Fri, 14 Jan 2022 15:17:13 +0000, conor.dooley@microchip.com wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> The Polarfire SoC is currently using two different compatible string
> prefixes. Fix this by changing "polarfire-soc-*" strings to "mpfs-*" in
> its system controller in order to match the compatible string used in
> the soc binding and device tree
>
> Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> ...larfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} | 6 +++---
> ...s-controller.yaml => microchip,mpfs-sys-controller.yaml} | 6 +++---
> 2 files changed, 6 insertions(+), 6 deletions(-)
> rename Documentation/devicetree/bindings/mailbox/{microchip,polarfire-soc-mailbox.yaml => microchip,mpfs-mailbox.yaml} (82%)
> rename Documentation/devicetree/bindings/soc/microchip/{microchip,polarfire-soc-sys-controller.yaml => microchip,mpfs-sys-controller.yaml} (75%)
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/mailbox/microchip,mpfs-mailbox.example.dt.yaml:0:0: /example-0/soc/mailbox@37020000: failed to match any schema with compatible: ['mpfs-mailbox']
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1580091
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v3 02/15] dt-bindings: soc/microchip: add services as children of sys ctrlr
2022-01-14 15:17 [PATCH v3 00/15] Update the Icicle Kit device tree conor.dooley
2022-01-14 15:17 ` [PATCH v3 01/15] dt-bindings: soc/microchip: update syscontroller compatibles conor.dooley
@ 2022-01-14 15:17 ` conor.dooley
2022-01-14 15:17 ` [PATCH v3 03/15] mailbox: change mailbox-mpfs compatible string conor.dooley
` (12 subsequent siblings)
14 siblings, 0 replies; 27+ messages in thread
From: conor.dooley @ 2022-01-14 15:17 UTC (permalink / raw)
To: linus.walleij, bgolaszewski, robh+dt, jassisinghbrar,
paul.walmsley, palmer, aou, a.zummo, alexandre.belloni, broonie,
gregkh, thierry.reding, u.kleine-koenig, lee.jones, linux-gpio,
devicetree, linux-kernel, linux-i2c, linux-pwm, linux-riscv,
linux-crypto, linux-rtc, linux-spi, linux-usb
Cc: krzysztof.kozlowski, geert, bin.meng, heiko, lewis.hanly,
conor.dooley, daire.mcnamara, ivan.griffin, atishp
From: Conor Dooley <conor.dooley@microchip.com>
Add mpfs-rng and mpfs-generic-services as children of the system
controller.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../microchip,mpfs-sys-controller.yaml | 44 +++++++++++++++++--
1 file changed, 41 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
index f699772fedf3..b69386b1a3e1 100644
--- a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
+++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-sys-controller.yaml
@@ -13,13 +13,45 @@ description: |
The PolarFire SoC system controller is communicated with via a mailbox.
This document describes the bindings for the client portion of that mailbox.
-
properties:
mboxes:
maxItems: 1
compatible:
- const: microchip,mpfs-sys-controller
+ items:
+ - const: microchip,mpfs-sys-controller
+
+ rng:
+ type: object
+
+ description: |
+ The hardware random number generator on the Polarfire SoC is
+ accessed via the mailbox interface provided by the system controller
+
+ properties:
+ compatible:
+ const: microchip,mpfs-rng
+
+ required:
+ - compatible
+
+ sysserv:
+ type: object
+
+ description: |
+ The PolarFire SoC system controller is communicated with via a mailbox.
+ This binding represents several of the functions provided by the system
+ controller which do not belong in a specific subsystem, such as reading
+ the fpga device certificate, all of which follow the same format:
+ - a command + optional payload sent to the sys controller
+ - a status + a payload returned to Linux
+
+ properties:
+ compatible:
+ const: microchip,mpfs-generic-service
+
+ required:
+ - compatible
required:
- compatible
@@ -29,7 +61,13 @@ additionalProperties: false
examples:
- |
- syscontroller: syscontroller {
+ syscontroller {
compatible = "microchip,mpfs-sys-controller";
mboxes = <&mbox 0>;
+ rng: rng {
+ compatible = "microchip,mpfs-rng";
+ };
+ sysserv: sysserv {
+ compatible = "microchip,mpfs-generic-service";
+ };
};
--
2.32.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v3 03/15] mailbox: change mailbox-mpfs compatible string
2022-01-14 15:17 [PATCH v3 00/15] Update the Icicle Kit device tree conor.dooley
2022-01-14 15:17 ` [PATCH v3 01/15] dt-bindings: soc/microchip: update syscontroller compatibles conor.dooley
2022-01-14 15:17 ` [PATCH v3 02/15] dt-bindings: soc/microchip: add services as children of sys ctrlr conor.dooley
@ 2022-01-14 15:17 ` conor.dooley
2022-01-14 15:40 ` Geert Uytterhoeven
2022-01-14 15:17 ` [PATCH v3 04/15] dt-bindings: i2c: add bindings for microchip mpfs i2c conor.dooley
` (11 subsequent siblings)
14 siblings, 1 reply; 27+ messages in thread
From: conor.dooley @ 2022-01-14 15:17 UTC (permalink / raw)
To: linus.walleij, bgolaszewski, robh+dt, jassisinghbrar,
paul.walmsley, palmer, aou, a.zummo, alexandre.belloni, broonie,
gregkh, thierry.reding, u.kleine-koenig, lee.jones, linux-gpio,
devicetree, linux-kernel, linux-i2c, linux-pwm, linux-riscv,
linux-crypto, linux-rtc, linux-spi, linux-usb
Cc: krzysztof.kozlowski, geert, bin.meng, heiko, lewis.hanly,
conor.dooley, daire.mcnamara, ivan.griffin, atishp
From: Conor Dooley <conor.dooley@microchip.com>
The Polarfire SoC is currently using two different compatible string
prefixes. Fix this by changing "polarfire-soc-*" strings to "mpfs-*" in
its system controller in order to match the compatible string used in
the soc binding and device tree.
Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
drivers/mailbox/mailbox-mpfs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mailbox/mailbox-mpfs.c b/drivers/mailbox/mailbox-mpfs.c
index 0d6e2231a2c7..4e34854d1238 100644
--- a/drivers/mailbox/mailbox-mpfs.c
+++ b/drivers/mailbox/mailbox-mpfs.c
@@ -232,7 +232,7 @@ static int mpfs_mbox_probe(struct platform_device *pdev)
}
static const struct of_device_id mpfs_mbox_of_match[] = {
- {.compatible = "microchip,polarfire-soc-mailbox", },
+ {.compatible = "microchip,mpfs-mailbox", },
{},
};
MODULE_DEVICE_TABLE(of, mpfs_mbox_of_match);
--
2.32.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH v3 03/15] mailbox: change mailbox-mpfs compatible string
2022-01-14 15:17 ` [PATCH v3 03/15] mailbox: change mailbox-mpfs compatible string conor.dooley
@ 2022-01-14 15:40 ` Geert Uytterhoeven
2022-01-14 16:15 ` conor dooley
0 siblings, 1 reply; 27+ messages in thread
From: Geert Uytterhoeven @ 2022-01-14 15:40 UTC (permalink / raw)
To: Conor Dooley
Cc: Linus Walleij, Bartosz Golaszewski, Rob Herring, Jassi Brar,
Paul Walmsley, Palmer Dabbelt, Albert Ou, Alessandro Zummo,
Alexandre Belloni, Mark Brown, Greg KH, Thierry Reding,
Uwe Kleine-König, Lee Jones, open list:GPIO SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, Linux I2C, Linux PWM List,
linux-riscv, Linux Crypto Mailing List, linux-rtc, linux-spi,
USB list, Krzysztof Kozlowski, Bin Meng, Heiko Stuebner,
Lewis Hanly, daire.mcnamara, ivan.griffin, Atish Patra
Hi Conor,
On Fri, Jan 14, 2022 at 4:16 PM <conor.dooley@microchip.com> wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> The Polarfire SoC is currently using two different compatible string
> prefixes. Fix this by changing "polarfire-soc-*" strings to "mpfs-*" in
> its system controller in order to match the compatible string used in
> the soc binding and device tree.
>
> Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
This is already upstream, commit f10b1fc0161cd99e ("mailbox: change
mailbox-mpfs compatible string").
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 27+ messages in thread
* Re: [PATCH v3 03/15] mailbox: change mailbox-mpfs compatible string
2022-01-14 15:40 ` Geert Uytterhoeven
@ 2022-01-14 16:15 ` conor dooley
0 siblings, 0 replies; 27+ messages in thread
From: conor dooley @ 2022-01-14 16:15 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Conor Dooley, Linus Walleij, Bartosz Golaszewski, Rob Herring,
Jassi Brar, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Alessandro Zummo, Alexandre Belloni, Mark Brown, Greg KH,
Thierry Reding, Uwe Kleine-König, Lee Jones,
open list:GPIO SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Linux Kernel Mailing List, Linux I2C, Linux PWM List,
linux-riscv, Linux Crypto Mailing List, linux-rtc, linux-spi,
USB list, Krzysztof Kozlowski, Bin Meng, Heiko Stuebner,
Lewis Hanly, daire.mcnamara, ivan.griffin, Atish Patra
> Hi Conor,
>
> On Fri, Jan 14, 2022 at 4:16 PM <conor.dooley@microchip.com> wrote:
> > From: Conor Dooley <conor.dooley@microchip.com>
> >
> > The Polarfire SoC is currently using two different compatible string
> > prefixes. Fix this by changing "polarfire-soc-*" strings to "mpfs-*" in
> > its system controller in order to match the compatible string used in
> > the soc binding and device tree.
> >
> > Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org>
> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>
> This is already upstream, commit f10b1fc0161cd99e ("mailbox: change
> mailbox-mpfs compatible string").
I would say great, but that means the new string is now in the driver
but the new dt-binding is not (and I just noticed contains an error).
Conor.
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
>
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v3 04/15] dt-bindings: i2c: add bindings for microchip mpfs i2c
2022-01-14 15:17 [PATCH v3 00/15] Update the Icicle Kit device tree conor.dooley
` (2 preceding siblings ...)
2022-01-14 15:17 ` [PATCH v3 03/15] mailbox: change mailbox-mpfs compatible string conor.dooley
@ 2022-01-14 15:17 ` conor.dooley
2022-01-15 17:22 ` Rob Herring
2022-01-14 15:17 ` [PATCH v3 05/15] dt-bindings: rtc: add bindings for microchip mpfs rtc conor.dooley
` (10 subsequent siblings)
14 siblings, 1 reply; 27+ messages in thread
From: conor.dooley @ 2022-01-14 15:17 UTC (permalink / raw)
To: linus.walleij, bgolaszewski, robh+dt, jassisinghbrar,
paul.walmsley, palmer, aou, a.zummo, alexandre.belloni, broonie,
gregkh, thierry.reding, u.kleine-koenig, lee.jones, linux-gpio,
devicetree, linux-kernel, linux-i2c, linux-pwm, linux-riscv,
linux-crypto, linux-rtc, linux-spi, linux-usb
Cc: krzysztof.kozlowski, geert, bin.meng, heiko, lewis.hanly,
conor.dooley, daire.mcnamara, ivan.griffin, atishp
From: Conor Dooley <conor.dooley@microchip.com>
Add device tree bindings for the i2c controller on
the Microchip PolarFire SoC.
Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/i2c/microchip,mpfs-i2c.yaml | 55 +++++++++++++++++++
1 file changed, 55 insertions(+)
create mode 100644 Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.yaml
diff --git a/Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.yaml b/Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.yaml
new file mode 100644
index 000000000000..ced843e78844
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/microchip,mpfs-i2c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip MPFS I2C Controller Device Tree Bindings
+
+maintainers:
+ - Daire McNamara <daire.mcnamara@microchip.com>
+
+allOf:
+ - $ref: /schemas/i2c/i2c-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - microchip,mpfs-i2c # Microchip PolarFire SoC compatible SoCs
+ - microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-frequency:
+ description: |
+ Desired I2C bus clock frequency in Hz. As only Standard and Fast
+ modes are supported, possible values are 100000 and 400000.
+ enum: [100000, 400000]
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/microchip,mpfs-clock.h>
+ i2c@2010a000 {
+ compatible = "microchip,mpfs-i2c";
+ reg = <0x2010a000 0x1000>;
+ clocks = <&clkcfg CLK_I2C0>;
+ interrupt-parent = <&plic>;
+ interrupts = <58>;
+ clock-frequency = <100000>;
+ };
+...
--
2.32.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH v3 04/15] dt-bindings: i2c: add bindings for microchip mpfs i2c
2022-01-14 15:17 ` [PATCH v3 04/15] dt-bindings: i2c: add bindings for microchip mpfs i2c conor.dooley
@ 2022-01-15 17:22 ` Rob Herring
0 siblings, 0 replies; 27+ messages in thread
From: Rob Herring @ 2022-01-15 17:22 UTC (permalink / raw)
To: conor.dooley
Cc: atishp, bgolaszewski, palmer, linux-rtc, linux-crypto,
thierry.reding, heiko, lee.jones, paul.walmsley, broonie, gregkh,
geert, devicetree, linus.walleij, ivan.griffin, linux-riscv,
linux-kernel, linux-pwm, linux-spi, u.kleine-koenig,
jassisinghbrar, aou, alexandre.belloni, linux-gpio, a.zummo,
krzysztof.kozlowski, daire.mcnamara, lewis.hanly, bin.meng,
robh+dt, linux-usb, linux-i2c
On Fri, 14 Jan 2022 15:17:16 +0000, conor.dooley@microchip.com wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> Add device tree bindings for the i2c controller on
> the Microchip PolarFire SoC.
>
> Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> .../bindings/i2c/microchip,mpfs-i2c.yaml | 55 +++++++++++++++++++
> 1 file changed, 55 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.example.dts:19:18: fatal error: dt-bindings/clock/microchip,mpfs-clock.h: No such file or directory
19 | #include <dt-bindings/clock/microchip,mpfs-clock.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:373: Documentation/devicetree/bindings/i2c/microchip,mpfs-i2c.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1413: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1580106
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v3 05/15] dt-bindings: rtc: add bindings for microchip mpfs rtc
2022-01-14 15:17 [PATCH v3 00/15] Update the Icicle Kit device tree conor.dooley
` (3 preceding siblings ...)
2022-01-14 15:17 ` [PATCH v3 04/15] dt-bindings: i2c: add bindings for microchip mpfs i2c conor.dooley
@ 2022-01-14 15:17 ` conor.dooley
2022-01-15 17:22 ` Rob Herring
2022-01-14 15:17 ` [PATCH v3 06/15] dt-bindings: gpio: add bindings for microchip mpfs gpio conor.dooley
` (9 subsequent siblings)
14 siblings, 1 reply; 27+ messages in thread
From: conor.dooley @ 2022-01-14 15:17 UTC (permalink / raw)
To: linus.walleij, bgolaszewski, robh+dt, jassisinghbrar,
paul.walmsley, palmer, aou, a.zummo, alexandre.belloni, broonie,
gregkh, thierry.reding, u.kleine-koenig, lee.jones, linux-gpio,
devicetree, linux-kernel, linux-i2c, linux-pwm, linux-riscv,
linux-crypto, linux-rtc, linux-spi, linux-usb
Cc: krzysztof.kozlowski, geert, bin.meng, heiko, lewis.hanly,
conor.dooley, daire.mcnamara, ivan.griffin, atishp
From: Conor Dooley <conor.dooley@microchip.com>
Add device tree bindings for the real time clock on
the Microchip PolarFire SoC.
Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/rtc/microchip,mfps-rtc.yaml | 63 +++++++++++++++++++
1 file changed, 63 insertions(+)
create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
diff --git a/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
new file mode 100644
index 000000000000..d57460cbe5e3
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml#
+
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip PolarFire Soc (MPFS) RTC Device Tree Bindings
+
+allOf:
+ - $ref: rtc.yaml#
+
+maintainers:
+ - Daire McNamara <daire.mcnamara@microchip.com>
+ - Lewis Hanly <lewis.hanly@microchip.com>
+
+properties:
+ compatible:
+ enum:
+ - microchip,mpfs-rtc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 2
+
+ microchip,prescaler:
+ description: |
+ The prescaler divides the input frequency to create a time-based strobe (typically 1 Hz) for
+ the calendar counter. The Alarm and Compare Registers, in conjunction with the calendar
+ counter, facilitate time-matched events. To properly operate in Calendar or Binary mode,
+ the 26-bit prescaler must be programmed to generate a strobe to the RTC.
+ maxItems: 1
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: rtc
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/microchip,mpfs-clock.h>
+ rtc@20124000 {
+ compatible = "microchip,mpfs-rtc";
+ reg = <0x20124000 0x1000>;
+ clocks = <&clkcfg CLK_RTC>;
+ clock-names = "rtc";
+ interrupts = <80>, <81>;
+ };
+...
--
2.32.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH v3 05/15] dt-bindings: rtc: add bindings for microchip mpfs rtc
2022-01-14 15:17 ` [PATCH v3 05/15] dt-bindings: rtc: add bindings for microchip mpfs rtc conor.dooley
@ 2022-01-15 17:22 ` Rob Herring
0 siblings, 0 replies; 27+ messages in thread
From: Rob Herring @ 2022-01-15 17:22 UTC (permalink / raw)
To: conor.dooley
Cc: alexandre.belloni, linux-i2c, geert, daire.mcnamara, aou,
a.zummo, bin.meng, thierry.reding, linux-spi, u.kleine-koenig,
linux-gpio, lee.jones, lewis.hanly, heiko, linux-crypto, robh+dt,
palmer, linux-rtc, ivan.griffin, atishp, linus.walleij, gregkh,
linux-usb, krzysztof.kozlowski, broonie, linux-pwm,
paul.walmsley, bgolaszewski, linux-kernel, jassisinghbrar,
devicetree, linux-riscv
On Fri, 14 Jan 2022 15:17:17 +0000, conor.dooley@microchip.com wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> Add device tree bindings for the real time clock on
> the Microchip PolarFire SoC.
>
> Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> .../bindings/rtc/microchip,mfps-rtc.yaml | 63 +++++++++++++++++++
> 1 file changed, 63 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.example.dts:19:18: fatal error: dt-bindings/clock/microchip,mpfs-clock.h: No such file or directory
19 | #include <dt-bindings/clock/microchip,mpfs-clock.h>
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:373: Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1413: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1580112
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v3 06/15] dt-bindings: gpio: add bindings for microchip mpfs gpio
2022-01-14 15:17 [PATCH v3 00/15] Update the Icicle Kit device tree conor.dooley
` (4 preceding siblings ...)
2022-01-14 15:17 ` [PATCH v3 05/15] dt-bindings: rtc: add bindings for microchip mpfs rtc conor.dooley
@ 2022-01-14 15:17 ` conor.dooley
2022-01-15 17:22 ` Rob Herring
2022-01-14 15:17 ` [PATCH v3 07/15] dt-bindings: spi: add bindings for microchip mpfs spi conor.dooley
` (8 subsequent siblings)
14 siblings, 1 reply; 27+ messages in thread
From: conor.dooley @ 2022-01-14 15:17 UTC (permalink / raw)
To: linus.walleij, bgolaszewski, robh+dt, jassisinghbrar,
paul.walmsley, palmer, aou, a.zummo, alexandre.belloni, broonie,
gregkh, thierry.reding, u.kleine-koenig, lee.jones, linux-gpio,
devicetree, linux-kernel, linux-i2c, linux-pwm, linux-riscv,
linux-crypto, linux-rtc, linux-spi, linux-usb
Cc: krzysztof.kozlowski, geert, bin.meng, heiko, lewis.hanly,
conor.dooley, daire.mcnamara, ivan.griffin, atishp
From: Conor Dooley <conor.dooley@microchip.com>
Add device tree bindings for the gpio controller on
the Microchip PolarFire SoC.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/gpio/microchip,mpfs-gpio.yaml | 80 +++++++++++++++++++
1 file changed, 80 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
diff --git a/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
new file mode 100644
index 000000000000..47a76f0e32b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/microchip,mpfs-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip MPFS GPIO Controller Device Tree Bindings
+
+maintainers:
+ - Conor Dooley <conor.dooley@microchip.com>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - microchip,mpfs-gpio
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description:
+ Interrupt mapping, one per GPIO. Maximum 32 GPIOs.
+ minItems: 1
+ maxItems: 32
+
+ interrupt-controller: true
+
+ clocks:
+ maxItems: 1
+
+ "#gpio-cells":
+ const: 2
+
+ "#interrupt-cells":
+ const: 1
+
+ ngpios:
+ description:
+ The number of GPIOs available.
+ minimum: 1
+ maximum: 32
+ default: 32
+
+ gpio-controller: true
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#interrupt-cells"
+ - interrupt-controller
+ - "#gpio-cells"
+ - gpio-controller
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include "dt-bindings/clock/microchip,mpfs-clock.h"
+ gpio@20122000 {
+ compatible = "microchip,mpfs-gpio";
+ reg = <0x20122000 0x1000>;
+ clocks = <&clkcfg CLK_GPIO2>;
+ interrupt-parent = <&plic>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupts = <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>;
+ };
+...
--
2.32.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH v3 06/15] dt-bindings: gpio: add bindings for microchip mpfs gpio
2022-01-14 15:17 ` [PATCH v3 06/15] dt-bindings: gpio: add bindings for microchip mpfs gpio conor.dooley
@ 2022-01-15 17:22 ` Rob Herring
0 siblings, 0 replies; 27+ messages in thread
From: Rob Herring @ 2022-01-15 17:22 UTC (permalink / raw)
To: conor.dooley
Cc: linus.walleij, heiko, linux-usb, linux-gpio, aou, linux-spi,
linux-kernel, atishp, bgolaszewski, palmer, a.zummo,
ivan.griffin, u.kleine-koenig, devicetree, daire.mcnamara,
thierry.reding, bin.meng, robh+dt, lewis.hanly, lee.jones,
linux-crypto, linux-pwm, jassisinghbrar, linux-riscv, geert,
linux-rtc, krzysztof.kozlowski, paul.walmsley, alexandre.belloni,
linux-i2c, broonie, gregkh
On Fri, 14 Jan 2022 15:17:18 +0000, conor.dooley@microchip.com wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> Add device tree bindings for the gpio controller on
> the Microchip PolarFire SoC.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> .../bindings/gpio/microchip,mpfs-gpio.yaml | 80 +++++++++++++++++++
> 1 file changed, 80 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.example.dts:19:18: fatal error: dt-bindings/clock/microchip,mpfs-clock.h: No such file or directory
19 | #include "dt-bindings/clock/microchip,mpfs-clock.h"
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:373: Documentation/devicetree/bindings/gpio/microchip,mpfs-gpio.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1413: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1580118
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v3 07/15] dt-bindings: spi: add bindings for microchip mpfs spi
2022-01-14 15:17 [PATCH v3 00/15] Update the Icicle Kit device tree conor.dooley
` (5 preceding siblings ...)
2022-01-14 15:17 ` [PATCH v3 06/15] dt-bindings: gpio: add bindings for microchip mpfs gpio conor.dooley
@ 2022-01-14 15:17 ` conor.dooley
2022-01-15 17:22 ` Rob Herring
2022-01-14 15:17 ` [PATCH v3 08/15] dt-bindings: usb: add bindings for microchip mpfs musb conor.dooley
` (7 subsequent siblings)
14 siblings, 1 reply; 27+ messages in thread
From: conor.dooley @ 2022-01-14 15:17 UTC (permalink / raw)
To: linus.walleij, bgolaszewski, robh+dt, jassisinghbrar,
paul.walmsley, palmer, aou, a.zummo, alexandre.belloni, broonie,
gregkh, thierry.reding, u.kleine-koenig, lee.jones, linux-gpio,
devicetree, linux-kernel, linux-i2c, linux-pwm, linux-riscv,
linux-crypto, linux-rtc, linux-spi, linux-usb
Cc: krzysztof.kozlowski, geert, bin.meng, heiko, lewis.hanly,
conor.dooley, daire.mcnamara, ivan.griffin, atishp
From: Conor Dooley <conor.dooley@microchip.com>
Add device tree bindings for the {q,}spi controller on
the Microchip PolarFire SoC.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/spi/microchip,mpfs-spi.yaml | 52 +++++++++++++++++++
1 file changed, 52 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
diff --git a/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
new file mode 100644
index 000000000000..ece261b8e963
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/microchip,mpfs-spi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip MPFS {Q,}SPI Controller Device Tree Bindings
+
+maintainers:
+ - Conor Dooley <conor.dooley@microchip.com>
+
+allOf:
+ - $ref: spi-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - microchip,mpfs-spi
+ - microchip,mpfs-qspi
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clock-names:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include "dt-bindings/clock/microchip,mpfs-clock.h"
+ spi@20108000 {
+ compatible = "microchip,mpfs-spi";
+ reg = <0x20108000 0x1000>;
+ clocks = <&clkcfg CLK_SPI0>;
+ interrupt-parent = <&plic>;
+ interrupts = <54>;
+ spi-max-frequency = <25000000>;
+ };
+...
--
2.32.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH v3 07/15] dt-bindings: spi: add bindings for microchip mpfs spi
2022-01-14 15:17 ` [PATCH v3 07/15] dt-bindings: spi: add bindings for microchip mpfs spi conor.dooley
@ 2022-01-15 17:22 ` Rob Herring
0 siblings, 0 replies; 27+ messages in thread
From: Rob Herring @ 2022-01-15 17:22 UTC (permalink / raw)
To: conor.dooley
Cc: aou, paul.walmsley, linux-spi, linux-crypto, jassisinghbrar,
palmer, linux-riscv, linux-rtc, devicetree, linux-kernel,
ivan.griffin, thierry.reding, gregkh, heiko, robh+dt,
alexandre.belloni, linux-pwm, linux-i2c, lewis.hanly,
daire.mcnamara, broonie, linus.walleij, lee.jones, linux-usb,
geert, atishp, krzysztof.kozlowski, linux-gpio, bin.meng,
bgolaszewski, u.kleine-koenig, a.zummo
On Fri, 14 Jan 2022 15:17:19 +0000, conor.dooley@microchip.com wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> Add device tree bindings for the {q,}spi controller on
> the Microchip PolarFire SoC.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> .../bindings/spi/microchip,mpfs-spi.yaml | 52 +++++++++++++++++++
> 1 file changed, 52 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/spi/microchip,mpfs-spi.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/spi/microchip,mpfs-spi.example.dts:19:18: fatal error: dt-bindings/clock/microchip,mpfs-clock.h: No such file or directory
19 | #include "dt-bindings/clock/microchip,mpfs-clock.h"
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:373: Documentation/devicetree/bindings/spi/microchip,mpfs-spi.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1413: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1580121
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v3 08/15] dt-bindings: usb: add bindings for microchip mpfs musb
2022-01-14 15:17 [PATCH v3 00/15] Update the Icicle Kit device tree conor.dooley
` (6 preceding siblings ...)
2022-01-14 15:17 ` [PATCH v3 07/15] dt-bindings: spi: add bindings for microchip mpfs spi conor.dooley
@ 2022-01-14 15:17 ` conor.dooley
2022-01-15 17:22 ` Rob Herring
2022-01-14 15:17 ` [PATCH v3 09/15] dt-bindings: pwm: add microchip corepwm binding conor.dooley
` (6 subsequent siblings)
14 siblings, 1 reply; 27+ messages in thread
From: conor.dooley @ 2022-01-14 15:17 UTC (permalink / raw)
To: linus.walleij, bgolaszewski, robh+dt, jassisinghbrar,
paul.walmsley, palmer, aou, a.zummo, alexandre.belloni, broonie,
gregkh, thierry.reding, u.kleine-koenig, lee.jones, linux-gpio,
devicetree, linux-kernel, linux-i2c, linux-pwm, linux-riscv,
linux-crypto, linux-rtc, linux-spi, linux-usb
Cc: krzysztof.kozlowski, geert, bin.meng, heiko, lewis.hanly,
conor.dooley, daire.mcnamara, ivan.griffin, atishp
From: Conor Dooley <conor.dooley@microchip.com>
Add device tree bindings for the usb controller on
the Microchip PolarFire SoC.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/usb/microchip,mpfs-musb.yaml | 59 +++++++++++++++++++
1 file changed, 59 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml
diff --git a/Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml b/Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml
new file mode 100644
index 000000000000..48c458c65848
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/microchip,mpfs-musb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip MPFS USB Controller Device Tree Bindings
+
+allOf:
+ - $ref: usb-drd.yaml#
+
+maintainers:
+ - Conor Dooley <conor.dooley@microchip.com>
+
+properties:
+ compatible:
+ enum:
+ - microchip,mpfs-musb
+
+ dr_mode: true
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 2
+ maxItems: 2
+
+ interrupt-names:
+ items:
+ - const: dma
+ - const: mc
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - interrupt-names
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include "dt-bindings/clock/microchip,mpfs-clock.h"
+ usb@20201000 {
+ compatible = "microchip,mpfs-musb";
+ reg = <0x20201000 0x1000>;
+ clocks = <&clkcfg CLK_USB>;
+ interrupt-parent = <&plic>;
+ interrupts = <86>, <87>;
+ interrupt-names = "dma", "mc";
+ dr_mode = "host";
+ };
+
+...
--
2.32.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH v3 08/15] dt-bindings: usb: add bindings for microchip mpfs musb
2022-01-14 15:17 ` [PATCH v3 08/15] dt-bindings: usb: add bindings for microchip mpfs musb conor.dooley
@ 2022-01-15 17:22 ` Rob Herring
0 siblings, 0 replies; 27+ messages in thread
From: Rob Herring @ 2022-01-15 17:22 UTC (permalink / raw)
To: conor.dooley
Cc: linux-pwm, palmer, a.zummo, krzysztof.kozlowski, heiko, robh+dt,
bin.meng, linux-kernel, lee.jones, aou, linux-riscv,
thierry.reding, geert, atishp, daire.mcnamara, linux-crypto,
linux-i2c, lewis.hanly, alexandre.belloni, linux-gpio, broonie,
linux-rtc, ivan.griffin, linus.walleij, paul.walmsley,
bgolaszewski, gregkh, u.kleine-koenig, linux-usb, linux-spi,
jassisinghbrar, devicetree
On Fri, 14 Jan 2022 15:17:20 +0000, conor.dooley@microchip.com wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> Add device tree bindings for the usb controller on
> the Microchip PolarFire SoC.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> .../bindings/usb/microchip,mpfs-musb.yaml | 59 +++++++++++++++++++
> 1 file changed, 59 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/usb/microchip,mpfs-musb.example.dts:19:18: fatal error: dt-bindings/clock/microchip,mpfs-clock.h: No such file or directory
19 | #include "dt-bindings/clock/microchip,mpfs-clock.h"
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:373: Documentation/devicetree/bindings/usb/microchip,mpfs-musb.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1413: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1580122
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v3 09/15] dt-bindings: pwm: add microchip corepwm binding
2022-01-14 15:17 [PATCH v3 00/15] Update the Icicle Kit device tree conor.dooley
` (7 preceding siblings ...)
2022-01-14 15:17 ` [PATCH v3 08/15] dt-bindings: usb: add bindings for microchip mpfs musb conor.dooley
@ 2022-01-14 15:17 ` conor.dooley
2022-01-15 17:22 ` Rob Herring
2022-01-14 15:17 ` [PATCH v3 10/15] riscv: dts: microchip: use clk defines for icicle kit conor.dooley
` (5 subsequent siblings)
14 siblings, 1 reply; 27+ messages in thread
From: conor.dooley @ 2022-01-14 15:17 UTC (permalink / raw)
To: linus.walleij, bgolaszewski, robh+dt, jassisinghbrar,
paul.walmsley, palmer, aou, a.zummo, alexandre.belloni, broonie,
gregkh, thierry.reding, u.kleine-koenig, lee.jones, linux-gpio,
devicetree, linux-kernel, linux-i2c, linux-pwm, linux-riscv,
linux-crypto, linux-rtc, linux-spi, linux-usb
Cc: krzysztof.kozlowski, geert, bin.meng, heiko, lewis.hanly,
conor.dooley, daire.mcnamara, ivan.griffin, atishp
From: Conor Dooley <conor.dooley@microchip.com>
Add device tree bindings for the Microchip fpga fabric based "core" PWM controller.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../bindings/pwm/microchip,corepwm.yaml | 75 +++++++++++++++++++
1 file changed, 75 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
diff --git a/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
new file mode 100644
index 000000000000..26a77cde2465
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/microchip,corepwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip ip core PWM controller bindings
+
+maintainers:
+ - Conor Dooley <conor.dooley@microchip.com>
+
+description: |
+ corePWM is an 16 channel pulse width modulator FPGA IP
+
+ https://www.microsemi.com/existing-parts/parts/152118
+
+properties:
+ compatible:
+ items:
+ - const: microchip,corepwm-rtl-v4
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ "#pwm-cells":
+ const: 2
+
+ microchip,sync-update:
+ description: |
+ In synchronous mode, all channels are updated at the beginning of the PWM period.
+ Asynchronous mode is relevant to applications such as LED control, where
+ synchronous updates are not required. Asynchronous mode lowers the area size,
+ reducing shadow register requirements. This can be set at run time, provided
+ SHADOW_REG_EN is asserted. SHADOW_REG_EN is set by the FPGA bitstream programmed
+ to the device.
+ Each bit corresponds to a PWM channel & represents whether synchronous mode is
+ possible for the PWM channel.
+
+ $ref: /schemas/types.yaml#/definitions/uint16
+ default: 0
+
+ microchip,dac-mode:
+ description: |
+ Optional, per-channel Low Ripple DAC mode is possible on this IP core. It creates
+ a minimum period pulse train whose High/Low average is that of the chosen duty
+ cycle. This "DAC" will have far better bandwidth and ripple performance than the
+ standard PWM algorithm can achieve.
+ Each bit corresponds to a PWM channel & represents whether dac mode is enabled
+ that PWM channel.
+
+ $ref: /schemas/types.yaml#/definitions/uint16
+ default: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - "#pwm-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include "dt-bindings/clock/microchip,mpfs-clock.h"
+ pwm@41000000 {
+ compatible = "microchip,corepwm-rtl-v4";
+ microchip,sync-update = /bits/ 16 <0>;
+ clocks = <&clkcfg CLK_FIC3>;
+ reg = <0x41000000 0xF0>;
+ #pwm-cells = <2>;
+ };
--
2.32.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH v3 09/15] dt-bindings: pwm: add microchip corepwm binding
2022-01-14 15:17 ` [PATCH v3 09/15] dt-bindings: pwm: add microchip corepwm binding conor.dooley
@ 2022-01-15 17:22 ` Rob Herring
0 siblings, 0 replies; 27+ messages in thread
From: Rob Herring @ 2022-01-15 17:22 UTC (permalink / raw)
To: conor.dooley
Cc: heiko, daire.mcnamara, palmer, bgolaszewski, alexandre.belloni,
linux-pwm, bin.meng, linux-riscv, robh+dt, atishp, broonie,
lee.jones, linux-gpio, thierry.reding, linux-spi, ivan.griffin,
gregkh, linux-crypto, lewis.hanly, u.kleine-koenig,
jassisinghbrar, krzysztof.kozlowski, a.zummo, linux-usb,
paul.walmsley, linux-rtc, geert, linus.walleij, linux-i2c,
linux-kernel, aou, devicetree
On Fri, 14 Jan 2022 15:17:21 +0000, conor.dooley@microchip.com wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> Add device tree bindings for the Microchip fpga fabric based "core" PWM controller.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> .../bindings/pwm/microchip,corepwm.yaml | 75 +++++++++++++++++++
> 1 file changed, 75 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pwm/microchip,corepwm.yaml
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Documentation/devicetree/bindings/pwm/microchip,corepwm.example.dts:19:18: fatal error: dt-bindings/clock/microchip,mpfs-clock.h: No such file or directory
19 | #include "dt-bindings/clock/microchip,mpfs-clock.h"
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
make[1]: *** [scripts/Makefile.lib:373: Documentation/devicetree/bindings/pwm/microchip,corepwm.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1413: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/1580131
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v3 10/15] riscv: dts: microchip: use clk defines for icicle kit
2022-01-14 15:17 [PATCH v3 00/15] Update the Icicle Kit device tree conor.dooley
` (8 preceding siblings ...)
2022-01-14 15:17 ` [PATCH v3 09/15] dt-bindings: pwm: add microchip corepwm binding conor.dooley
@ 2022-01-14 15:17 ` conor.dooley
2022-01-14 15:17 ` [PATCH v3 11/15] riscv: dts: microchip: add fpga fabric section to " conor.dooley
` (4 subsequent siblings)
14 siblings, 0 replies; 27+ messages in thread
From: conor.dooley @ 2022-01-14 15:17 UTC (permalink / raw)
To: linus.walleij, bgolaszewski, robh+dt, jassisinghbrar,
paul.walmsley, palmer, aou, a.zummo, alexandre.belloni, broonie,
gregkh, thierry.reding, u.kleine-koenig, lee.jones, linux-gpio,
devicetree, linux-kernel, linux-i2c, linux-pwm, linux-riscv,
linux-crypto, linux-rtc, linux-spi, linux-usb
Cc: krzysztof.kozlowski, geert, bin.meng, heiko, lewis.hanly,
conor.dooley, daire.mcnamara, ivan.griffin, atishp
From: Conor Dooley <conor.dooley@microchip.com>
Update the Microchip Icicle kit device tree by replacing clock
related magic numbers with their defined counterparts.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../microchip/microchip-mpfs-icicle-kit.dts | 2 +-
.../boot/dts/microchip/microchip-mpfs.dtsi | 25 ++++++++++---------
2 files changed, 14 insertions(+), 13 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
index 0c748ae1b006..6d19ba196f12 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
@@ -31,7 +31,7 @@ cpus {
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x40000000>;
- clocks = <&clkcfg 26>;
+ clocks = <&clkcfg CLK_DDRC>;
};
};
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index 869aaf0d5c06..717e39b30a15 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -2,6 +2,7 @@
/* Copyright (c) 2020 Microchip Technology Inc */
/dts-v1/;
+#include "dt-bindings/clock/microchip,mpfs-clock.h"
/ {
#address-cells = <2>;
@@ -14,7 +15,6 @@ cpus {
#size-cells = <0>;
cpu@0 {
- clock-frequency = <0>;
compatible = "sifive,e51", "sifive,rocket0", "riscv";
device_type = "cpu";
i-cache-block-size = <64>;
@@ -22,6 +22,7 @@ cpu@0 {
i-cache-size = <16384>;
reg = <0>;
riscv,isa = "rv64imac";
+ clocks = <&clkcfg CLK_CPU>;
status = "disabled";
cpu0_intc: interrupt-controller {
@@ -32,7 +33,6 @@ cpu0_intc: interrupt-controller {
};
cpu@1 {
- clock-frequency = <0>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -48,6 +48,7 @@ cpu@1 {
mmu-type = "riscv,sv39";
reg = <1>;
riscv,isa = "rv64imafdc";
+ clocks = <&clkcfg CLK_CPU>;
tlb-split;
status = "okay";
@@ -59,7 +60,6 @@ cpu1_intc: interrupt-controller {
};
cpu@2 {
- clock-frequency = <0>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -75,6 +75,7 @@ cpu@2 {
mmu-type = "riscv,sv39";
reg = <2>;
riscv,isa = "rv64imafdc";
+ clocks = <&clkcfg CLK_CPU>;
tlb-split;
status = "okay";
@@ -86,7 +87,6 @@ cpu2_intc: interrupt-controller {
};
cpu@3 {
- clock-frequency = <0>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -102,6 +102,7 @@ cpu@3 {
mmu-type = "riscv,sv39";
reg = <3>;
riscv,isa = "rv64imafdc";
+ clocks = <&clkcfg CLK_CPU>;
tlb-split;
status = "okay";
@@ -113,7 +114,6 @@ cpu3_intc: interrupt-controller {
};
cpu@4 {
- clock-frequency = <0>;
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -129,6 +129,7 @@ cpu@4 {
mmu-type = "riscv,sv39";
reg = <4>;
riscv,isa = "rv64imafdc";
+ clocks = <&clkcfg CLK_CPU>;
tlb-split;
status = "okay";
cpu4_intc: interrupt-controller {
@@ -210,7 +211,7 @@ serial0: serial@20000000 {
interrupt-parent = <&plic>;
interrupts = <90>;
current-speed = <115200>;
- clocks = <&clkcfg 8>;
+ clocks = <&clkcfg CLK_MMUART0>;
status = "disabled";
};
@@ -222,7 +223,7 @@ serial1: serial@20100000 {
interrupt-parent = <&plic>;
interrupts = <91>;
current-speed = <115200>;
- clocks = <&clkcfg 9>;
+ clocks = <&clkcfg CLK_MMUART1>;
status = "disabled";
};
@@ -234,7 +235,7 @@ serial2: serial@20102000 {
interrupt-parent = <&plic>;
interrupts = <92>;
current-speed = <115200>;
- clocks = <&clkcfg 10>;
+ clocks = <&clkcfg CLK_MMUART2>;
status = "disabled";
};
@@ -246,7 +247,7 @@ serial3: serial@20104000 {
interrupt-parent = <&plic>;
interrupts = <93>;
current-speed = <115200>;
- clocks = <&clkcfg 11>;
+ clocks = <&clkcfg CLK_MMUART3>;
status = "disabled";
};
@@ -256,7 +257,7 @@ mmc: mmc@20008000 {
reg = <0x0 0x20008000 0x0 0x1000>;
interrupt-parent = <&plic>;
interrupts = <88>, <89>;
- clocks = <&clkcfg 6>;
+ clocks = <&clkcfg CLK_MMC>;
max-frequency = <200000000>;
status = "disabled";
};
@@ -267,7 +268,7 @@ emac0: ethernet@20110000 {
interrupt-parent = <&plic>;
interrupts = <64>, <65>, <66>, <67>;
local-mac-address = [00 00 00 00 00 00];
- clocks = <&clkcfg 4>, <&clkcfg 2>;
+ clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
clock-names = "pclk", "hclk";
status = "disabled";
#address-cells = <1>;
@@ -280,7 +281,7 @@ emac1: ethernet@20112000 {
interrupt-parent = <&plic>;
interrupts = <70>, <71>, <72>, <73>;
local-mac-address = [00 00 00 00 00 00];
- clocks = <&clkcfg 5>, <&clkcfg 2>;
+ clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
status = "disabled";
clock-names = "pclk", "hclk";
#address-cells = <1>;
--
2.32.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v3 11/15] riscv: dts: microchip: add fpga fabric section to icicle kit
2022-01-14 15:17 [PATCH v3 00/15] Update the Icicle Kit device tree conor.dooley
` (9 preceding siblings ...)
2022-01-14 15:17 ` [PATCH v3 10/15] riscv: dts: microchip: use clk defines for icicle kit conor.dooley
@ 2022-01-14 15:17 ` conor.dooley
2022-01-14 15:17 ` [PATCH v3 12/15] riscv: dts: microchip: refactor icicle kit device tree conor.dooley
` (3 subsequent siblings)
14 siblings, 0 replies; 27+ messages in thread
From: conor.dooley @ 2022-01-14 15:17 UTC (permalink / raw)
To: linus.walleij, bgolaszewski, robh+dt, jassisinghbrar,
paul.walmsley, palmer, aou, a.zummo, alexandre.belloni, broonie,
gregkh, thierry.reding, u.kleine-koenig, lee.jones, linux-gpio,
devicetree, linux-kernel, linux-i2c, linux-pwm, linux-riscv,
linux-crypto, linux-rtc, linux-spi, linux-usb
Cc: krzysztof.kozlowski, geert, bin.meng, heiko, lewis.hanly,
conor.dooley, daire.mcnamara, ivan.griffin, atishp
From: Conor Dooley <conor.dooley@microchip.com>
Split the device tree for the Microchip MPFS into two sections by adding
microchip-mpfs-fabric.dtsi, which contains peripherals contained in the
FPGA fabric.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../dts/microchip/microchip-mpfs-fabric.dtsi | 25 +++++++++++++++++++
.../microchip/microchip-mpfs-icicle-kit.dts | 8 ++++++
.../boot/dts/microchip/microchip-mpfs.dtsi | 1 +
3 files changed, 34 insertions(+)
create mode 100644 arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
new file mode 100644
index 000000000000..c1dcd56b0679
--- /dev/null
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/* Copyright (c) 2020-2021 Microchip Technology Inc */
+
+/ {
+ core_pwm0: pwm@41000000 {
+ compatible = "microchip,corepwm-rtl-v4";
+ reg = <0x0 0x41000000 0x0 0xF0>;
+ microchip,sync-update = /bits/ 16 <0>;
+ #pwm-cells = <2>;
+ clocks = <&clkcfg CLK_FIC3>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@44000000 {
+ compatible = "microchip,corei2c-rtl-v7";
+ reg = <0x0 0x44000000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clkcfg CLK_FIC3>;
+ interrupt-parent = <&plic>;
+ interrupts = <122>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+};
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
index 6d19ba196f12..ab803f71626a 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
@@ -68,6 +68,10 @@ &mmc {
sd-uhs-sdr104;
};
+&i2c2 {
+ status = "okay";
+};
+
&emac0 {
phy-mode = "sgmii";
phy-handle = <&phy0>;
@@ -86,3 +90,7 @@ phy1: ethernet-phy@9 {
ti,fifo-depth = <0x01>;
};
};
+
+&core_pwm0 {
+ status = "okay";
+};
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index 717e39b30a15..c7d73756c9b8 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -3,6 +3,7 @@
/dts-v1/;
#include "dt-bindings/clock/microchip,mpfs-clock.h"
+#include "microchip-mpfs-fabric.dtsi"
/ {
#address-cells = <2>;
--
2.32.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v3 12/15] riscv: dts: microchip: refactor icicle kit device tree
2022-01-14 15:17 [PATCH v3 00/15] Update the Icicle Kit device tree conor.dooley
` (10 preceding siblings ...)
2022-01-14 15:17 ` [PATCH v3 11/15] riscv: dts: microchip: add fpga fabric section to " conor.dooley
@ 2022-01-14 15:17 ` conor.dooley
2022-01-14 15:17 ` [PATCH v3 13/15] riscv: dts: microchip: update peripherals in " conor.dooley
` (2 subsequent siblings)
14 siblings, 0 replies; 27+ messages in thread
From: conor.dooley @ 2022-01-14 15:17 UTC (permalink / raw)
To: linus.walleij, bgolaszewski, robh+dt, jassisinghbrar,
paul.walmsley, palmer, aou, a.zummo, alexandre.belloni, broonie,
gregkh, thierry.reding, u.kleine-koenig, lee.jones, linux-gpio,
devicetree, linux-kernel, linux-i2c, linux-pwm, linux-riscv,
linux-crypto, linux-rtc, linux-spi, linux-usb
Cc: krzysztof.kozlowski, geert, bin.meng, heiko, lewis.hanly,
conor.dooley, daire.mcnamara, ivan.griffin, atishp
From: Conor Dooley <conor.dooley@microchip.com>
Assorted minor changes to the MPFS/Icicle kit device tree:
- rename serial to mmuart to match microchip documentation
- move phy0 inside mac1 node to match phy configuration
- add labels where missing (cpus, cache controller)
- add missing address cells & interrupts to MACs
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../microchip/microchip-mpfs-icicle-kit.dts | 37 ++---
.../boot/dts/microchip/microchip-mpfs.dtsi | 65 +++++----
arch/riscv/configs/icicle_kit_defconfig | 134 ++++++++++++++++++
3 files changed, 186 insertions(+), 50 deletions(-)
create mode 100644 arch/riscv/configs/icicle_kit_defconfig
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
index ab803f71626a..c51bd7cf500f 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/* Copyright (c) 2020 Microchip Technology Inc */
+/* Copyright (c) 2020-2021 Microchip Technology Inc */
/dts-v1/;
@@ -13,11 +13,11 @@ / {
compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs";
aliases {
- ethernet0 = &emac1;
- serial0 = &serial0;
- serial1 = &serial1;
- serial2 = &serial2;
- serial3 = &serial3;
+ ethernet0 = &mac1;
+ serial0 = &mmuart0;
+ serial1 = &mmuart1;
+ serial2 = &mmuart2;
+ serial3 = &mmuart3;
};
chosen {
@@ -39,19 +39,19 @@ &refclk {
clock-frequency = <600000000>;
};
-&serial0 {
+&mmuart0 {
status = "okay";
};
-&serial1 {
+&mmuart1 {
status = "okay";
};
-&serial2 {
+&mmuart2 {
status = "okay";
};
-&serial3 {
+&mmuart3 {
status = "okay";
};
@@ -61,7 +61,10 @@ &mmc {
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
+ cap-mmc-highspeed;
card-detect-delay = <200>;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
@@ -72,22 +75,22 @@ &i2c2 {
status = "okay";
};
-&emac0 {
+&mac0 {
phy-mode = "sgmii";
phy-handle = <&phy0>;
- phy0: ethernet-phy@8 {
- reg = <8>;
- ti,fifo-depth = <0x01>;
- };
};
-&emac1 {
+&mac1 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&phy1>;
phy1: ethernet-phy@9 {
reg = <9>;
- ti,fifo-depth = <0x01>;
+ ti,fifo-depth = <0x1>;
+ };
+ phy0: ethernet-phy@8 {
+ reg = <8>;
+ ti,fifo-depth = <0x1>;
};
};
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index c7d73756c9b8..62bd00092bcc 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -1,5 +1,5 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/* Copyright (c) 2020 Microchip Technology Inc */
+/* Copyright (c) 2020-2021 Microchip Technology Inc */
/dts-v1/;
#include "dt-bindings/clock/microchip,mpfs-clock.h"
@@ -15,7 +15,7 @@ cpus {
#address-cells = <1>;
#size-cells = <0>;
- cpu@0 {
+ cpu0: cpu@0 {
compatible = "sifive,e51", "sifive,rocket0", "riscv";
device_type = "cpu";
i-cache-block-size = <64>;
@@ -33,7 +33,7 @@ cpu0_intc: interrupt-controller {
};
};
- cpu@1 {
+ cpu1: cpu@1 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -60,7 +60,7 @@ cpu1_intc: interrupt-controller {
};
};
- cpu@2 {
+ cpu2: cpu@2 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -87,7 +87,7 @@ cpu2_intc: interrupt-controller {
};
};
- cpu@3 {
+ cpu3: cpu@3 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -114,7 +114,7 @@ cpu3_intc: interrupt-controller {
};
};
- cpu@4 {
+ cpu4: cpu@4 {
compatible = "sifive,u54-mc", "sifive,rocket0", "riscv";
d-cache-block-size = <64>;
d-cache-sets = <64>;
@@ -152,8 +152,9 @@ soc {
compatible = "simple-bus";
ranges;
- cache-controller@2010000 {
+ cctrllr: cache-controller@2010000 {
compatible = "sifive,fu540-c000-ccache", "cache";
+ reg = <0x0 0x2010000 0x0 0x1000>;
cache-block-size = <64>;
cache-level = <2>;
cache-sets = <1024>;
@@ -161,10 +162,9 @@ cache-controller@2010000 {
cache-unified;
interrupt-parent = <&plic>;
interrupts = <1>, <2>, <3>;
- reg = <0x0 0x2010000 0x0 0x1000>;
};
- clint@2000000 {
+ clint: clint@2000000 {
compatible = "sifive,fu540-c000-clint", "sifive,clint0";
reg = <0x0 0x2000000 0x0 0xC000>;
interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
@@ -174,6 +174,15 @@ clint@2000000 {
<&cpu4_intc 3>, <&cpu4_intc 7>;
};
+ dma@3000000 {
+ compatible = "sifive,fu540-c000-pdma";
+ reg = <0x0 0x3000000 0x0 0x8000>;
+ interrupt-parent = <&plic>;
+ interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
+ <30>;
+ #dma-cells = <1>;
+ };
+
plic: interrupt-controller@c000000 {
compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
reg = <0x0 0xc000000 0x0 0x4000000>;
@@ -188,15 +197,6 @@ plic: interrupt-controller@c000000 {
riscv,ndev = <186>;
};
- dma@3000000 {
- compatible = "sifive,fu540-c000-pdma";
- reg = <0x0 0x3000000 0x0 0x8000>;
- interrupt-parent = <&plic>;
- interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
- <30>;
- #dma-cells = <1>;
- };
-
clkcfg: clkcfg@20002000 {
compatible = "microchip,mpfs-clkcfg";
reg = <0x0 0x20002000 0x0 0x1000>;
@@ -204,7 +204,7 @@ clkcfg: clkcfg@20002000 {
#clock-cells = <1>;
};
- serial0: serial@20000000 {
+ mmuart0: serial@20000000 {
compatible = "ns16550a";
reg = <0x0 0x20000000 0x0 0x400>;
reg-io-width = <4>;
@@ -216,7 +216,7 @@ serial0: serial@20000000 {
status = "disabled";
};
- serial1: serial@20100000 {
+ mmuart1: serial@20100000 {
compatible = "ns16550a";
reg = <0x0 0x20100000 0x0 0x400>;
reg-io-width = <4>;
@@ -228,7 +228,7 @@ serial1: serial@20100000 {
status = "disabled";
};
- serial2: serial@20102000 {
+ mmuart2: serial@20102000 {
compatible = "ns16550a";
reg = <0x0 0x20102000 0x0 0x400>;
reg-io-width = <4>;
@@ -240,7 +240,7 @@ serial2: serial@20102000 {
status = "disabled";
};
- serial3: serial@20104000 {
+ mmuart3: serial@20104000 {
compatible = "ns16550a";
reg = <0x0 0x20104000 0x0 0x400>;
reg-io-width = <4>;
@@ -257,37 +257,36 @@ mmc: mmc@20008000 {
compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";
reg = <0x0 0x20008000 0x0 0x1000>;
interrupt-parent = <&plic>;
- interrupts = <88>, <89>;
+ interrupts = <88>;
clocks = <&clkcfg CLK_MMC>;
max-frequency = <200000000>;
status = "disabled";
};
- emac0: ethernet@20110000 {
+ mac0: ethernet@20110000 {
compatible = "cdns,macb";
reg = <0x0 0x20110000 0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
interrupt-parent = <&plic>;
- interrupts = <64>, <65>, <66>, <67>;
+ interrupts = <64>, <65>, <66>, <67>, <68>, <69>;
local-mac-address = [00 00 00 00 00 00];
clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
clock-names = "pclk", "hclk";
status = "disabled";
- #address-cells = <1>;
- #size-cells = <0>;
};
- emac1: ethernet@20112000 {
+ mac1: ethernet@20112000 {
compatible = "cdns,macb";
reg = <0x0 0x20112000 0x0 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
interrupt-parent = <&plic>;
- interrupts = <70>, <71>, <72>, <73>;
+ interrupts = <70>, <71>, <72>, <73>, <74>, <75>;
local-mac-address = [00 00 00 00 00 00];
clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
- status = "disabled";
clock-names = "pclk", "hclk";
- #address-cells = <1>;
- #size-cells = <0>;
+ status = "disabled";
};
-
};
};
diff --git a/arch/riscv/configs/icicle_kit_defconfig b/arch/riscv/configs/icicle_kit_defconfig
new file mode 100644
index 000000000000..f484130e723d
--- /dev/null
+++ b/arch/riscv/configs/icicle_kit_defconfig
@@ -0,0 +1,134 @@
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_CFS_BANDWIDTH=y
+CONFIG_CGROUP_BPF=y
+CONFIG_NAMESPACES=y
+CONFIG_USER_NS=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EXPERT=y
+CONFIG_KALLSYMS_ALL=y
+CONFIG_BPF_SYSCALL=y
+CONFIG_SOC_MICROCHIP_POLARFIRE=y
+CONFIG_SMP=y
+CONFIG_CMDLINE="earlyprintk earlycon=sbi debug uio_pdrv_genirq.of_id=generic-uio"
+CONFIG_JUMP_LABEL=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_BLK_DEV_ZONED=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_NETLINK_DIAG=y
+CONFIG_PCI=y
+CONFIG_PCI_DEBUG=y
+CONFIG_PCI_HOST_GENERIC=y
+CONFIG_PCIE_MICROCHIP_HOST=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_NBD=y
+CONFIG_BLK_DEV_NVME=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_ATA=y
+CONFIG_NETDEVICES=y
+CONFIG_MACB=y
+CONFIG_R8169=y
+CONFIG_INPUT_MOUSEDEV=y
+CONFIG_INPUT_EVDEV=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_EARLYCON_RISCV_SBI=y
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_POLARFIRE_SOC=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MICROCHIP=y
+CONFIG_SPI=y
+CONFIG_SPI_POLARFIRE_SOC=y
+CONFIG_SPI_POLARFIRE_SOC_QSPI=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_POLARFIRE_SOC=y
+CONFIG_POWER_RESET=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=y
+CONFIG_V4L_PLATFORM_DRIVERS=y
+CONFIG_DRM=y
+CONFIG_DRM_RADEON=y
+CONFIG_DRM_NOUVEAU=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PLATFORM=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_HCD_PLATFORM=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_PLATFORM=y
+CONFIG_USB_ACM=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_MUSB_HDRC=y
+CONFIG_USB_MUSB_POLARFIRE_SOC=y
+CONFIG_USB_INVENTRA_DMA=y
+CONFIG_USB_SERIAL=y
+CONFIG_NOP_USB_XCEIV=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_CADENCE=y
+CONFIG_MMC_SPI=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_POLARFIRE_SOC=y
+CONFIG_DMADEVICES=y
+CONFIG_SF_PDMA=y
+CONFIG_UIO=y
+CONFIG_UIO_PDRV_GENIRQ=y
+CONFIG_UIO_DMEM_GENIRQ=y
+CONFIG_UIO_MICROCHIP_CAN=y
+CONFIG_UIO_MICROCHIP_PDMA=y
+CONFIG_UIO_MICROCHIP_DMA=y
+CONFIG_MAILBOX=y
+CONFIG_POLARFIRE_SOC_MAILBOX=y
+CONFIG_POLARFIRE_SOC_SYS_CTRL=y
+CONFIG_POLARFIRE_SOC_GENERIC_SERVICE=y
+CONFIG_IIO=y
+CONFIG_IIO_SW_DEVICE=y
+CONFIG_IIO_SW_TRIGGER=y
+CONFIG_PAC193X=y
+CONFIG_PWM=y
+CONFIG_PWM_MICROCHIP_CORE=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_FANOTIFY=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+CONFIG_EXFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_UTF8=y
+CONFIG_PRINTK_TIME=y
+CONFIG_SCHED_STACK_END_CHECK=y
+CONFIG_SOFTLOCKUP_DETECTOR=y
+CONFIG_WQ_WATCHDOG=y
+CONFIG_SCHEDSTATS=y
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_STACKTRACE=y
--
2.32.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v3 13/15] riscv: dts: microchip: update peripherals in icicle kit device tree
2022-01-14 15:17 [PATCH v3 00/15] Update the Icicle Kit device tree conor.dooley
` (11 preceding siblings ...)
2022-01-14 15:17 ` [PATCH v3 12/15] riscv: dts: microchip: refactor icicle kit device tree conor.dooley
@ 2022-01-14 15:17 ` conor.dooley
2022-01-14 15:17 ` [PATCH v3 14/15] riscv: dts: microchip: add new peripherals to " conor.dooley
2022-01-14 15:17 ` [PATCH v3 15/15] MAINTAINERS: update riscv/microchip entry conor.dooley
14 siblings, 0 replies; 27+ messages in thread
From: conor.dooley @ 2022-01-14 15:17 UTC (permalink / raw)
To: linus.walleij, bgolaszewski, robh+dt, jassisinghbrar,
paul.walmsley, palmer, aou, a.zummo, alexandre.belloni, broonie,
gregkh, thierry.reding, u.kleine-koenig, lee.jones, linux-gpio,
devicetree, linux-kernel, linux-i2c, linux-pwm, linux-riscv,
linux-crypto, linux-rtc, linux-spi, linux-usb
Cc: krzysztof.kozlowski, geert, bin.meng, heiko, lewis.hanly,
conor.dooley, daire.mcnamara, ivan.griffin, atishp
From: Conor Dooley <conor.dooley@microchip.com>
Assorted minor changes to the MPFS/Icicle kit device tree:
- enable mmuart4 instead of mmuart0
- remove sifive pdma
- split memory node to match updated fpga design
- move stdout path to serial1 to avoid collision with
bootloader running on the e51
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../microchip/microchip-mpfs-icicle-kit.dts | 23 +++++++++++++------
.../boot/dts/microchip/microchip-mpfs.dtsi | 23 +++++++++++--------
2 files changed, 29 insertions(+), 17 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
index c51bd7cf500f..dc5f351b10c4 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
@@ -18,20 +18,29 @@ aliases {
serial1 = &mmuart1;
serial2 = &mmuart2;
serial3 = &mmuart3;
+ serial4 = &mmuart4;
};
chosen {
- stdout-path = "serial0:115200n8";
+ stdout-path = "serial1:115200n8";
};
cpus {
timebase-frequency = <RTCCLK_FREQ>;
};
- memory@80000000 {
+ ddrc_cache_lo: memory@80000000 {
device_type = "memory";
- reg = <0x0 0x80000000 0x0 0x40000000>;
+ reg = <0x0 0x80000000 0x0 0x2e000000>;
clocks = <&clkcfg CLK_DDRC>;
+ status = "okay";
+ };
+
+ ddrc_cache_hi: memory@1000000000 {
+ device_type = "memory";
+ reg = <0x10 0x0 0x0 0x40000000>;
+ clocks = <&clkcfg CLK_DDRC>;
+ status = "okay";
};
};
@@ -39,10 +48,6 @@ &refclk {
clock-frequency = <600000000>;
};
-&mmuart0 {
- status = "okay";
-};
-
&mmuart1 {
status = "okay";
};
@@ -55,6 +60,10 @@ &mmuart3 {
status = "okay";
};
+&mmuart4 {
+ status = "okay";
+};
+
&mmc {
status = "okay";
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index 62bd00092bcc..5e7aaaf42cde 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -174,15 +174,6 @@ clint: clint@2000000 {
<&cpu4_intc 3>, <&cpu4_intc 7>;
};
- dma@3000000 {
- compatible = "sifive,fu540-c000-pdma";
- reg = <0x0 0x3000000 0x0 0x8000>;
- interrupt-parent = <&plic>;
- interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
- <30>;
- #dma-cells = <1>;
- };
-
plic: interrupt-controller@c000000 {
compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
reg = <0x0 0xc000000 0x0 0x4000000>;
@@ -213,7 +204,7 @@ mmuart0: serial@20000000 {
interrupts = <90>;
current-speed = <115200>;
clocks = <&clkcfg CLK_MMUART0>;
- status = "disabled";
+ status = "disabled"; /* Reserved for the HSS */
};
mmuart1: serial@20100000 {
@@ -252,6 +243,18 @@ mmuart3: serial@20104000 {
status = "disabled";
};
+ mmuart4: serial@20106000 {
+ compatible = "ns16550a";
+ reg = <0x0 0x20106000 0x0 0x400>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupt-parent = <&plic>;
+ interrupts = <94>;
+ clocks = <&clkcfg CLK_MMUART4>;
+ current-speed = <115200>;
+ status = "disabled";
+ };
+
/* Common node entry for emmc/sd */
mmc: mmc@20008000 {
compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";
--
2.32.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* [PATCH v3 14/15] riscv: dts: microchip: add new peripherals to icicle kit device tree
2022-01-14 15:17 [PATCH v3 00/15] Update the Icicle Kit device tree conor.dooley
` (12 preceding siblings ...)
2022-01-14 15:17 ` [PATCH v3 13/15] riscv: dts: microchip: update peripherals in " conor.dooley
@ 2022-01-14 15:17 ` conor.dooley
2022-01-14 16:35 ` conor dooley
2022-01-14 15:17 ` [PATCH v3 15/15] MAINTAINERS: update riscv/microchip entry conor.dooley
14 siblings, 1 reply; 27+ messages in thread
From: conor.dooley @ 2022-01-14 15:17 UTC (permalink / raw)
To: linus.walleij, bgolaszewski, robh+dt, jassisinghbrar,
paul.walmsley, palmer, aou, a.zummo, alexandre.belloni, broonie,
gregkh, thierry.reding, u.kleine-koenig, lee.jones, linux-gpio,
devicetree, linux-kernel, linux-i2c, linux-pwm, linux-riscv,
linux-crypto, linux-rtc, linux-spi, linux-usb
Cc: krzysztof.kozlowski, geert, bin.meng, heiko, lewis.hanly,
conor.dooley, daire.mcnamara, ivan.griffin, atishp
From: Conor Dooley <conor.dooley@microchip.com>
Add new peripherals to the MPFS, and enable them in the Icicle kit
device tree:
2x SPI, QSPI, 3x GPIO, 2x I2C, Real Time Counter, PCIE controller,
USB host & system controller.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../microchip/microchip-mpfs-icicle-kit.dts | 53 ++++++
.../boot/dts/microchip/microchip-mpfs.dtsi | 168 ++++++++++++++++++
2 files changed, 221 insertions(+)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
index dc5f351b10c4..cd2fe80fa81a 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts
@@ -80,6 +80,26 @@ &mmc {
sd-uhs-sdr104;
};
+&spi0 {
+ status = "okay";
+};
+
+&spi1 {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
&i2c2 {
status = "okay";
};
@@ -103,6 +123,39 @@ phy0: ethernet-phy@8 {
};
};
+&gpio2 {
+ interrupts = <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>,
+ <53>, <53>, <53>, <53>;
+ status = "okay";
+};
+
+&rtc {
+ status = "okay";
+};
+
+&usb {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&mbox {
+ status = "okay";
+};
+
+&syscontroller {
+ status = "okay";
+};
+
+&pcie {
+ status = "okay";
+};
+
&core_pwm0 {
status = "okay";
};
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index 5e7aaaf42cde..1d2447dfbf07 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -266,6 +266,66 @@ mmc: mmc@20008000 {
status = "disabled";
};
+ spi0: spi@20108000 {
+ compatible = "microchip,mpfs-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x20108000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupts = <54>;
+ clocks = <&clkcfg CLK_SPI0>;
+ spi-max-frequency = <25000000>;
+ status = "disabled";
+ };
+
+ spi1: spi@20109000 {
+ compatible = "microchip,mpfs-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x20109000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupts = <55>;
+ clocks = <&clkcfg CLK_SPI1>;
+ spi-max-frequency = <25000000>;
+ status = "disabled";
+ };
+
+ qspi: spi@21000000 {
+ compatible = "microchip,mpfs-qspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x21000000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupts = <85>;
+ clocks = <&clkcfg CLK_QSPI>;
+ spi-max-frequency = <25000000>;
+ status = "disabled";
+ };
+
+ i2c0: i2c@2010a000 {
+ compatible = "microchip,mpfs-i2c";
+ reg = <0x0 0x2010a000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&plic>;
+ interrupts = <58>;
+ clocks = <&clkcfg CLK_I2C0>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@2010b000 {
+ compatible = "microchip,mpfs-i2c";
+ reg = <0x0 0x2010b000 0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupt-parent = <&plic>;
+ interrupts = <61>;
+ clocks = <&clkcfg CLK_I2C1>;
+ clock-frequency = <100000>;
+ status = "disabled";
+ };
+
mac0: ethernet@20110000 {
compatible = "cdns,macb";
reg = <0x0 0x20110000 0x0 0x2000>;
@@ -291,5 +351,113 @@ mac1: ethernet@20112000 {
clock-names = "pclk", "hclk";
status = "disabled";
};
+
+ gpio0: gpio@20120000 {
+ compatible = "microchip,mpfs-gpio";
+ reg = <0x0 0x20120000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ clocks = <&clkcfg CLK_GPIO0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio1: gpio@20121000 {
+ compatible = "microchip,mpfs-gpio";
+ reg = <000 0x20121000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ clocks = <&clkcfg CLK_GPIO1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ gpio2: gpio@20122000 {
+ compatible = "microchip,mpfs-gpio";
+ reg = <0x0 0x20122000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ clocks = <&clkcfg CLK_GPIO2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ status = "disabled";
+ };
+
+ rtc: rtc@20124000 {
+ compatible = "microchip,mpfs-rtc";
+ reg = <0x0 0x20124000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupts = <80>, <81>;
+ clocks = <&clkcfg CLK_RTC>;
+ clock-names = "rtc";
+ status = "disabled";
+ };
+
+ usb: usb@20201000 {
+ compatible = "microchip,mpfs-musb";
+ reg = <0x0 0x20201000 0x0 0x1000>;
+ interrupt-parent = <&plic>;
+ interrupts = <86>, <87>;
+ clocks = <&clkcfg CLK_USB>;
+ interrupt-names = "dma","mc";
+ status = "disabled";
+ };
+
+ pcie: pcie@2000000000 {
+ compatible = "microchip,pcie-host-1.0";
+ #address-cells = <0x3>;
+ #interrupt-cells = <0x1>;
+ #size-cells = <0x2>;
+ device_type = "pci";
+ reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
+ reg-names = "cfg", "apb";
+ bus-range = <0x0 0x7f>;
+ interrupt-parent = <&plic>;
+ interrupts = <119>;
+ interrupt-map = <0 0 0 1 &pcie_intc 0>,
+ <0 0 0 2 &pcie_intc 1>,
+ <0 0 0 3 &pcie_intc 2>,
+ <0 0 0 4 &pcie_intc 3>;
+ interrupt-map-mask = <0 0 0 7>;
+ clocks = <&clkcfg CLK_FIC0>, <&clkcfg CLK_FIC1>, <&clkcfg CLK_FIC3>;
+ clock-names = "fic0", "fic1", "fic3";
+ ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>;
+ msi-parent = <&pcie>;
+ msi-controller;
+ microchip,axi-m-atr0 = <0x10 0x0>;
+ status = "disabled";
+ pcie_intc: legacy-interrupt-controller {
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
+ interrupt-controller;
+ };
+ };
+
+ mbox: mailbox@37020000 {
+ compatible = "microchip,mpfs-mailbox";
+ reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>;
+ interrupt-parent = <&plic>;
+ interrupts = <96>;
+ #mbox-cells = <1>;
+ status = "disabled";
+ };
+
+ syscontroller: syscontroller {
+ compatible = "microchip,mpfs-sys-controller";
+ mboxes = <&mbox 0>;
+
+ rng: rng {
+ compatible = "microchip,mpfs-rng";
+ };
+
+ sysserv: sysserv {
+ compatible = "microchip,mpfs-generic-service";
+ };
+ };
};
};
--
2.32.0
^ permalink raw reply related [flat|nested] 27+ messages in thread
* Re: [PATCH v3 14/15] riscv: dts: microchip: add new peripherals to icicle kit device tree
2022-01-14 15:17 ` [PATCH v3 14/15] riscv: dts: microchip: add new peripherals to " conor.dooley
@ 2022-01-14 16:35 ` conor dooley
0 siblings, 0 replies; 27+ messages in thread
From: conor dooley @ 2022-01-14 16:35 UTC (permalink / raw)
To: conor.dooley
Cc: linus.walleij, bgolaszewski, robh+dt, jassisinghbrar,
paul.walmsley, palmer, aou, a.zummo, alexandre.belloni, broonie,
gregkh, thierry.reding, u.kleine-koenig, lee.jones, linux-gpio,
devicetree, linux-kernel, linux-i2c, linux-pwm, linux-riscv,
linux-crypto, linux-rtc, linux-spi, linux-usb,
krzysztof.kozlowski, geert, bin.meng, heiko, lewis.hanly,
daire.mcnamara, ivan.griffin, atishp
> From: Conor Dooley <conor.dooley@microchip.com>
>
> Add new peripherals to the MPFS, and enable them in the Icicle kit
> device tree:
>
> 2x SPI, QSPI, 3x GPIO, 2x I2C, Real Time Counter, PCIE controller,
> USB host & system controller.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> .../microchip/microchip-mpfs-icicle-kit.dts | 53 ++++++
> .../boot/dts/microchip/microchip-mpfs.dtsi | 168 ++++++++++++++++++
> 2 files changed, 221 insertions(+)
>
realised i forgot to run checkpatch, will fix the trailing whitespace
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v3 15/15] MAINTAINERS: update riscv/microchip entry
2022-01-14 15:17 [PATCH v3 00/15] Update the Icicle Kit device tree conor.dooley
` (13 preceding siblings ...)
2022-01-14 15:17 ` [PATCH v3 14/15] riscv: dts: microchip: add new peripherals to " conor.dooley
@ 2022-01-14 15:17 ` conor.dooley
14 siblings, 0 replies; 27+ messages in thread
From: conor.dooley @ 2022-01-14 15:17 UTC (permalink / raw)
To: linus.walleij, bgolaszewski, robh+dt, jassisinghbrar,
paul.walmsley, palmer, aou, a.zummo, alexandre.belloni, broonie,
gregkh, thierry.reding, u.kleine-koenig, lee.jones, linux-gpio,
devicetree, linux-kernel, linux-i2c, linux-pwm, linux-riscv,
linux-crypto, linux-rtc, linux-spi, linux-usb
Cc: krzysztof.kozlowski, geert, bin.meng, heiko, lewis.hanly,
conor.dooley, daire.mcnamara, ivan.griffin, atishp
From: Conor Dooley <conor.dooley@microchip.com>
Update the RISC-V/Microchip entry by adding the microchip dts
directory and myself as maintainer
Reviewed-by: Lewis Hanly <lewis.hanly@microchip.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
MAINTAINERS | 2 ++
1 file changed, 2 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 7a2345ce8521..3b1d6be7bd56 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -16348,8 +16348,10 @@ K: riscv
RISC-V/MICROCHIP POLARFIRE SOC SUPPORT
M: Lewis Hanly <lewis.hanly@microchip.com>
+M: Conor Dooley <conor.dooley@microchip.com>
L: linux-riscv@lists.infradead.org
S: Supported
+F: arch/riscv/boot/dts/microchip/
F: drivers/mailbox/mailbox-mpfs.c
F: drivers/soc/microchip/
F: include/soc/microchip/mpfs.h
--
2.32.0
^ permalink raw reply related [flat|nested] 27+ messages in thread