[PATCH v8 0/8] spi/spi-atmel: add dmaengine support for atmel spi controller and to test the device tree support

[PATCH v8 0/8] spi/spi-atmel: add dmaengine support for atmel spi controller and to test the device tree support

[Wenyou Yang]

Hi Mark, 

The work is based on Nicolas and Richard's work.

It is based on v3.9-rc5 
	+ Joachim Eastwood's spi/atmel: fix speed_hz check in atmel_spi_transfer()
	+ the following four patches of the version 7 series, which you've applied.
		- detect the capabilities of SPI core by reading the VERSION register
		- add support transfer on CS1,2,3, not only on CS0
		- call unmapping on transfers buffers
		- status information passed through controller data

As per your suggestion, do some change for the patches.

Thanks a lot for your work.

Best Regards
Wenyou Yang


Changelog:
v8:
     1 ./ squash the following two patches into dmaengine patch.
     	   - fix spi-atmel driver to adapt to slave_config changes
	   - correct 16 bits transfers with DMA.
     2./ Add some commit log for patches.

v7:
     1./ remove patch: fix probing failure after xfer->speed_hz set.
     2./ remove patch: add pinctrl support for atmel spi.

v6:
     1./ remove: fix master->num_chipselect wrongly set patch which isn't a issue in v3.9-rc1.
     2./ fix probing failure after xfer->speed_hz set.

v5:
     1./ add pinctrl patches.
     2./ detect capabilities by reading spi version register to replace multiple compatiles.
     3./ change the "cs-gpios" property of spi node.
     4./ rebase on v3.8.

v4:
     1./ Take Joe Perches's adivce, rewrite atmel_spi_is_v2(struct atmel_spi *as) 
         and atmel_spi_use_dma(struct atmel_spi *as),
	 and remove atmel_spi_use_pdc(struct atmel_spi *as).
     2./ Rebase on v3.8-rc3.

V3:
     1./ Rebase on v3.8-rc2.
     2./ Remove some Jean-Christophe's patches which has been applied on v3.8-rc2.
     3./ Remove spi property "cs-gpios" from the SoC dtsi files to the board dts files
         to avoid some useless pin conflicts.

v2: 
     1./ Remove the patch :PATCH]mtd: m25p80: change the m25p80_read to reading page to page
	 which purpose to fix the BUG: when run "flashcp /bin/busybox /dev/mtdX" in the at91sam9g25ek
	 with DMA mode, it arises a OOPS. Now fix it in this patch:
	    [PATHC] spi/atmel_spi: add dmaengine support changing to fix the [BUG].
     2./ Remove two patches:
   	    which purpose to read dts property to select SPI IP version and DMA mode
	    Now they will be gat from device tree different compatile.
     3./ Fix DMA: when enable both spi0 AND spi1, the spi0 doesn't work BUG.
     4./ Rebase v3.7-rc8.


Nicolas Ferre (3):
  spi/spi-atmel: add physical base address
  spi/spi-atmel: add flag to controller data for lock operations
  spi/spi-atmel: add dmaengine support

Richard Genoud (4):
  spi/spi-atmel: BUG: fix doesn' support 16 bits transfers using PIO
  ARM: at91: add clocks for spi dt entries
  ARM: dts: add spi nodes for atmel SoC
  ARM: dts: add spi nodes for the atmel boards

Wenyou Yang (1):
  ARM: dts: add pinctrl property for spi node for atmel SoC

 arch/arm/boot/dts/at91sam9260.dtsi          |   40 ++
 arch/arm/boot/dts/at91sam9263.dtsi          |   40 ++
 arch/arm/boot/dts/at91sam9263ek.dts         |   10 +
 arch/arm/boot/dts/at91sam9g20ek_common.dtsi |   10 +
 arch/arm/boot/dts/at91sam9g45.dtsi          |   40 ++
 arch/arm/boot/dts/at91sam9m10g45ek.dts      |   10 +
 arch/arm/boot/dts/at91sam9n12.dtsi          |   40 ++
 arch/arm/boot/dts/at91sam9n12ek.dts         |   10 +
 arch/arm/boot/dts/at91sam9x5.dtsi           |   40 ++
 arch/arm/boot/dts/at91sam9x5ek.dtsi         |   10 +
 arch/arm/mach-at91/at91sam9260.c            |    2 +
 arch/arm/mach-at91/at91sam9g45.c            |    2 +
 arch/arm/mach-at91/at91sam9n12.c            |    2 +
 arch/arm/mach-at91/at91sam9x5.c             |    2 +
 drivers/spi/spi-atmel.c                     |  653 +++++++++++++++++++++++++--
 15 files changed, 876 insertions(+), 35 deletions(-)

-- 
1.7.9.5


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[PATCH v8 1/8] spi/spi-atmel: add physical base address

[Wenyou Yang]

From: Nicolas Ferre <nicolas.ferre@atmel.com>

Needed for future use with dmaengine enabled driver.

Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Cc: spi-devel-general@lists.sourceforge.net
Cc: linux-kernel@vger.kernel.org
[wenyou.yang@atmel.com: submit the patch]
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
---
 drivers/spi/spi-atmel.c |    2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index 15e8459..38f8c0d 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -196,6 +196,7 @@ struct atmel_spi_caps {
 struct atmel_spi {
 	spinlock_t		lock;
 
+	phys_addr_t		phybase;
 	void __iomem		*regs;
 	int			irq;
 	struct clk		*clk;
@@ -996,6 +997,7 @@ static int atmel_spi_probe(struct platform_device *pdev)
 	as->regs = ioremap(regs->start, resource_size(regs));
 	if (!as->regs)
 		goto out_free_buffer;
+	as->phybase = regs->start;
 	as->irq = irq;
 	as->clk = clk;
 
-- 
1.7.9.5

[PATCH v8 2/8] spi/spi-atmel: add flag to controller data for lock operations

[Wenyou Yang]

From: Nicolas Ferre <nicolas.ferre-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>

Will allow to drop the lock during DMA operations.

Replacing non-irqsave versions with irqsave versions of the lock
to make it correct in both pdc and dmaengine transfer mode

Signed-off-by: Nicolas Ferre <nicolas.ferre-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
Cc: spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
[wenyou.yang-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org: submit the patch]
Signed-off-by: Wenyou Yang <wenyou.yang-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
---
 drivers/spi/spi-atmel.c |   35 +++++++++++++++++++++--------------
 1 file changed, 21 insertions(+), 14 deletions(-)

diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index 38f8c0d..2df562f 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -195,6 +195,7 @@ struct atmel_spi_caps {
  */
 struct atmel_spi {
 	spinlock_t		lock;
+	unsigned long		flags;
 
 	phys_addr_t		phybase;
 	void __iomem		*regs;
@@ -333,6 +334,16 @@ static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
 		gpio_set_value(asd->npcs_pin, !active);
 }
 
+static void atmel_spi_lock(struct atmel_spi *as)
+{
+	spin_lock_irqsave(&as->lock, as->flags);
+}
+
+static void atmel_spi_unlock(struct atmel_spi *as)
+{
+	spin_unlock_irqrestore(&as->lock, as->flags);
+}
+
 static inline int atmel_spi_xfer_is_last(struct spi_message *msg,
 					struct spi_transfer *xfer)
 {
@@ -569,9 +580,9 @@ atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
 		"xfer complete: %u bytes transferred\n",
 		msg->actual_length);
 
-	spin_unlock(&as->lock);
+	atmel_spi_unlock(as);
 	msg->complete(msg->context);
-	spin_lock(&as->lock);
+	atmel_spi_lock(as);
 
 	as->current_transfer = NULL;
 	as->next_transfer = NULL;
@@ -594,7 +605,7 @@ atmel_spi_interrupt(int irq, void *dev_id)
 	u32			status, pending, imr;
 	int			ret = IRQ_NONE;
 
-	spin_lock(&as->lock);
+	atmel_spi_lock(as);
 
 	xfer = as->current_transfer;
 	msg = list_entry(as->queue.next, struct spi_message, queue);
@@ -697,7 +708,7 @@ atmel_spi_interrupt(int irq, void *dev_id)
 		}
 	}
 
-	spin_unlock(&as->lock);
+	atmel_spi_unlock(as);
 
 	return ret;
 }
@@ -802,13 +813,11 @@ static int atmel_spi_setup(struct spi_device *spi)
 		spi->controller_state = asd;
 		gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH));
 	} else {
-		unsigned long		flags;
-
-		spin_lock_irqsave(&as->lock, flags);
+		atmel_spi_lock(as);
 		if (as->stay == spi)
 			as->stay = NULL;
 		cs_deactivate(as, spi);
-		spin_unlock_irqrestore(&as->lock, flags);
+		atmel_spi_unlock(as);
 	}
 
 	asd->csr = csr;
@@ -827,7 +836,6 @@ static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
 {
 	struct atmel_spi	*as;
 	struct spi_transfer	*xfer;
-	unsigned long		flags;
 	struct device		*controller = spi->master->dev.parent;
 	u8			bits;
 	struct atmel_spi_device	*asd;
@@ -892,11 +900,11 @@ static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
 	msg->status = -EINPROGRESS;
 	msg->actual_length = 0;
 
-	spin_lock_irqsave(&as->lock, flags);
+	atmel_spi_lock(as);
 	list_add_tail(&msg->queue, &as->queue);
 	if (!as->current_transfer)
 		atmel_spi_next_message(spi->master);
-	spin_unlock_irqrestore(&as->lock, flags);
+	atmel_spi_unlock(as);
 
 	return 0;
 }
@@ -906,17 +914,16 @@ static void atmel_spi_cleanup(struct spi_device *spi)
 	struct atmel_spi	*as = spi_master_get_devdata(spi->master);
 	struct atmel_spi_device	*asd = spi->controller_state;
 	unsigned		gpio = (unsigned) spi->controller_data;
-	unsigned long		flags;
 
 	if (!asd)
 		return;
 
-	spin_lock_irqsave(&as->lock, flags);
+	atmel_spi_lock(as);
 	if (as->stay == spi) {
 		as->stay = NULL;
 		cs_deactivate(as, spi);
 	}
-	spin_unlock_irqrestore(&as->lock, flags);
+	atmel_spi_unlock(as);
 
 	spi->controller_state = NULL;
 	gpio_free(gpio);
-- 
1.7.9.5


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[PATCH v8 3/8] spi/spi-atmel: add dmaengine support

[Wenyou Yang]

From: Nicolas Ferre <nicolas.ferre-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>

Add dmaengine support.

Using "has_dma_support" member of struct is used to select
the transfer mode: dmaengine or pdc.

For the dmaengine transfer mode, it supports both 8 bits and 16 bits transfer.

For the dmaengine transfer mode, if it fails to config dmaengine,
or if the message length is less than 16 bytes, it will use the PIO transfer mode.

Signed-off-by: Nicolas Ferre <nicolas.ferre-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
[wenyou.yang-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org: using "has_dma_support" to select dmaengine as the spi xfer mode]
[wenyou.yang-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org: fix DMA: OOPS if buffer > 4096 bytes]
[wenyou.yang-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org: submit the patch]
Signed-off-by: Wenyou Yang <wenyou.yang-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
Cc: richard.genoud-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
Cc: spi-devel-general-5NWGOfrQmneRv+LV9MX5uv+2+P5yyue3@public.gmane.org
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
[richard.genoud-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org: update with dmaengine interface]
[richard.genoud-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org: fix __init/__devinit sections mismatch]
[richard.genoud-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org: adapt to slave_config changes]
[richard.genoud-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org: add support t0 16 bits transfer]
---
This patch is based on the original patch from Nicolas
	- add dmaengine support
and squash the below patches from Richard Genoud <richard.genoud-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
	- update with dmaengine interface
	- fix __init/__devinit sections mismatch
	- fix spi-atmel driver to adapt to slave_config changes
	- correct 16 bits transfers with DMA

Hi, Richard,

Could you sign your signature in this patch?

Best Regards,
Wenyou Yang

 drivers/spi/spi-atmel.c |  587 +++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 566 insertions(+), 21 deletions(-)

diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index 2df562f..759d83a 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -15,11 +15,13 @@
 #include <linux/platform_device.h>
 #include <linux/delay.h>
 #include <linux/dma-mapping.h>
+#include <linux/dmaengine.h>
 #include <linux/err.h>
 #include <linux/interrupt.h>
 #include <linux/spi/spi.h>
 #include <linux/slab.h>
 #include <linux/platform_data/atmel.h>
+#include <linux/platform_data/dma-atmel.h>
 #include <linux/of.h>
 
 #include <linux/io.h>
@@ -182,6 +184,22 @@
 #define spi_writel(port,reg,value) \
 	__raw_writel((value), (port)->regs + SPI_##reg)
 
+/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
+ * cache operations; better heuristics consider wordsize and bitrate.
+ */
+#define DMA_MIN_BYTES	16
+
+struct atmel_spi_dma {
+	struct dma_chan			*chan_rx;
+	struct dma_chan			*chan_tx;
+	struct scatterlist		sgrx;
+	struct scatterlist		sgtx;
+	struct dma_async_tx_descriptor	*data_desc_rx;
+	struct dma_async_tx_descriptor	*data_desc_tx;
+
+	struct at_dma_slave	dma_slave;
+};
+
 struct atmel_spi_caps {
 	bool	is_spi2;
 	bool	has_wdrbt;
@@ -206,16 +224,23 @@ struct atmel_spi {
 
 	u8			stopping;
 	struct list_head	queue;
+	struct tasklet_struct	tasklet;
 	struct spi_transfer	*current_transfer;
 	unsigned long		current_remaining_bytes;
 	struct spi_transfer	*next_transfer;
 	unsigned long		next_remaining_bytes;
 	int			done_status;
 
+	/* scratch buffer */
 	void			*buffer;
 	dma_addr_t		buffer_dma;
 
 	struct atmel_spi_caps	caps;
+
+	bool			use_dma;
+	bool			use_pdc;
+	/* dmaengine data */
+	struct atmel_spi_dma	dma;
 };
 
 /* Controller-specific per-slave state */
@@ -284,6 +309,7 @@ static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
 					| SPI_BIT(MODFDIS)
 					| SPI_BIT(MSTR));
 		}
+
 		mr = spi_readl(as, MR);
 		gpio_set_value(asd->npcs_pin, active);
 	} else {
@@ -344,6 +370,12 @@ static void atmel_spi_unlock(struct atmel_spi *as)
 	spin_unlock_irqrestore(&as->lock, as->flags);
 }
 
+static inline bool atmel_spi_use_dma(struct atmel_spi *as,
+				struct spi_transfer *xfer)
+{
+	return as->use_dma && xfer->len >= DMA_MIN_BYTES;
+}
+
 static inline int atmel_spi_xfer_is_last(struct spi_message *msg,
 					struct spi_transfer *xfer)
 {
@@ -355,6 +387,265 @@ static inline int atmel_spi_xfer_can_be_chained(struct spi_transfer *xfer)
 	return xfer->delay_usecs == 0 && !xfer->cs_change;
 }
 
+static int atmel_spi_dma_slave_config(struct atmel_spi *as,
+				struct dma_slave_config *slave_config,
+				u8 bits_per_word)
+{
+	int err = 0;
+
+	if (bits_per_word > 8) {
+		slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
+		slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
+	} else {
+		slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
+		slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
+	}
+
+	slave_config->dst_addr = (dma_addr_t)as->phybase + SPI_TDR;
+	slave_config->src_addr = (dma_addr_t)as->phybase + SPI_RDR;
+	slave_config->src_maxburst = 1;
+	slave_config->dst_maxburst = 1;
+	slave_config->device_fc = false;
+
+	slave_config->direction = DMA_MEM_TO_DEV;
+	if (dmaengine_slave_config(as->dma.chan_tx, slave_config)) {
+		dev_err(&as->pdev->dev,
+			"failed to configure tx dma channel\n");
+		err = -EINVAL;
+	}
+
+	slave_config->direction = DMA_DEV_TO_MEM;
+	if (dmaengine_slave_config(as->dma.chan_rx, slave_config)) {
+		dev_err(&as->pdev->dev,
+			"failed to configure rx dma channel\n");
+		err = -EINVAL;
+	}
+
+	return err;
+}
+
+static bool filter(struct dma_chan *chan, void *slave)
+{
+	struct	at_dma_slave *sl = slave;
+
+	if (sl->dma_dev == chan->device->dev) {
+		chan->private = sl;
+		return true;
+	} else {
+		return false;
+	}
+}
+
+static int atmel_spi_configure_dma(struct atmel_spi *as)
+{
+	struct at_dma_slave *sdata = &as->dma.dma_slave;
+	struct dma_slave_config	slave_config;
+	int err;
+
+	if (sdata && sdata->dma_dev) {
+		dma_cap_mask_t mask;
+
+		/* Try to grab two DMA channels */
+		dma_cap_zero(mask);
+		dma_cap_set(DMA_SLAVE, mask);
+		as->dma.chan_tx = dma_request_channel(mask, filter, sdata);
+		if (as->dma.chan_tx)
+			as->dma.chan_rx =
+				dma_request_channel(mask, filter, sdata);
+	}
+	if (!as->dma.chan_rx || !as->dma.chan_tx) {
+		dev_err(&as->pdev->dev,
+			"DMA channel not available, SPI unable to use DMA\n");
+		err = -EBUSY;
+		goto error;
+	}
+
+	err = atmel_spi_dma_slave_config(as, &slave_config, 8);
+	if (err)
+		goto error;
+
+	dev_info(&as->pdev->dev,
+			"Using %s (tx) and %s (rx) for DMA transfers\n",
+			dma_chan_name(as->dma.chan_tx),
+			dma_chan_name(as->dma.chan_rx));
+	return 0;
+error:
+	if (as->dma.chan_rx)
+		dma_release_channel(as->dma.chan_rx);
+	if (as->dma.chan_tx)
+		dma_release_channel(as->dma.chan_tx);
+	return err;
+}
+
+static void atmel_spi_stop_dma(struct atmel_spi *as)
+{
+	if (as->dma.chan_rx)
+		as->dma.chan_rx->device->device_control(as->dma.chan_rx,
+							DMA_TERMINATE_ALL, 0);
+	if (as->dma.chan_tx)
+		as->dma.chan_tx->device->device_control(as->dma.chan_tx,
+							DMA_TERMINATE_ALL, 0);
+}
+
+static void atmel_spi_release_dma(struct atmel_spi *as)
+{
+	if (as->dma.chan_rx)
+		dma_release_channel(as->dma.chan_rx);
+	if (as->dma.chan_tx)
+		dma_release_channel(as->dma.chan_tx);
+}
+
+/* This function is called by the DMA driver from tasklet context */
+static void dma_callback(void *data)
+{
+	struct spi_master	*master = data;
+	struct atmel_spi	*as = spi_master_get_devdata(master);
+
+	/* trigger SPI tasklet */
+	tasklet_schedule(&as->tasklet);
+}
+
+/*
+ * Next transfer using PIO.
+ * lock is held, spi tasklet is blocked
+ */
+static void atmel_spi_next_xfer_pio(struct spi_master *master,
+				struct spi_transfer *xfer)
+{
+	struct atmel_spi	*as = spi_master_get_devdata(master);
+
+	dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n");
+
+	as->current_remaining_bytes = xfer->len;
+
+	/* Make sure data is not remaining in RDR */
+	spi_readl(as, RDR);
+	while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
+		spi_readl(as, RDR);
+		cpu_relax();
+	}
+
+	if (xfer->tx_buf)
+		spi_writel(as, TDR, *(u8 *)(xfer->tx_buf));
+	else
+		spi_writel(as, TDR, 0);
+
+	dev_dbg(master->dev.parent,
+		"  start pio xfer %p: len %u tx %p rx %p\n",
+		xfer, xfer->len, xfer->tx_buf, xfer->rx_buf);
+
+	/* Enable relevant interrupts */
+	spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
+}
+
+/*
+ * Submit next transfer for DMA.
+ * lock is held, spi tasklet is blocked
+ */
+static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
+				struct spi_transfer *xfer,
+				u32 *plen)
+{
+	struct atmel_spi	*as = spi_master_get_devdata(master);
+	struct dma_chan		*rxchan = as->dma.chan_rx;
+	struct dma_chan		*txchan = as->dma.chan_tx;
+	struct dma_async_tx_descriptor *rxdesc;
+	struct dma_async_tx_descriptor *txdesc;
+	struct dma_slave_config	slave_config;
+	dma_cookie_t		cookie;
+	u32	len = *plen;
+
+	dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n");
+
+	/* Check that the channels are available */
+	if (!rxchan || !txchan)
+		return -ENODEV;
+
+	/* release lock for DMA operations */
+	atmel_spi_unlock(as);
+
+	/* prepare the RX dma transfer */
+	sg_init_table(&as->dma.sgrx, 1);
+	if (xfer->rx_buf) {
+		as->dma.sgrx.dma_address = xfer->rx_dma + xfer->len - *plen;
+	} else {
+		as->dma.sgrx.dma_address = as->buffer_dma;
+		if (len > BUFFER_SIZE)
+			len = BUFFER_SIZE;
+	}
+
+	/* prepare the TX dma transfer */
+	sg_init_table(&as->dma.sgtx, 1);
+	if (xfer->tx_buf) {
+		as->dma.sgtx.dma_address = xfer->tx_dma + xfer->len - *plen;
+	} else {
+		as->dma.sgtx.dma_address = as->buffer_dma;
+		if (len > BUFFER_SIZE)
+			len = BUFFER_SIZE;
+		memset(as->buffer, 0, len);
+	}
+
+	sg_dma_len(&as->dma.sgtx) = len;
+	sg_dma_len(&as->dma.sgrx) = len;
+
+	*plen = len;
+
+	if (atmel_spi_dma_slave_config(as, &slave_config, 8))
+		goto err_exit;
+
+	/* Send both scatterlists */
+	rxdesc = rxchan->device->device_prep_slave_sg(rxchan,
+					&as->dma.sgrx,
+					1,
+					DMA_FROM_DEVICE,
+					DMA_PREP_INTERRUPT | DMA_CTRL_ACK,
+					NULL);
+	if (!rxdesc)
+		goto err_dma;
+
+	txdesc = txchan->device->device_prep_slave_sg(txchan,
+					&as->dma.sgtx,
+					1,
+					DMA_TO_DEVICE,
+					DMA_PREP_INTERRUPT | DMA_CTRL_ACK,
+					NULL);
+	if (!txdesc)
+		goto err_dma;
+
+	dev_dbg(master->dev.parent,
+		"  start dma xfer %p: len %u tx %p/%08x rx %p/%08x\n",
+		xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
+		xfer->rx_buf, xfer->rx_dma);
+
+	/* Enable relevant interrupts */
+	spi_writel(as, IER, SPI_BIT(OVRES));
+
+	/* Put the callback on the RX transfer only, that should finish last */
+	rxdesc->callback = dma_callback;
+	rxdesc->callback_param = master;
+
+	/* Submit and fire RX and TX with TX last so we're ready to read! */
+	cookie = rxdesc->tx_submit(rxdesc);
+	if (dma_submit_error(cookie))
+		goto err_dma;
+	cookie = txdesc->tx_submit(txdesc);
+	if (dma_submit_error(cookie))
+		goto err_dma;
+	rxchan->device->device_issue_pending(rxchan);
+	txchan->device->device_issue_pending(txchan);
+
+	/* take back lock */
+	atmel_spi_lock(as);
+	return 0;
+
+err_dma:
+	spi_writel(as, IDR, SPI_BIT(OVRES));
+	atmel_spi_stop_dma(as);
+err_exit:
+	atmel_spi_lock(as);
+	return -ENOMEM;
+}
+
 static void atmel_spi_next_xfer_data(struct spi_master *master,
 				struct spi_transfer *xfer,
 				dma_addr_t *tx_dma,
@@ -372,6 +663,7 @@ static void atmel_spi_next_xfer_data(struct spi_master *master,
 		if (len > BUFFER_SIZE)
 			len = BUFFER_SIZE;
 	}
+
 	if (xfer->tx_buf)
 		*tx_dma = xfer->tx_dma + xfer->len - *plen;
 	else {
@@ -387,10 +679,10 @@ static void atmel_spi_next_xfer_data(struct spi_master *master,
 }
 
 /*
- * Submit next transfer for DMA.
+ * Submit next transfer for PDC.
  * lock is held, spi irq is blocked
  */
-static void atmel_spi_next_xfer(struct spi_master *master,
+static void atmel_spi_pdc_next_xfer(struct spi_master *master,
 				struct spi_message *msg)
 {
 	struct atmel_spi	*as = spi_master_get_devdata(master);
@@ -487,6 +779,48 @@ static void atmel_spi_next_xfer(struct spi_master *master,
 	spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
 }
 
+/*
+ * Choose way to submit next transfer and start it.
+ * lock is held, spi tasklet is blocked
+ */
+static void atmel_spi_dma_next_xfer(struct spi_master *master,
+				struct spi_message *msg)
+{
+	struct atmel_spi	*as = spi_master_get_devdata(master);
+	struct spi_transfer	*xfer;
+	u32	remaining, len;
+
+	remaining = as->current_remaining_bytes;
+	if (remaining) {
+		xfer = as->current_transfer;
+		len = remaining;
+	} else {
+		if (!as->current_transfer)
+			xfer = list_entry(msg->transfers.next,
+				struct spi_transfer, transfer_list);
+		else
+			xfer = list_entry(
+				as->current_transfer->transfer_list.next,
+					struct spi_transfer, transfer_list);
+
+		as->current_transfer = xfer;
+		len = xfer->len;
+	}
+
+	if (atmel_spi_use_dma(as, xfer)) {
+		u32 total = len;
+		if (!atmel_spi_next_xfer_dma_submit(master, xfer, &len)) {
+			as->current_remaining_bytes = total - len;
+			return;
+		} else {
+			dev_err(&msg->spi->dev, "unable to use DMA, fallback to PIO\n");
+		}
+	}
+
+	/* use PIO if error appened using DMA */
+	atmel_spi_next_xfer_pio(master, xfer);
+}
+
 static void atmel_spi_next_message(struct spi_master *master)
 {
 	struct atmel_spi	*as = spi_master_get_devdata(master);
@@ -511,7 +845,10 @@ static void atmel_spi_next_message(struct spi_master *master)
 	} else
 		cs_activate(as, spi);
 
-	atmel_spi_next_xfer(master, msg);
+	if (as->use_pdc)
+		atmel_spi_pdc_next_xfer(master, msg);
+	else
+		atmel_spi_dma_next_xfer(master, msg);
 }
 
 /*
@@ -564,6 +901,11 @@ static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
 				 xfer->len, DMA_FROM_DEVICE);
 }
 
+static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as)
+{
+	spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
+}
+
 static void
 atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
 		struct spi_message *msg, int stay)
@@ -589,14 +931,183 @@ atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
 	as->done_status = 0;
 
 	/* continue if needed */
-	if (list_empty(&as->queue) || as->stopping)
-		spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
-	else
+	if (list_empty(&as->queue) || as->stopping) {
+		if (as->use_pdc)
+			atmel_spi_disable_pdc_transfer(as);
+	} else {
 		atmel_spi_next_message(master);
+	}
+}
+
+/* Called from IRQ
+ * lock is held
+ *
+ * Must update "current_remaining_bytes" to keep track of data
+ * to transfer.
+ */
+static void
+atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
+{
+	u8		*txp;
+	u8		*rxp;
+	unsigned long	xfer_pos = xfer->len - as->current_remaining_bytes;
+
+	if (xfer->rx_buf) {
+		rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
+		*rxp = spi_readl(as, RDR);
+	} else {
+		spi_readl(as, RDR);
+	}
+
+	as->current_remaining_bytes--;
+
+	if (as->current_remaining_bytes) {
+		if (xfer->tx_buf) {
+			txp = ((u8 *)xfer->tx_buf) + xfer_pos + 1;
+			spi_writel(as, TDR, *txp);
+		} else {
+			spi_writel(as, TDR, 0);
+		}
+	}
+}
+
+/* Tasklet
+ * Called from DMA callback + pio transfer and overrun IRQ.
+ */
+static void atmel_spi_tasklet_func(unsigned long data)
+{
+	struct spi_master	*master = (struct spi_master *)data;
+	struct atmel_spi	*as = spi_master_get_devdata(master);
+	struct spi_message	*msg;
+	struct spi_transfer	*xfer;
+
+	dev_vdbg(master->dev.parent, "atmel_spi_tasklet_func\n");
+
+	atmel_spi_lock(as);
+
+	xfer = as->current_transfer;
+
+	if (xfer == NULL)
+		/* already been there */
+		goto tasklet_out;
+
+	msg = list_entry(as->queue.next, struct spi_message, queue);
+
+	if (as->current_remaining_bytes == 0) {
+		if (as->done_status < 0) {
+			/* error happened (overrun) */
+			if (atmel_spi_use_dma(as, xfer))
+				atmel_spi_stop_dma(as);
+		} else {
+			/* only update length if no error */
+			msg->actual_length += xfer->len;
+		}
+
+		if (atmel_spi_use_dma(as, xfer))
+			if (!msg->is_dma_mapped)
+				atmel_spi_dma_unmap_xfer(master, xfer);
+
+		if (xfer->delay_usecs)
+			udelay(xfer->delay_usecs);
+
+		if (atmel_spi_xfer_is_last(msg, xfer) || as->done_status < 0) {
+			/* report completed (or erroneous) message */
+			atmel_spi_msg_done(master, as, msg, xfer->cs_change);
+		} else {
+			if (xfer->cs_change) {
+				cs_deactivate(as, msg->spi);
+				udelay(1);
+				cs_activate(as, msg->spi);
+			}
+
+			/*
+			 * Not done yet. Submit the next transfer.
+			 *
+			 * FIXME handle protocol options for xfer
+			 */
+			atmel_spi_dma_next_xfer(master, msg);
+		}
+	} else {
+		/*
+		 * Keep going, we still have data to send in
+		 * the current transfer.
+		 */
+		atmel_spi_dma_next_xfer(master, msg);
+	}
+
+tasklet_out:
+	atmel_spi_unlock(as);
+}
+
+/* Interrupt
+ *
+ * No need for locking in this Interrupt handler: done_status is the
+ * only information modified. What we need is the update of this field
+ * before tasklet runs. This is ensured by using barrier.
+ */
+static irqreturn_t
+atmel_spi_pio_interrupt(int irq, void *dev_id)
+{
+	struct spi_master	*master = dev_id;
+	struct atmel_spi	*as = spi_master_get_devdata(master);
+	u32			status, pending, imr;
+	struct spi_transfer	*xfer;
+	int			ret = IRQ_NONE;
+
+	imr = spi_readl(as, IMR);
+	status = spi_readl(as, SR);
+	pending = status & imr;
+
+	if (pending & SPI_BIT(OVRES)) {
+		ret = IRQ_HANDLED;
+		spi_writel(as, IDR, SPI_BIT(OVRES));
+		dev_warn(master->dev.parent, "overrun\n");
+
+		/*
+		 * When we get an overrun, we disregard the current
+		 * transfer. Data will not be copied back from any
+		 * bounce buffer and msg->actual_len will not be
+		 * updated with the last xfer.
+		 *
+		 * We will also not process any remaning transfers in
+		 * the message.
+		 *
+		 * All actions are done in tasklet with done_status indication
+		 */
+		as->done_status = -EIO;
+		smp_wmb();
+
+		/* Clear any overrun happening while cleaning up */
+		spi_readl(as, SR);
+
+		tasklet_schedule(&as->tasklet);
+
+	} else if (pending & SPI_BIT(RDRF)) {
+		atmel_spi_lock(as);
+
+		if (as->current_remaining_bytes) {
+			ret = IRQ_HANDLED;
+			xfer = as->current_transfer;
+			atmel_spi_pump_pio_data(as, xfer);
+			if (!as->current_remaining_bytes) {
+				/* no more data to xfer, kick tasklet */
+				spi_writel(as, IDR, pending);
+				tasklet_schedule(&as->tasklet);
+			}
+		}
+
+		atmel_spi_unlock(as);
+	} else {
+		WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending);
+		ret = IRQ_HANDLED;
+		spi_writel(as, IDR, pending);
+	}
+
+	return ret;
 }
 
 static irqreturn_t
-atmel_spi_interrupt(int irq, void *dev_id)
+atmel_spi_pdc_interrupt(int irq, void *dev_id)
 {
 	struct spi_master	*master = dev_id;
 	struct atmel_spi	*as = spi_master_get_devdata(master);
@@ -697,14 +1208,14 @@ atmel_spi_interrupt(int irq, void *dev_id)
 				 *
 				 * FIXME handle protocol options for xfer
 				 */
-				atmel_spi_next_xfer(master, msg);
+				atmel_spi_pdc_next_xfer(master, msg);
 			}
 		} else {
 			/*
 			 * Keep going, we still have data to send in
 			 * the current transfer.
 			 */
-			atmel_spi_next_xfer(master, msg);
+			atmel_spi_pdc_next_xfer(master, msg);
 		}
 	}
 
@@ -875,13 +1386,10 @@ static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
 
 		/*
 		 * DMA map early, for performance (empties dcache ASAP) and
-		 * better fault reporting.  This is a DMA-only driver.
-		 *
-		 * NOTE that if dma_unmap_single() ever starts to do work on
-		 * platforms supported by this driver, we would need to clean
-		 * up mappings for previously-mapped transfers.
+		 * better fault reporting.
 		 */
-		if (!msg->is_dma_mapped) {
+		if ((!msg->is_dma_mapped) && (atmel_spi_use_dma(as, xfer)
+			|| as->use_pdc)) {
 			if (atmel_spi_dma_map_xfer(as, xfer) < 0)
 				return -ENOMEM;
 		}
@@ -1000,6 +1508,7 @@ static int atmel_spi_probe(struct platform_device *pdev)
 
 	spin_lock_init(&as->lock);
 	INIT_LIST_HEAD(&as->queue);
+
 	as->pdev = pdev;
 	as->regs = ioremap(regs->start, resource_size(regs));
 	if (!as->regs)
@@ -1010,8 +1519,28 @@ static int atmel_spi_probe(struct platform_device *pdev)
 
 	atmel_get_caps(as);
 
-	ret = request_irq(irq, atmel_spi_interrupt, 0,
-			dev_name(&pdev->dev), master);
+	as->use_dma = false;
+	as->use_pdc = false;
+	if (as->caps.has_dma_support) {
+		if (atmel_spi_configure_dma(as) == 0)
+			as->use_dma = true;
+	} else {
+		as->use_pdc = true;
+	}
+
+	if (as->caps.has_dma_support && !as->use_dma)
+		dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n");
+
+	if (as->use_pdc) {
+		ret = request_irq(irq, atmel_spi_pdc_interrupt, 0,
+					dev_name(&pdev->dev), master);
+	} else {
+		tasklet_init(&as->tasklet, atmel_spi_tasklet_func,
+					(unsigned long)master);
+
+		ret = request_irq(irq, atmel_spi_pio_interrupt, 0,
+					dev_name(&pdev->dev), master);
+	}
 	if (ret)
 		goto out_unmap_regs;
 
@@ -1025,7 +1554,9 @@ static int atmel_spi_probe(struct platform_device *pdev)
 	} else {
 		spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
 	}
-	spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
+
+	if (as->use_pdc)
+		spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
 	spi_writel(as, CR, SPI_BIT(SPIEN));
 
 	/* go! */
@@ -1034,11 +1565,14 @@ static int atmel_spi_probe(struct platform_device *pdev)
 
 	ret = spi_register_master(master);
 	if (ret)
-		goto out_reset_hw;
+		goto out_free_dma;
 
 	return 0;
 
-out_reset_hw:
+out_free_dma:
+	if (as->use_dma)
+		atmel_spi_release_dma(as);
+
 	spi_writel(as, CR, SPI_BIT(SWRST));
 	spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
 	clk_disable(clk);
@@ -1046,6 +1580,8 @@ out_reset_hw:
 out_unmap_regs:
 	iounmap(as->regs);
 out_free_buffer:
+	if (!as->use_pdc)
+		tasklet_kill(&as->tasklet);
 	dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
 			as->buffer_dma);
 out_free:
@@ -1064,6 +1600,11 @@ static int atmel_spi_remove(struct platform_device *pdev)
 	/* reset the hardware and block queue progress */
 	spin_lock_irq(&as->lock);
 	as->stopping = 1;
+	if (as->use_dma) {
+		atmel_spi_stop_dma(as);
+		atmel_spi_release_dma(as);
+	}
+
 	spi_writel(as, CR, SPI_BIT(SWRST));
 	spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
 	spi_readl(as, SR);
@@ -1072,13 +1613,17 @@ static int atmel_spi_remove(struct platform_device *pdev)
 	/* Terminate remaining queued transfers */
 	list_for_each_entry(msg, &as->queue, queue) {
 		list_for_each_entry(xfer, &msg->transfers, transfer_list) {
-			if (!msg->is_dma_mapped)
+			if (!msg->is_dma_mapped
+				&& (atmel_spi_use_dma(as, xfer)
+					|| as->use_pdc))
 				atmel_spi_dma_unmap_xfer(master, xfer);
 		}
 		msg->status = -ESHUTDOWN;
 		msg->complete(msg->context);
 	}
 
+	if (!as->use_pdc)
+		tasklet_kill(&as->tasklet);
 	dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
 			as->buffer_dma);
 
-- 
1.7.9.5


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[PATCH v8 4/8] spi/spi-atmel: BUG: fix doesn' support 16 bits transfers using PIO

[Wenyou Yang]

From: Richard Genoud <richard.genoud-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

Fix using PIO transfer mode only support 8 bits transfer, doesn't support 16 bits.

Signed-off-by: Richard Genoud <richard.genoud-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Cc: spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
[wenyou.yang-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org: submit the patch]
Signed-off-by: Wenyou Yang <wenyou.yang-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
---
 drivers/spi/spi-atmel.c |   47 ++++++++++++++++++++++++++++++++++++++---------
 1 file changed, 38 insertions(+), 9 deletions(-)

diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
index 759d83a..a619779 100644
--- a/drivers/spi/spi-atmel.c
+++ b/drivers/spi/spi-atmel.c
@@ -526,13 +526,17 @@ static void atmel_spi_next_xfer_pio(struct spi_master *master,
 	}
 
 	if (xfer->tx_buf)
-		spi_writel(as, TDR, *(u8 *)(xfer->tx_buf));
+		if (xfer->bits_per_word > 8)
+			spi_writel(as, TDR, *(u16 *)(xfer->tx_buf));
+		else
+			spi_writel(as, TDR, *(u8 *)(xfer->tx_buf));
 	else
 		spi_writel(as, TDR, 0);
 
 	dev_dbg(master->dev.parent,
-		"  start pio xfer %p: len %u tx %p rx %p\n",
-		xfer, xfer->len, xfer->tx_buf, xfer->rx_buf);
+		"  start pio xfer %p: len %u tx %p rx %p bitpw %d\n",
+		xfer, xfer->len, xfer->tx_buf, xfer->rx_buf,
+		xfer->bits_per_word);
 
 	/* Enable relevant interrupts */
 	spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
@@ -950,21 +954,39 @@ atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
 {
 	u8		*txp;
 	u8		*rxp;
+	u16		*txp16;
+	u16		*rxp16;
 	unsigned long	xfer_pos = xfer->len - as->current_remaining_bytes;
 
 	if (xfer->rx_buf) {
-		rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
-		*rxp = spi_readl(as, RDR);
+		if (xfer->bits_per_word > 8) {
+			rxp16 = (u16 *)(((u8 *)xfer->rx_buf) + xfer_pos);
+			*rxp16 = spi_readl(as, RDR);
+		} else {
+			rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
+			*rxp = spi_readl(as, RDR);
+		}
 	} else {
 		spi_readl(as, RDR);
 	}
-
-	as->current_remaining_bytes--;
+	if (xfer->bits_per_word > 8) {
+		as->current_remaining_bytes -= 2;
+		if (as->current_remaining_bytes < 0)
+			as->current_remaining_bytes = 0;
+	} else {
+		as->current_remaining_bytes--;
+	}
 
 	if (as->current_remaining_bytes) {
 		if (xfer->tx_buf) {
-			txp = ((u8 *)xfer->tx_buf) + xfer_pos + 1;
-			spi_writel(as, TDR, *txp);
+			if (xfer->bits_per_word > 8) {
+				txp16 = (u16 *)(((u8 *)xfer->tx_buf)
+							+ xfer_pos + 2);
+				spi_writel(as, TDR, *txp16);
+			} else {
+				txp = ((u8 *)xfer->tx_buf) + xfer_pos + 1;
+				spi_writel(as, TDR, *txp);
+			}
 		} else {
 			spi_writel(as, TDR, 0);
 		}
@@ -1378,6 +1400,13 @@ static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
 			}
 		}
 
+		if (xfer->bits_per_word > 8) {
+			if (xfer->len % 2) {
+				dev_dbg(&spi->dev, "buffer len should be 16 bits aligned\n");
+				return -EINVAL;
+			}
+		}
+
 		/* FIXME implement these protocol options!! */
 		if (xfer->speed_hz < spi->max_speed_hz) {
 			dev_dbg(&spi->dev, "can't change speed in transfer\n");
-- 
1.7.9.5


------------------------------------------------------------------------------
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[PATCH v8 5/8] ARM: at91: add clocks for spi dt entries

[Wenyou Yang]

From: Richard Genoud <richard.genoud@gmail.com>

Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
[<wenyou.yang@atmel.com: declare the spi clocks for sam9260, at91sam9g45, and at91sam9n12]
[wenyou.yang@atmel.com: submit the patch]
Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Cc: linux@arm.linux.org.uk
Cc: linux@maxim.org.za
Cc: linux-kernel@vger.kernel.org
---
 arch/arm/mach-at91/at91sam9260.c |    2 ++
 arch/arm/mach-at91/at91sam9g45.c |    2 ++
 arch/arm/mach-at91/at91sam9n12.c |    2 ++
 arch/arm/mach-at91/at91sam9x5.c  |    2 ++
 4 files changed, 8 insertions(+)

diff --git a/arch/arm/mach-at91/at91sam9260.c b/arch/arm/mach-at91/at91sam9260.c
index b67cd53..44199bc 100644
--- a/arch/arm/mach-at91/at91sam9260.c
+++ b/arch/arm/mach-at91/at91sam9260.c
@@ -232,6 +232,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("t2_clk", "fffdc000.timer", &tc5_clk),
 	CLKDEV_CON_DEV_ID("hclk", "500000.ohci", &ohci_clk),
 	CLKDEV_CON_DEV_ID("mci_clk", "fffa8000.mmc", &mmc_clk),
+	CLKDEV_CON_DEV_ID("spi_clk", "fffc8000.spi", &spi0_clk),
+	CLKDEV_CON_DEV_ID("spi_clk", "fffcc000.spi", &spi1_clk),
 	/* fake hclk clock */
 	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &ohci_clk),
 	CLKDEV_CON_ID("pioA", &pioA_clk),
diff --git a/arch/arm/mach-at91/at91sam9g45.c b/arch/arm/mach-at91/at91sam9g45.c
index d3addee..2ec5efe 100644
--- a/arch/arm/mach-at91/at91sam9g45.c
+++ b/arch/arm/mach-at91/at91sam9g45.c
@@ -262,6 +262,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("mci_clk", "fffd0000.mmc", &mmc1_clk),
 	CLKDEV_CON_DEV_ID(NULL, "fff84000.i2c", &twi0_clk),
 	CLKDEV_CON_DEV_ID(NULL, "fff88000.i2c", &twi1_clk),
+	CLKDEV_CON_DEV_ID("spi_clk", "fffa4000.spi", &spi0_clk),
+	CLKDEV_CON_DEV_ID("spi_clk", "fffa8000.spi", &spi1_clk),
 	/* fake hclk clock */
 	CLKDEV_CON_DEV_ID("hclk", "at91_ohci", &uhphs_clk),
 	CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk),
diff --git a/arch/arm/mach-at91/at91sam9n12.c b/arch/arm/mach-at91/at91sam9n12.c
index 5dfc8fd..ccd0783 100644
--- a/arch/arm/mach-at91/at91sam9n12.c
+++ b/arch/arm/mach-at91/at91sam9n12.c
@@ -172,6 +172,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID("dma_clk", "ffffec00.dma-controller", &dma_clk),
 	CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
 	CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
+	CLKDEV_CON_DEV_ID("spi_clk", "f0000000.spi", &spi0_clk),
+	CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi1_clk),
 	CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
 	CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
 	CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
diff --git a/arch/arm/mach-at91/at91sam9x5.c b/arch/arm/mach-at91/at91sam9x5.c
index 44a9a62..a200d8a 100644
--- a/arch/arm/mach-at91/at91sam9x5.c
+++ b/arch/arm/mach-at91/at91sam9x5.c
@@ -237,6 +237,8 @@ static struct clk_lookup periph_clocks_lookups[] = {
 	CLKDEV_CON_DEV_ID(NULL, "f8010000.i2c", &twi0_clk),
 	CLKDEV_CON_DEV_ID(NULL, "f8014000.i2c", &twi1_clk),
 	CLKDEV_CON_DEV_ID(NULL, "f8018000.i2c", &twi2_clk),
+	CLKDEV_CON_DEV_ID("spi_clk", "f0000000.spi", &spi0_clk),
+	CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi1_clk),
 	CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioAB_clk),
 	CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioAB_clk),
 	CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioCD_clk),
-- 
1.7.9.5

[PATCH v8 6/8] ARM: dts: add spi nodes for atmel SoC

[Wenyou Yang]

From: Richard Genoud <richard.genoud-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

Signed-off-by: Richard Genoud <richard.genoud-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
[wenyou.yang-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org: add spi nodes for sam9260, sam9263, sam9g45 and sam9n12]
[wenyou.yang-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org: remove spi property "cs-gpios" to the board dts files]
[wenyou.yang-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org: submit the patch]
Signed-off-by: Wenyou Yang <wenyou.yang-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
Cc: linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
 arch/arm/boot/dts/at91sam9260.dtsi |   18 ++++++++++++++++++
 arch/arm/boot/dts/at91sam9263.dtsi |   18 ++++++++++++++++++
 arch/arm/boot/dts/at91sam9g45.dtsi |   18 ++++++++++++++++++
 arch/arm/boot/dts/at91sam9n12.dtsi |   18 ++++++++++++++++++
 arch/arm/boot/dts/at91sam9x5.dtsi  |   18 ++++++++++++++++++
 5 files changed, 90 insertions(+)

diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index cb7bcc5..6e31dc8 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -471,6 +471,24 @@
 				status = "disabled";
 			};
 
+			spi0: spi@fffc8000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "atmel,at91rm9200-spi";
+				reg = <0xfffc8000 0x200>;
+				interrupts = <12 4 3>;
+				status = "disabled";
+			};
+
+			spi1: spi@fffcc000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "atmel,at91rm9200-spi";
+				reg = <0xfffcc000 0x200>;
+				interrupts = <13 4 3>;
+				status = "disabled";
+			};
+
 			adc0: adc@fffe0000 {
 				compatible = "atmel,at91sam9260-adc";
 				reg = <0xfffe0000 0x100>;
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 271d4de..6c6d9ae 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -462,6 +462,24 @@
 				reg = <0xfffffd40 0x10>;
 				status = "disabled";
 			};
+
+			spi0: spi@fffa4000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "atmel,at91rm9200-spi";
+				reg = <0xfffa4000 0x200>;
+				interrupts = <14 4 3>;
+				status = "disabled";
+			};
+
+			spi1: spi@fffa8000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "atmel,at91rm9200-spi";
+				reg = <0xfffa8000 0x200>;
+				interrupts = <15 4 3>;
+				status = "disabled";
+			};
 		};
 
 		nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index 6b1d4ca..e085b8a 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -531,6 +531,24 @@
 				reg = <0xfffffd40 0x10>;
 				status = "disabled";
 			};
+
+			spi0: spi@fffa4000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "atmel,at91rm9200-spi";
+				reg = <0xfffa4000 0x200>;
+				interrupts = <14 4 3>;
+				status = "disabled";
+			};
+
+			spi1: spi@fffa8000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "atmel,at91rm9200-spi";
+				reg = <0xfffa8000 0x200>;
+				interrupts = <15 4 3>;
+				status = "disabled";
+			};
 		};
 
 		nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index 7750f98..f3f87ef3 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -373,6 +373,24 @@
 				#size-cells = <0>;
 				status = "disabled";
 			};
+
+			spi0: spi@f0000000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "atmel,at91rm9200-spi";
+				reg = <0xf0000000 0x100>;
+				interrupts = <13 4 3>;
+				status = "disabled";
+			};
+
+			spi1: spi@f0004000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "atmel,at91rm9200-spi";
+				reg = <0xf0004000 0x100>;
+				interrupts = <14 4 3>;
+				status = "disabled";
+			};
 		};
 
 		nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index a98c0d5..77ce2e1 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -529,6 +529,24 @@
 					trigger-value = <0x6>;
 				};
 			};
+
+			spi0: spi@f0000000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "atmel,at91rm9200-spi";
+				reg = <0xf0000000 0x100>;
+				interrupts = <13 4 3>;
+				status = "disabled";
+			};
+
+			spi1: spi@f0004000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "atmel,at91rm9200-spi";
+				reg = <0xf0004000 0x100>;
+				interrupts = <14 4 3>;
+				status = "disabled";
+			};
 		};
 
 		nand0: nand@40000000 {
-- 
1.7.9.5


------------------------------------------------------------------------------
Minimize network downtime and maximize team effectiveness.
Reduce network management and security costs.Learn how to hire 
the most talented Cisco Certified professionals. Visit the 
Employer Resources Portal
http://www.cisco.com/web/learning/employer_resources/index.html

[PATCH v8 7/8] ARM: dts: add spi nodes for the atmel boards

[Wenyou Yang]

From: Richard Genoud <richard.genoud-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

Signed-off-by: Richard Genoud <richard.genoud-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
[wenyou.yang-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org: added spi nodes for the sam9263ek, sam9g20ek, sam9m10g45ek and sam9n12ek boards]
[wenyou.yang-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org: submit the patch]
Signed-off-by: Wenyou Yang <wenyou.yang-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
Cc: linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
---
 arch/arm/boot/dts/at91sam9263ek.dts         |   10 ++++++++++
 arch/arm/boot/dts/at91sam9g20ek_common.dtsi |   10 ++++++++++
 arch/arm/boot/dts/at91sam9m10g45ek.dts      |   10 ++++++++++
 arch/arm/boot/dts/at91sam9n12ek.dts         |   10 ++++++++++
 arch/arm/boot/dts/at91sam9x5ek.dtsi         |   10 ++++++++++
 5 files changed, 50 insertions(+)

diff --git a/arch/arm/boot/dts/at91sam9263ek.dts b/arch/arm/boot/dts/at91sam9263ek.dts
index 1eb0872..a14e424 100644
--- a/arch/arm/boot/dts/at91sam9263ek.dts
+++ b/arch/arm/boot/dts/at91sam9263ek.dts
@@ -79,6 +79,16 @@
 					};
 				};
 			};
+
+			spi0: spi@fffa4000 {
+				status = "okay";
+				cs-gpios = <&pioA 5 0>, <0>, <0>, <0>;
+				mtd_dataflash@0 {
+					compatible = "atmel,at45", "atmel,dataflash";
+					spi-max-frequency = <50000000>;
+					reg = <0>;
+				};
+			};
 		};
 
 		nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
index da15e83..23d1f46 100644
--- a/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
+++ b/arch/arm/boot/dts/at91sam9g20ek_common.dtsi
@@ -96,6 +96,16 @@
 				status = "okay";
 				pinctrl-0 = <&pinctrl_ssc0_tx>;
 			};
+
+			spi0: spi@fffc8000 {
+				status = "okay";
+				cs-gpios = <0>, <&pioC 11 0>, <0>, <0>;
+				mtd_dataflash@0 {
+					compatible = "atmel,at45", "atmel,dataflash";
+					spi-max-frequency = <50000000>;
+					reg = <1>;
+				};
+			};
 		};
 
 		nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9m10g45ek.dts b/arch/arm/boot/dts/at91sam9m10g45ek.dts
index 20c3191..92c52a7 100644
--- a/arch/arm/boot/dts/at91sam9m10g45ek.dts
+++ b/arch/arm/boot/dts/at91sam9m10g45ek.dts
@@ -102,6 +102,16 @@
 					};
 				};
 			};
+
+			spi0: spi@fffa4000{
+				status = "okay";
+				cs-gpios = <&pioB 3 0>, <0>, <0>, <0>;
+				mtd_dataflash@0 {
+					compatible = "atmel,at45", "atmel,dataflash";
+					spi-max-frequency = <13000000>;
+					reg = <0>;
+				};
+			};
 		};
 
 		nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9n12ek.dts b/arch/arm/boot/dts/at91sam9n12ek.dts
index d400f8d..34c842b 100644
--- a/arch/arm/boot/dts/at91sam9n12ek.dts
+++ b/arch/arm/boot/dts/at91sam9n12ek.dts
@@ -67,6 +67,16 @@
 					};
 				};
 			};
+
+			spi0: spi@f0000000 {
+				status = "okay";
+				cs-gpios = <&pioA 14 0>, <0>, <0>, <0>;
+				m25p80@0 {
+					compatible = "atmel,at25df321a";
+					spi-max-frequency = <50000000>;
+					reg = <0>;
+				};
+			};
 		};
 
 		nand0: nand@40000000 {
diff --git a/arch/arm/boot/dts/at91sam9x5ek.dtsi b/arch/arm/boot/dts/at91sam9x5ek.dtsi
index 8a7cf1d..09f5e66 100644
--- a/arch/arm/boot/dts/at91sam9x5ek.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5ek.dtsi
@@ -84,6 +84,16 @@
 					};
 				};
 			};
+
+			spi0: spi@f0000000 {
+				status = "okay";
+				cs-gpios = <&pioA 14 0>, <0>, <0>, <0>;
+				m25p80@0 {
+					compatible = "atmel,at25df321a";
+					spi-max-frequency = <50000000>;
+					reg = <0>;
+				};
+			};
 		};
 
 		usb0: ohci@00600000 {
-- 
1.7.9.5


------------------------------------------------------------------------------
Minimize network downtime and maximize team effectiveness.
Reduce network management and security costs.Learn how to hire 
the most talented Cisco Certified professionals. Visit the 
Employer Resources Portal
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[PATCH v8 8/8] ARM: dts: add pinctrl property for spi node for atmel SoC

[Wenyou Yang]

Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
Cc: linux@arm.linux.org.uk
Cc: linux-kernel@vger.kernel.org
---
 arch/arm/boot/dts/at91sam9260.dtsi |   22 ++++++++++++++++++++++
 arch/arm/boot/dts/at91sam9263.dtsi |   22 ++++++++++++++++++++++
 arch/arm/boot/dts/at91sam9g45.dtsi |   22 ++++++++++++++++++++++
 arch/arm/boot/dts/at91sam9n12.dtsi |   22 ++++++++++++++++++++++
 arch/arm/boot/dts/at91sam9x5.dtsi  |   22 ++++++++++++++++++++++
 5 files changed, 110 insertions(+)

diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
index 6e31dc8..39253b9 100644
--- a/arch/arm/boot/dts/at91sam9260.dtsi
+++ b/arch/arm/boot/dts/at91sam9260.dtsi
@@ -322,6 +322,24 @@
 					};
 				};
 
+				spi0 {
+					pinctrl_spi0: spi0-0 {
+						atmel,pins =
+							<0 0 0x1 0x0	/* PA0 periph A SPI0_MISO pin */
+							 0 1 0x1 0x0	/* PA1 periph A SPI0_MOSI pin */
+							 0 2 0x1 0x0>;	/* PA2 periph A SPI0_SPCK pin */
+					};
+				};
+
+				spi1 {
+					pinctrl_spi1: spi1-0 {
+						atmel,pins =
+							<1 0 0x1 0x0	/* PB0 periph A SPI1_MISO pin */
+							 1 1 0x1 0x0	/* PB1 periph A SPI1_MOSI pin */
+							 1 2 0x1 0x0>;	/* PB2 periph A SPI1_SPCK pin */
+					};
+				};
+
 				pioA: gpio@fffff400 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff400 0x200>;
@@ -477,6 +495,8 @@
 				compatible = "atmel,at91rm9200-spi";
 				reg = <0xfffc8000 0x200>;
 				interrupts = <12 4 3>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_spi0>;
 				status = "disabled";
 			};
 
@@ -486,6 +506,8 @@
 				compatible = "atmel,at91rm9200-spi";
 				reg = <0xfffcc000 0x200>;
 				interrupts = <13 4 3>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_spi1>;
 				status = "disabled";
 			};
 
diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
index 6c6d9ae..94b58ab 100644
--- a/arch/arm/boot/dts/at91sam9263.dtsi
+++ b/arch/arm/boot/dts/at91sam9263.dtsi
@@ -303,6 +303,24 @@
 					};
 				};
 
+				spi0 {
+					pinctrl_spi0: spi0-0 {
+						atmel,pins =
+							<0 0 0x2 0x0	/* PA0 periph B SPI0_MISO pin */
+							 0 1 0x2 0x0	/* PA1 periph B SPI0_MOSI pin */
+							 0 2 0x2 0x0>;	/* PA2 periph B SPI0_SPCK pin */
+					};
+				};
+
+				spi1 {
+					pinctrl_spi1: spi1-0 {
+						atmel,pins =
+							<1 12 0x1 0x0	/* PB12 periph A SPI1_MISO pin */
+							 1 13 0x1 0x0	/* PB13 periph A SPI1_MOSI pin */
+							 1 14 0x1 0x0>;	/* PB14 periph A SPI1_SPCK pin */
+					};
+				};
+
 				pioA: gpio@fffff200 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff200 0x200>;
@@ -469,6 +487,8 @@
 				compatible = "atmel,at91rm9200-spi";
 				reg = <0xfffa4000 0x200>;
 				interrupts = <14 4 3>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_spi0>;
 				status = "disabled";
 			};
 
@@ -478,6 +498,8 @@
 				compatible = "atmel,at91rm9200-spi";
 				reg = <0xfffa8000 0x200>;
 				interrupts = <15 4 3>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_spi1>;
 				status = "disabled";
 			};
 		};
diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
index e085b8a..cfdf429 100644
--- a/arch/arm/boot/dts/at91sam9g45.dtsi
+++ b/arch/arm/boot/dts/at91sam9g45.dtsi
@@ -322,6 +322,24 @@
 					};
 				};
 
+				spi0 {
+					pinctrl_spi0: spi0-0 {
+						atmel,pins =
+							<1 0 0x1 0x0	/* PB0 periph A SPI0_MISO pin */
+							 1 1 0x1 0x0	/* PB1 periph A SPI0_MOSI pin */
+							 1 2 0x1 0x0>;	/* PB2 periph A SPI0_SPCK pin */
+					};
+				};
+
+				spi1 {
+					pinctrl_spi1: spi1-0 {
+						atmel,pins =
+							<1 14 0x1 0x0	/* PB14 periph A SPI1_MISO pin */
+							 1 15 0x1 0x0	/* PB15 periph A SPI1_MOSI pin */
+							 1 16 0x1 0x0>;	/* PB16 periph A SPI1_SPCK pin */
+					};
+				};
+
 				pioA: gpio@fffff200 {
 					compatible = "atmel,at91rm9200-gpio";
 					reg = <0xfffff200 0x200>;
@@ -538,6 +556,8 @@
 				compatible = "atmel,at91rm9200-spi";
 				reg = <0xfffa4000 0x200>;
 				interrupts = <14 4 3>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_spi0>;
 				status = "disabled";
 			};
 
@@ -547,6 +567,8 @@
 				compatible = "atmel,at91rm9200-spi";
 				reg = <0xfffa8000 0x200>;
 				interrupts = <15 4 3>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_spi1>;
 				status = "disabled";
 			};
 		};
diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
index f3f87ef3..b2961f1 100644
--- a/arch/arm/boot/dts/at91sam9n12.dtsi
+++ b/arch/arm/boot/dts/at91sam9n12.dtsi
@@ -261,6 +261,24 @@
 					};
 				};
 
+				spi0 {
+					pinctrl_spi0: spi0-0 {
+						atmel,pins =
+							<0 11 0x1 0x0	/* PA11 periph A SPI0_MISO pin */
+							 0 12 0x1 0x0	/* PA12 periph A SPI0_MOSI pin */
+							 0 13 0x1 0x0>;	/* PA13 periph A SPI0_SPCK pin */
+					};
+				};
+
+				spi1 {
+					pinctrl_spi1: spi1-0 {
+						atmel,pins =
+							<0 21 0x2 0x0	/* PA21 periph B SPI1_MISO pin */
+							 0 22 0x2 0x0	/* PA22 periph B SPI1_MOSI pin */
+							 0 23 0x2 0x0>;	/* PA23 periph B SPI1_SPCK pin */
+					};
+				};
+
 				pioA: gpio@fffff400 {
 					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 					reg = <0xfffff400 0x200>;
@@ -380,6 +398,8 @@
 				compatible = "atmel,at91rm9200-spi";
 				reg = <0xf0000000 0x100>;
 				interrupts = <13 4 3>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_spi0>;
 				status = "disabled";
 			};
 
@@ -389,6 +409,8 @@
 				compatible = "atmel,at91rm9200-spi";
 				reg = <0xf0004000 0x100>;
 				interrupts = <14 4 3>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_spi1>;
 				status = "disabled";
 			};
 		};
diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
index 77ce2e1..347b438 100644
--- a/arch/arm/boot/dts/at91sam9x5.dtsi
+++ b/arch/arm/boot/dts/at91sam9x5.dtsi
@@ -343,6 +343,24 @@
 					};
 				};
 
+				spi0 {
+					pinctrl_spi0: spi0-0 {
+						atmel,pins =
+							<0 11 0x1 0x0	/* PA11 periph A SPI0_MISO pin */
+							 0 12 0x1 0x0	/* PA12 periph A SPI0_MOSI pin */
+							 0 13 0x1 0x0>;	/* PA13 periph A SPI0_SPCK pin */
+					};
+				};
+
+				spi1 {
+					pinctrl_spi1: spi1-0 {
+						atmel,pins =
+							<0 21 0x2 0x0	/* PA21 periph B SPI1_MISO pin */
+							 0 22 0x2 0x0	/* PA22 periph B SPI1_MOSI pin */
+							 0 23 0x2 0x0>;	/* PA23 periph B SPI1_SPCK pin */
+					};
+				};
+
 				pioA: gpio@fffff400 {
 					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
 					reg = <0xfffff400 0x200>;
@@ -536,6 +554,8 @@
 				compatible = "atmel,at91rm9200-spi";
 				reg = <0xf0000000 0x100>;
 				interrupts = <13 4 3>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_spi0>;
 				status = "disabled";
 			};
 
@@ -545,6 +565,8 @@
 				compatible = "atmel,at91rm9200-spi";
 				reg = <0xf0004000 0x100>;
 				interrupts = <14 4 3>;
+				pinctrl-names = "default";
+				pinctrl-0 = <&pinctrl_spi1>;
 				status = "disabled";
 			};
 		};
-- 
1.7.9.5

Re: [PATCH v8 1/8] spi/spi-atmel: add physical base address

[Richard GENOUD]

On [mer., 03.04.2013 13:57:42], Wenyou Yang wrote:
> From: Nicolas Ferre <nicolas.ferre-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
> 
> Needed for future use with dmaengine enabled driver.
> 
> Signed-off-by: Nicolas Ferre <nicolas.ferre-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
> Cc: spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org
> Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> [wenyou.yang-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org: submit the patch]
> Signed-off-by: Wenyou Yang <wenyou.yang-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
> ---
>  drivers/spi/spi-atmel.c |    2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
> index 15e8459..38f8c0d 100644
> --- a/drivers/spi/spi-atmel.c
> +++ b/drivers/spi/spi-atmel.c
> @@ -196,6 +196,7 @@ struct atmel_spi_caps {
>  struct atmel_spi {
>  	spinlock_t		lock;
>  
> +	phys_addr_t		phybase;
>  	void __iomem		*regs;
>  	int			irq;
>  	struct clk		*clk;
> @@ -996,6 +997,7 @@ static int atmel_spi_probe(struct platform_device *pdev)
>  	as->regs = ioremap(regs->start, resource_size(regs));
>  	if (!as->regs)
>  		goto out_free_buffer;
> +	as->phybase = regs->start;
>  	as->irq = irq;
>  	as->clk = clk;
>  
> -- 
> 1.7.9.5
> 
Tested-by: Richard Genoud <richard.genoud-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

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Re: [PATCH v8 2/8] spi/spi-atmel: add flag to controller data for lock operations

[Richard GENOUD]

On [mer., 03.04.2013 13:58:36], Wenyou Yang wrote:
> From: Nicolas Ferre <nicolas.ferre-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
> 
> Will allow to drop the lock during DMA operations.
> 
> Replacing non-irqsave versions with irqsave versions of the lock
> to make it correct in both pdc and dmaengine transfer mode
> 
> Signed-off-by: Nicolas Ferre <nicolas.ferre-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
> Cc: spi-devel-general-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f@public.gmane.org
> Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> [wenyou.yang-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org: submit the patch]
> Signed-off-by: Wenyou Yang <wenyou.yang-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
> ---
>  drivers/spi/spi-atmel.c |   35 +++++++++++++++++++++--------------
>  1 file changed, 21 insertions(+), 14 deletions(-)
> 
> diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
> index 38f8c0d..2df562f 100644
> --- a/drivers/spi/spi-atmel.c
> +++ b/drivers/spi/spi-atmel.c
> @@ -195,6 +195,7 @@ struct atmel_spi_caps {
>   */
>  struct atmel_spi {
>  	spinlock_t		lock;
> +	unsigned long		flags;
>  
>  	phys_addr_t		phybase;
>  	void __iomem		*regs;
> @@ -333,6 +334,16 @@ static void cs_deactivate(struct atmel_spi *as, struct spi_device *spi)
>  		gpio_set_value(asd->npcs_pin, !active);
>  }
>  
> +static void atmel_spi_lock(struct atmel_spi *as)
> +{
> +	spin_lock_irqsave(&as->lock, as->flags);
> +}
> +
> +static void atmel_spi_unlock(struct atmel_spi *as)
> +{
> +	spin_unlock_irqrestore(&as->lock, as->flags);
> +}
> +
>  static inline int atmel_spi_xfer_is_last(struct spi_message *msg,
>  					struct spi_transfer *xfer)
>  {
> @@ -569,9 +580,9 @@ atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
>  		"xfer complete: %u bytes transferred\n",
>  		msg->actual_length);
>  
> -	spin_unlock(&as->lock);
> +	atmel_spi_unlock(as);
>  	msg->complete(msg->context);
> -	spin_lock(&as->lock);
> +	atmel_spi_lock(as);
>  
>  	as->current_transfer = NULL;
>  	as->next_transfer = NULL;
> @@ -594,7 +605,7 @@ atmel_spi_interrupt(int irq, void *dev_id)
>  	u32			status, pending, imr;
>  	int			ret = IRQ_NONE;
>  
> -	spin_lock(&as->lock);
> +	atmel_spi_lock(as);
>  
>  	xfer = as->current_transfer;
>  	msg = list_entry(as->queue.next, struct spi_message, queue);
> @@ -697,7 +708,7 @@ atmel_spi_interrupt(int irq, void *dev_id)
>  		}
>  	}
>  
> -	spin_unlock(&as->lock);
> +	atmel_spi_unlock(as);
>  
>  	return ret;
>  }
> @@ -802,13 +813,11 @@ static int atmel_spi_setup(struct spi_device *spi)
>  		spi->controller_state = asd;
>  		gpio_direction_output(npcs_pin, !(spi->mode & SPI_CS_HIGH));
>  	} else {
> -		unsigned long		flags;
> -
> -		spin_lock_irqsave(&as->lock, flags);
> +		atmel_spi_lock(as);
>  		if (as->stay == spi)
>  			as->stay = NULL;
>  		cs_deactivate(as, spi);
> -		spin_unlock_irqrestore(&as->lock, flags);
> +		atmel_spi_unlock(as);
>  	}
>  
>  	asd->csr = csr;
> @@ -827,7 +836,6 @@ static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
>  {
>  	struct atmel_spi	*as;
>  	struct spi_transfer	*xfer;
> -	unsigned long		flags;
>  	struct device		*controller = spi->master->dev.parent;
>  	u8			bits;
>  	struct atmel_spi_device	*asd;
> @@ -892,11 +900,11 @@ static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
>  	msg->status = -EINPROGRESS;
>  	msg->actual_length = 0;
>  
> -	spin_lock_irqsave(&as->lock, flags);
> +	atmel_spi_lock(as);
>  	list_add_tail(&msg->queue, &as->queue);
>  	if (!as->current_transfer)
>  		atmel_spi_next_message(spi->master);
> -	spin_unlock_irqrestore(&as->lock, flags);
> +	atmel_spi_unlock(as);
>  
>  	return 0;
>  }
> @@ -906,17 +914,16 @@ static void atmel_spi_cleanup(struct spi_device *spi)
>  	struct atmel_spi	*as = spi_master_get_devdata(spi->master);
>  	struct atmel_spi_device	*asd = spi->controller_state;
>  	unsigned		gpio = (unsigned) spi->controller_data;
> -	unsigned long		flags;
>  
>  	if (!asd)
>  		return;
>  
> -	spin_lock_irqsave(&as->lock, flags);
> +	atmel_spi_lock(as);
>  	if (as->stay == spi) {
>  		as->stay = NULL;
>  		cs_deactivate(as, spi);
>  	}
> -	spin_unlock_irqrestore(&as->lock, flags);
> +	atmel_spi_unlock(as);
>  
>  	spi->controller_state = NULL;
>  	gpio_free(gpio);
> -- 
> 1.7.9.5
>
On sam9g35 with DMA and PIO (3.9-rc5 + device tree patches)
Tested-by: Richard Genoud <richard.genoud-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

------------------------------------------------------------------------------
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Reduce network management and security costs.Learn how to hire 
the most talented Cisco Certified professionals. Visit the 
Employer Resources Portal
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Re: [PATCH v8 3/8] spi/spi-atmel: add dmaengine support

[Richard GENOUD]

On [mer., 03.04.2013 13:59:19], Wenyou Yang wrote:
> From: Nicolas Ferre <nicolas.ferre-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
> 
> Add dmaengine support.
> 
> Using "has_dma_support" member of struct is used to select
> the transfer mode: dmaengine or pdc.
> 
> For the dmaengine transfer mode, it supports both 8 bits and 16 bits transfer.
> 
> For the dmaengine transfer mode, if it fails to config dmaengine,
> or if the message length is less than 16 bytes, it will use the PIO transfer mode.
> 
> Signed-off-by: Nicolas Ferre <nicolas.ferre-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
> [wenyou.yang-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org: using "has_dma_support" to select dmaengine as the spi xfer mode]
> [wenyou.yang-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org: fix DMA: OOPS if buffer > 4096 bytes]
> [wenyou.yang-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org: submit the patch]
> Signed-off-by: Wenyou Yang <wenyou.yang-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
> Cc: richard.genoud-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
> Cc: spi-devel-general-5NWGOfrQmneRv+LV9MX5uv+2+P5yyue3@public.gmane.org
> Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> [richard.genoud-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org: update with dmaengine interface]
> [richard.genoud-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org: fix __init/__devinit sections mismatch]
> [richard.genoud-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org: adapt to slave_config changes]
> [richard.genoud-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org: add support t0 16 bits transfer]
> ---
> This patch is based on the original patch from Nicolas
> 	- add dmaengine support
> and squash the below patches from Richard Genoud <richard.genoud-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> 	- update with dmaengine interface
> 	- fix __init/__devinit sections mismatch
> 	- fix spi-atmel driver to adapt to slave_config changes
> 	- correct 16 bits transfers with DMA
> 
> Hi, Richard,
> 
> Could you sign your signature in this patch?
> 
> Best Regards,
> Wenyou Yang
> 
>  drivers/spi/spi-atmel.c |  587 +++++++++++++++++++++++++++++++++++++++++++++--
>  1 file changed, 566 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/spi/spi-atmel.c b/drivers/spi/spi-atmel.c
> index 2df562f..759d83a 100644
> --- a/drivers/spi/spi-atmel.c
> +++ b/drivers/spi/spi-atmel.c
> @@ -15,11 +15,13 @@
>  #include <linux/platform_device.h>
>  #include <linux/delay.h>
>  #include <linux/dma-mapping.h>
> +#include <linux/dmaengine.h>
>  #include <linux/err.h>
>  #include <linux/interrupt.h>
>  #include <linux/spi/spi.h>
>  #include <linux/slab.h>
>  #include <linux/platform_data/atmel.h>
> +#include <linux/platform_data/dma-atmel.h>
>  #include <linux/of.h>
>  
>  #include <linux/io.h>
> @@ -182,6 +184,22 @@
>  #define spi_writel(port,reg,value) \
>  	__raw_writel((value), (port)->regs + SPI_##reg)
>  
> +/* use PIO for small transfers, avoiding DMA setup/teardown overhead and
> + * cache operations; better heuristics consider wordsize and bitrate.
> + */
> +#define DMA_MIN_BYTES	16
> +
> +struct atmel_spi_dma {
> +	struct dma_chan			*chan_rx;
> +	struct dma_chan			*chan_tx;
> +	struct scatterlist		sgrx;
> +	struct scatterlist		sgtx;
> +	struct dma_async_tx_descriptor	*data_desc_rx;
> +	struct dma_async_tx_descriptor	*data_desc_tx;
> +
> +	struct at_dma_slave	dma_slave;
> +};
> +
>  struct atmel_spi_caps {
>  	bool	is_spi2;
>  	bool	has_wdrbt;
> @@ -206,16 +224,23 @@ struct atmel_spi {
>  
>  	u8			stopping;
>  	struct list_head	queue;
> +	struct tasklet_struct	tasklet;
>  	struct spi_transfer	*current_transfer;
>  	unsigned long		current_remaining_bytes;
>  	struct spi_transfer	*next_transfer;
>  	unsigned long		next_remaining_bytes;
>  	int			done_status;
>  
> +	/* scratch buffer */
>  	void			*buffer;
>  	dma_addr_t		buffer_dma;
>  
>  	struct atmel_spi_caps	caps;
> +
> +	bool			use_dma;
> +	bool			use_pdc;
> +	/* dmaengine data */
> +	struct atmel_spi_dma	dma;
>  };
>  
>  /* Controller-specific per-slave state */
> @@ -284,6 +309,7 @@ static void cs_activate(struct atmel_spi *as, struct spi_device *spi)
>  					| SPI_BIT(MODFDIS)
>  					| SPI_BIT(MSTR));
>  		}
> +
>  		mr = spi_readl(as, MR);
>  		gpio_set_value(asd->npcs_pin, active);
>  	} else {
> @@ -344,6 +370,12 @@ static void atmel_spi_unlock(struct atmel_spi *as)
>  	spin_unlock_irqrestore(&as->lock, as->flags);
>  }
>  
> +static inline bool atmel_spi_use_dma(struct atmel_spi *as,
> +				struct spi_transfer *xfer)
> +{
> +	return as->use_dma && xfer->len >= DMA_MIN_BYTES;
> +}
> +
>  static inline int atmel_spi_xfer_is_last(struct spi_message *msg,
>  					struct spi_transfer *xfer)
>  {
> @@ -355,6 +387,265 @@ static inline int atmel_spi_xfer_can_be_chained(struct spi_transfer *xfer)
>  	return xfer->delay_usecs == 0 && !xfer->cs_change;
>  }
>  
> +static int atmel_spi_dma_slave_config(struct atmel_spi *as,
> +				struct dma_slave_config *slave_config,
> +				u8 bits_per_word)
> +{
> +	int err = 0;
> +
> +	if (bits_per_word > 8) {
> +		slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
> +		slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
> +	} else {
> +		slave_config->dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
> +		slave_config->src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
> +	}
> +
> +	slave_config->dst_addr = (dma_addr_t)as->phybase + SPI_TDR;
> +	slave_config->src_addr = (dma_addr_t)as->phybase + SPI_RDR;
> +	slave_config->src_maxburst = 1;
> +	slave_config->dst_maxburst = 1;
> +	slave_config->device_fc = false;
> +
> +	slave_config->direction = DMA_MEM_TO_DEV;
> +	if (dmaengine_slave_config(as->dma.chan_tx, slave_config)) {
> +		dev_err(&as->pdev->dev,
> +			"failed to configure tx dma channel\n");
> +		err = -EINVAL;
> +	}
> +
> +	slave_config->direction = DMA_DEV_TO_MEM;
> +	if (dmaengine_slave_config(as->dma.chan_rx, slave_config)) {
> +		dev_err(&as->pdev->dev,
> +			"failed to configure rx dma channel\n");
> +		err = -EINVAL;
> +	}
> +
> +	return err;
> +}
> +
> +static bool filter(struct dma_chan *chan, void *slave)
> +{
> +	struct	at_dma_slave *sl = slave;
> +
> +	if (sl->dma_dev == chan->device->dev) {
> +		chan->private = sl;
> +		return true;
> +	} else {
> +		return false;
> +	}
> +}
> +
> +static int atmel_spi_configure_dma(struct atmel_spi *as)
> +{
> +	struct at_dma_slave *sdata = &as->dma.dma_slave;
> +	struct dma_slave_config	slave_config;
> +	int err;
> +
> +	if (sdata && sdata->dma_dev) {
> +		dma_cap_mask_t mask;
> +
> +		/* Try to grab two DMA channels */
> +		dma_cap_zero(mask);
> +		dma_cap_set(DMA_SLAVE, mask);
> +		as->dma.chan_tx = dma_request_channel(mask, filter, sdata);
> +		if (as->dma.chan_tx)
> +			as->dma.chan_rx =
> +				dma_request_channel(mask, filter, sdata);
> +	}
> +	if (!as->dma.chan_rx || !as->dma.chan_tx) {
> +		dev_err(&as->pdev->dev,
> +			"DMA channel not available, SPI unable to use DMA\n");
> +		err = -EBUSY;
> +		goto error;
> +	}
> +
> +	err = atmel_spi_dma_slave_config(as, &slave_config, 8);
> +	if (err)
> +		goto error;
> +
> +	dev_info(&as->pdev->dev,
> +			"Using %s (tx) and %s (rx) for DMA transfers\n",
> +			dma_chan_name(as->dma.chan_tx),
> +			dma_chan_name(as->dma.chan_rx));
> +	return 0;
> +error:
> +	if (as->dma.chan_rx)
> +		dma_release_channel(as->dma.chan_rx);
> +	if (as->dma.chan_tx)
> +		dma_release_channel(as->dma.chan_tx);
> +	return err;
> +}
> +
> +static void atmel_spi_stop_dma(struct atmel_spi *as)
> +{
> +	if (as->dma.chan_rx)
> +		as->dma.chan_rx->device->device_control(as->dma.chan_rx,
> +							DMA_TERMINATE_ALL, 0);
> +	if (as->dma.chan_tx)
> +		as->dma.chan_tx->device->device_control(as->dma.chan_tx,
> +							DMA_TERMINATE_ALL, 0);
> +}
> +
> +static void atmel_spi_release_dma(struct atmel_spi *as)
> +{
> +	if (as->dma.chan_rx)
> +		dma_release_channel(as->dma.chan_rx);
> +	if (as->dma.chan_tx)
> +		dma_release_channel(as->dma.chan_tx);
> +}
> +
> +/* This function is called by the DMA driver from tasklet context */
> +static void dma_callback(void *data)
> +{
> +	struct spi_master	*master = data;
> +	struct atmel_spi	*as = spi_master_get_devdata(master);
> +
> +	/* trigger SPI tasklet */
> +	tasklet_schedule(&as->tasklet);
> +}
> +
> +/*
> + * Next transfer using PIO.
> + * lock is held, spi tasklet is blocked
> + */
> +static void atmel_spi_next_xfer_pio(struct spi_master *master,
> +				struct spi_transfer *xfer)
> +{
> +	struct atmel_spi	*as = spi_master_get_devdata(master);
> +
> +	dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_pio\n");
> +
> +	as->current_remaining_bytes = xfer->len;
> +
> +	/* Make sure data is not remaining in RDR */
> +	spi_readl(as, RDR);
> +	while (spi_readl(as, SR) & SPI_BIT(RDRF)) {
> +		spi_readl(as, RDR);
> +		cpu_relax();
> +	}
> +
> +	if (xfer->tx_buf)
> +		spi_writel(as, TDR, *(u8 *)(xfer->tx_buf));
> +	else
> +		spi_writel(as, TDR, 0);
> +
> +	dev_dbg(master->dev.parent,
> +		"  start pio xfer %p: len %u tx %p rx %p\n",
> +		xfer, xfer->len, xfer->tx_buf, xfer->rx_buf);
> +
> +	/* Enable relevant interrupts */
> +	spi_writel(as, IER, SPI_BIT(RDRF) | SPI_BIT(OVRES));
> +}
> +
> +/*
> + * Submit next transfer for DMA.
> + * lock is held, spi tasklet is blocked
> + */
> +static int atmel_spi_next_xfer_dma_submit(struct spi_master *master,
> +				struct spi_transfer *xfer,
> +				u32 *plen)
> +{
> +	struct atmel_spi	*as = spi_master_get_devdata(master);
> +	struct dma_chan		*rxchan = as->dma.chan_rx;
> +	struct dma_chan		*txchan = as->dma.chan_tx;
> +	struct dma_async_tx_descriptor *rxdesc;
> +	struct dma_async_tx_descriptor *txdesc;
> +	struct dma_slave_config	slave_config;
> +	dma_cookie_t		cookie;
> +	u32	len = *plen;
> +
> +	dev_vdbg(master->dev.parent, "atmel_spi_next_xfer_dma_submit\n");
> +
> +	/* Check that the channels are available */
> +	if (!rxchan || !txchan)
> +		return -ENODEV;
> +
> +	/* release lock for DMA operations */
> +	atmel_spi_unlock(as);
> +
> +	/* prepare the RX dma transfer */
> +	sg_init_table(&as->dma.sgrx, 1);
> +	if (xfer->rx_buf) {
> +		as->dma.sgrx.dma_address = xfer->rx_dma + xfer->len - *plen;
> +	} else {
> +		as->dma.sgrx.dma_address = as->buffer_dma;
> +		if (len > BUFFER_SIZE)
> +			len = BUFFER_SIZE;
> +	}
> +
> +	/* prepare the TX dma transfer */
> +	sg_init_table(&as->dma.sgtx, 1);
> +	if (xfer->tx_buf) {
> +		as->dma.sgtx.dma_address = xfer->tx_dma + xfer->len - *plen;
> +	} else {
> +		as->dma.sgtx.dma_address = as->buffer_dma;
> +		if (len > BUFFER_SIZE)
> +			len = BUFFER_SIZE;
> +		memset(as->buffer, 0, len);
> +	}
> +
> +	sg_dma_len(&as->dma.sgtx) = len;
> +	sg_dma_len(&as->dma.sgrx) = len;
> +
> +	*plen = len;
> +
> +	if (atmel_spi_dma_slave_config(as, &slave_config, 8))
> +		goto err_exit;
> +
> +	/* Send both scatterlists */
> +	rxdesc = rxchan->device->device_prep_slave_sg(rxchan,
> +					&as->dma.sgrx,
> +					1,
> +					DMA_FROM_DEVICE,
> +					DMA_PREP_INTERRUPT | DMA_CTRL_ACK,
> +					NULL);
> +	if (!rxdesc)
> +		goto err_dma;
> +
> +	txdesc = txchan->device->device_prep_slave_sg(txchan,
> +					&as->dma.sgtx,
> +					1,
> +					DMA_TO_DEVICE,
> +					DMA_PREP_INTERRUPT | DMA_CTRL_ACK,
> +					NULL);
> +	if (!txdesc)
> +		goto err_dma;
> +
> +	dev_dbg(master->dev.parent,
> +		"  start dma xfer %p: len %u tx %p/%08x rx %p/%08x\n",
> +		xfer, xfer->len, xfer->tx_buf, xfer->tx_dma,
> +		xfer->rx_buf, xfer->rx_dma);
> +
> +	/* Enable relevant interrupts */
> +	spi_writel(as, IER, SPI_BIT(OVRES));
> +
> +	/* Put the callback on the RX transfer only, that should finish last */
> +	rxdesc->callback = dma_callback;
> +	rxdesc->callback_param = master;
> +
> +	/* Submit and fire RX and TX with TX last so we're ready to read! */
> +	cookie = rxdesc->tx_submit(rxdesc);
> +	if (dma_submit_error(cookie))
> +		goto err_dma;
> +	cookie = txdesc->tx_submit(txdesc);
> +	if (dma_submit_error(cookie))
> +		goto err_dma;
> +	rxchan->device->device_issue_pending(rxchan);
> +	txchan->device->device_issue_pending(txchan);
> +
> +	/* take back lock */
> +	atmel_spi_lock(as);
> +	return 0;
> +
> +err_dma:
> +	spi_writel(as, IDR, SPI_BIT(OVRES));
> +	atmel_spi_stop_dma(as);
> +err_exit:
> +	atmel_spi_lock(as);
> +	return -ENOMEM;
> +}
> +
>  static void atmel_spi_next_xfer_data(struct spi_master *master,
>  				struct spi_transfer *xfer,
>  				dma_addr_t *tx_dma,
> @@ -372,6 +663,7 @@ static void atmel_spi_next_xfer_data(struct spi_master *master,
>  		if (len > BUFFER_SIZE)
>  			len = BUFFER_SIZE;
>  	}
> +
>  	if (xfer->tx_buf)
>  		*tx_dma = xfer->tx_dma + xfer->len - *plen;
>  	else {
> @@ -387,10 +679,10 @@ static void atmel_spi_next_xfer_data(struct spi_master *master,
>  }
>  
>  /*
> - * Submit next transfer for DMA.
> + * Submit next transfer for PDC.
>   * lock is held, spi irq is blocked
>   */
> -static void atmel_spi_next_xfer(struct spi_master *master,
> +static void atmel_spi_pdc_next_xfer(struct spi_master *master,
>  				struct spi_message *msg)
>  {
>  	struct atmel_spi	*as = spi_master_get_devdata(master);
> @@ -487,6 +779,48 @@ static void atmel_spi_next_xfer(struct spi_master *master,
>  	spi_writel(as, PTCR, SPI_BIT(TXTEN) | SPI_BIT(RXTEN));
>  }
>  
> +/*
> + * Choose way to submit next transfer and start it.
> + * lock is held, spi tasklet is blocked
> + */
> +static void atmel_spi_dma_next_xfer(struct spi_master *master,
> +				struct spi_message *msg)
> +{
> +	struct atmel_spi	*as = spi_master_get_devdata(master);
> +	struct spi_transfer	*xfer;
> +	u32	remaining, len;
> +
> +	remaining = as->current_remaining_bytes;
> +	if (remaining) {
> +		xfer = as->current_transfer;
> +		len = remaining;
> +	} else {
> +		if (!as->current_transfer)
> +			xfer = list_entry(msg->transfers.next,
> +				struct spi_transfer, transfer_list);
> +		else
> +			xfer = list_entry(
> +				as->current_transfer->transfer_list.next,
> +					struct spi_transfer, transfer_list);
> +
> +		as->current_transfer = xfer;
> +		len = xfer->len;
> +	}
> +
> +	if (atmel_spi_use_dma(as, xfer)) {
> +		u32 total = len;
> +		if (!atmel_spi_next_xfer_dma_submit(master, xfer, &len)) {
> +			as->current_remaining_bytes = total - len;
> +			return;
> +		} else {
> +			dev_err(&msg->spi->dev, "unable to use DMA, fallback to PIO\n");
> +		}
> +	}
> +
> +	/* use PIO if error appened using DMA */
> +	atmel_spi_next_xfer_pio(master, xfer);
> +}
> +
>  static void atmel_spi_next_message(struct spi_master *master)
>  {
>  	struct atmel_spi	*as = spi_master_get_devdata(master);
> @@ -511,7 +845,10 @@ static void atmel_spi_next_message(struct spi_master *master)
>  	} else
>  		cs_activate(as, spi);
>  
> -	atmel_spi_next_xfer(master, msg);
> +	if (as->use_pdc)
> +		atmel_spi_pdc_next_xfer(master, msg);
> +	else
> +		atmel_spi_dma_next_xfer(master, msg);
>  }
>  
>  /*
> @@ -564,6 +901,11 @@ static void atmel_spi_dma_unmap_xfer(struct spi_master *master,
>  				 xfer->len, DMA_FROM_DEVICE);
>  }
>  
> +static void atmel_spi_disable_pdc_transfer(struct atmel_spi *as)
> +{
> +	spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
> +}
> +
>  static void
>  atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
>  		struct spi_message *msg, int stay)
> @@ -589,14 +931,183 @@ atmel_spi_msg_done(struct spi_master *master, struct atmel_spi *as,
>  	as->done_status = 0;
>  
>  	/* continue if needed */
> -	if (list_empty(&as->queue) || as->stopping)
> -		spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
> -	else
> +	if (list_empty(&as->queue) || as->stopping) {
> +		if (as->use_pdc)
> +			atmel_spi_disable_pdc_transfer(as);
> +	} else {
>  		atmel_spi_next_message(master);
> +	}
> +}
> +
> +/* Called from IRQ
> + * lock is held
> + *
> + * Must update "current_remaining_bytes" to keep track of data
> + * to transfer.
> + */
> +static void
> +atmel_spi_pump_pio_data(struct atmel_spi *as, struct spi_transfer *xfer)
> +{
> +	u8		*txp;
> +	u8		*rxp;
> +	unsigned long	xfer_pos = xfer->len - as->current_remaining_bytes;
> +
> +	if (xfer->rx_buf) {
> +		rxp = ((u8 *)xfer->rx_buf) + xfer_pos;
> +		*rxp = spi_readl(as, RDR);
> +	} else {
> +		spi_readl(as, RDR);
> +	}
> +
> +	as->current_remaining_bytes--;
> +
> +	if (as->current_remaining_bytes) {
> +		if (xfer->tx_buf) {
> +			txp = ((u8 *)xfer->tx_buf) + xfer_pos + 1;
> +			spi_writel(as, TDR, *txp);
> +		} else {
> +			spi_writel(as, TDR, 0);
> +		}
> +	}
> +}
> +
> +/* Tasklet
> + * Called from DMA callback + pio transfer and overrun IRQ.
> + */
> +static void atmel_spi_tasklet_func(unsigned long data)
> +{
> +	struct spi_master	*master = (struct spi_master *)data;
> +	struct atmel_spi	*as = spi_master_get_devdata(master);
> +	struct spi_message	*msg;
> +	struct spi_transfer	*xfer;
> +
> +	dev_vdbg(master->dev.parent, "atmel_spi_tasklet_func\n");
> +
> +	atmel_spi_lock(as);
> +
> +	xfer = as->current_transfer;
> +
> +	if (xfer == NULL)
> +		/* already been there */
> +		goto tasklet_out;
> +
> +	msg = list_entry(as->queue.next, struct spi_message, queue);
> +
> +	if (as->current_remaining_bytes == 0) {
> +		if (as->done_status < 0) {
> +			/* error happened (overrun) */
> +			if (atmel_spi_use_dma(as, xfer))
> +				atmel_spi_stop_dma(as);
> +		} else {
> +			/* only update length if no error */
> +			msg->actual_length += xfer->len;
> +		}
> +
> +		if (atmel_spi_use_dma(as, xfer))
> +			if (!msg->is_dma_mapped)
> +				atmel_spi_dma_unmap_xfer(master, xfer);
> +
> +		if (xfer->delay_usecs)
> +			udelay(xfer->delay_usecs);
> +
> +		if (atmel_spi_xfer_is_last(msg, xfer) || as->done_status < 0) {
> +			/* report completed (or erroneous) message */
> +			atmel_spi_msg_done(master, as, msg, xfer->cs_change);
> +		} else {
> +			if (xfer->cs_change) {
> +				cs_deactivate(as, msg->spi);
> +				udelay(1);
> +				cs_activate(as, msg->spi);
> +			}
> +
> +			/*
> +			 * Not done yet. Submit the next transfer.
> +			 *
> +			 * FIXME handle protocol options for xfer
> +			 */
> +			atmel_spi_dma_next_xfer(master, msg);
> +		}
> +	} else {
> +		/*
> +		 * Keep going, we still have data to send in
> +		 * the current transfer.
> +		 */
> +		atmel_spi_dma_next_xfer(master, msg);
> +	}
> +
> +tasklet_out:
> +	atmel_spi_unlock(as);
> +}
> +
> +/* Interrupt
> + *
> + * No need for locking in this Interrupt handler: done_status is the
> + * only information modified. What we need is the update of this field
> + * before tasklet runs. This is ensured by using barrier.
> + */
> +static irqreturn_t
> +atmel_spi_pio_interrupt(int irq, void *dev_id)
> +{
> +	struct spi_master	*master = dev_id;
> +	struct atmel_spi	*as = spi_master_get_devdata(master);
> +	u32			status, pending, imr;
> +	struct spi_transfer	*xfer;
> +	int			ret = IRQ_NONE;
> +
> +	imr = spi_readl(as, IMR);
> +	status = spi_readl(as, SR);
> +	pending = status & imr;
> +
> +	if (pending & SPI_BIT(OVRES)) {
> +		ret = IRQ_HANDLED;
> +		spi_writel(as, IDR, SPI_BIT(OVRES));
> +		dev_warn(master->dev.parent, "overrun\n");
> +
> +		/*
> +		 * When we get an overrun, we disregard the current
> +		 * transfer. Data will not be copied back from any
> +		 * bounce buffer and msg->actual_len will not be
> +		 * updated with the last xfer.
> +		 *
> +		 * We will also not process any remaning transfers in
> +		 * the message.
> +		 *
> +		 * All actions are done in tasklet with done_status indication
> +		 */
> +		as->done_status = -EIO;
> +		smp_wmb();
> +
> +		/* Clear any overrun happening while cleaning up */
> +		spi_readl(as, SR);
> +
> +		tasklet_schedule(&as->tasklet);
> +
> +	} else if (pending & SPI_BIT(RDRF)) {
> +		atmel_spi_lock(as);
> +
> +		if (as->current_remaining_bytes) {
> +			ret = IRQ_HANDLED;
> +			xfer = as->current_transfer;
> +			atmel_spi_pump_pio_data(as, xfer);
> +			if (!as->current_remaining_bytes) {
> +				/* no more data to xfer, kick tasklet */
> +				spi_writel(as, IDR, pending);
> +				tasklet_schedule(&as->tasklet);
> +			}
> +		}
> +
> +		atmel_spi_unlock(as);
> +	} else {
> +		WARN_ONCE(pending, "IRQ not handled, pending = %x\n", pending);
> +		ret = IRQ_HANDLED;
> +		spi_writel(as, IDR, pending);
> +	}
> +
> +	return ret;
>  }
>  
>  static irqreturn_t
> -atmel_spi_interrupt(int irq, void *dev_id)
> +atmel_spi_pdc_interrupt(int irq, void *dev_id)
>  {
>  	struct spi_master	*master = dev_id;
>  	struct atmel_spi	*as = spi_master_get_devdata(master);
> @@ -697,14 +1208,14 @@ atmel_spi_interrupt(int irq, void *dev_id)
>  				 *
>  				 * FIXME handle protocol options for xfer
>  				 */
> -				atmel_spi_next_xfer(master, msg);
> +				atmel_spi_pdc_next_xfer(master, msg);
>  			}
>  		} else {
>  			/*
>  			 * Keep going, we still have data to send in
>  			 * the current transfer.
>  			 */
> -			atmel_spi_next_xfer(master, msg);
> +			atmel_spi_pdc_next_xfer(master, msg);
>  		}
>  	}
>  
> @@ -875,13 +1386,10 @@ static int atmel_spi_transfer(struct spi_device *spi, struct spi_message *msg)
>  
>  		/*
>  		 * DMA map early, for performance (empties dcache ASAP) and
> -		 * better fault reporting.  This is a DMA-only driver.
> -		 *
> -		 * NOTE that if dma_unmap_single() ever starts to do work on
> -		 * platforms supported by this driver, we would need to clean
> -		 * up mappings for previously-mapped transfers.
> +		 * better fault reporting.
>  		 */
> -		if (!msg->is_dma_mapped) {
> +		if ((!msg->is_dma_mapped) && (atmel_spi_use_dma(as, xfer)
> +			|| as->use_pdc)) {
>  			if (atmel_spi_dma_map_xfer(as, xfer) < 0)
>  				return -ENOMEM;
>  		}
> @@ -1000,6 +1508,7 @@ static int atmel_spi_probe(struct platform_device *pdev)
>  
>  	spin_lock_init(&as->lock);
>  	INIT_LIST_HEAD(&as->queue);
> +
>  	as->pdev = pdev;
>  	as->regs = ioremap(regs->start, resource_size(regs));
>  	if (!as->regs)
> @@ -1010,8 +1519,28 @@ static int atmel_spi_probe(struct platform_device *pdev)
>  
>  	atmel_get_caps(as);
>  
> -	ret = request_irq(irq, atmel_spi_interrupt, 0,
> -			dev_name(&pdev->dev), master);
> +	as->use_dma = false;
> +	as->use_pdc = false;
> +	if (as->caps.has_dma_support) {
> +		if (atmel_spi_configure_dma(as) == 0)
> +			as->use_dma = true;
> +	} else {
> +		as->use_pdc = true;
> +	}
> +
> +	if (as->caps.has_dma_support && !as->use_dma)
> +		dev_info(&pdev->dev, "Atmel SPI Controller using PIO only\n");
> +
> +	if (as->use_pdc) {
> +		ret = request_irq(irq, atmel_spi_pdc_interrupt, 0,
> +					dev_name(&pdev->dev), master);
> +	} else {
> +		tasklet_init(&as->tasklet, atmel_spi_tasklet_func,
> +					(unsigned long)master);
> +
> +		ret = request_irq(irq, atmel_spi_pio_interrupt, 0,
> +					dev_name(&pdev->dev), master);
> +	}
>  	if (ret)
>  		goto out_unmap_regs;
>  
> @@ -1025,7 +1554,9 @@ static int atmel_spi_probe(struct platform_device *pdev)
>  	} else {
>  		spi_writel(as, MR, SPI_BIT(MSTR) | SPI_BIT(MODFDIS));
>  	}
> -	spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
> +
> +	if (as->use_pdc)
> +		spi_writel(as, PTCR, SPI_BIT(RXTDIS) | SPI_BIT(TXTDIS));
>  	spi_writel(as, CR, SPI_BIT(SPIEN));
>  
>  	/* go! */
> @@ -1034,11 +1565,14 @@ static int atmel_spi_probe(struct platform_device *pdev)
>  
>  	ret = spi_register_master(master);
>  	if (ret)
> -		goto out_reset_hw;
> +		goto out_free_dma;
>  
>  	return 0;
>  
> -out_reset_hw:
> +out_free_dma:
> +	if (as->use_dma)
> +		atmel_spi_release_dma(as);
> +
>  	spi_writel(as, CR, SPI_BIT(SWRST));
>  	spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
>  	clk_disable(clk);
> @@ -1046,6 +1580,8 @@ out_reset_hw:
>  out_unmap_regs:
>  	iounmap(as->regs);
>  out_free_buffer:
> +	if (!as->use_pdc)
> +		tasklet_kill(&as->tasklet);
>  	dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
>  			as->buffer_dma);
>  out_free:
> @@ -1064,6 +1600,11 @@ static int atmel_spi_remove(struct platform_device *pdev)
>  	/* reset the hardware and block queue progress */
>  	spin_lock_irq(&as->lock);
>  	as->stopping = 1;
> +	if (as->use_dma) {
> +		atmel_spi_stop_dma(as);
> +		atmel_spi_release_dma(as);
> +	}
> +
>  	spi_writel(as, CR, SPI_BIT(SWRST));
>  	spi_writel(as, CR, SPI_BIT(SWRST)); /* AT91SAM9263 Rev B workaround */
>  	spi_readl(as, SR);
> @@ -1072,13 +1613,17 @@ static int atmel_spi_remove(struct platform_device *pdev)
>  	/* Terminate remaining queued transfers */
>  	list_for_each_entry(msg, &as->queue, queue) {
>  		list_for_each_entry(xfer, &msg->transfers, transfer_list) {
> -			if (!msg->is_dma_mapped)
> +			if (!msg->is_dma_mapped
> +				&& (atmel_spi_use_dma(as, xfer)
> +					|| as->use_pdc))
>  				atmel_spi_dma_unmap_xfer(master, xfer);
>  		}
>  		msg->status = -ESHUTDOWN;
>  		msg->complete(msg->context);
>  	}
>  
> +	if (!as->use_pdc)
> +		tasklet_kill(&as->tasklet);
>  	dma_free_coherent(&pdev->dev, BUFFER_SIZE, as->buffer,
>  			as->buffer_dma);
>  
> -- 
> 1.7.9.5
> 
As I did some work on that one:
Signed-off-by: Richard Genoud <richard.genoud-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

BUT, there's one thing not working (at least for me !):
With DMA enabled, using spidev.
if we use the ioctl SPI_IOC_MESSAGE(x) (tested with x=3):

#define SMALL 2
#define BIG 120
#define NB 3
struct spi_ioc_transfer	xfer[NB];
char buffer[BIG];
char rx_header[SMALL];
char rx_footer[SMALL];
char tx_header[SMALL];
char tx_footer[SMALL];

xfer[0].tx_buf = (unsigned long)&tx_header;
xfer[0].rx_buf = (unsigned long)&rx_header;
xfer[0].len = SMALL;
xfer[1].tx_buf = (unsigned long)buffer;
xfer[1].rx_buf = (unsigned long)buffer;
xfer[1].len = BIG;
xfer[2].tx_buf = (unsigned long)&tx_footer;
xfer[2].rx_buf = (unsigned long)&rx_footer;
xfer[2].len = SMALL
ioctl(fd, SPI_IOC_MESSAGE(NB), xfer);

In this use case, the buffer received contains weird stuff *sometimes*
(header corrupted for example).
BUT if I set 
+#define DMA_MIN_BYTES	1
instead of:
+#define DMA_MIN_BYTES	16
Everything works fine.
So I suggest for now:
+/*
+ * FIXME: alternating DMA and PIO transfert (with SPI_IOC_MESSAGE() for
+ * instance), seems to corrupt data.
+ */
+#define DMA_MIN_BYTES	1

With that change:
On sam9g35 with DMA and PIO (3.9-rc5 + device tree patches)
Tested-by: Richard Genoud <richard.genoud-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>



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Re: [PATCH v8 8/8] ARM: dts: add pinctrl property for spi node for atmel SoC

[Richard GENOUD]

On [mer., 03.04.2013 14:03:52], Wenyou Yang wrote:
> Signed-off-by: Wenyou Yang <wenyou.yang-AIFe0yeh4nAAvxtiuMwx3w@public.gmane.org>
> Cc: linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org
> Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> ---
>  arch/arm/boot/dts/at91sam9260.dtsi |   22 ++++++++++++++++++++++
>  arch/arm/boot/dts/at91sam9263.dtsi |   22 ++++++++++++++++++++++
>  arch/arm/boot/dts/at91sam9g45.dtsi |   22 ++++++++++++++++++++++
>  arch/arm/boot/dts/at91sam9n12.dtsi |   22 ++++++++++++++++++++++
>  arch/arm/boot/dts/at91sam9x5.dtsi  |   22 ++++++++++++++++++++++
>  5 files changed, 110 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/at91sam9260.dtsi b/arch/arm/boot/dts/at91sam9260.dtsi
> index 6e31dc8..39253b9 100644
> --- a/arch/arm/boot/dts/at91sam9260.dtsi
> +++ b/arch/arm/boot/dts/at91sam9260.dtsi
> @@ -322,6 +322,24 @@
>  					};
>  				};
>  
> +				spi0 {
> +					pinctrl_spi0: spi0-0 {
> +						atmel,pins =
> +							<0 0 0x1 0x0	/* PA0 periph A SPI0_MISO pin */
> +							 0 1 0x1 0x0	/* PA1 periph A SPI0_MOSI pin */
> +							 0 2 0x1 0x0>;	/* PA2 periph A SPI0_SPCK pin */
> +					};
> +				};
> +
> +				spi1 {
> +					pinctrl_spi1: spi1-0 {
> +						atmel,pins =
> +							<1 0 0x1 0x0	/* PB0 periph A SPI1_MISO pin */
> +							 1 1 0x1 0x0	/* PB1 periph A SPI1_MOSI pin */
> +							 1 2 0x1 0x0>;	/* PB2 periph A SPI1_SPCK pin */
> +					};
> +				};
> +
>  				pioA: gpio@fffff400 {
>  					compatible = "atmel,at91rm9200-gpio";
>  					reg = <0xfffff400 0x200>;
> @@ -477,6 +495,8 @@
>  				compatible = "atmel,at91rm9200-spi";
>  				reg = <0xfffc8000 0x200>;
>  				interrupts = <12 4 3>;
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&pinctrl_spi0>;
>  				status = "disabled";
>  			};
>  
> @@ -486,6 +506,8 @@
>  				compatible = "atmel,at91rm9200-spi";
>  				reg = <0xfffcc000 0x200>;
>  				interrupts = <13 4 3>;
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&pinctrl_spi1>;
>  				status = "disabled";
>  			};
>  
> diff --git a/arch/arm/boot/dts/at91sam9263.dtsi b/arch/arm/boot/dts/at91sam9263.dtsi
> index 6c6d9ae..94b58ab 100644
> --- a/arch/arm/boot/dts/at91sam9263.dtsi
> +++ b/arch/arm/boot/dts/at91sam9263.dtsi
> @@ -303,6 +303,24 @@
>  					};
>  				};
>  
> +				spi0 {
> +					pinctrl_spi0: spi0-0 {
> +						atmel,pins =
> +							<0 0 0x2 0x0	/* PA0 periph B SPI0_MISO pin */
> +							 0 1 0x2 0x0	/* PA1 periph B SPI0_MOSI pin */
> +							 0 2 0x2 0x0>;	/* PA2 periph B SPI0_SPCK pin */
> +					};
> +				};
> +
> +				spi1 {
> +					pinctrl_spi1: spi1-0 {
> +						atmel,pins =
> +							<1 12 0x1 0x0	/* PB12 periph A SPI1_MISO pin */
> +							 1 13 0x1 0x0	/* PB13 periph A SPI1_MOSI pin */
> +							 1 14 0x1 0x0>;	/* PB14 periph A SPI1_SPCK pin */
> +					};
> +				};
> +
>  				pioA: gpio@fffff200 {
>  					compatible = "atmel,at91rm9200-gpio";
>  					reg = <0xfffff200 0x200>;
> @@ -469,6 +487,8 @@
>  				compatible = "atmel,at91rm9200-spi";
>  				reg = <0xfffa4000 0x200>;
>  				interrupts = <14 4 3>;
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&pinctrl_spi0>;
>  				status = "disabled";
>  			};
>  
> @@ -478,6 +498,8 @@
>  				compatible = "atmel,at91rm9200-spi";
>  				reg = <0xfffa8000 0x200>;
>  				interrupts = <15 4 3>;
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&pinctrl_spi1>;
>  				status = "disabled";
>  			};
>  		};
> diff --git a/arch/arm/boot/dts/at91sam9g45.dtsi b/arch/arm/boot/dts/at91sam9g45.dtsi
> index e085b8a..cfdf429 100644
> --- a/arch/arm/boot/dts/at91sam9g45.dtsi
> +++ b/arch/arm/boot/dts/at91sam9g45.dtsi
> @@ -322,6 +322,24 @@
>  					};
>  				};
>  
> +				spi0 {
> +					pinctrl_spi0: spi0-0 {
> +						atmel,pins =
> +							<1 0 0x1 0x0	/* PB0 periph A SPI0_MISO pin */
> +							 1 1 0x1 0x0	/* PB1 periph A SPI0_MOSI pin */
> +							 1 2 0x1 0x0>;	/* PB2 periph A SPI0_SPCK pin */
> +					};
> +				};
> +
> +				spi1 {
> +					pinctrl_spi1: spi1-0 {
> +						atmel,pins =
> +							<1 14 0x1 0x0	/* PB14 periph A SPI1_MISO pin */
> +							 1 15 0x1 0x0	/* PB15 periph A SPI1_MOSI pin */
> +							 1 16 0x1 0x0>;	/* PB16 periph A SPI1_SPCK pin */
> +					};
> +				};
> +
>  				pioA: gpio@fffff200 {
>  					compatible = "atmel,at91rm9200-gpio";
>  					reg = <0xfffff200 0x200>;
> @@ -538,6 +556,8 @@
>  				compatible = "atmel,at91rm9200-spi";
>  				reg = <0xfffa4000 0x200>;
>  				interrupts = <14 4 3>;
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&pinctrl_spi0>;
>  				status = "disabled";
>  			};
>  
> @@ -547,6 +567,8 @@
>  				compatible = "atmel,at91rm9200-spi";
>  				reg = <0xfffa8000 0x200>;
>  				interrupts = <15 4 3>;
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&pinctrl_spi1>;
>  				status = "disabled";
>  			};
>  		};
> diff --git a/arch/arm/boot/dts/at91sam9n12.dtsi b/arch/arm/boot/dts/at91sam9n12.dtsi
> index f3f87ef3..b2961f1 100644
> --- a/arch/arm/boot/dts/at91sam9n12.dtsi
> +++ b/arch/arm/boot/dts/at91sam9n12.dtsi
> @@ -261,6 +261,24 @@
>  					};
>  				};
>  
> +				spi0 {
> +					pinctrl_spi0: spi0-0 {
> +						atmel,pins =
> +							<0 11 0x1 0x0	/* PA11 periph A SPI0_MISO pin */
> +							 0 12 0x1 0x0	/* PA12 periph A SPI0_MOSI pin */
> +							 0 13 0x1 0x0>;	/* PA13 periph A SPI0_SPCK pin */
> +					};
> +				};
> +
> +				spi1 {
> +					pinctrl_spi1: spi1-0 {
> +						atmel,pins =
> +							<0 21 0x2 0x0	/* PA21 periph B SPI1_MISO pin */
> +							 0 22 0x2 0x0	/* PA22 periph B SPI1_MOSI pin */
> +							 0 23 0x2 0x0>;	/* PA23 periph B SPI1_SPCK pin */
> +					};
> +				};
> +
>  				pioA: gpio@fffff400 {
>  					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
>  					reg = <0xfffff400 0x200>;
> @@ -380,6 +398,8 @@
>  				compatible = "atmel,at91rm9200-spi";
>  				reg = <0xf0000000 0x100>;
>  				interrupts = <13 4 3>;
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&pinctrl_spi0>;
>  				status = "disabled";
>  			};
>  
> @@ -389,6 +409,8 @@
>  				compatible = "atmel,at91rm9200-spi";
>  				reg = <0xf0004000 0x100>;
>  				interrupts = <14 4 3>;
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&pinctrl_spi1>;
>  				status = "disabled";
>  			};
>  		};
> diff --git a/arch/arm/boot/dts/at91sam9x5.dtsi b/arch/arm/boot/dts/at91sam9x5.dtsi
> index 77ce2e1..347b438 100644
> --- a/arch/arm/boot/dts/at91sam9x5.dtsi
> +++ b/arch/arm/boot/dts/at91sam9x5.dtsi
> @@ -343,6 +343,24 @@
>  					};
>  				};
>  
> +				spi0 {
> +					pinctrl_spi0: spi0-0 {
> +						atmel,pins =
> +							<0 11 0x1 0x0	/* PA11 periph A SPI0_MISO pin */
> +							 0 12 0x1 0x0	/* PA12 periph A SPI0_MOSI pin */
> +							 0 13 0x1 0x0>;	/* PA13 periph A SPI0_SPCK pin */
> +					};
> +				};
> +
> +				spi1 {
> +					pinctrl_spi1: spi1-0 {
> +						atmel,pins =
> +							<0 21 0x2 0x0	/* PA21 periph B SPI1_MISO pin */
> +							 0 22 0x2 0x0	/* PA22 periph B SPI1_MOSI pin */
> +							 0 23 0x2 0x0>;	/* PA23 periph B SPI1_SPCK pin */
> +					};
> +				};
> +
>  				pioA: gpio@fffff400 {
>  					compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
>  					reg = <0xfffff400 0x200>;
> @@ -536,6 +554,8 @@
>  				compatible = "atmel,at91rm9200-spi";
>  				reg = <0xf0000000 0x100>;
>  				interrupts = <13 4 3>;
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&pinctrl_spi0>;
>  				status = "disabled";
>  			};
>  
> @@ -545,6 +565,8 @@
>  				compatible = "atmel,at91rm9200-spi";
>  				reg = <0xf0004000 0x100>;
>  				interrupts = <14 4 3>;
> +				pinctrl-names = "default";
> +				pinctrl-0 = <&pinctrl_spi1>;
>  				status = "disabled";
>  			};
>  		};
> -- 
> 1.7.9.5
> 
On sam9g35 with DMA and PIO (3.9-rc5 + device tree patches)
Tested-by: Richard Genoud <richard.genoud-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

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the most talented Cisco Certified professionals. Visit the 
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Re: [PATCH v8 1/8] spi/spi-atmel: add physical base address

[Mark Brown]

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On Wed, Apr 03, 2013 at 01:57:42PM +0800, Wenyou Yang wrote:
> From: Nicolas Ferre <nicolas.ferre@atmel.com>
> 
> Needed for future use with dmaengine enabled driver.

Applied, thanks.

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Re: [PATCH v8 2/8] spi/spi-atmel: add flag to controller data for lock operations

[Mark Brown]

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On Wed, Apr 03, 2013 at 01:58:36PM +0800, Wenyou Yang wrote:
> From: Nicolas Ferre <nicolas.ferre@atmel.com>
> 
> Will allow to drop the lock during DMA operations.

Applied, thanks.

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Re: [PATCH v8 3/8] spi/spi-atmel: add dmaengine support

[Mark Brown]

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On Wed, Apr 03, 2013 at 12:23:35PM +0200, Richard GENOUD wrote:

Richard, delete irrelevant context from your mails - it makes it much
easier to find the content you added.

> On [mer., 03.04.2013 13:59:19], Wenyou Yang wrote:

> As I did some work on that one:
> Signed-off-by: Richard Genoud <richard.genoud@gmail.com>
> 
> BUT, there's one thing not working (at least for me !):
> With DMA enabled, using spidev.
> if we use the ioctl SPI_IOC_MESSAGE(x) (tested with x=3):

I'd been expecting an updated series with this rolled in?

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Re: [PATCH v8 3/8] spi/spi-atmel: add dmaengine support

[Richard Genoud]

2013/4/23 Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>:
> On Wed, Apr 03, 2013 at 12:23:35PM +0200, Richard GENOUD wrote:
>
> Richard, delete irrelevant context from your mails - it makes it much
> easier to find the content you added.
>
>> On [mer., 03.04.2013 13:59:19], Wenyou Yang wrote:
>
>> As I did some work on that one:
>> Signed-off-by: Richard Genoud <richard.genoud-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>>
>> BUT, there's one thing not working (at least for me !):
>> With DMA enabled, using spidev.
>> if we use the ioctl SPI_IOC_MESSAGE(x) (tested with x=3):
>
> I'd been expecting an updated series with this rolled in?

I did some more test with spidev and a MISO-MOSI loop as Wenyou suggested.

It's ok for me, on kernel 3.9-rc8 sam9g35, I didn't see any error.

Signed-off-by: Richard Genoud <richard.genoud-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Tested-by: Richard Genoud <richard.genoud-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

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Re: [PATCH v8 3/8] spi/spi-atmel: add dmaengine support

[Mark Brown]

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On Wed, Apr 03, 2013 at 01:59:19PM +0800, Wenyou Yang wrote:
> From: Nicolas Ferre <nicolas.ferre@atmel.com>
> 
> Add dmaengine support.
> 
> Using "has_dma_support" member of struct is used to select
> the transfer mode: dmaengine or pdc.

Applied, thanks.

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Re: [PATCH v8 4/8] spi/spi-atmel: BUG: fix doesn' support 16 bits transfers using PIO

[Mark Brown]

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On Wed, Apr 03, 2013 at 02:00:05PM +0800, Wenyou Yang wrote:
> From: Richard Genoud <richard.genoud@gmail.com>
> 
> Fix using PIO transfer mode only support 8 bits transfer, doesn't support 16 bits.

This doesn't apply to my -next branch, please check and regenerate.

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Re: [PATCH v8 5/8] ARM: at91: add clocks for spi dt entries

[Mark Brown]

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On Wed, Apr 03, 2013 at 02:01:22PM +0800, Wenyou Yang wrote:
> From: Richard Genoud <richard.genoud@gmail.com>

Applied, thanks.

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Re: [PATCH v8 6/8] ARM: dts: add spi nodes for atmel SoC

[Mark Brown]

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On Wed, Apr 03, 2013 at 02:02:18PM +0800, Wenyou Yang wrote:
> From: Richard Genoud <richard.genoud@gmail.com>
> 
> Signed-off-by: Richard Genoud <richard.genoud@gmail.com>

Applied, thanks.

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Re: [PATCH v8 7/8] ARM: dts: add spi nodes for the atmel boards

[Mark Brown]

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On Wed, Apr 03, 2013 at 02:03:05PM +0800, Wenyou Yang wrote:
> From: Richard Genoud <richard.genoud@gmail.com>

Applied, thanks.

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Re: [PATCH v8 8/8] ARM: dts: add pinctrl property for spi node for atmel SoC

[Mark Brown]

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On Wed, Apr 03, 2013 at 02:03:52PM +0800, Wenyou Yang wrote:
> Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>

Applied, thanks.

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