From: Boris Brezillon <bbrezillon@kernel.org>
To: <Tudor.Ambarus@microchip.com>
Cc: <broonie@kernel.org>, <robh+dt@kernel.org>,
<mark.rutland@arm.com>, <Nicolas.Ferre@microchip.com>,
<alexandre.belloni@bootlin.com>,
<Ludovic.Desroches@microchip.com>, <linux-spi@vger.kernel.org>,
<devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <linux-mtd@lists.infradead.org>
Subject: Re: [PATCH v2 10/10] spi: atmel-quadspi: add support for sam9x60 qspi controller
Date: Fri, 1 Feb 2019 08:57:39 +0100 [thread overview]
Message-ID: <20190201085739.775add3f@bbrezillon> (raw)
In-Reply-To: <947f148d-3fd8-4e7d-4301-9d67715fbf7d@microchip.com>
On Fri, 1 Feb 2019 07:07:40 +0000
<Tudor.Ambarus@microchip.com> wrote:
> >
> >> #define QSPI_IFR_TFRTYP_MASK GENMASK(13, 12)
> >> #define QSPI_IFR_TFRTYP_TRSFR_READ (0 << 12)
> >> #define QSPI_IFR_TFRTYP_TRSFR_READ_MEM (1 << 12)
> >
> > Looks like the read/write flag is on bit 13. Can we just add
>
> for sama5d2 only
Feel free to prefix macros with the SoC name to make it clear:
#define QSPI_IFR_SAMA5D2_WRITE_TRSFR BIT(13)
>
> >
> > #define QSPI_IFR_TFRTYP_TRSFR_WRITE BIT(13)
> >
> > and drop all others def? This way the implementation is consistent
> > between sam9x60 and sama5d2.
>
> BIT(13) has no meaning for sam9x60. I can drop the macros with zero value for
> sama5d2 in a separate patch.
> >
> >> +#define QSPI_IFR_APBTFRTYP_READ BIT(24)
And this one would be
define QSPI_IFR_SAM9X60_READ_TRSFR BIT(24)
> >>
> >> /* Bitfields in QSPI_SMR (Scrambling Mode Register) */
> >> #define QSPI_SMR_SCREN BIT(0)
> >> @@ -137,16 +144,37 @@
> >> #define QSPI_WPSR_WPVSRC(src) (((src) << 8) & QSPI_WPSR_WPVSRC)
> >>
> >>
> >> +/* Describes register values. */
> >> +struct atmel_qspi_cfg {
> >> + u32 icr;
> >> + u32 iar;
> >> + u32 ifr;
> >> +};
> >> +
> >> +struct atmel_qspi_caps;
> >> +
> >> struct atmel_qspi {
> >> void __iomem *regs;
> >> void __iomem *mem;
> >> struct clk *clk;
> >
> > Can we rename that on pclk?
>
> will rename it, together with the support for unnamed clock of sama5d2 in a separate
> patch. The dt-bindings patch that imposes "pclk" for sama5d2 should be separated too.
Sounds good.
next prev parent reply other threads:[~2019-02-01 7:57 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-31 16:15 [PATCH v2 00/10] spi: atmel-quadspi: introduce sam9x60 qspi controller Tudor.Ambarus
2019-01-31 16:15 ` [PATCH v2 01/10] spi: atmel-quadspi: cache MR value to avoid a write access Tudor.Ambarus
2019-01-31 16:55 ` Boris Brezillon
2019-02-01 6:51 ` Tudor.Ambarus
2019-01-31 16:15 ` [PATCH v2 02/10] spi: atmel-quadspi: order header files inclusion alphabetically Tudor.Ambarus
2019-01-31 16:15 ` [PATCH v2 03/10] spi: atmel-quadspi: drop wrappers for iomem accesses Tudor.Ambarus
2019-01-31 16:15 ` [PATCH v2 04/10] spi: atmel-quadspi: fix naming scheme Tudor.Ambarus
2019-01-31 16:15 ` [PATCH v2 05/10] spi: atmel-quadspi: remove unnecessary cast Tudor.Ambarus
2019-01-31 16:15 ` [PATCH v2 06/10] spi: atmel-quadspi: return appropriate error code Tudor.Ambarus
2019-01-31 16:15 ` [PATCH v2 07/10] spi: atmel-quadspi: switch to SPDX license identifiers Tudor.Ambarus
2019-01-31 16:15 ` [PATCH v2 08/10] dt-bindings: spi: atmel-quadspi: update example to new clock binding Tudor.Ambarus
2019-01-31 16:15 ` [PATCH v2 09/10] dt-bindings: spi: atmel-quadspi: QuadSPI driver for Microchip SAM9X60 Tudor.Ambarus
2019-01-31 16:15 ` [PATCH v2 10/10] spi: atmel-quadspi: add support for sam9x60 qspi controller Tudor.Ambarus
2019-01-31 16:32 ` Boris Brezillon
2019-02-01 7:07 ` Tudor.Ambarus
2019-02-01 7:57 ` Boris Brezillon [this message]
2019-02-01 14:49 ` Tudor.Ambarus
2019-02-01 15:45 ` Boris Brezillon
2019-02-01 14:43 ` Tudor.Ambarus
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