[PATCH 0/1] Enable SSP controller for CS toggle

[PATCH 0/1] Enable SSP controller for CS toggle

[Shobhit Srivastava]

SPI CS assert may not always be accompanied by data. There are cases
where we want to assert CS, wait and then deassert CS. There is no
clocking or reading required. On Intel CNL LPSS controller, it was
observed that the above flow is broken after an S0ix cycle. There
is no issue after S3 flow.
https://patchwork.kernel.org/patch/11377019/ is an attempt to fix
this and it does fix the issue. However we are unsure if that is
the actual rootcause for the issue. As per the LPSS spec, to
propagate the retained CS to output,  SPI controller needs to be
enabled. The below patch tries to do the same and it fixes the issue.
The reason why there is no issue after S3 flow is because during
resume, BIOS re-initializes and enables SPI before doing kernel hand-off.
To test this issue we are probing the SPI_CS line on CRO. This is
because, even though the mmio writes to CS_CONTROL register sticks,
it doesnt toggle the CS line. Physically probing is the best way
to identify the fix.


Shobhit Srivastava (1):
  spi: pxa2xx: Enable SSP controller for CS toggle

 drivers/spi/spi-pxa2xx.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

-- 
2.17.1

[PATCH 1/1] spi: pxa2xx: Enable SSP controller for CS toggle

[Shobhit Srivastava]

In some circumstances on Intel LPSS controllers, toggling the LPSS
CS control register doesn't actually cause the CS line to toggle.
This ruins SPI transactions that either rely on delay_usecs,
or toggle the CS line without sending any data.
This seems to be because the SSP controller is in disabled state.
As per the spec, the controller needs to be enabled for CS change
to take effect.
This issue is not seen in cases where there is data to be
transferred because then the SSCR0 gets enabled via
pxa2xx_configure_sscr0().

Signed-off-by: Shobhit Srivastava <shobhit.srivastava-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>

---

 drivers/spi/spi-pxa2xx.c | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index 4c7a71f0fb3e..414afc72ef44 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -370,7 +370,7 @@ static void lpss_ssp_cs_control(struct spi_device *spi, bool enable)
 	struct driver_data *drv_data =
 		spi_controller_get_devdata(spi->controller);
 	const struct lpss_config *config;
-	u32 value;
+	u32 value, sscr0;
 
 	config = lpss_get_config(drv_data);
 
@@ -382,7 +382,18 @@ static void lpss_ssp_cs_control(struct spi_device *spi, bool enable)
 		value &= ~LPSS_CS_CONTROL_CS_HIGH;
 	else
 		value |= LPSS_CS_CONTROL_CS_HIGH;
+
+	/* To propagate CS value to output, the controller should
+	 * be enabled. This is needed for devices that just do
+	 * CS assert, wait and CS deassert without sending any data.
+	 */
+	sscr0 = pxa2xx_spi_read(drv_data, SSCR0);
+	pxa2xx_spi_write(drv_data, SSCR0, sscr0 | SSCR0_SSE);
+
 	__lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
+
+	/* Restore the original SSCR0 config*/
+	 pxa2xx_spi_write(drv_data, SSCR0, sscr0);
 }
 
 static void cs_assert(struct spi_device *spi)
-- 
2.17.1

Re: [PATCH 0/1] Enable SSP controller for CS toggle

[Mark Brown]

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On Tue, Feb 18, 2020 at 07:19:05PM +0530, Shobhit Srivastava wrote:
> 
> SPI CS assert may not always be accompanied by data. There are cases
> where we want to assert CS, wait and then deassert CS. There is no
> clocking or reading required. On Intel CNL LPSS controller, it was

Please don't send cover letters for single patches, if there is anything
that needs saying put it in the changelog of the patch or after the ---
if it's administrative stuff.  This reduces mail volume and ensures that 
any important information is recorded in the changelog rather than being
lost. 

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