* [PATCH v5 1/7] spi: dw: Fix typo in few registers name
2020-05-05 13:06 [PATCH v5 0/7] spi: dw: Add support for Intel Keem Bay SPI Wan Ahmad Zainie
@ 2020-05-05 13:06 ` Wan Ahmad Zainie
2020-05-05 13:06 ` [PATCH v5 2/7] spi: dw: Add update_cr0() callback to update CTRLR0 Wan Ahmad Zainie
` (6 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Wan Ahmad Zainie @ 2020-05-05 13:06 UTC (permalink / raw)
To: broonie, robh+dt
Cc: linux-spi, devicetree, andriy.shevchenko, wan.ahmad.zainie.wan.mohamad
This patch will fix typo in the register name used in the source code,
to be consistent with the register name used in the databook.
Databook: DW_apb_ssi_databook.pdf version 4.01a
Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/spi/spi-dw.c | 18 +++++++++---------
drivers/spi/spi-dw.h | 8 ++++----
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c
index 2b79c5a983c0..72a1c99ce9e6 100644
--- a/drivers/spi/spi-dw.c
+++ b/drivers/spi/spi-dw.c
@@ -47,9 +47,9 @@ static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf,
len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
"=================================\n");
len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
- "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0));
+ "CTRLR0: \t0x%08x\n", dw_readl(dws, DW_SPI_CTRLR0));
len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
- "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1));
+ "CTRLR1: \t0x%08x\n", dw_readl(dws, DW_SPI_CTRLR1));
len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
"SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
@@ -57,9 +57,9 @@ static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf,
len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
"BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
- "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR));
+ "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFTLR));
len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
- "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR));
+ "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFTLR));
len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
"TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
len += scnprintf(buf + len, SPI_REGS_BUFSIZE - len,
@@ -304,7 +304,7 @@ static int dw_spi_transfer_one(struct spi_controller *master,
(((spi->mode & SPI_LOOP) ? 1 : 0) << SPI_SRL_OFFSET))
| (chip->tmode << SPI_TMOD_OFFSET);
- dw_writel(dws, DW_SPI_CTRL0, cr0);
+ dw_writel(dws, DW_SPI_CTRLR0, cr0);
/* Check if current transfer is a DMA transaction */
if (master->can_dma && master->can_dma(master, spi, transfer))
@@ -325,7 +325,7 @@ static int dw_spi_transfer_one(struct spi_controller *master,
}
} else {
txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes);
- dw_writel(dws, DW_SPI_TXFLTR, txlevel);
+ dw_writel(dws, DW_SPI_TXFTLR, txlevel);
/* Set the interrupt mask */
imask |= SPI_INT_TXEI | SPI_INT_TXOI |
@@ -397,11 +397,11 @@ static void spi_hw_init(struct device *dev, struct dw_spi *dws)
u32 fifo;
for (fifo = 1; fifo < 256; fifo++) {
- dw_writel(dws, DW_SPI_TXFLTR, fifo);
- if (fifo != dw_readl(dws, DW_SPI_TXFLTR))
+ dw_writel(dws, DW_SPI_TXFTLR, fifo);
+ if (fifo != dw_readl(dws, DW_SPI_TXFTLR))
break;
}
- dw_writel(dws, DW_SPI_TXFLTR, 0);
+ dw_writel(dws, DW_SPI_TXFTLR, 0);
dws->fifo_len = (fifo == 1) ? 0 : fifo;
dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len);
diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
index 44ef18187c15..6c34720b1b1d 100644
--- a/drivers/spi/spi-dw.h
+++ b/drivers/spi/spi-dw.h
@@ -6,14 +6,14 @@
#include <linux/scatterlist.h>
/* Register offsets */
-#define DW_SPI_CTRL0 0x00
-#define DW_SPI_CTRL1 0x04
+#define DW_SPI_CTRLR0 0x00
+#define DW_SPI_CTRLR1 0x04
#define DW_SPI_SSIENR 0x08
#define DW_SPI_MWCR 0x0c
#define DW_SPI_SER 0x10
#define DW_SPI_BAUDR 0x14
-#define DW_SPI_TXFLTR 0x18
-#define DW_SPI_RXFLTR 0x1c
+#define DW_SPI_TXFTLR 0x18
+#define DW_SPI_RXFTLR 0x1c
#define DW_SPI_TXFLR 0x20
#define DW_SPI_RXFLR 0x24
#define DW_SPI_SR 0x28
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v5 2/7] spi: dw: Add update_cr0() callback to update CTRLR0
2020-05-05 13:06 [PATCH v5 0/7] spi: dw: Add support for Intel Keem Bay SPI Wan Ahmad Zainie
2020-05-05 13:06 ` [PATCH v5 1/7] spi: dw: Fix typo in few registers name Wan Ahmad Zainie
@ 2020-05-05 13:06 ` Wan Ahmad Zainie
2020-05-05 13:06 ` [PATCH v5 3/7] spi: dw: Add support for DesignWare DWC_ssi Wan Ahmad Zainie
` (5 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Wan Ahmad Zainie @ 2020-05-05 13:06 UTC (permalink / raw)
To: broonie, robh+dt
Cc: linux-spi, devicetree, andriy.shevchenko, wan.ahmad.zainie.wan.mohamad
This patch adds update_cr0() callback, in struct dw_spi.
Existing code that configure register CTRLR0 is moved into a new
function, dw_spi_update_cr0(), and this will be the default.
Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/spi/spi-dw-mid.c | 4 ++++
drivers/spi/spi-dw-mmio.c | 21 ++++++++++++++++++---
drivers/spi/spi-dw.c | 29 +++++++++++++++++++++--------
drivers/spi/spi-dw.h | 5 +++++
4 files changed, 48 insertions(+), 11 deletions(-)
diff --git a/drivers/spi/spi-dw-mid.c b/drivers/spi/spi-dw-mid.c
index 0d86c37e0aeb..9cc010e9737e 100644
--- a/drivers/spi/spi-dw-mid.c
+++ b/drivers/spi/spi-dw-mid.c
@@ -318,5 +318,9 @@ int dw_spi_mid_init(struct dw_spi *dws)
dws->dma_rx = &mid_dma_rx;
dws->dma_ops = &mid_dma_ops;
#endif
+
+ /* Register hook to configure CTRLR0 */
+ dws->update_cr0 = dw_spi_update_cr0;
+
return 0;
}
diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
index 384a3ab6dc2d..a52f75e22109 100644
--- a/drivers/spi/spi-dw-mmio.c
+++ b/drivers/spi/spi-dw-mmio.c
@@ -106,6 +106,9 @@ static int dw_spi_mscc_init(struct platform_device *pdev,
dwsmmio->dws.set_cs = dw_spi_mscc_set_cs;
dwsmmio->priv = dwsmscc;
+ /* Register hook to configure CTRLR0 */
+ dwsmmio->dws.update_cr0 = dw_spi_update_cr0;
+
return 0;
}
@@ -128,6 +131,18 @@ static int dw_spi_alpine_init(struct platform_device *pdev,
{
dwsmmio->dws.cs_override = 1;
+ /* Register hook to configure CTRLR0 */
+ dwsmmio->dws.update_cr0 = dw_spi_update_cr0;
+
+ return 0;
+}
+
+static int dw_spi_dw_apb_init(struct platform_device *pdev,
+ struct dw_spi_mmio *dwsmmio)
+{
+ /* Register hook to configure CTRLR0 */
+ dwsmmio->dws.update_cr0 = dw_spi_update_cr0;
+
return 0;
}
@@ -224,17 +239,17 @@ static int dw_spi_mmio_remove(struct platform_device *pdev)
}
static const struct of_device_id dw_spi_mmio_of_match[] = {
- { .compatible = "snps,dw-apb-ssi", },
+ { .compatible = "snps,dw-apb-ssi", .data = dw_spi_dw_apb_init},
{ .compatible = "mscc,ocelot-spi", .data = dw_spi_mscc_ocelot_init},
{ .compatible = "mscc,jaguar2-spi", .data = dw_spi_mscc_jaguar2_init},
{ .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init},
- { .compatible = "renesas,rzn1-spi", },
+ { .compatible = "renesas,rzn1-spi", .data = dw_spi_dw_apb_init},
{ /* end of table */}
};
MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);
static const struct acpi_device_id dw_spi_mmio_acpi_match[] = {
- {"HISI0173", 0},
+ {"HISI0173", (kernel_ulong_t)dw_spi_dw_apb_init},
{},
};
MODULE_DEVICE_TABLE(acpi, dw_spi_mmio_acpi_match);
diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c
index 72a1c99ce9e6..4905457641ef 100644
--- a/drivers/spi/spi-dw.c
+++ b/drivers/spi/spi-dw.c
@@ -257,6 +257,26 @@ static irqreturn_t dw_spi_irq(int irq, void *dev_id)
return dws->transfer_handler(dws);
}
+/* Configure CTRLR0 for DW_apb_ssi */
+u32 dw_spi_update_cr0(struct spi_controller *master, struct spi_device *spi,
+ struct spi_transfer *transfer)
+{
+ struct dw_spi *dws = spi_controller_get_devdata(master);
+ struct chip_data *chip = spi_get_ctldata(spi);
+ u32 cr0;
+
+ /* Default SPI mode is SCPOL = 0, SCPH = 0 */
+ cr0 = (transfer->bits_per_word - 1)
+ | (chip->type << SPI_FRF_OFFSET)
+ | ((((spi->mode & SPI_CPOL) ? 1 : 0) << SPI_SCOL_OFFSET) |
+ (((spi->mode & SPI_CPHA) ? 1 : 0) << SPI_SCPH_OFFSET) |
+ (((spi->mode & SPI_LOOP) ? 1 : 0) << SPI_SRL_OFFSET))
+ | (chip->tmode << SPI_TMOD_OFFSET);
+
+ return cr0;
+}
+EXPORT_SYMBOL_GPL(dw_spi_update_cr0);
+
static int dw_spi_transfer_one(struct spi_controller *master,
struct spi_device *spi, struct spi_transfer *transfer)
{
@@ -296,14 +316,7 @@ static int dw_spi_transfer_one(struct spi_controller *master,
dws->n_bytes = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);
dws->dma_width = DIV_ROUND_UP(transfer->bits_per_word, BITS_PER_BYTE);
- /* Default SPI mode is SCPOL = 0, SCPH = 0 */
- cr0 = (transfer->bits_per_word - 1)
- | (chip->type << SPI_FRF_OFFSET)
- | ((((spi->mode & SPI_CPOL) ? 1 : 0) << SPI_SCOL_OFFSET) |
- (((spi->mode & SPI_CPHA) ? 1 : 0) << SPI_SCPH_OFFSET) |
- (((spi->mode & SPI_LOOP) ? 1 : 0) << SPI_SRL_OFFSET))
- | (chip->tmode << SPI_TMOD_OFFSET);
-
+ cr0 = dws->update_cr0(master, spi, transfer);
dw_writel(dws, DW_SPI_CTRLR0, cr0);
/* Check if current transfer is a DMA transaction */
diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
index 6c34720b1b1d..2745a7e7405c 100644
--- a/drivers/spi/spi-dw.h
+++ b/drivers/spi/spi-dw.h
@@ -114,6 +114,8 @@ struct dw_spi {
u16 bus_num;
u16 num_cs; /* supported slave numbers */
void (*set_cs)(struct spi_device *spi, bool enable);
+ u32 (*update_cr0)(struct spi_controller *master, struct spi_device *spi,
+ struct spi_transfer *transfer);
/* Current message transfer state info */
size_t len;
@@ -240,6 +242,9 @@ extern int dw_spi_add_host(struct device *dev, struct dw_spi *dws);
extern void dw_spi_remove_host(struct dw_spi *dws);
extern int dw_spi_suspend_host(struct dw_spi *dws);
extern int dw_spi_resume_host(struct dw_spi *dws);
+extern u32 dw_spi_update_cr0(struct spi_controller *master,
+ struct spi_device *spi,
+ struct spi_transfer *transfer);
/* platform related setup */
extern int dw_spi_mid_init(struct dw_spi *dws); /* Intel MID platforms */
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v5 3/7] spi: dw: Add support for DesignWare DWC_ssi
2020-05-05 13:06 [PATCH v5 0/7] spi: dw: Add support for Intel Keem Bay SPI Wan Ahmad Zainie
2020-05-05 13:06 ` [PATCH v5 1/7] spi: dw: Fix typo in few registers name Wan Ahmad Zainie
2020-05-05 13:06 ` [PATCH v5 2/7] spi: dw: Add update_cr0() callback to update CTRLR0 Wan Ahmad Zainie
@ 2020-05-05 13:06 ` Wan Ahmad Zainie
2020-05-05 13:06 ` [PATCH v5 4/7] dt-bindings: spi: dw-apb-ssi: Add compatible string " Wan Ahmad Zainie
` (4 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Wan Ahmad Zainie @ 2020-05-05 13:06 UTC (permalink / raw)
To: broonie, robh+dt
Cc: linux-spi, devicetree, andriy.shevchenko, wan.ahmad.zainie.wan.mohamad
This patch adds initial support for DesignWare DWC_ssi soft IP. DWC_ssi is
the enhanced version of DW_apb_ssi, which is currently supported by this
driver. Their registers are same, but the bit fields of register CTRLR0
are different.
DWC_ssi has additional features compared to DW_apb_ssi. Major enhancements
in DWC_ssi are hyper bus protocol, boot mode support and advanced XIP
support. DWC_ssi is an AHB slave device, whilst DW_apb_ssi is an APB slave
device.
Register offset
DW_ssi DW_apb_ssi
CTRLR0 0x00 0x00
CTRLR1 0x04 0x04
SSIENR 0x08 0x08
MWCR 0x0c 0x0c
SER 0x10 0x10
BAUDR 0x14 0x14
TXFTLR 0x18 0x18
RXFTLR 0x1c 0x1c
TXFLR 0x20 0x20
RXFLR 0x24 0x24
SR 0x28 0x28
IMR 0x2c 0x2c
ISR 0x30 0x30
RISR 0x34 0x34
TXOICR 0x38 0x38
RXOICR 0x3c 0x3c
RXUICR 0x40 0x40
MSTICR 0x44 0x44
ICR 0x48 0x48
DMACR 0x4c 0x4c
DMATDLR 0x50 0x50
DMARDLR 0x54 0x54
IDR 0x58 0x58
SSI_VERSION_ID 0x5c 0x5c
DRx (0 to 35) 0x60+i*0x4 0x60+i*0x4
RX_SAMPLE_DLY 0xf0 0xf0
SPI_CTRLR0 0xf4 0xf4
TXD_DRIVE_EDGE 0xf8 0xf8
XIP_MODE_BITS 0xfc RSVD
Register configuration - CTRLR0
DW_ssi DW_apb_ssi
SPI_HYPERBUS_EN bit[24] NONE
SPI_FRF bit[23:22] bit[22:21]
DFS_32 NONE bit[20:16]
CFS bit[19:16] bit[15:12]
SSTE bit[14] bit[24]
SRL bit[13] bit[11]
SLV_OE bit[12] bit[10]
TMOD bit[11:10] bit[9:8]
SCPOL | SPHA bit[9:8] bit[7:6]
FRF bit[7:6] bit[5:4]
DFS bit[4:0] bit[3:0]
The documents used are
[1] DW_apb_ssi_databook.pdf version 4.01a (2016.10a).
[2] DWC_ssi_databook.pdf version 1.01a.
Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/spi/spi-dw-mmio.c | 10 ++++++++++
drivers/spi/spi-dw.c | 33 +++++++++++++++++++++++++++++++++
drivers/spi/spi-dw.h | 12 ++++++++++++
3 files changed, 55 insertions(+)
diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
index a52f75e22109..1df6f3deee2c 100644
--- a/drivers/spi/spi-dw-mmio.c
+++ b/drivers/spi/spi-dw-mmio.c
@@ -146,6 +146,15 @@ static int dw_spi_dw_apb_init(struct platform_device *pdev,
return 0;
}
+static int dw_spi_dwc_ssi_init(struct platform_device *pdev,
+ struct dw_spi_mmio *dwsmmio)
+{
+ /* Register hook to configure CTRLR0 */
+ dwsmmio->dws.update_cr0 = dw_spi_update_cr0_v1_01a;
+
+ return 0;
+}
+
static int dw_spi_mmio_probe(struct platform_device *pdev)
{
int (*init_func)(struct platform_device *pdev,
@@ -244,6 +253,7 @@ static const struct of_device_id dw_spi_mmio_of_match[] = {
{ .compatible = "mscc,jaguar2-spi", .data = dw_spi_mscc_jaguar2_init},
{ .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init},
{ .compatible = "renesas,rzn1-spi", .data = dw_spi_dw_apb_init},
+ { .compatible = "snps,dwc-ssi-1.01a", .data = dw_spi_dwc_ssi_init},
{ /* end of table */}
};
MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);
diff --git a/drivers/spi/spi-dw.c b/drivers/spi/spi-dw.c
index 4905457641ef..240a61b66a06 100644
--- a/drivers/spi/spi-dw.c
+++ b/drivers/spi/spi-dw.c
@@ -277,6 +277,39 @@ u32 dw_spi_update_cr0(struct spi_controller *master, struct spi_device *spi,
}
EXPORT_SYMBOL_GPL(dw_spi_update_cr0);
+/* Configure CTRLR0 for DWC_ssi */
+u32 dw_spi_update_cr0_v1_01a(struct spi_controller *master,
+ struct spi_device *spi,
+ struct spi_transfer *transfer)
+{
+ struct dw_spi *dws = spi_controller_get_devdata(master);
+ struct chip_data *chip = spi_get_ctldata(spi);
+ u32 cr0;
+
+ /* CTRLR0[ 4: 0] Data Frame Size */
+ cr0 = (transfer->bits_per_word - 1);
+
+ /* CTRLR0[ 7: 6] Frame Format */
+ cr0 |= chip->type << DWC_SSI_CTRLR0_FRF_OFFSET;
+
+ /*
+ * SPI mode (SCPOL|SCPH)
+ * CTRLR0[ 8] Serial Clock Phase
+ * CTRLR0[ 9] Serial Clock Polarity
+ */
+ cr0 |= ((spi->mode & SPI_CPOL) ? 1 : 0) << DWC_SSI_CTRLR0_SCPOL_OFFSET;
+ cr0 |= ((spi->mode & SPI_CPHA) ? 1 : 0) << DWC_SSI_CTRLR0_SCPH_OFFSET;
+
+ /* CTRLR0[11:10] Transfer Mode */
+ cr0 |= chip->tmode << DWC_SSI_CTRLR0_TMOD_OFFSET;
+
+ /* CTRLR0[13] Shift Register Loop */
+ cr0 |= ((spi->mode & SPI_LOOP) ? 1 : 0) << DWC_SSI_CTRLR0_SRL_OFFSET;
+
+ return cr0;
+}
+EXPORT_SYMBOL_GPL(dw_spi_update_cr0_v1_01a);
+
static int dw_spi_transfer_one(struct spi_controller *master,
struct spi_device *spi, struct spi_transfer *transfer)
{
diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
index 2745a7e7405c..8fe724279d15 100644
--- a/drivers/spi/spi-dw.h
+++ b/drivers/spi/spi-dw.h
@@ -57,6 +57,15 @@
#define SPI_SRL_OFFSET 11
#define SPI_CFS_OFFSET 12
+/* Bit fields in CTRLR0 based on DWC_ssi_databook.pdf v1.01a */
+#define DWC_SSI_CTRLR0_SRL_OFFSET 13
+#define DWC_SSI_CTRLR0_TMOD_OFFSET 10
+#define DWC_SSI_CTRLR0_TMOD_MASK GENMASK(11, 10)
+#define DWC_SSI_CTRLR0_SCPOL_OFFSET 9
+#define DWC_SSI_CTRLR0_SCPH_OFFSET 8
+#define DWC_SSI_CTRLR0_FRF_OFFSET 6
+#define DWC_SSI_CTRLR0_DFS_OFFSET 0
+
/* Bit fields in SR, 7 bits */
#define SR_MASK 0x7f /* cover 7 bits */
#define SR_BUSY (1 << 0)
@@ -245,6 +254,9 @@ extern int dw_spi_resume_host(struct dw_spi *dws);
extern u32 dw_spi_update_cr0(struct spi_controller *master,
struct spi_device *spi,
struct spi_transfer *transfer);
+extern u32 dw_spi_update_cr0_v1_01a(struct spi_controller *master,
+ struct spi_device *spi,
+ struct spi_transfer *transfer);
/* platform related setup */
extern int dw_spi_mid_init(struct dw_spi *dws); /* Intel MID platforms */
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v5 4/7] dt-bindings: spi: dw-apb-ssi: Add compatible string for DesignWare DWC_ssi
2020-05-05 13:06 [PATCH v5 0/7] spi: dw: Add support for Intel Keem Bay SPI Wan Ahmad Zainie
` (2 preceding siblings ...)
2020-05-05 13:06 ` [PATCH v5 3/7] spi: dw: Add support for DesignWare DWC_ssi Wan Ahmad Zainie
@ 2020-05-05 13:06 ` Wan Ahmad Zainie
2020-05-05 13:06 ` [PATCH v5 5/7] spi: dw: Add support for Intel Keem Bay SPI Wan Ahmad Zainie
` (3 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Wan Ahmad Zainie @ 2020-05-05 13:06 UTC (permalink / raw)
To: broonie, robh+dt
Cc: linux-spi, devicetree, andriy.shevchenko, wan.ahmad.zainie.wan.mohamad
This patch adds compatible string "snps,dwc-ssi-1.01a" to the above DT
binding document, to provide support for DesignWare DWC_ssi IP [1].
Current driver supports DW_apb_ssi IP [2].
References:
[1] https://www.synopsys.com/dw/ipdir.php?c=dwc_ssi
[2] https://www.synopsys.com/dw/ipdir.php?c=DW_apb_ssi
Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
---
Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
index 3ed08ee9feba..2ead46b633ea 100644
--- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
@@ -2,7 +2,7 @@ Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface.
Required properties:
- compatible : "snps,dw-apb-ssi" or "mscc,<soc>-spi", where soc is "ocelot" or
- "jaguar2", or "amazon,alpine-dw-apb-ssi"
+ "jaguar2", or "amazon,alpine-dw-apb-ssi", or "snps,dwc-ssi-1.01a"
- reg : The register base for the controller. For "mscc,<soc>-spi", a second
register set is required (named ICPU_CFG:SPI_MST)
- interrupts : One interrupt, used by the controller.
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v5 5/7] spi: dw: Add support for Intel Keem Bay SPI
2020-05-05 13:06 [PATCH v5 0/7] spi: dw: Add support for Intel Keem Bay SPI Wan Ahmad Zainie
` (3 preceding siblings ...)
2020-05-05 13:06 ` [PATCH v5 4/7] dt-bindings: spi: dw-apb-ssi: Add compatible string " Wan Ahmad Zainie
@ 2020-05-05 13:06 ` Wan Ahmad Zainie
2020-05-05 13:06 ` [PATCH v5 6/7] dt-bindings: spi: dw-apb-ssi: Add Intel Keem Bay support Wan Ahmad Zainie
` (2 subsequent siblings)
7 siblings, 0 replies; 10+ messages in thread
From: Wan Ahmad Zainie @ 2020-05-05 13:06 UTC (permalink / raw)
To: broonie, robh+dt
Cc: linux-spi, devicetree, andriy.shevchenko, wan.ahmad.zainie.wan.mohamad
Add support for Intel Keem Bay SPI controller, which uses DesignWare
DWC_ssi core. Bit 31 of CTRLR0 register is added for Keem Bay, to
configure the device as a master or as a slave serial peripheral.
Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
---
drivers/spi/spi-dw-mmio.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/drivers/spi/spi-dw-mmio.c b/drivers/spi/spi-dw-mmio.c
index 1df6f3deee2c..abd3bb5e52db 100644
--- a/drivers/spi/spi-dw-mmio.c
+++ b/drivers/spi/spi-dw-mmio.c
@@ -44,6 +44,13 @@ struct dw_spi_mmio {
#define MSCC_SPI_MST_SW_MODE_SW_PIN_CTRL_MODE BIT(13)
#define MSCC_SPI_MST_SW_MODE_SW_SPI_CS(x) (x << 5)
+/*
+ * For Keem Bay, CTRLR0[31] is used to select controller mode.
+ * 0: SSI is slave
+ * 1: SSI is master
+ */
+#define KEEMBAY_CTRLR0_SSIC_IS_MST BIT(31)
+
struct dw_spi_mscc {
struct regmap *syscon;
void __iomem *spi_mst;
@@ -155,6 +162,24 @@ static int dw_spi_dwc_ssi_init(struct platform_device *pdev,
return 0;
}
+static u32 dw_spi_update_cr0_keembay(struct spi_controller *master,
+ struct spi_device *spi,
+ struct spi_transfer *transfer)
+{
+ u32 cr0 = dw_spi_update_cr0_v1_01a(master, spi, transfer);
+
+ return cr0 | KEEMBAY_CTRLR0_SSIC_IS_MST;
+}
+
+static int dw_spi_keembay_init(struct platform_device *pdev,
+ struct dw_spi_mmio *dwsmmio)
+{
+ /* Register hook to configure CTRLR0 */
+ dwsmmio->dws.update_cr0 = dw_spi_update_cr0_keembay;
+
+ return 0;
+}
+
static int dw_spi_mmio_probe(struct platform_device *pdev)
{
int (*init_func)(struct platform_device *pdev,
@@ -254,6 +279,7 @@ static const struct of_device_id dw_spi_mmio_of_match[] = {
{ .compatible = "amazon,alpine-dw-apb-ssi", .data = dw_spi_alpine_init},
{ .compatible = "renesas,rzn1-spi", .data = dw_spi_dw_apb_init},
{ .compatible = "snps,dwc-ssi-1.01a", .data = dw_spi_dwc_ssi_init},
+ { .compatible = "intel,keembay-ssi", .data = dw_spi_keembay_init},
{ /* end of table */}
};
MODULE_DEVICE_TABLE(of, dw_spi_mmio_of_match);
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v5 6/7] dt-bindings: spi: dw-apb-ssi: Add Intel Keem Bay support
2020-05-05 13:06 [PATCH v5 0/7] spi: dw: Add support for Intel Keem Bay SPI Wan Ahmad Zainie
` (4 preceding siblings ...)
2020-05-05 13:06 ` [PATCH v5 5/7] spi: dw: Add support for Intel Keem Bay SPI Wan Ahmad Zainie
@ 2020-05-05 13:06 ` Wan Ahmad Zainie
2020-05-05 13:06 ` [PATCH v5 7/7] dt-bindings: spi: dw-apb-ssi: Convert bindings to json-schema Wan Ahmad Zainie
2020-05-05 14:08 ` [PATCH v5 0/7] spi: dw: Add support for Intel Keem Bay SPI Mark Brown
7 siblings, 0 replies; 10+ messages in thread
From: Wan Ahmad Zainie @ 2020-05-05 13:06 UTC (permalink / raw)
To: broonie, robh+dt
Cc: linux-spi, devicetree, andriy.shevchenko, wan.ahmad.zainie.wan.mohamad
Document Intel Keem Bay SPI controller DT bindings.
Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
---
Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
index 2ead46b633ea..7a4702edf896 100644
--- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
@@ -2,7 +2,8 @@ Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface.
Required properties:
- compatible : "snps,dw-apb-ssi" or "mscc,<soc>-spi", where soc is "ocelot" or
- "jaguar2", or "amazon,alpine-dw-apb-ssi", or "snps,dwc-ssi-1.01a"
+ "jaguar2", or "amazon,alpine-dw-apb-ssi", or "snps,dwc-ssi-1.01a" or
+ "intel,keembay-ssi"
- reg : The register base for the controller. For "mscc,<soc>-spi", a second
register set is required (named ICPU_CFG:SPI_MST)
- interrupts : One interrupt, used by the controller.
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v5 7/7] dt-bindings: spi: dw-apb-ssi: Convert bindings to json-schema
2020-05-05 13:06 [PATCH v5 0/7] spi: dw: Add support for Intel Keem Bay SPI Wan Ahmad Zainie
` (5 preceding siblings ...)
2020-05-05 13:06 ` [PATCH v5 6/7] dt-bindings: spi: dw-apb-ssi: Add Intel Keem Bay support Wan Ahmad Zainie
@ 2020-05-05 13:06 ` Wan Ahmad Zainie
2020-05-05 19:19 ` Rob Herring
2020-05-05 14:08 ` [PATCH v5 0/7] spi: dw: Add support for Intel Keem Bay SPI Mark Brown
7 siblings, 1 reply; 10+ messages in thread
From: Wan Ahmad Zainie @ 2020-05-05 13:06 UTC (permalink / raw)
To: broonie, robh+dt
Cc: linux-spi, devicetree, andriy.shevchenko, wan.ahmad.zainie.wan.mohamad
Convert the Synopsis DesignWare dw-apb-ssi binding to DT schema format
using json-schema.
Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
---
.../bindings/spi/snps,dw-apb-ssi.txt | 42 -----------
.../bindings/spi/snps,dw-apb-ssi.yaml | 72 +++++++++++++++++++
2 files changed, 72 insertions(+), 42 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
create mode 100644 Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
deleted file mode 100644
index 7a4702edf896..000000000000
--- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
+++ /dev/null
@@ -1,42 +0,0 @@
-Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface.
-
-Required properties:
-- compatible : "snps,dw-apb-ssi" or "mscc,<soc>-spi", where soc is "ocelot" or
- "jaguar2", or "amazon,alpine-dw-apb-ssi", or "snps,dwc-ssi-1.01a" or
- "intel,keembay-ssi"
-- reg : The register base for the controller. For "mscc,<soc>-spi", a second
- register set is required (named ICPU_CFG:SPI_MST)
-- interrupts : One interrupt, used by the controller.
-- #address-cells : <1>, as required by generic SPI binding.
-- #size-cells : <0>, also as required by generic SPI binding.
-- clocks : phandles for the clocks, see the description of clock-names below.
- The phandle for the "ssi_clk" is required. The phandle for the "pclk" clock
- is optional. If a single clock is specified but no clock-name, it is the
- "ssi_clk" clock. If both clocks are listed, the "ssi_clk" must be first.
-
-Optional properties:
-- clock-names : Contains the names of the clocks:
- "ssi_clk", for the core clock used to generate the external SPI clock.
- "pclk", the interface clock, required for register access. If a clock domain
- used to enable this clock then it should be named "pclk_clkdomain".
-- cs-gpios : Specifies the gpio pins to be used for chipselects.
-- num-cs : The number of chipselects. If omitted, this will default to 4.
-- reg-io-width : The I/O register width (in bytes) implemented by this
- device. Supported values are 2 or 4 (the default).
-
-Child nodes as per the generic SPI binding.
-
-Example:
-
- spi@fff00000 {
- compatible = "snps,dw-apb-ssi";
- reg = <0xfff00000 0x1000>;
- interrupts = <0 154 4>;
- #address-cells = <1>;
- #size-cells = <0>;
- clocks = <&spi_m_clk>;
- num-cs = <2>;
- cs-gpios = <&gpio0 13 0>,
- <&gpio0 14 0>;
- };
-
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
new file mode 100644
index 000000000000..edc1e6fb9993
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface
+
+maintainers:
+ - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
+
+allOf:
+ - $ref: "spi-controller.yaml#"
+
+properties:
+ compatible:
+ enum:
+ - mscc,ocelot-spi
+ - mscc,jaguar2-spi
+ - amazon,alpine-dw-apb-ssi
+ - snps,dw-apb-ssi
+ - snps,dwc-ssi-1.01a
+ - intel,keembay-ssi
+
+ reg:
+ minItems: 1
+ maxItems: 2
+ items:
+ - description: The register base for the controller.
+ - description: For "mscc,<soc>-spi", a second register set is required.
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 2
+ items:
+ - description: The core clock used to generate the external SPI clock.
+ - description: The interface clock required for register access.
+
+ clock-names:
+ items:
+ - const: ssi_clk
+ - const: pclk
+
+ reg-io-width:
+ allOf:
+ - $ref: /schemas/types.yaml#/definitions/uint32
+ - enum: [ 2, 4 ]
+ - default: 4
+ description: The I/O register width (in bytes) implemented by this device.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+examples:
+ - |
+ spi@fff00000 {
+ compatible = "snps,dw-apb-ssi";
+ reg = <0xfff00000 0x1000>;
+ interrupts = <0 154 4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&spi_m_clk>;
+ num-cs = <2>;
+ cs-gpios = <&gpio0 13 0>,
+ <&gpio0 14 0>;
+ };
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v5 7/7] dt-bindings: spi: dw-apb-ssi: Convert bindings to json-schema
2020-05-05 13:06 ` [PATCH v5 7/7] dt-bindings: spi: dw-apb-ssi: Convert bindings to json-schema Wan Ahmad Zainie
@ 2020-05-05 19:19 ` Rob Herring
0 siblings, 0 replies; 10+ messages in thread
From: Rob Herring @ 2020-05-05 19:19 UTC (permalink / raw)
To: Wan Ahmad Zainie; +Cc: broonie, linux-spi, devicetree, andriy.shevchenko
On Tue, May 05, 2020 at 09:06:18PM +0800, Wan Ahmad Zainie wrote:
> Convert the Synopsis DesignWare dw-apb-ssi binding to DT schema format
> using json-schema.
>
> Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
> ---
> .../bindings/spi/snps,dw-apb-ssi.txt | 42 -----------
> .../bindings/spi/snps,dw-apb-ssi.yaml | 72 +++++++++++++++++++
> 2 files changed, 72 insertions(+), 42 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
> create mode 100644 Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> new file mode 100644
> index 000000000000..edc1e6fb9993
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml
> @@ -0,0 +1,72 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/spi/snps,dw-apb-ssi.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface
> +
> +maintainers:
> + - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>
> +
> +allOf:
> + - $ref: "spi-controller.yaml#"
> +
> +properties:
> + compatible:
> + enum:
> + - mscc,ocelot-spi
> + - mscc,jaguar2-spi
> + - amazon,alpine-dw-apb-ssi
> + - snps,dw-apb-ssi
> + - snps,dwc-ssi-1.01a
> + - intel,keembay-ssi
This doesn't match what's in dts files. You have to list out every
combination.
> +
> + reg:
> + minItems: 1
> + maxItems: 2
> + items:
> + - description: The register base for the controller.
> + - description: For "mscc,<soc>-spi", a second register set is required.
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + minItems: 1
> + maxItems: 2
> + items:
> + - description: The core clock used to generate the external SPI clock.
> + - description: The interface clock required for register access.
> +
> + clock-names:
> + items:
> + - const: ssi_clk
> + - const: pclk
> +
> + reg-io-width:
> + allOf:
> + - $ref: /schemas/types.yaml#/definitions/uint32
> + - enum: [ 2, 4 ]
> + - default: 4
> + description: The I/O register width (in bytes) implemented by this device.
> +
> +required:
> + - compatible
> + - reg
> + - interrupts
> + - clocks
> +
> +examples:
> + - |
> + spi@fff00000 {
> + compatible = "snps,dw-apb-ssi";
> + reg = <0xfff00000 0x1000>;
> + interrupts = <0 154 4>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&spi_m_clk>;
> + num-cs = <2>;
> + cs-gpios = <&gpio0 13 0>,
> + <&gpio0 14 0>;
> + };
> --
> 2.17.1
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v5 0/7] spi: dw: Add support for Intel Keem Bay SPI
2020-05-05 13:06 [PATCH v5 0/7] spi: dw: Add support for Intel Keem Bay SPI Wan Ahmad Zainie
` (6 preceding siblings ...)
2020-05-05 13:06 ` [PATCH v5 7/7] dt-bindings: spi: dw-apb-ssi: Convert bindings to json-schema Wan Ahmad Zainie
@ 2020-05-05 14:08 ` Mark Brown
7 siblings, 0 replies; 10+ messages in thread
From: Mark Brown @ 2020-05-05 14:08 UTC (permalink / raw)
To: robh+dt, Wan Ahmad Zainie; +Cc: andriy.shevchenko, linux-spi, devicetree
On Tue, 5 May 2020 21:06:11 +0800, Wan Ahmad Zainie wrote:
> This patchset adds support for DesignWare DWC_ssi. This soft IP
> is an AMBA version 2.0-compliant AHB slave device. Existing driver
> already supports the older APB version.
>
> Intel Keem Bay SPI controller is using this IP. This patchset is
> tested on Keem Bay evaluation module board.
>
> [...]
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-5.8
Thanks!
[1/7] spi: dw: Fix typo in few registers name
commit: 299cb65c9dd4791242a102f216583773d962c1ac
[2/7] spi: dw: Add update_cr0() callback to update CTRLR0
commit: c4eadee21fa9afd3dc9dd867c71b642177bf671f
[3/7] spi: dw: Add support for DesignWare DWC_ssi
commit: e539f435cb9c78c6984b75f16b65a2ece7867981
[4/7] spi: dw-apb-ssi: Add compatible string for DesignWare DWC_ssi
commit: 3812a081d2fcc297d039c4ffafa7778d75abcbe2
[5/7] spi: dw: Add support for Intel Keem Bay SPI
commit: f42377916ed534649341777669628f22ef1edf59
[6/7] spi: dw-apb-ssi: Add Intel Keem Bay support
commit: c48e0c533e72ca264ac914addccab8a328806ed3
[7/7] dt-bindings: spi: dw-apb-ssi: Convert bindings to json-schema
(not applied)
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
Thanks,
Mark
^ permalink raw reply [flat|nested] 10+ messages in thread