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From: Serge Semin <fancer.lancer@gmail.com>
To: Mark Brown <broonie@kernel.org>
Cc: Sean Anderson <seanga2@gmail.com>,
	Damien Le Moal <damien.lemoal@wdc.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	linux-riscv@lists.infradead.org, Rob Herring <robh+dt@kernel.org>,
	Frank Rowand <frowand.list@gmail.com>,
	devicetree@vger.kernel.org, linux-spi@vger.kernel.org,
	Stephen Boyd <sboyd@kernel.org>,
	linux-clk@vger.kernel.org,
	Linus Walleij <linus.walleij@linaro.org>,
	linux-gpio@vger.kernel.org,
	Philipp Zabel <p.zabel@pengutronix.de>
Subject: Re: [PATCH 03/32] spi: dw: Fix driving MOSI low while recieving
Date: Tue, 10 Nov 2020 00:05:31 +0300	[thread overview]
Message-ID: <20201109210531.wp4dmug4w2r4kh4p@mobilestation> (raw)
In-Reply-To: <20201109202052.GL6380@sirena.org.uk>

On Mon, Nov 09, 2020 at 08:20:52PM +0000, Mark Brown wrote:
> On Mon, Nov 09, 2020 at 10:19:09PM +0300, Serge Semin wrote:
> > On Mon, Nov 09, 2020 at 02:14:22PM +0000, Mark Brown wrote:
> 
> > > I'd expect it'd perform better, especially on systems that are
> > > apparently struggling for CPU bandwidth like yours seems to.
> 
> > CPU-wise. RO-mode won't help in that case. Moreover it will be even
> > more errors-prone for the systems with small CPU bandwidth. As I said
> 
> Right, these are two separate issues - one is that the client device
> has requirements on the transmit data at times when the driver isn't
> defining what should be transmitted, the other is that the controller
> driver is using full duplex mode even for single duplex data.  I just
> happened to notice the second issue while reviewing the change - there
> shouldn't be any code for setting the dummy transmit pattern in the
> driver in the first place.
> 
> > 2) Rx-only with atomic CPU utilization. In order to make sure that the
> > CPU keeps up with fetching the data from the Rx FIFO, we have to
> > disable the local CPU IRQs while performing the Rx-only transfers, so
> > to prevent the Rx FIFO overflow while the CPU is doing something else.
> 
> ...
> 
> > So in all other cases for normal CPU-based SPI-transfers when
> > GPIO-based chip-select is available the safest solution would be to
> > use a normal Push-Pull mode. In this case we have no risk in getting
> > the Rx FIFO overflow unless there is a bug in the code, which is
> > fixable anyway.
> 

> I'm not clear why we would have issues with the FIFO overflowing in PIO
> mode, especially with a GPIO chip select - even if we're forced to tell
> the controller how big the transfer is if we're using a GPIO chip select

> we could just tell it we're doing a series of FIFO sized transfers?

Hm, you are right. Splitting the Rx-only transfers on the chunks with
lengths smaller than the FIFO size indeed would have solved the
problem of the Rx FIFO overflow with GPIO-based CS hardware. Don't
really know how I missed that. Most likely because when concerning the
Tx-only/Rx-only/EEPROM-read modes I always think about the native
chip-select automatic assertion/de-assertion, in which case we have no
other way but to provide the SPI-transfers/message atomicity.

> 
> > Another possible solution for the problem would be to fix the SPI core
> > so aside with tx_buf being set to the NULL-pointer, a client driver
> > would provide a default level or some specific value being put to the
> > SPI bus on Rx-only transfers. If an SPI-controller is capable of
> > satisfying the request, then it will accept the transfer. If it's not,
> > then the SPI core may try to convert the Rx-only transfer into the
> > Full-duplex transfer with the Tx-buffer being initialized with the
> > requested level.
> 

> We do have support in the core for creating dummy data buffers for
> controllers that can't do half duplex - that's the SPI_MUST_TX and
> matching SPI_MUST_RX that I mentioned in my initial reply.  Currently we
> always zero fill transmit buffers, the expected semantic is that if the
> client driver isn't supplying data that means the device doesn't care
> what gets sent and it's not clear to me that it isn't sensible to just
> keep that like I said earlier,

> I don't know how common it's going to be
> to need this since most half duplex transfers generally are half duplex.
> The whole point with the SPI_MUST_ flags was to remove the need for
> controller drivers to open code handling this, it was adding
> complication and supporting configuration of the dummy data feels like
> it's adding room for things to go wrong.

If by general Rx-only half-duplex transfers you meant that the client
SPI-device shall just not care what the MOSI level, then the only
acceptable solution of the noted in this patch problem is to fix the
client driver. Since in case of the MMC-SPI client device sometimes it
does care about the level.

-Sergey


  reply	other threads:[~2020-11-09 21:05 UTC|newest]

Thread overview: 132+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-07  8:13 [PATCH 00/32] RISC-V Kendryte K210 support improvments Damien Le Moal
2020-11-07  8:13 ` [PATCH 01/32] of: Fix property supplier parsing Damien Le Moal
2020-11-09 15:05   ` Serge Semin
2020-11-09 15:14   ` Andy Shevchenko
2020-11-09 17:44     ` Serge Semin
2020-11-09 20:52       ` Rob Herring
2020-11-07  8:13 ` [PATCH 02/32] spi: dw: Add support for 32-bits ctrlr0 layout Damien Le Moal
2020-11-07 13:28   ` Sean Anderson
2020-11-09 14:25   ` Serge Semin
2020-11-09 14:33     ` Sean Anderson
2020-11-09 14:35       ` Sean Anderson
2020-11-09 14:40       ` Andy Shevchenko
2020-11-09 14:41         ` Andy Shevchenko
2020-11-09 14:49           ` Sean Anderson
2020-11-09 15:10             ` Andy Shevchenko
2020-11-09 14:36     ` Andy Shevchenko
2020-11-09 17:56       ` Serge Semin
2020-11-07  8:13 ` [PATCH 03/32] spi: dw: Fix driving MOSI low while recieving Damien Le Moal
2020-11-07 13:30   ` Sean Anderson
2020-11-09 13:29   ` Mark Brown
2020-11-09 13:47     ` Sean Anderson
2020-11-09 14:14       ` Mark Brown
2020-11-09 14:48         ` Serge Semin
2020-11-09 16:45           ` Mark Brown
2020-11-09 19:19         ` Serge Semin
2020-11-09 19:40           ` Sean Anderson
2020-11-09 20:17             ` Serge Semin
2020-11-09 20:29               ` Mark Brown
2020-11-09 20:20           ` Mark Brown
2020-11-09 21:05             ` Serge Semin [this message]
2020-11-10 13:43               ` Mark Brown
2020-11-07  8:13 ` [PATCH 04/32] spi: dw: Introduce polling device tree property Damien Le Moal
2020-11-09 16:04   ` Mark Brown
2020-11-09 19:59   ` Serge Semin
2020-11-13  9:22     ` Damien Le Moal
2020-11-15 16:01       ` Serge Semin
2020-11-16  7:47         ` Damien Le Moal
2020-11-16 12:33           ` Mark Brown
2020-11-16 21:55           ` Serge Semin
2020-11-17 14:44             ` Damien Le Moal
2020-11-17 18:26               ` Serge Semin
2020-11-18  4:41                 ` Damien Le Moal
2020-11-18 15:16                   ` Serge Semin
2020-11-19  5:12                     ` Damien Le Moal
2020-11-19  8:51                       ` Serge Semin
2020-11-19  8:57                         ` Damien Le Moal
2020-11-07  8:13 ` [PATCH 05/32] spi: dw: Introduce DW_SPI_CAP_POLL_NODELAY Damien Le Moal
2020-11-09 14:03   ` Mark Brown
2020-11-09 20:45   ` Serge Semin
2020-11-07  8:13 ` [PATCH 06/32] spi: dw: Add support for the Kendryte K210 SoC Damien Le Moal
2020-11-07 13:31   ` Sean Anderson
2020-11-07 13:42     ` Damien Le Moal
2020-11-07 13:52       ` Sean Anderson
2020-11-09 14:15         ` Mark Brown
2020-11-13  8:00     ` Damien Le Moal
2020-11-09 21:21   ` Serge Semin
2020-11-09 21:39     ` Damien Le Moal
2020-11-09 21:55       ` Rob Herring
2020-11-09 22:00         ` Damien Le Moal
2020-11-09 23:07           ` Rob Herring
2020-11-10  0:35             ` Damien Le Moal
2020-11-07  8:13 ` [PATCH 07/32] dt-bindings: Update DW SPI device tree bindings Damien Le Moal
2020-11-07  8:13 ` [PATCH 08/32] riscv: Fix kernel time_init() Damien Le Moal
2020-11-12  7:21   ` Atish Patra
2020-11-13  7:31   ` Stephen Boyd
2020-11-07  8:13 ` [PATCH 09/32] riscv: Fix SiFive gpio probe Damien Le Moal
2020-11-10 14:39   ` Linus Walleij
2020-11-07  8:13 ` [PATCH 10/32] riscv: Fix sifive serial driver Damien Le Moal
2020-11-07  8:13 ` [PATCH 11/32] riscv: Enable interrupts during syscalls with M-Mode Damien Le Moal
2020-11-07  8:14 ` [PATCH 12/32] riscv: Automatically select sysctl config options Damien Le Moal
2020-11-07  8:14 ` [PATCH 13/32] riscv: Fix builtin DTB handling Damien Le Moal
2020-11-15  4:17   ` kernel test robot
2020-11-07  8:14 ` [PATCH 14/32] dt-bindings: Define all Kendryte K210 clock IDs Damien Le Moal
2020-11-07 13:33   ` Sean Anderson
2020-11-07  8:14 ` [PATCH 15/32] dt-bindings: Define Kendryte K210 sysctl registers Damien Le Moal
2020-11-07 13:34   ` Sean Anderson
2020-11-09 21:59   ` Rob Herring
2020-11-09 22:10     ` Sean Anderson
2020-11-09 23:01       ` Rob Herring
2020-11-07  8:14 ` [PATCH 16/32] dt-bindings: Define Kendryte K210 pin functions Damien Le Moal
2020-11-07 13:38   ` Sean Anderson
2020-11-07  8:14 ` [PATCH 17/32] dt-bindings: Define Kendryte K210 reset signals Damien Le Moal
2020-11-07 13:38   ` Sean Anderson
2020-11-07  8:14 ` [PATCH 18/32] riscv: Add Kendryte K210 SoC clock driver Damien Le Moal
2020-11-07 13:48   ` Sean Anderson
2020-11-07  8:14 ` [PATCH 19/32] riscv: Add Kendryte K210 SoC reset controller Damien Le Moal
2020-11-07 13:58   ` Sean Anderson
2020-11-07  8:14 ` [PATCH 20/32] riscv: Add Kendryte K210 FPIOA pinctrl driver Damien Le Moal
2020-11-09 18:48   ` kernel test robot
2020-11-15  0:28   ` kernel test robot
2020-11-24  8:43   ` Linus Walleij
2020-11-24  8:53     ` Damien Le Moal
2020-11-29 21:33       ` Linus Walleij
2020-11-30  3:13         ` Damien Le Moal
2020-11-30  7:05           ` Serge Semin
2020-11-30  7:27             ` Damien Le Moal
2020-11-24  8:56     ` Damien Le Moal
2020-11-07  8:14 ` [PATCH 21/32] dt-bindings: Add Kendryte and Canaan vendor prefix Damien Le Moal
2020-11-07 14:03   ` Sean Anderson
2020-11-13  8:17     ` Damien Le Moal
2020-11-09 22:01   ` Rob Herring
2020-11-09 22:04     ` Damien Le Moal
2020-11-07  8:14 ` [PATCH 22/32] dt-binding: Document kendryte,k210-sysctl bindings Damien Le Moal
2020-11-07 14:05   ` Sean Anderson
2020-11-09 15:32   ` Rob Herring
2020-11-07  8:14 ` [PATCH 23/32] dt-binding: Document kendryte,k210-clk bindings Damien Le Moal
2020-11-07 14:05   ` Sean Anderson
2020-11-09 21:58   ` Rob Herring
2020-11-07  8:14 ` [PATCH 24/32] dt-bindings: Document kendryte,k210-fpioa bindings Damien Le Moal
2020-11-07 14:06   ` Sean Anderson
2020-11-09 15:32   ` Rob Herring
2020-11-09 15:36   ` Rob Herring
2020-11-09 15:45     ` Sean Anderson
2020-11-11 14:32       ` Rob Herring
2020-11-19 10:57       ` Geert Uytterhoeven
2020-11-19 11:22         ` Damien Le Moal
2020-11-07  8:14 ` [PATCH 25/32] dt-bindings: Document kendryte,k210-rst bindings Damien Le Moal
2020-11-07 14:07   ` Sean Anderson
2020-11-09 15:37   ` Rob Herring
2020-11-09 15:41   ` Rob Herring
2020-11-07  8:14 ` [PATCH 26/32] riscv: Update Kendryte K210 device tree Damien Le Moal
2020-11-07 14:08   ` Sean Anderson
2020-11-07  8:14 ` [PATCH 27/32] riscv: Add SiPeed MAIX BiT board " Damien Le Moal
2020-11-07 14:13   ` Sean Anderson
2020-11-07  8:14 ` [PATCH 28/32] riscv: Add SiPeed MAIX DOCK " Damien Le Moal
2020-11-07  8:14 ` [PATCH 29/32] riscv: Add SiPeed MAIX GO " Damien Le Moal
2020-11-07  8:14 ` [PATCH 30/32] riscv: Add SiPeed MAIXDUINO " Damien Le Moal
2020-11-07 14:14   ` Sean Anderson
2020-11-07  8:14 ` [PATCH 31/32] riscv: Add Kendryte KD233 " Damien Le Moal
2020-11-07  8:14 ` [PATCH 32/32] riscv: Update Kendryte K210 defconfig Damien Le Moal
2020-11-09 12:51 ` [PATCH 00/32] RISC-V Kendryte K210 support improvments Mark Brown
2020-11-09 12:55   ` Damien Le Moal

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