* [PATCH v8 0/9] Add octal DTR support for Macronix flash
@ 2024-02-01 9:43 Jaime Liao
2024-02-01 9:43 ` [PATCH v8 1/9] mtd: spi-nor: add Octal " Jaime Liao
` (9 more replies)
0 siblings, 10 replies; 20+ messages in thread
From: Jaime Liao @ 2024-02-01 9:43 UTC (permalink / raw)
To: linux-mtd, linux-spi, tudor.ambarus, pratyush, mwalle,
miquel.raynal, richard, vigneshr, broonie
Cc: leoyu, jaimeliao
From: JaimeLiao <jaimeliao@mxic.com.tw>
Add method for Macronix Octal DTR Eable/Disable.
Merge Tudor's patch "Allow specifying the byte order in DTR mode"
Add support for Macronix flash
v8:
Supplement missing S-o-b
Remove function spi_nor_is_octal_dtr_swab16
Split IDs by MX25 & MX66
Add dump of capability in debugfs
Add dump of params in debugfs
Add dump of reult for mtd-utils tests
Add SNOR_ID(0xC2) in last of Macronix ID table
v7:
Add dtr_swab16 judgement to enable/disable Macronix xSPI host
controller swap byte feature.
v6:
Add byte swap support for spi-mxic.c
Remove flash name in ID table.
v5:
Remove manufacturer read id function.
For increased readability, separate Flash IDs based on whether
it supports RWW feature.
v4:
Add patch for adding manufacturer read id function.
remove patch "hook manufacturer by checking first byte id"
v3:
Add patch for hook manufacturer by comparing ID 1st byte.
Add patches for specifying the byte order in DTR mode by merging
Tudor's patch.
v2:
Following exsting rules to re-create Macronix specify Octal DTR method.
change signature to jaimeliao@mxic.com.tw
Clear sector size information in flash INFO.
JaimeLiao (9):
mtd: spi-nor: add Octal DTR support for Macronix flash
spi: spi-mem: Allow specifying the byte order in Octal DTR mode
mtd: spi-nor: core: Allow specifying the byte order in Octal DTR mode
mtd: spi-nor: sfdp: Get the 8D-8D-8D byte order from BFPT
spi: mxic: Add support for swapping byte
mtd: spi-nor: add support for Macronix Octal flash MX25 series with
RWW feature
mtd: spi-nor: add support for Macronix Octal flash MX66 series with
RWW feature
mtd: spi-nor: add support for Macronix Octal flash MX25 series
mtd: spi-nor: add support for Macronix Octal flash MX66 series
drivers/mtd/spi-nor/core.c | 5 +
drivers/mtd/spi-nor/core.h | 1 +
drivers/mtd/spi-nor/macronix.c | 169 +++++++++++++++++++++++++++++++++
drivers/mtd/spi-nor/sfdp.c | 4 +
drivers/mtd/spi-nor/sfdp.h | 1 +
drivers/spi/spi-mem.c | 4 +
drivers/spi/spi-mxic.c | 17 +++-
include/linux/spi/spi-mem.h | 6 ++
8 files changed, 203 insertions(+), 4 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v8 1/9] mtd: spi-nor: add Octal DTR support for Macronix flash
2024-02-01 9:43 [PATCH v8 0/9] Add octal DTR support for Macronix flash Jaime Liao
@ 2024-02-01 9:43 ` Jaime Liao
2024-02-01 9:43 ` [PATCH v8 2/9] spi: spi-mem: Allow specifying the byte order in Octal DTR mode Jaime Liao
` (8 subsequent siblings)
9 siblings, 0 replies; 20+ messages in thread
From: Jaime Liao @ 2024-02-01 9:43 UTC (permalink / raw)
To: linux-mtd, linux-spi, tudor.ambarus, pratyush, mwalle,
miquel.raynal, richard, vigneshr, broonie
Cc: leoyu, jaimeliao
From: JaimeLiao <jaimeliao@mxic.com.tw>
Create Macronix specify method for enable Octal DTR mode and
set 20 dummy cycles to allow running at the maximum supported
frequency for Macronix Octal flash.
Use number of dummy cycles which is parse by SFDP then convert
it to bit pattern and set in CR2 register.
Set CR2 register for enable octal DTR mode.
Use Read ID to confirm that enabling/diabling octal DTR mode
was successful.
Macronix ID format is A-A-B-B-C-C in octal DTR mode.
To ensure the successful enablement of octal DTR mode, confirm
that the 6-byte data is entirely correct.
Co-developed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw>
Acked-by: Michael Walle <mwalle@kernel.org>
---
drivers/mtd/spi-nor/macronix.c | 100 +++++++++++++++++++++++++++++++++
1 file changed, 100 insertions(+)
diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
index ea6be95e75a5..dee71776b1a8 100644
--- a/drivers/mtd/spi-nor/macronix.c
+++ b/drivers/mtd/spi-nor/macronix.c
@@ -8,6 +8,24 @@
#include "core.h"
+#define SPINOR_OP_MXIC_RD_ANY_REG 0x71 /* Read volatile configuration register 2 */
+#define SPINOR_OP_MXIC_WR_ANY_REG 0x72 /* Write volatile configuration register 2 */
+#define SPINOR_REG_MXIC_CR2_MODE 0x00000000 /* CR2 address for setting octal DTR mode */
+#define SPINOR_REG_MXIC_CR2_DC 0x00000300 /* CR2 address for setting dummy cycles */
+#define SPINOR_REG_MXIC_OPI_DTR_EN 0x2 /* Enable Octal DTR */
+#define SPINOR_REG_MXIC_SPI_EN 0x0 /* Enable SPI */
+#define SPINOR_REG_MXIC_ADDR_BYTES 4 /* Fixed R/W volatile address bytes to 4 */
+/* Convert dummy cycles to bit pattern */
+#define SPINOR_REG_MXIC_DC(p) \
+ ((20 - p)/2)
+
+/* Macronix SPI NOR flash operations. */
+#define MXIC_NOR_WR_ANY_REG_OP(naddr, addr, ndata, buf) \
+ SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_MXIC_WR_ANY_REG, 0), \
+ SPI_MEM_OP_ADDR(naddr, addr, 0), \
+ SPI_MEM_OP_NO_DUMMY, \
+ SPI_MEM_OP_DATA_OUT(ndata, buf, 0))
+
static int
mx25l25635_post_bfpt_fixups(struct spi_nor *nor,
const struct sfdp_parameter_header *bfpt_header,
@@ -185,6 +203,87 @@ static const struct flash_info macronix_nor_parts[] = {
}
};
+static int macronix_nor_octal_dtr_en(struct spi_nor *nor)
+{
+ struct spi_mem_op op;
+ u8 *buf = nor->bouncebuf, i;
+ int ret;
+
+ /* Use dummy cycles which is parse by SFDP and convert to bit pattern. */
+ buf[0] = SPINOR_REG_MXIC_DC(nor->params->reads[SNOR_CMD_READ_8_8_8_DTR].num_wait_states);
+ op = (struct spi_mem_op)
+ MXIC_NOR_WR_ANY_REG_OP(SPINOR_REG_MXIC_ADDR_BYTES,
+ SPINOR_REG_MXIC_CR2_DC, 1, buf);
+
+ ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
+ if (ret)
+ return ret;
+
+ /* Set the octal and DTR enable bits. */
+ buf[0] = SPINOR_REG_MXIC_OPI_DTR_EN;
+ op = (struct spi_mem_op)
+ MXIC_NOR_WR_ANY_REG_OP(SPINOR_REG_MXIC_ADDR_BYTES,
+ SPINOR_REG_MXIC_CR2_MODE, 1, buf);
+ ret = spi_nor_write_any_volatile_reg(nor, &op, nor->reg_proto);
+ if (ret)
+ return ret;
+
+ /* Read flash ID to make sure the switch was successful. */
+ ret = spi_nor_read_id(nor, 4, 4, buf, SNOR_PROTO_8_8_8_DTR);
+ if (ret) {
+ dev_dbg(nor->dev, "error %d reading JEDEC ID after enabling 8D-8D-8D mode\n", ret);
+ return ret;
+ }
+
+ /* Macronix SPI-NOR flash 8D-8D-8D read ID would get 6 bytes data A-A-B-B-C-C */
+ for (i = 0; i < nor->info->id->len; i++)
+ if (buf[i * 2] != buf[(i * 2) + 1] ||
+ buf[i * 2] != nor->info->id->bytes[i])
+ return -EINVAL;
+
+ return 0;
+}
+
+static int macronix_nor_octal_dtr_dis(struct spi_nor *nor)
+{
+ struct spi_mem_op op;
+ u8 *buf = nor->bouncebuf;
+ int ret;
+
+ /*
+ * The register is 1-byte wide, but 1-byte transactions are not
+ * allowed in 8D-8D-8D mode. Since there is no register at the
+ * next location, just initialize the value to 0 and let the
+ * transaction go on.
+ */
+ buf[0] = SPINOR_REG_MXIC_SPI_EN;
+ buf[1] = 0x0;
+ op = (struct spi_mem_op)
+ MXIC_NOR_WR_ANY_REG_OP(SPINOR_REG_MXIC_ADDR_BYTES,
+ SPINOR_REG_MXIC_CR2_MODE, 2, buf);
+ ret = spi_nor_write_any_volatile_reg(nor, &op, SNOR_PROTO_8_8_8_DTR);
+ if (ret)
+ return ret;
+
+ /* Read flash ID to make sure the switch was successful. */
+ ret = spi_nor_read_id(nor, 0, 0, buf, SNOR_PROTO_1_1_1);
+ if (ret) {
+ dev_dbg(nor->dev, "error %d reading JEDEC ID after disabling 8D-8D-8D mode\n", ret);
+ return ret;
+ }
+
+ if (memcmp(buf, nor->info->id->bytes, nor->info->id->len))
+ return -EINVAL;
+
+ return 0;
+}
+
+static int macronix_nor_set_octal_dtr(struct spi_nor *nor, bool enable)
+{
+ return enable ? macronix_nor_octal_dtr_en(nor) :
+ macronix_nor_octal_dtr_dis(nor);
+}
+
static void macronix_nor_default_init(struct spi_nor *nor)
{
nor->params->quad_enable = spi_nor_sr1_bit6_quad_enable;
@@ -194,6 +293,7 @@ static int macronix_nor_late_init(struct spi_nor *nor)
{
if (!nor->params->set_4byte_addr_mode)
nor->params->set_4byte_addr_mode = spi_nor_set_4byte_addr_mode_en4b_ex4b;
+ nor->params->set_octal_dtr = macronix_nor_set_octal_dtr;
return 0;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v8 2/9] spi: spi-mem: Allow specifying the byte order in Octal DTR mode
2024-02-01 9:43 [PATCH v8 0/9] Add octal DTR support for Macronix flash Jaime Liao
2024-02-01 9:43 ` [PATCH v8 1/9] mtd: spi-nor: add Octal " Jaime Liao
@ 2024-02-01 9:43 ` Jaime Liao
2024-02-01 12:04 ` Mark Brown
2024-02-01 15:18 ` Michael Walle
2024-02-01 9:43 ` [PATCH v8 3/9] mtd: spi-nor: core: " Jaime Liao
` (7 subsequent siblings)
9 siblings, 2 replies; 20+ messages in thread
From: Jaime Liao @ 2024-02-01 9:43 UTC (permalink / raw)
To: linux-mtd, linux-spi, tudor.ambarus, pratyush, mwalle,
miquel.raynal, richard, vigneshr, broonie
Cc: leoyu, jaimeliao
From: JaimeLiao <jaimeliao@mxic.com.tw>
There are NOR flashes (Macronix) that swap the bytes on a 16-bit
boundary when configured in Octal DTR mode. The byte order of
16-bit words is swapped when read or written in Octal Double
Transfer Rate (DTR) mode compared to Single Transfer Rate (STR)
modes. If one writes D0 D1 D2 D3 bytes using 1-1-1 mode, and uses
8D-8D-8D SPI mode for reading, it will read back D1 D0 D3 D2.
Swapping the bytes may introduce some endianness problems. It can
affect the boot sequence if the entire boot sequence is not handled
in either 8D-8D-8D mode or 1-1-1 mode. So we must swap the bytes
back to have the same byte order as in STR modes. Fortunately there
are controllers that could swap the bytes back at runtime,
addressing the flash's endiannesses requirements. Provide a way for
the upper layers to specify the byte order in Octal DTR mode.
Merge Tudor's patch and add modifications for suiting newer version
of Linux kernel.
Suggested-by: Michael Walle <mwalle@kernel.org>
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw>
---
drivers/spi/spi-mem.c | 4 ++++
include/linux/spi/spi-mem.h | 6 ++++++
2 files changed, 10 insertions(+)
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index 2dc8ceb85374..f8120f6b288f 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -172,6 +172,10 @@ bool spi_mem_default_supports_op(struct spi_mem *mem,
if (!spi_mem_controller_is_capable(ctlr, dtr))
return false;
+ if (op->data.swap16 &&
+ !spi_mem_controller_is_capable(ctlr, swap16))
+ return false;
+
if (op->cmd.nbytes != 2)
return false;
} else {
diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h
index f866d5c8ed32..8df44fbc9d99 100644
--- a/include/linux/spi/spi-mem.h
+++ b/include/linux/spi/spi-mem.h
@@ -89,6 +89,8 @@ enum spi_mem_data_dir {
* @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not
* @data.buswidth: number of IO lanes used to send/receive the data
* @data.dtr: whether the data should be sent in DTR mode or not
+ * @data.swap16: whether the byte order of 16-bit words is swapped when read
+ * or written in Octal DTR mode compared to STR mode.
* @data.ecc: whether error correction is required or not
* @data.dir: direction of the transfer
* @data.nbytes: number of data bytes to send/receive. Can be zero if the
@@ -123,6 +125,7 @@ struct spi_mem_op {
struct {
u8 buswidth;
u8 dtr : 1;
+ u8 swap16 : 1;
u8 ecc : 1;
u8 __pad : 6;
enum spi_mem_data_dir dir;
@@ -296,10 +299,13 @@ struct spi_controller_mem_ops {
/**
* struct spi_controller_mem_caps - SPI memory controller capabilities
* @dtr: Supports DTR operations
+ * @swap16: Supports swapping bytes on a 16 bit boundary when configured in
+ * Octal DTR
* @ecc: Supports operations with error correction
*/
struct spi_controller_mem_caps {
bool dtr;
+ bool swap16;
bool ecc;
};
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v8 3/9] mtd: spi-nor: core: Allow specifying the byte order in Octal DTR mode
2024-02-01 9:43 [PATCH v8 0/9] Add octal DTR support for Macronix flash Jaime Liao
2024-02-01 9:43 ` [PATCH v8 1/9] mtd: spi-nor: add Octal " Jaime Liao
2024-02-01 9:43 ` [PATCH v8 2/9] spi: spi-mem: Allow specifying the byte order in Octal DTR mode Jaime Liao
@ 2024-02-01 9:43 ` Jaime Liao
2024-02-01 15:28 ` Michael Walle
2024-02-01 9:43 ` [PATCH v8 4/9] mtd: spi-nor: sfdp: Get the 8D-8D-8D byte order from BFPT Jaime Liao
` (6 subsequent siblings)
9 siblings, 1 reply; 20+ messages in thread
From: Jaime Liao @ 2024-02-01 9:43 UTC (permalink / raw)
To: linux-mtd, linux-spi, tudor.ambarus, pratyush, mwalle,
miquel.raynal, richard, vigneshr, broonie
Cc: leoyu, jaimeliao
From: JaimeLiao <jaimeliao@mxic.com.tw>
Macronix swaps bytes on a 16-bit boundary when configured in Octal DTR.
The byte order of 16-bit words is swapped when read or written in 8D-8D-8D
mode compared to STR modes. Allow operations to specify the byte order in
DTR mode, so that controllers can swap the bytes back at run-time to
address the flash's endianness requirements, if they are capable. If the
controllers are not capable of swapping the bytes, the protocol is
downgrade via spi_nor_spimem_adjust_hwcaps(). When available, the swapping
of the bytes is always done regardless if it's a data or register access,
so that we comply with the JESD216 requirements: "Byte order of 16-bit
words is swapped when read in 8D-8D-8D mode compared to 1-1-1".
Merge Tudor's patch and add modifications for suiting newer version
of Linux kernel.
Suggested-by: Michael Walle <mwalle@kernel.org>
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw>
---
drivers/mtd/spi-nor/core.c | 5 +++++
drivers/mtd/spi-nor/core.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 4129764fad8c..0076007e1cde 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -113,6 +113,11 @@ void spi_nor_spimem_setup_op(const struct spi_nor *nor,
op->cmd.opcode = (op->cmd.opcode << 8) | ext;
op->cmd.nbytes = 2;
}
+
+ /* SWAP16 is only applicable when Octal DTR mode */
+ if (nor->read_proto == SNOR_PROTO_8_8_8_DTR)
+ if (nor->flags & SNOR_F_SWAP16)
+ op->data.swap16 = true;
}
/**
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index d36c0e072954..3c5190ac0a79 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -140,6 +140,7 @@ enum spi_nor_option_flags {
SNOR_F_RWW = BIT(14),
SNOR_F_ECC = BIT(15),
SNOR_F_NO_WP = BIT(16),
+ SNOR_F_SWAP16 = BIT(17),
};
struct spi_nor_read_command {
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v8 4/9] mtd: spi-nor: sfdp: Get the 8D-8D-8D byte order from BFPT
2024-02-01 9:43 [PATCH v8 0/9] Add octal DTR support for Macronix flash Jaime Liao
` (2 preceding siblings ...)
2024-02-01 9:43 ` [PATCH v8 3/9] mtd: spi-nor: core: " Jaime Liao
@ 2024-02-01 9:43 ` Jaime Liao
2024-02-01 9:43 ` [PATCH v8 5/9] spi: mxic: Add support for swapping byte Jaime Liao
` (5 subsequent siblings)
9 siblings, 0 replies; 20+ messages in thread
From: Jaime Liao @ 2024-02-01 9:43 UTC (permalink / raw)
To: linux-mtd, linux-spi, tudor.ambarus, pratyush, mwalle,
miquel.raynal, richard, vigneshr, broonie
Cc: leoyu, jaimeliao
From: JaimeLiao <jaimeliao@mxic.com.tw>
Parse BFPT in order to retrieve the byte order in 8D-8D-8D mode.
This info flag will be used as a basis to determine whether
there is byte swapping of data for SPI NOR flash in octal
DTR mode.
The controller driver will check whether byte swapping is supported
to determin whether the corresponding operation are supported, thus
avoiding the generation of unexpected data order.
Merge Tudor's patch and add modifications for suiting newer version
of Linux kernel.
Reviewed-by: Michael Walle <mwalle@kernel.org>
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw>
---
drivers/mtd/spi-nor/sfdp.c | 4 ++++
drivers/mtd/spi-nor/sfdp.h | 1 +
2 files changed, 5 insertions(+)
diff --git a/drivers/mtd/spi-nor/sfdp.c b/drivers/mtd/spi-nor/sfdp.c
index 57713de32832..1bdb82c1328c 100644
--- a/drivers/mtd/spi-nor/sfdp.c
+++ b/drivers/mtd/spi-nor/sfdp.c
@@ -677,6 +677,10 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,
return -EOPNOTSUPP;
}
+ /* Byte order in 8D-8D-8D mode */
+ if (bfpt.dwords[SFDP_DWORD(18)] & BFPT_DWORD18_BYTE_ORDER_SWAPPED)
+ nor->flags |= SNOR_F_SWAP16;
+
return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt);
}
diff --git a/drivers/mtd/spi-nor/sfdp.h b/drivers/mtd/spi-nor/sfdp.h
index da0fe5aa9bb0..6089d5bc1e4f 100644
--- a/drivers/mtd/spi-nor/sfdp.h
+++ b/drivers/mtd/spi-nor/sfdp.h
@@ -130,6 +130,7 @@ struct sfdp_bfpt {
#define BFPT_DWORD18_CMD_EXT_INV (0x1UL << 29) /* Invert */
#define BFPT_DWORD18_CMD_EXT_RES (0x2UL << 29) /* Reserved */
#define BFPT_DWORD18_CMD_EXT_16B (0x3UL << 29) /* 16-bit opcode */
+#define BFPT_DWORD18_BYTE_ORDER_SWAPPED BIT(31) /* Byte order of 16-bit words in 8D-8D-8D mode */
struct sfdp_parameter_header {
u8 id_lsb;
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v8 5/9] spi: mxic: Add support for swapping byte
2024-02-01 9:43 [PATCH v8 0/9] Add octal DTR support for Macronix flash Jaime Liao
` (3 preceding siblings ...)
2024-02-01 9:43 ` [PATCH v8 4/9] mtd: spi-nor: sfdp: Get the 8D-8D-8D byte order from BFPT Jaime Liao
@ 2024-02-01 9:43 ` Jaime Liao
2024-02-01 12:05 ` Mark Brown
2024-02-01 15:39 ` Michael Walle
2024-02-01 9:43 ` [PATCH v8 6/9] mtd: spi-nor: add support for Macronix Octal flash MX25 series with RWW feature Jaime Liao
` (4 subsequent siblings)
9 siblings, 2 replies; 20+ messages in thread
From: Jaime Liao @ 2024-02-01 9:43 UTC (permalink / raw)
To: linux-mtd, linux-spi, tudor.ambarus, pratyush, mwalle,
miquel.raynal, richard, vigneshr, broonie
Cc: leoyu, jaimeliao
From: JaimeLiao <jaimeliao@mxic.com.tw>
Some SPI-NOR flash swap the bytes on a 16-bit boundary when
configured in Octal DTR mode. It means data format D0 D1 D2 D3
would be swapped to D1 D0 D3 D2. So that whether controller
support swapping bytes should be checked before enable Octal
DTR mode. Add swap byte support on a 16-bit boundary when
configured in Octal DTR mode for Macronix xSPI host controller
dirver.
According dtr_swab in operation to enable/disable Macronix
xSPI host controller swap byte feature.
To make sure swap byte feature is working well, program data in
1S-1S-1S mode then read back and compare read data in 8D-8D-8D
mode.
This feature have been validated on byte-swap flash and
non-byte-swap flash.
Macronix xSPI host controller bit "HC_CFG_DATA_PASS" determine
the byte swap feature disabled/enabled and swap byte feature is
working on 8D-8D-8D mode only.
Suggested-by: Michael Walle <mwalle@kernel.org>
Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw>
---
drivers/spi/spi-mxic.c | 17 +++++++++++++----
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c
index 60c9f3048ac9..8ac302e48c9f 100644
--- a/drivers/spi/spi-mxic.c
+++ b/drivers/spi/spi-mxic.c
@@ -294,7 +294,8 @@ static void mxic_spi_hw_init(struct mxic_spi *mxic)
mxic->regs + HC_CFG);
}
-static u32 mxic_spi_prep_hc_cfg(struct spi_device *spi, u32 flags)
+static u32 mxic_spi_prep_hc_cfg(struct spi_device *spi, u32 flags,
+ bool swap16)
{
int nio = 1;
@@ -305,6 +306,11 @@ static u32 mxic_spi_prep_hc_cfg(struct spi_device *spi, u32 flags)
else if (spi->mode & (SPI_TX_DUAL | SPI_RX_DUAL))
nio = 2;
+ if (!swap16)
+ flags |= HC_CFG_DATA_PASS;
+ else
+ flags &= ~HC_CFG_DATA_PASS;
+
return flags | HC_CFG_NIO(nio) |
HC_CFG_TYPE(spi_get_chipselect(spi, 0), HC_CFG_TYPE_SPI_NOR) |
HC_CFG_SLV_ACT(spi_get_chipselect(spi, 0)) | HC_CFG_IDLE_SIO_LVL(1);
@@ -397,7 +403,8 @@ static ssize_t mxic_spi_mem_dirmap_read(struct spi_mem_dirmap_desc *desc,
if (WARN_ON(offs + desc->info.offset + len > U32_MAX))
return -EINVAL;
- writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0), mxic->regs + HC_CFG);
+ writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0, desc->info.op_tmpl.data.swap16),
+ mxic->regs + HC_CFG);
writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl, len),
mxic->regs + LRD_CFG);
@@ -441,7 +448,8 @@ static ssize_t mxic_spi_mem_dirmap_write(struct spi_mem_dirmap_desc *desc,
if (WARN_ON(offs + desc->info.offset + len > U32_MAX))
return -EINVAL;
- writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0), mxic->regs + HC_CFG);
+ writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0, desc->info.op_tmpl.data.swap16),
+ mxic->regs + HC_CFG);
writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl, len),
mxic->regs + LWR_CFG);
@@ -518,7 +526,7 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem,
if (ret)
return ret;
- writel(mxic_spi_prep_hc_cfg(mem->spi, HC_CFG_MAN_CS_EN),
+ writel(mxic_spi_prep_hc_cfg(mem->spi, HC_CFG_MAN_CS_EN, op->data.swap16),
mxic->regs + HC_CFG);
writel(HC_EN_BIT, mxic->regs + HC_EN);
@@ -572,6 +580,7 @@ static const struct spi_controller_mem_ops mxic_spi_mem_ops = {
static const struct spi_controller_mem_caps mxic_spi_mem_caps = {
.dtr = true,
+ .swap16 = true,
.ecc = true,
};
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v8 6/9] mtd: spi-nor: add support for Macronix Octal flash MX25 series with RWW feature
2024-02-01 9:43 [PATCH v8 0/9] Add octal DTR support for Macronix flash Jaime Liao
` (4 preceding siblings ...)
2024-02-01 9:43 ` [PATCH v8 5/9] spi: mxic: Add support for swapping byte Jaime Liao
@ 2024-02-01 9:43 ` Jaime Liao
2024-02-01 15:48 ` Michael Walle
2024-02-01 9:43 ` [PATCH v8 7/9] mtd: spi-nor: add support for Macronix Octal flash MX66 " Jaime Liao
` (3 subsequent siblings)
9 siblings, 1 reply; 20+ messages in thread
From: Jaime Liao @ 2024-02-01 9:43 UTC (permalink / raw)
To: linux-mtd, linux-spi, tudor.ambarus, pratyush, mwalle,
miquel.raynal, richard, vigneshr, broonie
Cc: leoyu, jaimeliao
From: JaimeLiao <jaimeliao@mxic.com.tw>
Adding Macronix Octal flash for Octal DTR support.
The octaflash series can be divided into the following types:
MX25 series : Serial NOR Flash.
LM/UM series : Up to 250MHz clock frequency with both DTR/STR operation.
LW/UW series : Support simultaneous Read-while-Write operation in multiple
bank architecture. Read-while-write feature which means read
data one bank while another bank is programing or erasing.
MX25LW : 3.0V Octal I/O with Read-while-Write
MX25UW : 1.8V Octal I/O with Read-while-Write
MX25LM : 3.0V Octal I/O
Link: https://www.mxic.com.tw/Lists/Datasheet/Attachments/8729/MX25LM51245G,%203V,%20512Mb,%20v1.1.pdf
MX25UM : 1.8V Octal I/O
Link: https://www.mxic.com.tw/Lists/Datasheet/Attachments/8967/MX25UM51245G,%201.8V,%20512Mb,%20v1.5.pdf
Those flash have been tested on Xilinx Zynq-picozed board using
MXIC SPI controller.
As below are debugfs data, the SFDP table and result of mtd-utils
tests dump.
---
zynq> cat jedec_id
c28437
zynq> cat manufacturer
macronix
zynq> cat partname
mx25uw6345g
zynq> xxd -p sfdp
53464450080104fd00070114400000ff8701011c900000ff0a0001080001
00ff05000105200100ff84000102340100ff0000000000000000ffffffff
ffffffffe5208affffffff0300ff00ff00ff00ffeeffffffffff00ffffff
00ff0c2010d800ff00ff8b7901008f1200c4cc04674630b030b0f4bdd55c
000000ff101000200000000000007c234800000000008888000000000000
00400fd1fff30fd1fff300050090000500b1002b0095002b0096727103b8
727103b80000000090a3188200c069960000000000000000727100987271
00b8727100990000000072710098727100f872710099727100f900000000
00000000011501d0727106d8000086500000060100000000020001030002
00000000060100000000000072060002000000eec0697272717100d8f7f6
000a00001445988043060f0021dcffff
zynq> md5sum sfdp
c6fb57b8fdd4c35b5f0dacc4a1f7d4f4 sfdp
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x13
mode cycles 0
dummy cycles 0
8D-8D-8D
opcode 0xee
mode cycles 0
dummy cycles 20
Supported page program modes by the flash
1S-1S-1S
opcode 0x12
8D-8D-8D
opcode 0x12
zynq>
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id c2 84 37 c2 84 37
size 8.00 MiB
write size 1
page size 256
address nbytes 4
flags 4B_OPCODES | HAS_4BAIT | HAS_16BIT_SR | IO_MODE_EN_VOLATILE | SOFT_RESET | RWW
opcodes
read 0xee
dummy cycles 20
erase 0x21
program 0x12
8D extension invert
protocols
read 8D-8D-8D
write 8D-8D-8D
register 8D-8D-8D
erase commands
21 (4.00 KiB) [2]
dc (64.0 KiB) [3]
c7 (8.00 MiB)
sector map
region (in hex) | erase mask | flags
------------------+------------+----------
00000000-007fffff | [ 23] |
zynq>
zynq> dd if=/dev/urandom of=./spi_test bs=1M count=2
2+0 records in
2+0 records out
2097152 bytes (2.0MB) copied, 0.099455 seconds, 20.1MB/s
zynq> mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
zynq> sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
zynq> mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> sha256sum spi_*
893a6650d6ab3622b5d8f0110541b4dbe9f6adc2ab68dd2609c376d38cd58e98 spi_read
893a6650d6ab3622b5d8f0110541b4dbe9f6adc2ab68dd2609c376d38cd58e98 spi_test
zynq> mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 8388608 (8M)
mtd.erasesize = 4096 (4K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
zynq> cat jedec_id
c28137
zynq> cat manufacturer
macronix
zynq> cat partname
mx25uw6445g
zynq> xxd -p sfdp
53464450080104fd00070114400000ff8701011c900000ff0a0001080001
00ff05000105200100ff84000102340100ff0000000000000000ffffffff
ffffffffe5208affffffff0300ff00ff00ff00ffeeffffffffff00ffffff
00ff0c2010d800ff00ff897901008d1200c4cc04674630b030b0f4bdd55c
000000ff101000200000000000007ca34800000000008888000000000000
00400fd1fff30fd1fff300050090000500b1002b0095002b0096727103b8
727103b80000000090a3188200c069960000000000000000727100987271
00b8727100990000000072710098727100f872710099727100f900000000
00000000011501d0727106d8000086500000060100000000020001030002
00000000060100000000000072060002000000eec0697272717100d8f7f6
000a00001445988043060f0021dcffff
zynq> md5sum sfdp
b09aeedb0cfd0f77adc7e08592d295a9 sfdp
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x13
mode cycles 0
dummy cycles 0
8D-8D-8D
opcode 0xee
mode cycles 0
dummy cycles 20
Supported page program modes by the flash
1S-1S-1S
opcode 0x12
8D-8D-8D
opcode 0x12
zynq>
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id c2 81 37 c2 81 37
size 8.00 MiB
write size 1
page size 256
address nbytes 4
flags 4B_OPCODES | HAS_4BAIT | HAS_16BIT_SR | IO_MODE_EN_VOLATILE | SOFT_RESET | RWW | 1<<17
opcodes
read 0xee
dummy cycles 20
erase 0x21
program 0x12
8D extension invert
protocols
read 8D-8D-8D
write 8D-8D-8D
register 8D-8D-8D
erase commands
21 (4.00 KiB) [2]
dc (64.0 KiB) [3]
c7 (8.00 MiB)
sector map
region (in hex) | erase mask | flags
------------------+------------+----------
00000000-007fffff | [ 23] |
zynq>
zynq> dd if=/dev/urandom of=./spi_test bs=1M count=2
2+0 records in
2+0 records out
2097152 bytes (2.0MB) copied, 0.099360 seconds, 20.1MB/s
zynq> mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
zynq> sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
zynq> mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> sha256sum spi_*
1f9fc3b1c9ab9c20b38d8cd5e9331c0806017561f844761237909fb41ae94f4c spi_read
1f9fc3b1c9ab9c20b38d8cd5e9331c0806017561f844761237909fb41ae94f4c spi_test
zynq> mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 8388608 (8M)
mtd.erasesize = 4096 (4K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
zynq> cat jedec_id
c28438
zynq> cat manufacturer
macronix
zynq> cat partname
mx25uw12345g
zynq> xxd -p sfdp
53464450080104fd00070114400000ff8701011c900000ff0a0001080001
00ff05000105200100ff84000102340100ff0000000000000000ffffffff
ffffffffe5208affffffff0700ff00ff00ff00ffeeffffffffff00ffffff
00ff0c2010d800ff00ff8b7901008f1200c9cc04674630b030b0f4bdd55c
000000ff101000200000000000007c234800000000008888000000000000
00400fd1fff30fd1fff300050090000500b1002b0095002b0096727103b8
727103b80000000090a3188200c069960000000000000000727100987271
00b8727100990000000072710098727100f872710099727100f900000000
00000000011501d0727106d8000086500000060100000000020001030002
00000000060100000000000072060002000000eec0697272717100d8f7f6
000a00001445988043060f0021dcffff
zynq> md5sum sfdp
a3eb609c08894c84270ad06efc03766c sfdp
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x13
mode cycles 0
dummy cycles 0
8D-8D-8D
opcode 0xee
mode cycles 0
dummy cycles 20
Supported page program modes by the flash
1S-1S-1S
opcode 0x12
8D-8D-8D
opcode 0x12
zynq>
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id c2 84 38 c2 84 38
size 16.0 MiB
write size 1
page size 256
address nbytes 4
flags 4B_OPCODES | HAS_4BAIT | HAS_16BIT_SR | IO_MODE_EN_VOLATILE | SOFT_RESET | RWW
opcodes
read 0xee
dummy cycles 20
erase 0x21
program 0x12
8D extension invert
protocols
read 8D-8D-8D
write 8D-8D-8D
register 8D-8D-8D
erase commands
21 (4.00 KiB) [2]
dc (64.0 KiB) [3]
c7 (16.0 MiB)
sector map
region (in hex) | erase mask | flags
------------------+------------+----------
00000000-00ffffff | [ 23] |
zynq>
zynq> dd if=/dev/urandom of=./spi_test bs=1M count=2
2+0 records in
2+0 records out
2097152 bytes (2.0MB) copied, 0.100084 seconds, 20.0MB/s
zynq> mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
zynq> sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
zynq> mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> sha256sum spi_*
c930efc31337aa6f45d2f5a64a68bc7f74db4866144e4ad4b87a6bbae0538916 spi_read
c930efc31337aa6f45d2f5a64a68bc7f74db4866144e4ad4b87a6bbae0538916 spi_test
zynq> mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 16777216 (16M)
mtd.erasesize = 4096 (4K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
zynq> cat jedec_id
c28138
zynq> cat manufacturer
macronix
zynq> cat partname
mx25uw12845g
zynq> xxd -p sfdp
53464450080104fd00070114400000ff8701011c900000ff0a0001080001
00ff05000105200100ff84000102340100ff000000000000000000000000
00000000e5208affffffff0700ff00ff00ff00ffeeffffffffff00ffffff
00ff0c2010d800ff00ff8b7901008f1200c9cc04674630b030b0f4bdd55c
000000ff101000200000000000007ca34800000000008888000000000000
00400fd1fff30fd1fff300050090000500b1002b0095002b0096727103b8
727103b80000000090a3188200c069960000000000000000727100987271
00b8727100990000000072710098727100f872710099727100f900000000
00000000011501d0727106d8000086500000060100000000020001030002
00000000060100000000000072060002000000eec0697272717100d8f7f6
000a00001445988043060f0021dcffff
zynq> md5sum sfdp
9eacff90d7aa7cf737b970e0f2a7f2c6 sfdp
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x13
mode cycles 0
dummy cycles 0
8D-8D-8D
opcode 0xee
mode cycles 0
dummy cycles 20
Supported page program modes by the flash
1S-1S-1S
opcode 0x12
8D-8D-8D
opcode 0x12
zynq>
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id c2 81 38 c2 81 38
size 16.0 MiB
write size 1
page size 256
address nbytes 4
flags 4B_OPCODES | HAS_4BAIT | HAS_16BIT_SR | IO_MODE_EN_VOLATILE | SOFT_RESET | RWW | 1<<17
opcodes
read 0xee
dummy cycles 20
erase 0x21
program 0x12
8D extension invert
protocols
read 8D-8D-8D
write 8D-8D-8D
register 8D-8D-8D
erase commands
21 (4.00 KiB) [2]
dc (64.0 KiB) [3]
c7 (16.0 MiB)
sector map
region (in hex) | erase mask | flags
------------------+------------+----------
00000000-00ffffff | [ 23] |
zynq>
zynq> dd if=/dev/urandom of=./spi_test bs=1M count=2
2+0 records in
2+0 records out
2097152 bytes (2.0MB) copied, 0.100118 seconds, 20.0MB/s
zynq> mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
zynq> sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
zynq> mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> sha256sum spi_*
0b843b2638d248f4e520ed96fa15f480800a2e210ef69762ed3a176f2d16268c spi_read
0b843b2638d248f4e520ed96fa15f480800a2e210ef69762ed3a176f2d16268c spi_test
zynq> mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 16777216 (16M)
mtd.erasesize = 4096 (4K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
zynq> cat jedec_id
c28439
zynq> cat manufacturer
macronix
zynq> cat partname
mx25uw25345g
zynq> xxd -p sfdp
53464450080104fd00070114400000ff8701011c900000ff0a0001080001
00ff05000105200100ff84000102340100ff0000000000000000ffffffff
ffffffffe5208affffffff0f00ff00ff00ff00ffeeffffffffff00ffffff
00ff0c2010d800ff00ff897901008d1200d2cc04674630b030b0f4bdd55c
000000ff101000200000147c00007c234800000000008888000000000000
00400fd1fff30fd1fff300050090060500b1002b0095002b0096727103b8
727103b80000000090a3188200c069960000000000000000000000000000
0000000000000000000072710098727100f872710099727100f900000000
00000000011501d0727106d8000086500000060100000000020001030002
00000000060100000000000072060002000000eec0697272717100d8f7f6
000a00001445988043061f0021dcffff
zynq> md5sum sfdp
765e310356fb92fdd77b2af1c725fbcb sfdp
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x13
mode cycles 0
dummy cycles 0
1S-1S-8S
opcode 0x7c
mode cycles 0
dummy cycles 20
8D-8D-8D
opcode 0xee
mode cycles 0
dummy cycles 20
Supported page program modes by the flash
1S-1S-1S
opcode 0x12
8D-8D-8D
opcode 0x12
zynq>
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id c2 84 39 c2 84 39
size 32.0 MiB
write size 1
page size 256
address nbytes 4
flags 4B_OPCODES | HAS_4BAIT | HAS_16BIT_SR | IO_MODE_EN_VOLATILE | SOFT_RESET | RWW
opcodes
read 0xee
dummy cycles 20
erase 0x21
program 0x12
8D extension invert
protocols
read 8D-8D-8D
write 8D-8D-8D
register 8D-8D-8D
erase commands
21 (4.00 KiB) [2]
dc (64.0 KiB) [3]
c7 (32.0 MiB)
sector map
region (in hex) | erase mask | flags
------------------+------------+----------
00000000-01ffffff | [ 23] |
zynq>
zynq> dd if=/dev/urandom of=./spi_test bs=1M count=2
2+0 records in
2+0 records out
2097152 bytes (2.0MB) copied, 0.099890 seconds, 20.0MB/s
zynq> mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
zynq> sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
zynq> mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> sha256sum spi_*
d0996b13ba4b92f55270c47f3abcf91a44f00856e5c3307c50a40a21bca9f2b0 spi_read
d0996b13ba4b92f55270c47f3abcf91a44f00856e5c3307c50a40a21bca9f2b0 spi_test
zynq> mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 33554432 (32M)
mtd.erasesize = 4096 (4K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
zynq> cat jedec_id
c28139
zynq> cat manufacturer
macronix
zynq> cat partname
mx25uw25645g
zynq> xxd -p sfdp
53464450080104fd00070114400000ff8701011c900000ff0a0001080001
00ff05000105200100ff84000102340100ff0000000000000000ffffffff
ffffffffe5208affffffff0f00ff00ff00ff00ffeeffffffffff00ffffff
00ff0c2010d800ff00ff897901008d1200d2cc04674630b030b0f4bdd55c
000000ff101000200000000000007ca34800000000008888000000000000
00400fd1fff30fd1fff300050090000500b1002b0095002b0096727103b8
727103b80000000090a3188200c069960000000000000000727100987271
00b8727100990000000072710098727100f872710099727100f900000000
00000000011501d0727106d8000086500000060100000000020001030002
00000000060100000000000072060002000000eec0697272717100d8f7f6
000a00001445988043060f0021dcffff
zynq> md5sum sfdp
e43ab2dbcbcf99cebc74964c5dcf3ee2 sfdp
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x13
mode cycles 0
dummy cycles 0
8D-8D-8D
opcode 0xee
mode cycles 0
dummy cycles 20
Supported page program modes by the flash
1S-1S-1S
opcode 0x12
8D-8D-8D
opcode 0x12
zynq>
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id c2 81 39 c2 81 39
size 32.0 MiB
write size 1
page size 256
address nbytes 4
flags 4B_OPCODES | HAS_4BAIT | HAS_16BIT_SR | IO_MODE_EN_VOLATILE | SOFT_RESET | RWW | 1<<17
opcodes
read 0xee
dummy cycles 20
erase 0x21
program 0x12
8D extension invert
protocols
read 8D-8D-8D
write 8D-8D-8D
register 8D-8D-8D
erase commands
21 (4.00 KiB) [2]
dc (64.0 KiB) [3]
c7 (32.0 MiB)
sector map
region (in hex) | erase mask | flags
------------------+------------+----------
00000000-01ffffff | [ 23] |
zynq>
zynq> dd if=/dev/urandom of=./spi_test bs=1M count=2
2+0 records in
2+0 records out
2097152 bytes (2.0MB) copied, 0.099750 seconds, 20.0MB/s
zynq> mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
zynq> sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
zynq> mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> sha256sum spi_*
92f0ac2c79c4ff3b7a71942ce1a9a4937107b48bffd94135962340213b9caea1 spi_read
92f0ac2c79c4ff3b7a71942ce1a9a4937107b48bffd94135962340213b9caea1 spi_test
zynq> mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 33554432 (32M)
mtd.erasesize = 4096 (4K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
zynq> cat jedec_id
c28639
zynq> cat manufacturer
macronix
zynq> cat partname
mx25lw25645g
zynq> xxd -p sfdp
53464450080104fd00070114400000ff8701011c900000ff0a0001080001
00ff05000105200100ff84000102340100ff0000000000000000ffffffff
ffffffffe5208affffffff0f00ff00ff00ff00ffeeffffffffff00ffffff
00ff0c2010d800ff00ff897901008d1200d2cc04674630b030b0f4bdd55c
000000ff101000200000000000007ca34800000000006666000000000000
00400fd1fff30fd1fff300050090000500b1002b0095002b0096727103b8
727103b80000000090a3188200c069960000000000000000727100987271
00b8727100990000000072710098727100f872710099727100f900000000
00000000011501d0727106d8000086500000060100000000020001030002
00000000060100000000000072060002000000eec0697272717100d8f7f6
0000000014351c0043060f0021dcffff
zynq> md5sum sfdp
b5db9fe24f814b5cc6a392c4c56ed331 sfdp
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x13
mode cycles 0
dummy cycles 0
8D-8D-8D
opcode 0xee
mode cycles 0
dummy cycles 14
Supported page program modes by the flash
1S-1S-1S
opcode 0x12
8D-8D-8D
opcode 0x12
zynq>
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id c2 86 39 c2 86 39
size 32.0 MiB
write size 1
page size 256
address nbytes 4
flags 4B_OPCODES | HAS_4BAIT | HAS_16BIT_SR | IO_MODE_EN_VOLATILE | SOFT_RESET | RWW | 1<<17
opcodes
read 0xee
dummy cycles 14
erase 0x21
program 0x12
8D extension invert
protocols
read 8D-8D-8D
write 8D-8D-8D
register 8D-8D-8D
erase commands
21 (4.00 KiB) [2]
dc (64.0 KiB) [3]
c7 (32.0 MiB)
sector map
region (in hex) | erase mask | flags
------------------+------------+----------
00000000-01ffffff | [ 23] |
zynq>
zynq> dd if=/dev/urandom of=./spi_test bs=1M count=2
2+0 records in
2+0 records out
2097152 bytes (2.0MB) copied, 0.100542 seconds, 19.9MB/s
zynq> mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
zynq> sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
zynq> mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> sha256sum spi_*
d8ba27cdac64fc61c761ad0718058435768bb7d1f5afbade8e4ad039b361691d spi_read
d8ba27cdac64fc61c761ad0718058435768bb7d1f5afbade8e4ad039b361691d spi_test
zynq> mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 33554432 (32M)
mtd.erasesize = 4096 (4K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
zynq> cat jedec_id
c2843a
zynq> cat manufacturer
macronix
zynq> cat partname
mx25uw51345g
zynq> xxd -p sfdp
53464450080104fd00070114400000ff8701011c900000ff0a0001080001
00ff05000105200100ff84000102340100ff0000000000000000ffffffff
ffffffffe5208affffffff1f00ff00ff00ff00ffeeffffffffff00ffffff
00ff0c2010d800ff00ff8b7901008f1200e2cc04674630b030b0f4bdd55c
000000ff101000200000147c00007c234800000000008888000000000000
00400fd1fff30fd1fff300050090060500b1002b0095002b0096727103b8
727103b80000000090a3188200c069960000000000000000000000000000
0000000000000000000072710098727100f872710099727100f900000000
00000000011501d0727106d8000086500000060100000000020001030002
00000000060100000000000072060002000000eec0697272717100d8f7f6
000a00001445988043061f0021dcffff
zynq> md5sum sfdp
b3c82acb473b65117fe0c063be9d8546 sfdp
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x13
mode cycles 0
dummy cycles 0
1S-1S-8S
opcode 0x7c
mode cycles 0
dummy cycles 20
8D-8D-8D
opcode 0xee
mode cycles 0
dummy cycles 20
Supported page program modes by the flash
1S-1S-1S
opcode 0x12
8D-8D-8D
opcode 0x12
zynq>
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id c2 84 3a c2 84 3a
size 64.0 MiB
write size 1
page size 256
address nbytes 4
flags 4B_OPCODES | HAS_4BAIT | HAS_16BIT_SR | IO_MODE_EN_VOLATILE | SOFT_RESET | RWW
opcodes
read 0xee
dummy cycles 20
erase 0x21
program 0x12
8D extension invert
protocols
read 8D-8D-8D
write 8D-8D-8D
register 8D-8D-8D
erase commands
21 (4.00 KiB) [2]
dc (64.0 KiB) [3]
c7 (64.0 MiB)
sector map
region (in hex) | erase mask | flags
------------------+------------+----------
00000000-03ffffff | [ 23] |
zynq>
zynq> dd if=/dev/urandom of=./spi_test bs=1M count=2
2+0 records in
2+0 records out
2097152 bytes (2.0MB) copied, 0.100939 seconds, 19.8MB/s
zynq> mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
zynq> sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
zynq> mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> sha256sum spi_*
e86eff36985f6517c78981422a39d047c80de424d98c09d274fcff8890744727 spi_read
e86eff36985f6517c78981422a39d047c80de424d98c09d274fcff8890744727 spi_test
zynq> mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 67108864 (64M)
mtd.erasesize = 4096 (4K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
zynq> cat jedec_id
c2863a
zynq> cat manufacturer
macronix
zynq> cat partname
mx25lw51245g
zynq> xxd -p sfdp
53464450080104fd00070114400000ff8701011c900000ff0a0001080001
00ff05000105200100ff84000102340100ff000000000000000000000000
00000000e5208affffffff1f00ff00ff00ff00ffeeffffffffff00ffffff
00ff0c2010d800ff00ff8b7901008f1200e2cc04674630b030b0f4bdd55c
000000ff101000200000000000007ca34800000000006666000000000000
00400fd1fff30fd1fff300050090000500b1002b0095002b0096727103b8
727103b80000000090a3188200c069960000000000000000727100987271
00b8727100990000000072710098727100f872710099727100f900000000
00000000011501d0727106d8000086500000060100000000020001030002
00000000060100000000000072060002000000eec0697272717100d8f7f6
0000000014351c0043060f0021dcffff
zynq> md5sum sfdp
bb32ccaca6814f3104b985ac91bd65ac sfdp
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x13
mode cycles 0
dummy cycles 0
8D-8D-8D
opcode 0xee
mode cycles 0
dummy cycles 14
Supported page program modes by the flash
1S-1S-1S
opcode 0x12
8D-8D-8D
opcode 0x12
zynq>
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id c2 86 3a c2 86 3a
size 64.0 MiB
write size 1
page size 256
address nbytes 4
flags 4B_OPCODES | HAS_4BAIT | HAS_16BIT_SR | IO_MODE_EN_VOLATILE | SOFT_RESET | RWW | 1<<17
opcodes
read 0xee
dummy cycles 14
erase 0x21
program 0x12
8D extension invert
protocols
read 8D-8D-8D
write 8D-8D-8D
register 8D-8D-8D
erase commands
21 (4.00 KiB) [2]
dc (64.0 KiB) [3]
c7 (64.0 MiB)
sector map
region (in hex) | erase mask | flags
------------------+------------+----------
00000000-03ffffff | [ 23] |
zynq>
zynq> dd if=/dev/urandom of=./spi_test bs=1M count=2
2+0 records in
2+0 records out
2097152 bytes (2.0MB) copied, 0.100369 seconds, 19.9MB/s
zynq> mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
zynq> sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
zynq> mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> sha256sum spi_*
3b2a81e0e8f3a6f8e09d905a5c0d77598e9b41bdba0c4974eb3a35bc7f87f2a7 spi_read
3b2a81e0e8f3a6f8e09d905a5c0d77598e9b41bdba0c4974eb3a35bc7f87f2a7 spi_test
zynq> mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 67108864 (64M)
mtd.erasesize = 4096 (4K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw>
---
drivers/mtd/spi-nor/macronix.c | 40 ++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
index dee71776b1a8..467bb5c97d6c 100644
--- a/drivers/mtd/spi-nor/macronix.c
+++ b/drivers/mtd/spi-nor/macronix.c
@@ -200,6 +200,46 @@ static const struct flash_info macronix_nor_parts[] = {
.name = "mx25l3255e",
.size = SZ_4M,
.no_sfdp_flags = SECT_4K,
+ }, {
+ .id = SNOR_ID(0xc2, 0x84, 0x37),
+ .n_banks = 4,
+ .flags = SPI_NOR_RWW,
+ }, {
+ .id = SNOR_ID(0xc2, 0x81, 0x37),
+ .n_banks = 4,
+ .flags = SPI_NOR_RWW,
+ }, {
+ .id = SNOR_ID(0xc2, 0x84, 0x38),
+ .n_banks = 4,
+ .flags = SPI_NOR_RWW,
+ }, {
+ .id = SNOR_ID(0xc2, 0x81, 0x38),
+ .n_banks = 4,
+ .flags = SPI_NOR_RWW,
+ }, {
+ .id = SNOR_ID(0xc2, 0x84, 0x39),
+ .n_banks = 4,
+ .flags = SPI_NOR_RWW,
+ }, {
+ .id = SNOR_ID(0xc2, 0x81, 0x39),
+ .n_banks = 4,
+ .flags = SPI_NOR_RWW,
+ }, {
+ .id = SNOR_ID(0xc2, 0x86, 0x39),
+ .n_banks = 4,
+ .flags = SPI_NOR_RWW,
+ }, {
+ .id = SNOR_ID(0xc2, 0x84, 0x3a),
+ .n_banks = 4,
+ .flags = SPI_NOR_RWW,
+ }, {
+ .id = SNOR_ID(0xc2, 0x86, 0x3a),
+ .n_banks = 4,
+ .flags = SPI_NOR_RWW,
+ }, {
+ .id = SNOR_ID(0xc2, 0x84, 0x3b),
+ .n_banks = 4,
+ .flags = SPI_NOR_RWW,
}
};
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v8 7/9] mtd: spi-nor: add support for Macronix Octal flash MX66 series with RWW feature
2024-02-01 9:43 [PATCH v8 0/9] Add octal DTR support for Macronix flash Jaime Liao
` (5 preceding siblings ...)
2024-02-01 9:43 ` [PATCH v8 6/9] mtd: spi-nor: add support for Macronix Octal flash MX25 series with RWW feature Jaime Liao
@ 2024-02-01 9:43 ` Jaime Liao
2024-02-01 9:43 ` [PATCH v8 8/9] mtd: spi-nor: add support for Macronix Octal flash MX25 series Jaime Liao
` (2 subsequent siblings)
9 siblings, 0 replies; 20+ messages in thread
From: Jaime Liao @ 2024-02-01 9:43 UTC (permalink / raw)
To: linux-mtd, linux-spi, tudor.ambarus, pratyush, mwalle,
miquel.raynal, richard, vigneshr, broonie
Cc: leoyu, jaimeliao
From: JaimeLiao <jaimeliao@mxic.com.tw>
Adding Macronix Octal flash for Octal DTR support.
The octaflash series can be divided into the following types:
MX66 series : Serial NOR Flash with stacked die.(Size larger than 1Gb)
LM/UM series : Up to 250MHz clock frequency with both DTR/STR operation.
LW/UW series : Support simultaneous Read-while-Write operation in multiple
bank architecture. Read-while-write feature which means read
data one bank while another bank is programing or erasing.
MX66LW : 3.0V Octal I/O with Read-while-Write and stack die
MX66UW : 1.8V Octal I/O with Read-while-Write and stack die
MX66LM : 3.0V Octal I/O with stacked die
Link: https://www.mxic.com.tw/Lists/Datasheet/Attachments/8748/MX66LM1G45G,%203V,%201Gb,%20v1.1.pdf
MX66UM : 1.8V Octal I/O with stacked die
Link: https://www.mxic.com.tw/Lists/Datasheet/Attachments/8711/MX66UM1G45G,%201.8V,%201Gb,%20v1.1.pdf
Those flash have been tested on Xilinx Zynq-picozed board using
MXIC SPI controller.
As below are debugfs data, the SFDP table and result of mtd-utils
tests dump.
---
zynq> cat jedec_id
c2843b
zynq> cat manufacturer
macronix
zynq> cat partname
mx66uw1g345g
zynq> xxd -p sfdp
53464450080104fd00070114400000ff8701011c900000ff0a0001080001
00ff05000105200100ff84000102340100ff0000000000000000ffffffff
ffffffffe5208affffffff3f00ff00ff00ff00ffeeffffffffff00ffffff
00ff0c2010d800ff00ff8b7901008f1200e2cc04674630b030b0f4bdd55c
000000ff101000200000147c00007c234800000000008888000000000000
00400fd1fff30fd1fff300050090060500b1002b0095002b0096727103b8
727103b80000000090a3188200c069960000000000000000000000000000
0000000000000000000072710098727100f872710099727100f900000000
00000000011501d0727106d8000086500000060100000000020001030002
00000000060100000000000072060002000000eec0697272717100d8f7f6
000a00001445988043061f0021dcffff
zynq> md5sum sfdp
dd3ef0a8d22ee81fc5bccdcb67dee6ca sfdp
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x13
mode cycles 0
dummy cycles 0
1S-1S-8S
opcode 0x7c
mode cycles 0
dummy cycles 20
8D-8D-8D
opcode 0xee
mode cycles 0
dummy cycles 20
Supported page program modes by the flash
1S-1S-1S
opcode 0x12
8D-8D-8D
opcode 0x12
zynq>
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id c2 84 3b c2 84 3b
size 128 MiB
write size 1
page size 256
address nbytes 4
flags 4B_OPCODES | HAS_4BAIT | HAS_16BIT_SR | IO_MODE_EN_VOLATILE | SOFT_RESET | RWW
opcodes
read 0xee
dummy cycles 20
erase 0x21
program 0x12
8D extension invert
protocols
read 8D-8D-8D
write 8D-8D-8D
register 8D-8D-8D
erase commands
21 (4.00 KiB) [2]
dc (64.0 KiB) [3]
c7 (128 MiB)
sector map
region (in hex) | erase mask | flags
------------------+------------+----------
00000000-07ffffff | [ 23] |
zynq>
zynq> dd if=/dev/urandom of=./spi_test bs=1M count=2
2+0 records in
2+0 records out
2097152 bytes (2.0MB) copied, 0.100350 seconds, 19.9MB/s
zynq> mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
zynq> sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
zynq> mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> sha256sum spi_*
22b2febd5a62c552b82c4089f511b269bcd2da3ab23aaed44e0a9d1e71349251 spi_read
22b2febd5a62c552b82c4089f511b269bcd2da3ab23aaed44e0a9d1e71349251 spi_test
zynq> mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 134217728 (128M)
mtd.erasesize = 4096 (4K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
zynq> cat jedec_id
c2813b
zynq> cat manufacturer
macronix
zynq> cat partname
mx66uw1g45g
zynq> xxd -p sfdp
53464450080104fd00070114400000ff8701011c900000ff0a0001080001
00ff05000105200100ff84000102340100ff0000000000000000ffffffff
ffffffffe5208affffffff3f00ff00ff00ff00ffeeffffffffff00ffffff
00ff0c2010d800ff00ff8b7901008f1200e2cc04674630b030b0f4bdd55c
000000ff101000200000000000007ca34800000000008888000000000000
00400fd1fff30fd1fff300050090000500b1002b0095002b0096727103b8
727103b80000000090a3188200c069960000000000000000727100987271
00b8727100990000000072710098727100f872710099727100f900000000
00000000011501d0727106d8000086500000060100000000020001030002
00000000060100000000000072060002000000eec0697272717100d8f7f6
000a00001445988043060f0021dcffff
zynq> md5sum sfdp
b89a53266007fce06ba7cc4c0956f917 sfdp
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x13
mode cycles 0
dummy cycles 0
8D-8D-8D
opcode 0xee
mode cycles 0
dummy cycles 20
Supported page program modes by the flash
1S-1S-1S
opcode 0x12
8D-8D-8D
opcode 0x12
zynq>
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id c2 81 3b c2 81 3b
size 128 MiB
write size 1
page size 256
address nbytes 4
flags 4B_OPCODES | HAS_4BAIT | HAS_16BIT_SR | IO_MODE_EN_VOLATILE | SOFT_RESET | RWW | 1<<17
opcodes
read 0xee
dummy cycles 20
erase 0x21
program 0x12
8D extension invert
protocols
read 8D-8D-8D
write 8D-8D-8D
register 8D-8D-8D
erase commands
21 (4.00 KiB) [2]
dc (64.0 KiB) [3]
c7 (128 MiB)
sector map
region (in hex) | erase mask | flags
------------------+------------+----------
00000000-07ffffff | [ 23] |
zynq>
zynq> dd if=/dev/urandom of=./spi_test bs=1M count=2
2+0 records in
2+0 records out
2097152 bytes (2.0MB) copied, 0.100452 seconds, 19.9MB/s
zynq> mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
zynq> sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
zynq> mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> sha256sum spi_*
85c3736186d77b75a9442c958e6b2610f8e5e0b59f5534fb91db4dbf9130f04e spi_read
85c3736186d77b75a9442c958e6b2610f8e5e0b59f5534fb91db4dbf9130f04e spi_test
zynq> mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 134217728 (128M)
mtd.erasesize = 4096 (4K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
zynq> cat jedec_id
c2843c
zynq> cat manufacturer
macronix
zynq> cat partname
mx66uw2g345g
zynq> xxd -p sfdp
53464450080104fd00070114400000ff8701011c900000ff0a0001080001
00ff05000105200100ff84000102340100ff0000000000000000ffffffff
ffffffffe5208affffffff7f00ff00ff00ff00ffeeffffffffff00ffffff
00ff0c2010d800ff00ff87790100841200e2cc04674630b030b0f4bdd55c
000000ff101000200000147c00007c234800000000007777000000000000
00400fd1fff30fd1fff300050090000500b1002b0095002b0096727103b8
727103b80000000090a3188200c069960000000000000000727100987271
00b8727100990000000072710098727100f872710099727100f900000000
00000000011501d0727106d8000086500000060100000000020001030002
00000000060100000000000072060002000000eec0697272717100d8f7f6
000000001445988043061f0021dcffff
zynq> md5sum sfdp
00447475e039e67c256a8d75d5885ae8 sfdp
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x13
mode cycles 0
dummy cycles 0
1S-1S-8S
opcode 0x7c
mode cycles 0
dummy cycles 20
8D-8D-8D
opcode 0xee
mode cycles 0
dummy cycles 16
Supported page program modes by the flash
1S-1S-1S
opcode 0x12
8D-8D-8D
opcode 0x12
zynq>
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id c2 84 3c c2 84 3c
size 256 MiB
write size 1
page size 256
address nbytes 4
flags 4B_OPCODES | HAS_4BAIT | HAS_16BIT_SR | IO_MODE_EN_VOLATILE | SOFT_RESET | RWW
opcodes
read 0xee
dummy cycles 16
erase 0x21
program 0x12
8D extension invert
protocols
read 8D-8D-8D
write 8D-8D-8D
register 8D-8D-8D
erase commands
21 (4.00 KiB) [2]
dc (64.0 KiB) [3]
c7 (256 MiB)
sector map
region (in hex) | erase mask | flags
------------------+------------+----------
00000000-0fffffff | [ 23] |
zynq>
zynq> dd if=/dev/urandom of=./spi_test bs=1M count=2
2+0 records in
2+0 records out
2097152 bytes (2.0MB) copied, 0.099340 seconds, 20.1MB/s
zynq> mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
zynq> sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
zynq> mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> sha256sum spi_*
5d9db592d7964b71151f8b130f27143cef4debd66801571b50f56fcb81f77222 spi_read
5d9db592d7964b71151f8b130f27143cef4debd66801571b50f56fcb81f77222 spi_test
zynq> mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 268435456 (256M)
mtd.erasesize = 4096 (4K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
zynq> cat jedec_id
c2943c
zynq> cat manufacturer
macronix
zynq> cat partname
mx66uw2g345gx0
zynq> xxd -p sfdp
53464450080104fd00070114400000ff8701011c900000ff0a0001080001
00ff05000105200100ff84000102340100ff0000000000000000ffffffff
ffffffffe5208affffffff7f00ff00ff00ff00ffeeffffffffff00ffffff
00ff0c2010d800ff00ff87790100841200e2cc04674630b030b0f4bdd55c
000000ff101000200000087c00007c234800000000008888000000000000
00400fd1fff30fd1fff300050090060500b1002b0095002b0096727103b8
727103b80000000090a3188200c069960000000000000000000000000000
0000000000000000000072710098727100f872710099727100f900000000
00000000011501d0727106d8000086500000060100000000020001030002
00000000060100000000000072060002000000eec0697272717100d8f7f6
000a00001445988043061f0021dcffff
zynq> md5sum sfdp
e6226263b999578a2f034ea969988d7f sfdp
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x13
mode cycles 0
dummy cycles 0
1S-1S-8S
opcode 0x7c
mode cycles 0
dummy cycles 8
8D-8D-8D
opcode 0xee
mode cycles 0
dummy cycles 20
Supported page program modes by the flash
1S-1S-1S
opcode 0x12
8D-8D-8D
opcode 0x12
zynq>
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id c2 94 3c c2 94 3c
size 256 MiB
write size 1
page size 256
address nbytes 4
flags 4B_OPCODES | HAS_4BAIT | HAS_16BIT_SR | IO_MODE_EN_VOLATILE | SOFT_RESET | RWW
opcodes
read 0xee
dummy cycles 20
erase 0x21
program 0x12
8D extension invert
protocols
read 8D-8D-8D
write 8D-8D-8D
register 8D-8D-8D
erase commands
21 (4.00 KiB) [2]
dc (64.0 KiB) [3]
c7 (256 MiB)
sector map
region (in hex) | erase mask | flags
------------------+------------+----------
00000000-0fffffff | [ 23] |
zynq>
zynq> dd if=/dev/urandom of=./spi_test bs=1M count=2
2+0 records in
2+0 records out
2097152 bytes (2.0MB) copied, 0.098722 seconds, 20.3MB/s
zynq> mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
zynq> sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
zynq> mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> sha256sum spi_*
51134f432316a683a3375850143a40ca924b7eec21b5ec706039864ac7a8f744 spi_read
51134f432316a683a3375850143a40ca924b7eec21b5ec706039864ac7a8f744 spi_test
zynq> mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 268435456 (256M)
mtd.erasesize = 4096 (4K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw>
---
drivers/mtd/spi-nor/macronix.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
index 467bb5c97d6c..29bd5f0b32ec 100644
--- a/drivers/mtd/spi-nor/macronix.c
+++ b/drivers/mtd/spi-nor/macronix.c
@@ -240,6 +240,18 @@ static const struct flash_info macronix_nor_parts[] = {
.id = SNOR_ID(0xc2, 0x84, 0x3b),
.n_banks = 4,
.flags = SPI_NOR_RWW,
+ }, {
+ .id = SNOR_ID(0xc2, 0x81, 0x3b),
+ .n_banks = 4,
+ .flags = SPI_NOR_RWW,
+ }, {
+ .id = SNOR_ID(0xc2, 0x84, 0x3c),
+ .n_banks = 4,
+ .flags = SPI_NOR_RWW,
+ }, {
+ .id = SNOR_ID(0xc2, 0x94, 0x3c),
+ .n_banks = 4,
+ .flags = SPI_NOR_RWW,
}
};
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v8 8/9] mtd: spi-nor: add support for Macronix Octal flash MX25 series
2024-02-01 9:43 [PATCH v8 0/9] Add octal DTR support for Macronix flash Jaime Liao
` (6 preceding siblings ...)
2024-02-01 9:43 ` [PATCH v8 7/9] mtd: spi-nor: add support for Macronix Octal flash MX66 " Jaime Liao
@ 2024-02-01 9:43 ` Jaime Liao
2024-02-01 9:43 ` [PATCH v8 9/9] mtd: spi-nor: add support for Macronix Octal flash MX66 series Jaime Liao
2024-02-22 9:32 ` [PATCH v8 0/9] Add octal DTR support for Macronix flash Tudor Ambarus
9 siblings, 0 replies; 20+ messages in thread
From: Jaime Liao @ 2024-02-01 9:43 UTC (permalink / raw)
To: linux-mtd, linux-spi, tudor.ambarus, pratyush, mwalle,
miquel.raynal, richard, vigneshr, broonie
Cc: leoyu, jaimeliao
From: JaimeLiao <jaimeliao@mxic.com.tw>
Adding Macronix Octal flash for Octal DTR support.
The octaflash series can be divided into the following types:
MX25 series : Serial NOR Flash.
MX66 series : Serial NOR Flash with stacked die.(Size larger than 1Gb)
LM/UM series : Up to 250MHz clock frequency with both DTR/STR operation.
LW/UW series : Support simultaneous Read-while-Write operation in multiple
bank architecture. Read-while-write feature which means read
data one bank while another bank is programing or erasing.
MX25LW : 3.0V Octal I/O with Read-while-Write
MX25UW : 1.8V Octal I/O with Read-while-Write
MX25LM : 3.0V Octal I/O
Link: https://www.mxic.com.tw/Lists/Datasheet/Attachments/8729/MX25LM51245G,%203V,%20512Mb,%20v1.1.pdf
MX25UM : 1.8V Octal I/O
Link: https://www.mxic.com.tw/Lists/Datasheet/Attachments/8967/MX25UM51245G,%201.8V,%20512Mb,%20v1.5.pdf
Those flash have been tested on Xilinx Zynq-picozed board using
MXIC SPI controller.
As below are debugfs data, the SFDP table and result of mtd-utils
tests dump.
---
zynq> cat jedec_id
c28339
zynq> cat manufacturer
macronix
zynq> cat partname
mx25um25345g
zynq> xxd -p sfdp
53464450080104fd00070114400000ff8701011c900000ff0a0001080001
00ff05000105200100ff84000102340100ff0000000000000000ffffffff
ffffffffe5208affffffff0f00ff00ff00ff00ffeeffffffffff00ffffff
00ff0c2010d800ff00ff87690100821200d2cc02673830b030b0f4bdd55c
000000ff101000200000000000007c234800000000008888000000000000
00400fd1fff30fd1fff300050090000500b1002b0095002b0096727103b8
727103b80000000090a3188200c069960000000000000000727100987271
00b8727100990000000072710098727100f872710099727100f900000000
00000000011501d0727106d8000086500000060100000000020001030002
00000000060100000000000072060002000000eec0697272717100d8f7f6
040900001445988043060f0021dcffff
zynq> md5sum sfdp
950e623745a002e1747008592e6dbdf9 sfdp
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x13
mode cycles 0
dummy cycles 0
8D-8D-8D
opcode 0xee
mode cycles 0
dummy cycles 18
Supported page program modes by the flash
1S-1S-1S
opcode 0x12
8D-8D-8D
opcode 0x12
zynq>
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id c2 83 39 c2 83 39
size 32.0 MiB
write size 1
page size 256
address nbytes 4
flags 4B_OPCODES | HAS_4BAIT | HAS_16BIT_SR | IO_MODE_EN_VOLATILE | SOFT_RESET
opcodes
read 0xee
dummy cycles 18
erase 0x21
program 0x12
8D extension invert
protocols
read 8D-8D-8D
write 8D-8D-8D
register 8D-8D-8D
erase commands
21 (4.00 KiB) [2]
dc (64.0 KiB) [3]
c7 (32.0 MiB)
sector map
region (in hex) | erase mask | flags
------------------+------------+----------
00000000-01ffffff | [ 23] |
zynq>
zynq> dd if=/dev/urandom of=./spi_test bs=1M count=2
2+0 records in
2+0 records out
2097152 bytes (2.0MB) copied, 0.100104 seconds, 20.0MB/s
zynq> mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
zynq> sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
zynq> mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> sha256sum spi_*
3bd63265e92e5101716839b337a4c36ab1031f4e34bc462388727aee68cf5e37 spi_read
3bd63265e92e5101716839b337a4c36ab1031f4e34bc462388727aee68cf5e37 spi_test
zynq> mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 33554432 (32M)
mtd.erasesize = 4096 (4K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
zynq> cat jedec_id
c28039
zynq> cat manufacturer
macronix
zynq> cat partname
mx25um25645g
zynq> xxd -p sfdp
53464450080104fd00070114400000ff8701011c900000ff0a0001080001
00ff05000105200100ff84000102340100ff0000000000000000ffffffff
ffffffffe5208affffffff0f00ff00ff00ff00ffeeffffffffff00ffffff
00ff0c2010d800ff00ff87790100841200d2cc02673830b030b0f4bdd55c
000000ff101000200000000000007ca34800000000008888000000000000
00400fd1fff30fd1fff300050090000500b1002b0095002b0096727103b8
727103b80000000090a3188200c069960000000000000000727100987271
00b8727100990000000072710098727100f872710099727100f900000000
00000000011501d0727106d8000086500000060100000000020001030002
00000000060100000000000072060002000000eec0697272717100d8f7f6
000a000014359c8043060f0021dcffff
zynq> md5sum sfdp
d652779f17770dc833cd96262cb2a620 sfdp
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x13
mode cycles 0
dummy cycles 0
8D-8D-8D
opcode 0xee
mode cycles 0
dummy cycles 20
Supported page program modes by the flash
1S-1S-1S
opcode 0x12
8D-8D-8D
opcode 0x12
zynq>
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id c2 80 39 c2 80 39
size 32.0 MiB
write size 1
page size 256
address nbytes 4
flags 4B_OPCODES | HAS_4BAIT | HAS_16BIT_SR | IO_MODE_EN_VOLATILE | SOFT_RESET | 1<<17
opcodes
read 0xee
dummy cycles 20
erase 0x21
program 0x12
8D extension invert
protocols
read 8D-8D-8D
write 8D-8D-8D
register 8D-8D-8D
erase commands
21 (4.00 KiB) [2]
dc (64.0 KiB) [3]
c7 (32.0 MiB)
sector map
region (in hex) | erase mask | flags
------------------+------------+----------
00000000-01ffffff | [ 23] |
zynq>
zynq> dd if=/dev/urandom of=./spi_test bs=1M count=2
2+0 records in
2+0 records out
2097152 bytes (2.0MB) copied, 0.100539 seconds, 19.9MB/s
zynq> mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
zynq> sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
zynq> mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> sha256sum spi_*
5f37a5bbdade66b0c1b7d0b3934c8b235466af9d435a98fef9b55beeb772e919 spi_read
5f37a5bbdade66b0c1b7d0b3934c8b235466af9d435a98fef9b55beeb772e919 spi_test
zynq> mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 33554432 (32M)
mtd.erasesize = 4096 (4K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
zynq> cat jedec_id
c28539
zynq> cat manufacturer
macronix
zynq> cat partname
mx25lm25645g
zynq> xxd -p sfdp
53464450080104fd00070114400000ff8701011c900000ff0a0001080001
00ff05000105200100ff84000102340100ff0000000000000000ffffffff
ffffffffe5208affffffff0f00ff00ff00ff00ffeeffffffffff00ffffff
00ff0c2010d800ff00ff87690100821200d2cc02673830b030b0f4bdd55c
000000ff101000200000000000007ca34800000000006666000000000000
00400fd1fff30fd1fff300050090000500b1002b0095002b0096727103b8
727103b80000000090a3188200c069960000000000000000727100987271
00b8727100990000000072710098727100f872710099727100f900000000
00000000011501d0727106d8000086500000060100000000020001030002
00000000060100000000000072060002000000eec0697272717100d8f7f6
0000000014351c0043060f0021dcffff
zynq> md5sum sfdp
ec258f831ac737454c7eb9f6a8a4495a sfdp
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x13
mode cycles 0
dummy cycles 0
8D-8D-8D
opcode 0xee
mode cycles 0
dummy cycles 14
Supported page program modes by the flash
1S-1S-1S
opcode 0x12
8D-8D-8D
opcode 0x12
zynq>
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id c2 85 39 c2 85 39
size 32.0 MiB
write size 1
page size 256
address nbytes 4
flags 4B_OPCODES | HAS_4BAIT | HAS_16BIT_SR | IO_MODE_EN_VOLATILE | SOFT_RESET | 1<<17
opcodes
read 0xee
dummy cycles 14
erase 0x21
program 0x12
8D extension invert
protocols
read 8D-8D-8D
write 8D-8D-8D
register 8D-8D-8D
erase commands
21 (4.00 KiB) [2]
dc (64.0 KiB) [3]
c7 (32.0 MiB)
sector map
region (in hex) | erase mask | flags
------------------+------------+----------
00000000-01ffffff | [ 23] |
zynq>
zynq> dd if=/dev/urandom of=./spi_test bs=1M count=2
2+0 records in
2+0 records out
2097152 bytes (2.0MB) copied, 0.100846 seconds, 19.8MB/s
zynq> mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
zynq> sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
zynq> mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> sha256sum spi_*
bd7d61f6862ac08a0d87bef4c7e04ff7c73ebe3cc785376baa2f0891ca38fc00 spi_read
bd7d61f6862ac08a0d87bef4c7e04ff7c73ebe3cc785376baa2f0891ca38fc00 spi_test
zynq> mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 33554432 (32M)
mtd.erasesize = 4096 (4K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
zynq> cat jedec_id
c2803a
zynq> cat manufacturer
macronix
zynq> cat partname
mx25um51245g
zynq> xxd -p sfdp
53464450080104fd00070114400000ff8701011c900000ff0a0001080001
00ff05000105200100ff84000102340100ff0000000000000000ffffffff
ffffffffe5208affffffff1f00ff00ff00ff00ffeeffffffffff00ffffff
00ff0c2010d800ff00ff8b7901008f1200e2cc04674630b030b0f4bdd55c
000000ff101000200000000000007ca34800000000008888000000000000
00400fd1fff30fd1fff300050090000500b1002b0095002b0096727103b8
727103b80000000090a3188200c069960000000000000000727100987271
00b8727100990000000072710098727100f872710099727100f900000000
00000000011501d0727106d8000086500000060100000000020001030002
00000000060100000000000072060002000000eec0697272717100d8f7f6
000a000014359c8043060f0021dcffff
zynq> md5sum sfdp
75d81c1eb2fd2767634f1d0dfbb3be35 sfdp
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x13
mode cycles 0
dummy cycles 0
8D-8D-8D
opcode 0xee
mode cycles 0
dummy cycles 20
Supported page program modes by the flash
1S-1S-1S
opcode 0x12
8D-8D-8D
opcode 0x12
zynq>
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id c2 80 3a c2 80 3a
size 64.0 MiB
write size 1
page size 256
address nbytes 4
flags 4B_OPCODES | HAS_4BAIT | HAS_16BIT_SR | IO_MODE_EN_VOLATILE | SOFT_RESET | 1<<17
opcodes
read 0xee
dummy cycles 20
erase 0x21
program 0x12
8D extension invert
protocols
read 8D-8D-8D
write 8D-8D-8D
register 8D-8D-8D
erase commands
21 (4.00 KiB) [2]
dc (64.0 KiB) [3]
c7 (64.0 MiB)
sector map
region (in hex) | erase mask | flags
------------------+------------+----------
00000000-03ffffff | [ 23] |
zynq>
zynq> dd if=/dev/urandom of=./spi_test bs=1M count=2
2+0 records in
2+0 records out
2097152 bytes (2.0MB) copied, 0.101156 seconds, 19.8MB/s
zynq> mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
zynq> sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
zynq> mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> sha256sum spi_*
bdf2135e7e809e0733400d84f5d13487febd8d45ab27004189efdecc1ae94ce6 spi_read
bdf2135e7e809e0733400d84f5d13487febd8d45ab27004189efdecc1ae94ce6 spi_test
zynq> mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 67108864 (64M)
mtd.erasesize = 4096 (4K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
zynq> cat jedec_id
c2853a
zynq> cat manufacturer
macronix
zynq> cat partname
mx25lm51245g
zynq> xxd -p sfdp
53464450080104fd00070114400000ff8701011c900000ff0a0001080001
00ff05000105200100ff84000102340100ff0000000000000000ffffffff
ffffffffe5208affffffff1f00ff00ff00ff00ffeeffffffffff00ffffff
00ff0c2010d800ff00ff897901008d1200e2cc02674430b030b0f4bdd55c
000000ff101000200000000000007ca34800000000006666000000000000
00400fd1fff30fd1fff300050090000500b1002b0095002b0096727103b8
727103b80000000090a3188200c069960000000000000000727100987271
00b8727100990000000072710098727100f872710099727100f900000000
00000000011501d0727106d8000086500000060100000000020001030002
00000000060100000000000072060002000000eec0697272717100d8f7f6
0000000014351c0043060f0021dcffff
zynq> md5sum sfdp
214868617d74e6bfb2c45444d5d6fff0 sfdp
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x13
mode cycles 0
dummy cycles 0
8D-8D-8D
opcode 0xee
mode cycles 0
dummy cycles 14
Supported page program modes by the flash
1S-1S-1S
opcode 0x12
8D-8D-8D
opcode 0x12
zynq>
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id c2 85 3a c2 85 3a
size 64.0 MiB
write size 1
page size 256
address nbytes 4
flags 4B_OPCODES | HAS_4BAIT | HAS_16BIT_SR | IO_MODE_EN_VOLATILE | SOFT_RESET | 1<<17
opcodes
read 0xee
dummy cycles 14
erase 0x21
program 0x12
8D extension invert
protocols
read 8D-8D-8D
write 8D-8D-8D
register 8D-8D-8D
erase commands
21 (4.00 KiB) [2]
dc (64.0 KiB) [3]
c7 (64.0 MiB)
sector map
region (in hex) | erase mask | flags
------------------+------------+----------
00000000-03ffffff | [ 23] |
zynq>
zynq> dd if=/dev/urandom of=./spi_test bs=1M count=2
2+0 records in
2+0 records out
2097152 bytes (2.0MB) copied, 0.100120 seconds, 20.0MB/s
zynq> mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
zynq> sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
zynq> mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> sha256sum spi_*
b9e2e3283620cdd6f7e55e116f7bb3b40d9826f86de08fdda27322adad482389 spi_read
b9e2e3283620cdd6f7e55e116f7bb3b40d9826f86de08fdda27322adad482389 spi_test
zynq> mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 67108864 (64M)
mtd.erasesize = 4096 (4K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw>
---
drivers/mtd/spi-nor/macronix.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
index 29bd5f0b32ec..42b1e2fec4f2 100644
--- a/drivers/mtd/spi-nor/macronix.c
+++ b/drivers/mtd/spi-nor/macronix.c
@@ -252,6 +252,16 @@ static const struct flash_info macronix_nor_parts[] = {
.id = SNOR_ID(0xc2, 0x94, 0x3c),
.n_banks = 4,
.flags = SPI_NOR_RWW,
+ }, {
+ .id = SNOR_ID(0xc2, 0x83, 0x39),
+ }, {
+ .id = SNOR_ID(0xc2, 0x80, 0x39),
+ }, {
+ .id = SNOR_ID(0xc2, 0x85, 0x39),
+ }, {
+ .id = SNOR_ID(0xc2, 0x80, 0x3a),
+ }, {
+ .id = SNOR_ID(0xc2, 0x85, 0x3a),
}
};
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH v8 9/9] mtd: spi-nor: add support for Macronix Octal flash MX66 series
2024-02-01 9:43 [PATCH v8 0/9] Add octal DTR support for Macronix flash Jaime Liao
` (7 preceding siblings ...)
2024-02-01 9:43 ` [PATCH v8 8/9] mtd: spi-nor: add support for Macronix Octal flash MX25 series Jaime Liao
@ 2024-02-01 9:43 ` Jaime Liao
2024-02-01 15:52 ` Michael Walle
2024-02-22 9:32 ` [PATCH v8 0/9] Add octal DTR support for Macronix flash Tudor Ambarus
9 siblings, 1 reply; 20+ messages in thread
From: Jaime Liao @ 2024-02-01 9:43 UTC (permalink / raw)
To: linux-mtd, linux-spi, tudor.ambarus, pratyush, mwalle,
miquel.raynal, richard, vigneshr, broonie
Cc: leoyu, jaimeliao
From: JaimeLiao <jaimeliao@mxic.com.tw>
Adding Macronix Octal flash for Octal DTR support.
Adding Manufacture ID 0xC2 in last of ID table because of
Octal Flash need manufacturer fixup for enabling/disabling
Octal DTR mode.
The octaflash series can be divided into the following types:
MX66 series : Serial NOR Flash with stacked die.(Size larger than 1Gb)
LM/UM series : Up to 250MHz clock frequency with both DTR/STR operation.
LW/UW series : Support simultaneous Read-while-Write operation in multiple
bank architecture. Read-while-write feature which means read
data one bank while another bank is programing or erasing.
MX66LW : 3.0V Octal I/O with Read-while-Write and stack die
MX66UW : 1.8V Octal I/O with Read-while-Write and stack die
MX66LM : 3.0V Octal I/O with stacked die
Link: https://www.mxic.com.tw/Lists/Datasheet/Attachments/8748/MX66LM1G45G,%203V,%201Gb,%20v1.1.pdf
MX66UM : 1.8V Octal I/O with stacked die
Link: https://www.mxic.com.tw/Lists/Datasheet/Attachments/8711/MX66UM1G45G,%201.8V,%201Gb,%20v1.1.pdf
Those flash have been tested on Xilinx Zynq-picozed board using
MXIC SPI controller.
As below are debugfs data, the SFDP table and result of mtd-utils
tests dump.
---
zynq> cat jedec_id
c2803b
zynq> cat manufacturer
macronix
zynq> cat partname
mx66um1g45g
zynq> xxd -p sfdp
53464450080104fd00070114400000ff8701011c900000ff0a0001080001
00ff05000105200100ff84000102340100ff0000000000000000ffffffff
ffffffffe5208affffffff3f00ff00ff00ff00ffeeffffffffff00ffffff
00ff0c2010d800ff00ff897901008d1200e2cc02674430b030b0f4bdd55c
000000ff101000200000000000007ca34800000000008888000000000000
00400fd1fff30fd1fff300050090000500b1002b0095002b0096727103b8
727103b80000000090a3188200c069960000000000000000727100987271
00b8727100990000000072710098727100f872710099727100f900000000
00000000011501d0727106d8000086500000060100000000020001030002
00000000060100000000000072060002000000eec0697272717100d8f7f6
000a000014359c8043060f0021dcffff
zynq> md5sum sfdp
eea09d64679e64f627402b39a177e356 sfdp
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x13
mode cycles 0
dummy cycles 0
8D-8D-8D
opcode 0xee
mode cycles 0
dummy cycles 20
Supported page program modes by the flash
1S-1S-1S
opcode 0x12
8D-8D-8D
opcode 0x12
zynq>
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id c2 80 3b c2 80 3b
size 128 MiB
write size 1
page size 256
address nbytes 4
flags 4B_OPCODES | HAS_4BAIT | HAS_16BIT_SR | IO_MODE_EN_VOLATILE | SOFT_RESET | 1<<17
opcodes
read 0xee
dummy cycles 20
erase 0x21
program 0x12
8D extension invert
protocols
read 8D-8D-8D
write 8D-8D-8D
register 8D-8D-8D
erase commands
21 (4.00 KiB) [2]
dc (64.0 KiB) [3]
c7 (128 MiB)
sector map
region (in hex) | erase mask | flags
------------------+------------+----------
00000000-07ffffff | [ 23] |
zynq>
zynq> dd if=/dev/urandom of=./spi_test bs=1M count=2
2+0 records in
2+0 records out
2097152 bytes (2.0MB) copied, 0.099845 seconds, 20.0MB/s
zynq> mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
zynq> sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
zynq> mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> sha256sum spi_*
7f7b735ea26eb74d77203c82347a06b51e1ef1f5b9a0fda956ffc4087caa2ed8 spi_read
7f7b735ea26eb74d77203c82347a06b51e1ef1f5b9a0fda956ffc4087caa2ed8 spi_test
zynq> mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 134217728 (128M)
mtd.erasesize = 4096 (4K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
zynq> cat jedec_id
c2853b
zynq> cat manufacturer
macronix
zynq> cat partname
mx66lm1g45g
zynq> xxd -p sfdp
53464450080104fd00070114400000ff8701011c900000ff0a0001080001
00ff05000105200100ff84000102340100ff0000000000000000ffffffff
ffffffffe5208affffffff3f00ff00ff00ff00ffeeffffffffff00ffffff
00ff0c2010d800ff00ff87690100821200e2cc02673830b030b0f4bdd55c
000000ff101000200000000000007ca34800000000006666000000000000
00400fd1fff30fd1fff300050090000500b1002b0095002b0096727103b8
727103b80000000090a3188200c069960000000000000000727100987271
00b8727100990000000072710098727100f872710099727100f900000000
00000000011501d0727106d8000086500000060100000000020001030002
00000000060100000000000072060002000000eec0697272717100d8f7f6
0000000014351c0043060f0021dcffff
zynq> md5sum sfdp
7b46113b529d58a6335531a10f14a76e sfdp
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/capabilities
Supported read modes by the flash
1S-1S-1S
opcode 0x13
mode cycles 0
dummy cycles 0
8D-8D-8D
opcode 0xee
mode cycles 0
dummy cycles 14
Supported page program modes by the flash
1S-1S-1S
opcode 0x12
8D-8D-8D
opcode 0x12
zynq>
zynq> cat /sys/kernel/debug/spi-nor/spi0.0/params
name (null)
id c2 85 3b c2 85 3b
size 128 MiB
write size 1
page size 256
address nbytes 4
flags 4B_OPCODES | HAS_4BAIT | HAS_16BIT_SR | IO_MODE_EN_VOLATILE | SOFT_RESET | 1<<17
opcodes
read 0xee
dummy cycles 14
erase 0x21
program 0x12
8D extension invert
protocols
read 8D-8D-8D
write 8D-8D-8D
register 8D-8D-8D
erase commands
21 (4.00 KiB) [2]
dc (64.0 KiB) [3]
c7 (128 MiB)
sector map
region (in hex) | erase mask | flags
------------------+------------+----------
00000000-07ffffff | [ 23] |
zynq>
zynq> dd if=/dev/urandom of=./spi_test bs=1M count=2
2+0 records in
2+0 records out
2097152 bytes (2.0MB) copied, 0.100305 seconds, 19.9MB/s
zynq> mtd_debug erase /dev/mtd0 0 2097152
Erased 2097152 bytes from address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> hexdump spi_read
0000000 ffff ffff ffff ffff ffff ffff ffff ffff
*
0200000
zynq> sha256sum spi_read
4bda3a28f4ffe603c0ec1258c0034d65a1a0d35ab7bd523a834608adabf03cc5 spi_read
zynq> mtd_debug write /dev/mtd0 0 2097152 spi_test
Copied 2097152 bytes from spi_test to address 0x00000000 in flash
zynq> mtd_debug read /dev/mtd0 0 2097152 spi_read
Copied 2097152 bytes from address 0x00000000 in flash to spi_read
zynq> sha256sum spi_*
5607ddcf8d16b481e78fc4e90b21795c19d1f9a7eb77182a20536cab82eb55a2 spi_read
5607ddcf8d16b481e78fc4e90b21795c19d1f9a7eb77182a20536cab82eb55a2 spi_test
zynq> mtd_debug info /dev/mtd0
mtd.type = MTD_NORFLASH
mtd.flags = MTD_CAP_NORFLASH
mtd.size = 134217728 (128M)
mtd.erasesize = 4096 (4K)
mtd.writesize = 1
mtd.oobsize = 0
regions = 0
Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw>
---
drivers/mtd/spi-nor/macronix.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/mtd/spi-nor/macronix.c b/drivers/mtd/spi-nor/macronix.c
index 42b1e2fec4f2..ba729007a92e 100644
--- a/drivers/mtd/spi-nor/macronix.c
+++ b/drivers/mtd/spi-nor/macronix.c
@@ -262,6 +262,13 @@ static const struct flash_info macronix_nor_parts[] = {
.id = SNOR_ID(0xc2, 0x80, 0x3a),
}, {
.id = SNOR_ID(0xc2, 0x85, 0x3a),
+ }, {
+ .id = SNOR_ID(0xc2, 0x80, 0x3b),
+ }, {
+ .id = SNOR_ID(0xc2, 0x85, 0x3b),
+ }, {
+ /* Need the manufacturer fixups. Keep this last */
+ .id = SNOR_ID(0xc2),
}
};
--
2.25.1
^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH v8 2/9] spi: spi-mem: Allow specifying the byte order in Octal DTR mode
2024-02-01 9:43 ` [PATCH v8 2/9] spi: spi-mem: Allow specifying the byte order in Octal DTR mode Jaime Liao
@ 2024-02-01 12:04 ` Mark Brown
2024-02-01 15:18 ` Michael Walle
1 sibling, 0 replies; 20+ messages in thread
From: Mark Brown @ 2024-02-01 12:04 UTC (permalink / raw)
To: Jaime Liao
Cc: linux-mtd, linux-spi, tudor.ambarus, pratyush, mwalle,
miquel.raynal, richard, vigneshr, leoyu, jaimeliao
[-- Attachment #1: Type: text/plain, Size: 486 bytes --]
On Thu, Feb 01, 2024 at 05:43:46PM +0800, Jaime Liao wrote:
> From: JaimeLiao <jaimeliao@mxic.com.tw>
>
> There are NOR flashes (Macronix) that swap the bytes on a 16-bit
> boundary when configured in Octal DTR mode. The byte order of
> 16-bit words is swapped when read or written in Octal Double
> Transfer Rate (DTR) mode compared to Single Transfer Rate (STR)
> modes. If one writes D0 D1 D2 D3 bytes using 1-1-1 mode, and uses
Acked-by: Mark Brown <broonie@kernel.org>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v8 5/9] spi: mxic: Add support for swapping byte
2024-02-01 9:43 ` [PATCH v8 5/9] spi: mxic: Add support for swapping byte Jaime Liao
@ 2024-02-01 12:05 ` Mark Brown
2024-02-01 15:39 ` Michael Walle
1 sibling, 0 replies; 20+ messages in thread
From: Mark Brown @ 2024-02-01 12:05 UTC (permalink / raw)
To: Jaime Liao
Cc: linux-mtd, linux-spi, tudor.ambarus, pratyush, mwalle,
miquel.raynal, richard, vigneshr, leoyu, jaimeliao
[-- Attachment #1: Type: text/plain, Size: 547 bytes --]
On Thu, Feb 01, 2024 at 05:43:49PM +0800, Jaime Liao wrote:
> From: JaimeLiao <jaimeliao@mxic.com.tw>
>
> Some SPI-NOR flash swap the bytes on a 16-bit boundary when
> configured in Octal DTR mode. It means data format D0 D1 D2 D3
> would be swapped to D1 D0 D3 D2. So that whether controller
> support swapping bytes should be checked before enable Octal
> DTR mode. Add swap byte support on a 16-bit boundary when
> configured in Octal DTR mode for Macronix xSPI host controller
> dirver.
Acked-by: Mark Brown <broonie@kernel.org>
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v8 2/9] spi: spi-mem: Allow specifying the byte order in Octal DTR mode
2024-02-01 9:43 ` [PATCH v8 2/9] spi: spi-mem: Allow specifying the byte order in Octal DTR mode Jaime Liao
2024-02-01 12:04 ` Mark Brown
@ 2024-02-01 15:18 ` Michael Walle
1 sibling, 0 replies; 20+ messages in thread
From: Michael Walle @ 2024-02-01 15:18 UTC (permalink / raw)
To: Jaime Liao
Cc: linux-mtd, linux-spi, tudor.ambarus, pratyush, miquel.raynal,
richard, vigneshr, broonie, leoyu, jaimeliao
Hi,
> From: JaimeLiao <jaimeliao@mxic.com.tw>
I think Tudor told you to keep his name/mail here.
> There are NOR flashes (Macronix) that swap the bytes on a 16-bit
> boundary when configured in Octal DTR mode. The byte order of
> 16-bit words is swapped when read or written in Octal Double
> Transfer Rate (DTR) mode compared to Single Transfer Rate (STR)
> modes. If one writes D0 D1 D2 D3 bytes using 1-1-1 mode, and uses
> 8D-8D-8D SPI mode for reading, it will read back D1 D0 D3 D2.
> Swapping the bytes may introduce some endianness problems. It can
> affect the boot sequence if the entire boot sequence is not handled
> in either 8D-8D-8D mode or 1-1-1 mode. So we must swap the bytes
> back to have the same byte order as in STR modes. Fortunately there
> are controllers that could swap the bytes back at runtime,
> addressing the flash's endiannesses requirements. Provide a way for
> the upper layers to specify the byte order in Octal DTR mode.
>
> Merge Tudor's patch and add modifications for suiting newer version
> of Linux kernel.
>
> Suggested-by: Michael Walle <mwalle@kernel.org>
> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
> Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw>
> ---
> drivers/spi/spi-mem.c | 4 ++++
> include/linux/spi/spi-mem.h | 6 ++++++
> 2 files changed, 10 insertions(+)
>
> diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
> index 2dc8ceb85374..f8120f6b288f 100644
> --- a/drivers/spi/spi-mem.c
> +++ b/drivers/spi/spi-mem.c
> @@ -172,6 +172,10 @@ bool spi_mem_default_supports_op(struct spi_mem
> *mem,
> if (!spi_mem_controller_is_capable(ctlr, dtr))
> return false;
>
> + if (op->data.swap16 &&
> + !spi_mem_controller_is_capable(ctlr, swap16))
Since you need to redo this anyway (see below):
This can now be one line. Please keep in mind that the 80char limit
was extended to 100 chars some time ago. And I think this reads
better if its just one line.
> + return false;
> +
> if (op->cmd.nbytes != 2)
> return false;
> } else {
> diff --git a/include/linux/spi/spi-mem.h b/include/linux/spi/spi-mem.h
> index f866d5c8ed32..8df44fbc9d99 100644
> --- a/include/linux/spi/spi-mem.h
> +++ b/include/linux/spi/spi-mem.h
> @@ -89,6 +89,8 @@ enum spi_mem_data_dir {
> * @dummy.dtr: whether the dummy bytes should be sent in DTR mode or
> not
> * @data.buswidth: number of IO lanes used to send/receive the data
> * @data.dtr: whether the data should be sent in DTR mode or not
> + * @data.swap16: whether the byte order of 16-bit words is swapped
> when read
> + * or written in Octal DTR mode compared to STR mode.
I think this was ordered alphabetically in the former patch, but since
you've renamed it to swap16 now the order would change. I don't have
any preference here, just wanted to point that out. I just noticed
because the new member "swap16" in spi_controller_mem_caps was added in
the middle, which looked odd.
> * @data.ecc: whether error correction is required or not
> * @data.dir: direction of the transfer
> * @data.nbytes: number of data bytes to send/receive. Can be zero if
> the
> @@ -123,6 +125,7 @@ struct spi_mem_op {
> struct {
> u8 buswidth;
> u8 dtr : 1;
> + u8 swap16 : 1;
> u8 ecc : 1;
> u8 __pad : 6;
Still wrong, please go over all the previous remarks, to be clear you
have
to use "__pad : 5" here.
Otherwise looks good. So with the above fixed:
Reviewed-by: Michael Walle <mwalle@kernel.org>
-michael
> enum spi_mem_data_dir dir;
> @@ -296,10 +299,13 @@ struct spi_controller_mem_ops {
> /**
> * struct spi_controller_mem_caps - SPI memory controller capabilities
> * @dtr: Supports DTR operations
> + * @swap16: Supports swapping bytes on a 16 bit boundary when
> configured in
> + * Octal DTR
> * @ecc: Supports operations with error correction
> */
> struct spi_controller_mem_caps {
> bool dtr;
> + bool swap16;
> bool ecc;
> };
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v8 3/9] mtd: spi-nor: core: Allow specifying the byte order in Octal DTR mode
2024-02-01 9:43 ` [PATCH v8 3/9] mtd: spi-nor: core: " Jaime Liao
@ 2024-02-01 15:28 ` Michael Walle
0 siblings, 0 replies; 20+ messages in thread
From: Michael Walle @ 2024-02-01 15:28 UTC (permalink / raw)
To: Jaime Liao
Cc: linux-mtd, linux-spi, tudor.ambarus, pratyush, miquel.raynal,
richard, vigneshr, broonie, leoyu, jaimeliao
> From: JaimeLiao <jaimeliao@mxic.com.tw>
Same remark as for patch 2/9.
> Macronix swaps bytes on a 16-bit boundary when configured in Octal DTR.
> The byte order of 16-bit words is swapped when read or written in
> 8D-8D-8D
> mode compared to STR modes. Allow operations to specify the byte order
> in
> DTR mode, so that controllers can swap the bytes back at run-time to
> address the flash's endianness requirements, if they are capable. If
> the
> controllers are not capable of swapping the bytes, the protocol is
> downgrade via spi_nor_spimem_adjust_hwcaps(). When available, the
> swapping
> of the bytes is always done regardless if it's a data or register
> access,
> so that we comply with the JESD216 requirements: "Byte order of 16-bit
> words is swapped when read in 8D-8D-8D mode compared to 1-1-1".
>
> Merge Tudor's patch and add modifications for suiting newer version
> of Linux kernel.
>
> Suggested-by: Michael Walle <mwalle@kernel.org>
> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
> Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw>
> ---
> drivers/mtd/spi-nor/core.c | 5 +++++
> drivers/mtd/spi-nor/core.h | 1 +
> 2 files changed, 6 insertions(+)
>
> diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
> index 4129764fad8c..0076007e1cde 100644
> --- a/drivers/mtd/spi-nor/core.c
> +++ b/drivers/mtd/spi-nor/core.c
> @@ -113,6 +113,11 @@ void spi_nor_spimem_setup_op(const struct spi_nor
> *nor,
> op->cmd.opcode = (op->cmd.opcode << 8) | ext;
> op->cmd.nbytes = 2;
> }
> +
> + /* SWAP16 is only applicable when Octal DTR mode */
> + if (nor->read_proto == SNOR_PROTO_8_8_8_DTR)
Why is it read_proto now? For all the former patches, the local
proto variable was used.
> + if (nor->flags & SNOR_F_SWAP16)
Please fold this into the former condition.
if (proto == SNOR_PROTO_8_8_8_DTR && nor->flags & SNOR_F_SWAP16)
op->data.swap16 = true;
-michael
> + op->data.swap16 = true;
> }
>
> /**
> diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
> index d36c0e072954..3c5190ac0a79 100644
> --- a/drivers/mtd/spi-nor/core.h
> +++ b/drivers/mtd/spi-nor/core.h
> @@ -140,6 +140,7 @@ enum spi_nor_option_flags {
> SNOR_F_RWW = BIT(14),
> SNOR_F_ECC = BIT(15),
> SNOR_F_NO_WP = BIT(16),
> + SNOR_F_SWAP16 = BIT(17),
> };
>
> struct spi_nor_read_command {
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v8 5/9] spi: mxic: Add support for swapping byte
2024-02-01 9:43 ` [PATCH v8 5/9] spi: mxic: Add support for swapping byte Jaime Liao
2024-02-01 12:05 ` Mark Brown
@ 2024-02-01 15:39 ` Michael Walle
1 sibling, 0 replies; 20+ messages in thread
From: Michael Walle @ 2024-02-01 15:39 UTC (permalink / raw)
To: Jaime Liao
Cc: linux-mtd, linux-spi, tudor.ambarus, pratyush, miquel.raynal,
richard, vigneshr, broonie, leoyu, jaimeliao
Hi,
> From: JaimeLiao <jaimeliao@mxic.com.tw>
>
> Some SPI-NOR flash swap the bytes on a 16-bit boundary when
> configured in Octal DTR mode. It means data format D0 D1 D2 D3
> would be swapped to D1 D0 D3 D2. So that whether controller
> support swapping bytes should be checked before enable Octal
> DTR mode. Add swap byte support on a 16-bit boundary when
> configured in Octal DTR mode for Macronix xSPI host controller
> dirver.
>
> According dtr_swab in operation to enable/disable Macronix
> xSPI host controller swap byte feature.
>
> To make sure swap byte feature is working well, program data in
> 1S-1S-1S mode then read back and compare read data in 8D-8D-8D
> mode.
>
> This feature have been validated on byte-swap flash and
> non-byte-swap flash.
>
> Macronix xSPI host controller bit "HC_CFG_DATA_PASS" determine
> the byte swap feature disabled/enabled and swap byte feature is
> working on 8D-8D-8D mode only.
>
> Suggested-by: Michael Walle <mwalle@kernel.org>
> Signed-off-by: JaimeLiao <jaimeliao@mxic.com.tw>
> ---
> drivers/spi/spi-mxic.c | 17 +++++++++++++----
> 1 file changed, 13 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/spi/spi-mxic.c b/drivers/spi/spi-mxic.c
> index 60c9f3048ac9..8ac302e48c9f 100644
> --- a/drivers/spi/spi-mxic.c
> +++ b/drivers/spi/spi-mxic.c
> @@ -294,7 +294,8 @@ static void mxic_spi_hw_init(struct mxic_spi *mxic)
> mxic->regs + HC_CFG);
> }
>
> -static u32 mxic_spi_prep_hc_cfg(struct spi_device *spi, u32 flags)
> +static u32 mxic_spi_prep_hc_cfg(struct spi_device *spi, u32 flags,
> + bool swap16)
> {
> int nio = 1;
>
> @@ -305,6 +306,11 @@ static u32 mxic_spi_prep_hc_cfg(struct spi_device
> *spi, u32 flags)
> else if (spi->mode & (SPI_TX_DUAL | SPI_RX_DUAL))
> nio = 2;
>
> + if (!swap16)
> + flags |= HC_CFG_DATA_PASS;
> + else
> + flags &= ~HC_CFG_DATA_PASS;
Again, not my driver and I don't care too much, but you are changing
the behavior of this driver. If I had to guess, with this patch applied,
you'd read data (in octal mode) with the bytes swapped compared to
kernel
without this patch.
And compared to the former version, you just made it harder to read
by using negated logic.
-michael
> +
> return flags | HC_CFG_NIO(nio) |
> HC_CFG_TYPE(spi_get_chipselect(spi, 0), HC_CFG_TYPE_SPI_NOR) |
> HC_CFG_SLV_ACT(spi_get_chipselect(spi, 0)) |
> HC_CFG_IDLE_SIO_LVL(1);
> @@ -397,7 +403,8 @@ static ssize_t mxic_spi_mem_dirmap_read(struct
> spi_mem_dirmap_desc *desc,
> if (WARN_ON(offs + desc->info.offset + len > U32_MAX))
> return -EINVAL;
>
> - writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0), mxic->regs + HC_CFG);
> + writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0,
> desc->info.op_tmpl.data.swap16),
> + mxic->regs + HC_CFG);
>
> writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl, len),
> mxic->regs + LRD_CFG);
> @@ -441,7 +448,8 @@ static ssize_t mxic_spi_mem_dirmap_write(struct
> spi_mem_dirmap_desc *desc,
> if (WARN_ON(offs + desc->info.offset + len > U32_MAX))
> return -EINVAL;
>
> - writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0), mxic->regs + HC_CFG);
> + writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0,
> desc->info.op_tmpl.data.swap16),
> + mxic->regs + HC_CFG);
>
> writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl, len),
> mxic->regs + LWR_CFG);
> @@ -518,7 +526,7 @@ static int mxic_spi_mem_exec_op(struct spi_mem
> *mem,
> if (ret)
> return ret;
>
> - writel(mxic_spi_prep_hc_cfg(mem->spi, HC_CFG_MAN_CS_EN),
> + writel(mxic_spi_prep_hc_cfg(mem->spi, HC_CFG_MAN_CS_EN,
> op->data.swap16),
> mxic->regs + HC_CFG);
>
> writel(HC_EN_BIT, mxic->regs + HC_EN);
> @@ -572,6 +580,7 @@ static const struct spi_controller_mem_ops
> mxic_spi_mem_ops = {
>
> static const struct spi_controller_mem_caps mxic_spi_mem_caps = {
> .dtr = true,
> + .swap16 = true,
> .ecc = true,
> };
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v8 6/9] mtd: spi-nor: add support for Macronix Octal flash MX25 series with RWW feature
2024-02-01 9:43 ` [PATCH v8 6/9] mtd: spi-nor: add support for Macronix Octal flash MX25 series with RWW feature Jaime Liao
@ 2024-02-01 15:48 ` Michael Walle
0 siblings, 0 replies; 20+ messages in thread
From: Michael Walle @ 2024-02-01 15:48 UTC (permalink / raw)
To: Jaime Liao
Cc: linux-mtd, linux-spi, tudor.ambarus, pratyush, miquel.raynal,
richard, vigneshr, broonie, leoyu, jaimeliao
Hi,
> From: JaimeLiao <jaimeliao@mxic.com.tw>
>
> Adding Macronix Octal flash for Octal DTR support.
>
> The octaflash series can be divided into the following types:
>
> MX25 series : Serial NOR Flash.
> LM/UM series : Up to 250MHz clock frequency with both DTR/STR
> operation.
> LW/UW series : Support simultaneous Read-while-Write operation in
> multiple
> bank architecture. Read-while-write feature which means
> read
> data one bank while another bank is programing or
> erasing.
>
> MX25LW : 3.0V Octal I/O with Read-while-Write
> MX25UW : 1.8V Octal I/O with Read-while-Write
>
> MX25LM : 3.0V Octal I/O
> Link:
> https://www.mxic.com.tw/Lists/Datasheet/Attachments/8729/MX25LM51245G,%203V,%20512Mb,%20v1.1.pdf
>
> MX25UM : 1.8V Octal I/O
> Link:
> https://www.mxic.com.tw/Lists/Datasheet/Attachments/8967/MX25UM51245G,%201.8V,%20512Mb,%20v1.5.pdf
>
> Those flash have been tested on Xilinx Zynq-picozed board using
> MXIC SPI controller.
> As below are debugfs data, the SFDP table and result of mtd-utils
> tests dump.
>
> ---
What is this? There is already a "---" below.
It goes like this:
[From:]
Patch description.
Link:
Link:
Signed-off-by:
---
Test data and SFDP dump
diff --git a/drivers/mtd/spi-nor/macronix.c
b/drivers/mtd/spi-nor/macronix.c
...
-michael
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v8 9/9] mtd: spi-nor: add support for Macronix Octal flash MX66 series
2024-02-01 9:43 ` [PATCH v8 9/9] mtd: spi-nor: add support for Macronix Octal flash MX66 series Jaime Liao
@ 2024-02-01 15:52 ` Michael Walle
0 siblings, 0 replies; 20+ messages in thread
From: Michael Walle @ 2024-02-01 15:52 UTC (permalink / raw)
To: Jaime Liao
Cc: linux-mtd, linux-spi, tudor.ambarus, pratyush, miquel.raynal,
richard, vigneshr, broonie, leoyu, jaimeliao
Hi,
> --- a/drivers/mtd/spi-nor/macronix.c
> +++ b/drivers/mtd/spi-nor/macronix.c
> @@ -262,6 +262,13 @@ static const struct flash_info
> macronix_nor_parts[] = {
> .id = SNOR_ID(0xc2, 0x80, 0x3a),
> }, {
> .id = SNOR_ID(0xc2, 0x85, 0x3a),
> + }, {
> + .id = SNOR_ID(0xc2, 0x80, 0x3b),
> + }, {
> + .id = SNOR_ID(0xc2, 0x85, 0x3b),
These and all of patch 8/9 is not needed because you add the whole
manufacturer in the next line.
> + }, {
> + /* Need the manufacturer fixups. Keep this last */
> + .id = SNOR_ID(0xc2),
> }
> };
Replace patch 8/9 and 9/9 with just the following:
+ /* Need the manufacturer fixups. Keep this last */
+ { .id = SNOR_ID(0xc2) }
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v8 0/9] Add octal DTR support for Macronix flash
2024-02-01 9:43 [PATCH v8 0/9] Add octal DTR support for Macronix flash Jaime Liao
` (8 preceding siblings ...)
2024-02-01 9:43 ` [PATCH v8 9/9] mtd: spi-nor: add support for Macronix Octal flash MX66 series Jaime Liao
@ 2024-02-22 9:32 ` Tudor Ambarus
2024-02-22 9:55 ` liao jaime
9 siblings, 1 reply; 20+ messages in thread
From: Tudor Ambarus @ 2024-02-22 9:32 UTC (permalink / raw)
To: Jaime Liao, linux-mtd, linux-spi, pratyush, mwalle,
miquel.raynal, richard, vigneshr, broonie
Cc: leoyu, jaimeliao
Jaime,
You're so close to have these integrated, I see there are no major
comments for the patch set. Would you please address the comments and
re-submit?
I plan to do the PR next Monday.
ta
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v8 0/9] Add octal DTR support for Macronix flash
2024-02-22 9:32 ` [PATCH v8 0/9] Add octal DTR support for Macronix flash Tudor Ambarus
@ 2024-02-22 9:55 ` liao jaime
2024-02-26 2:02 ` Alvin Zhou
0 siblings, 1 reply; 20+ messages in thread
From: liao jaime @ 2024-02-22 9:55 UTC (permalink / raw)
To: Tudor Ambarus
Cc: linux-mtd, linux-spi, pratyush, mwalle, miquel.raynal, richard,
vigneshr, broonie, leoyu, jaimeliao, alvinzhou.tw, Alvin Zhou
Hi Tudor
>
> Jaime,
>
> You're so close to have these integrated, I see there are no major
> comments for the patch set. Would you please address the comments and
> re-submit?
This patchset would be take over by Alvin.
Thank you for always giving useful and kind advice.
>
> I plan to do the PR next Monday.
>
> ta
Thanks
Jaime
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH v8 0/9] Add octal DTR support for Macronix flash
2024-02-22 9:55 ` liao jaime
@ 2024-02-26 2:02 ` Alvin Zhou
0 siblings, 0 replies; 20+ messages in thread
From: Alvin Zhou @ 2024-02-26 2:02 UTC (permalink / raw)
To: Tudor Ambarus
Cc: linux-mtd, linux-spi, pratyush, mwalle, miquel.raynal, richard,
vigneshr, broonie, leoyu, jaimeliao, Alvin Zhou
Hi Tudor,
>
> Hi Tudor
>
>
> >
> > Jaime,
> >
> > You're so close to have these integrated, I see there are no major
> > comments for the patch set. Would you please address the comments and
> > re-submit?
> This patchset would be take over by Alvin.
> Thank you for always giving useful and kind advice.
>
> >
> > I plan to do the PR next Monday.
Because I just received the patchwork from Jaime, so I need to spend
some time studying the comments to prepare for the next PR.
Thank you for your understanding.
> >
> > ta
>
> Thanks
> Jaime
Thanks
Alvin
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2024-02-26 2:03 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-02-01 9:43 [PATCH v8 0/9] Add octal DTR support for Macronix flash Jaime Liao
2024-02-01 9:43 ` [PATCH v8 1/9] mtd: spi-nor: add Octal " Jaime Liao
2024-02-01 9:43 ` [PATCH v8 2/9] spi: spi-mem: Allow specifying the byte order in Octal DTR mode Jaime Liao
2024-02-01 12:04 ` Mark Brown
2024-02-01 15:18 ` Michael Walle
2024-02-01 9:43 ` [PATCH v8 3/9] mtd: spi-nor: core: " Jaime Liao
2024-02-01 15:28 ` Michael Walle
2024-02-01 9:43 ` [PATCH v8 4/9] mtd: spi-nor: sfdp: Get the 8D-8D-8D byte order from BFPT Jaime Liao
2024-02-01 9:43 ` [PATCH v8 5/9] spi: mxic: Add support for swapping byte Jaime Liao
2024-02-01 12:05 ` Mark Brown
2024-02-01 15:39 ` Michael Walle
2024-02-01 9:43 ` [PATCH v8 6/9] mtd: spi-nor: add support for Macronix Octal flash MX25 series with RWW feature Jaime Liao
2024-02-01 15:48 ` Michael Walle
2024-02-01 9:43 ` [PATCH v8 7/9] mtd: spi-nor: add support for Macronix Octal flash MX66 " Jaime Liao
2024-02-01 9:43 ` [PATCH v8 8/9] mtd: spi-nor: add support for Macronix Octal flash MX25 series Jaime Liao
2024-02-01 9:43 ` [PATCH v8 9/9] mtd: spi-nor: add support for Macronix Octal flash MX66 series Jaime Liao
2024-02-01 15:52 ` Michael Walle
2024-02-22 9:32 ` [PATCH v8 0/9] Add octal DTR support for Macronix flash Tudor Ambarus
2024-02-22 9:55 ` liao jaime
2024-02-26 2:02 ` Alvin Zhou
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