* [PATCH] ARM: dts: at91: sama5d2 Xplained: add QSPI0 + SPI NOR memory nodes
@ 2018-12-10 17:15 Tudor.Ambarus
2018-12-10 21:35 ` Alexandre Belloni
2018-12-11 14:40 ` Boris Brezillon
0 siblings, 2 replies; 8+ messages in thread
From: Tudor.Ambarus @ 2018-12-10 17:15 UTC (permalink / raw)
To: Nicolas.Ferre, alexandre.belloni, Ludovic.Desroches, robh+dt,
mark.rutland, Cyrille.Pitchen
Cc: linux-arm-kernel, devicetree, linux-kernel, boris.brezillon,
linux-mtd, broonie, linux-spi, Tudor.Ambarus
From: Cyrille Pitchen <cyrille.pitchen@microchip.com>
This patch configures the QSPI0 controller pin muxing and declares
a jedec,spi-nor memory.
sama5d2 Xplained RevB and RevC use the Macronix MX25L25673G flash
memory which advertises a maximum frequency of 80MHz for Quad IO
Fast Read. Set the spi-max-frequency to 80MHz knowing that actually
the QSPI drver will set the SPI bus clock to 166MHz / 3 = 55.3MHz.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@microchip.com>
[tudor.ambarus@microchip.com:
- drop partitions,
- add spi-rx/tx-bus-width
- change spi-max-frequency to match the 80MHz limit advertised by
MX25L25673G for Quad IO Fast Read,
- reword commit message and subject.]
Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
---
arch/arm/boot/dts/at91-sama5d2_xplained.dts | 31 +++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
index 518e2b095ccf..171bc82cfbbf 100644
--- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
+++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
@@ -108,6 +108,21 @@
};
apb {
+ qspi0: spi@f0020000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_qspi0_default>;
+ /* status = "okay"; */ /* conflict with sdmmc1 */
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <80000000>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ m25p,fast-read;
+ };
+ };
+
spi0: spi@f8000000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0_default>;
@@ -485,6 +500,22 @@
bias-disable;
};
+ pinctrl_qspi0_default: qspi0_default {
+ sck_cs {
+ pinmux = <PIN_PA22__QSPI0_SCK>,
+ <PIN_PA23__QSPI0_CS>;
+ bias-disable;
+ };
+
+ data {
+ pinmux = <PIN_PA24__QSPI0_IO0>,
+ <PIN_PA25__QSPI0_IO1>,
+ <PIN_PA26__QSPI0_IO2>,
+ <PIN_PA27__QSPI0_IO3>;
+ bias-pull-up;
+ };
+ };
+
pinctrl_sdmmc0_default: sdmmc0_default {
cmd_data {
pinmux = <PIN_PA1__SDMMC0_CMD>,
--
2.9.4
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH] ARM: dts: at91: sama5d2 Xplained: add QSPI0 + SPI NOR memory nodes
2018-12-10 17:15 [PATCH] ARM: dts: at91: sama5d2 Xplained: add QSPI0 + SPI NOR memory nodes Tudor.Ambarus
@ 2018-12-10 21:35 ` Alexandre Belloni
2018-12-11 12:32 ` Tudor.Ambarus
2018-12-11 14:40 ` Boris Brezillon
1 sibling, 1 reply; 8+ messages in thread
From: Alexandre Belloni @ 2018-12-10 21:35 UTC (permalink / raw)
To: Tudor.Ambarus
Cc: Nicolas.Ferre, Ludovic.Desroches, robh+dt, mark.rutland,
Cyrille.Pitchen, linux-arm-kernel, devicetree, linux-kernel,
boris.brezillon, linux-mtd, broonie, linux-spi
Hi,
On 10/12/2018 17:15:29+0000, Tudor.Ambarus@microchip.com wrote:
> From: Cyrille Pitchen <cyrille.pitchen@microchip.com>
>
> This patch configures the QSPI0 controller pin muxing and declares
> a jedec,spi-nor memory.
>
> sama5d2 Xplained RevB and RevC use the Macronix MX25L25673G flash
> memory which advertises a maximum frequency of 80MHz for Quad IO
> Fast Read. Set the spi-max-frequency to 80MHz knowing that actually
> the QSPI drver will set the SPI bus clock to 166MHz / 3 = 55.3MHz.
>
> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@microchip.com>
> [tudor.ambarus@microchip.com:
> - drop partitions,
> - add spi-rx/tx-bus-width
> - change spi-max-frequency to match the 80MHz limit advertised by
> MX25L25673G for Quad IO Fast Read,
> - reword commit message and subject.]
> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
> ---
> arch/arm/boot/dts/at91-sama5d2_xplained.dts | 31 +++++++++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
>
> diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> index 518e2b095ccf..171bc82cfbbf 100644
> --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> @@ -108,6 +108,21 @@
> };
>
> apb {
> + qspi0: spi@f0020000 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_qspi0_default>;
> + /* status = "okay"; */ /* conflict with sdmmc1 */
Isn't that conflicting then because I think the default is okay.
> +
> + flash@0 {
> + compatible = "jedec,spi-nor";
> + reg = <0>;
> + spi-max-frequency = <80000000>;
> + spi-tx-bus-width = <4>;
> + spi-rx-bus-width = <4>;
> + m25p,fast-read;
> + };
> + };
> +
> spi0: spi@f8000000 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_spi0_default>;
> @@ -485,6 +500,22 @@
> bias-disable;
> };
>
> + pinctrl_qspi0_default: qspi0_default {
> + sck_cs {
> + pinmux = <PIN_PA22__QSPI0_SCK>,
> + <PIN_PA23__QSPI0_CS>;
> + bias-disable;
> + };
> +
> + data {
> + pinmux = <PIN_PA24__QSPI0_IO0>,
> + <PIN_PA25__QSPI0_IO1>,
> + <PIN_PA26__QSPI0_IO2>,
> + <PIN_PA27__QSPI0_IO3>;
> + bias-pull-up;
> + };
> + };
> +
> pinctrl_sdmmc0_default: sdmmc0_default {
> cmd_data {
> pinmux = <PIN_PA1__SDMMC0_CMD>,
> --
> 2.9.4
>
--
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] ARM: dts: at91: sama5d2 Xplained: add QSPI0 + SPI NOR memory nodes
2018-12-10 21:35 ` Alexandre Belloni
@ 2018-12-11 12:32 ` Tudor.Ambarus
2018-12-11 14:35 ` Alexandre Belloni
0 siblings, 1 reply; 8+ messages in thread
From: Tudor.Ambarus @ 2018-12-11 12:32 UTC (permalink / raw)
To: alexandre.belloni
Cc: Nicolas.Ferre, Ludovic.Desroches, robh+dt, mark.rutland,
Cyrille.Pitchen, linux-arm-kernel, devicetree, linux-kernel,
boris.brezillon, linux-mtd, broonie, linux-spi
Hi, Alexandre,
On 12/10/2018 11:35 PM, Alexandre Belloni wrote:
> Hi,
>
> On 10/12/2018 17:15:29+0000, Tudor.Ambarus@microchip.com wrote:
>> From: Cyrille Pitchen <cyrille.pitchen@microchip.com>
>>
>> This patch configures the QSPI0 controller pin muxing and declares
>> a jedec,spi-nor memory.
>>
>> sama5d2 Xplained RevB and RevC use the Macronix MX25L25673G flash
>> memory which advertises a maximum frequency of 80MHz for Quad IO
>> Fast Read. Set the spi-max-frequency to 80MHz knowing that actually
>> the QSPI drver will set the SPI bus clock to 166MHz / 3 = 55.3MHz.
>>
>> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@microchip.com>
>> [tudor.ambarus@microchip.com:
>> - drop partitions,
>> - add spi-rx/tx-bus-width
>> - change spi-max-frequency to match the 80MHz limit advertised by
>> MX25L25673G for Quad IO Fast Read,
>> - reword commit message and subject.]
>> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
>> ---
>> arch/arm/boot/dts/at91-sama5d2_xplained.dts | 31 +++++++++++++++++++++++++++++
>> 1 file changed, 31 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
>> index 518e2b095ccf..171bc82cfbbf 100644
>> --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
>> +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
>> @@ -108,6 +108,21 @@
>> };
>>
>> apb {
>> + qspi0: spi@f0020000 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_qspi0_default>;
>> + /* status = "okay"; */ /* conflict with sdmmc1 */
>
> Isn't that conflicting then because I think the default is okay.
qspi0 is disabled in sama5d2.dtsi.
Thanks,
ta
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] ARM: dts: at91: sama5d2 Xplained: add QSPI0 + SPI NOR memory nodes
2018-12-11 12:32 ` Tudor.Ambarus
@ 2018-12-11 14:35 ` Alexandre Belloni
2018-12-11 14:50 ` Ludovic Desroches
0 siblings, 1 reply; 8+ messages in thread
From: Alexandre Belloni @ 2018-12-11 14:35 UTC (permalink / raw)
To: Tudor.Ambarus
Cc: Nicolas.Ferre, Ludovic.Desroches, robh+dt, mark.rutland,
Cyrille.Pitchen, linux-arm-kernel, devicetree, linux-kernel,
boris.brezillon, linux-mtd, broonie, linux-spi
On 11/12/2018 12:32:40+0000, Tudor.Ambarus@microchip.com wrote:
> Hi, Alexandre,
>
> On 12/10/2018 11:35 PM, Alexandre Belloni wrote:
> > Hi,
> >
> > On 10/12/2018 17:15:29+0000, Tudor.Ambarus@microchip.com wrote:
> >> From: Cyrille Pitchen <cyrille.pitchen@microchip.com>
> >>
> >> This patch configures the QSPI0 controller pin muxing and declares
> >> a jedec,spi-nor memory.
> >>
> >> sama5d2 Xplained RevB and RevC use the Macronix MX25L25673G flash
> >> memory which advertises a maximum frequency of 80MHz for Quad IO
> >> Fast Read. Set the spi-max-frequency to 80MHz knowing that actually
> >> the QSPI drver will set the SPI bus clock to 166MHz / 3 = 55.3MHz.
> >>
> >> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@microchip.com>
> >> [tudor.ambarus@microchip.com:
> >> - drop partitions,
> >> - add spi-rx/tx-bus-width
> >> - change spi-max-frequency to match the 80MHz limit advertised by
> >> MX25L25673G for Quad IO Fast Read,
> >> - reword commit message and subject.]
> >> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
> >> ---
> >> arch/arm/boot/dts/at91-sama5d2_xplained.dts | 31 +++++++++++++++++++++++++++++
> >> 1 file changed, 31 insertions(+)
> >>
> >> diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> >> index 518e2b095ccf..171bc82cfbbf 100644
> >> --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> >> +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> >> @@ -108,6 +108,21 @@
> >> };
> >>
> >> apb {
> >> + qspi0: spi@f0020000 {
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&pinctrl_qspi0_default>;
> >> + /* status = "okay"; */ /* conflict with sdmmc1 */
> >
> > Isn't that conflicting then because I think the default is okay.
> qspi0 is disabled in sama5d2.dtsi.
>
Ok, then maybe that comment is not necessary at all.
--
Alexandre Belloni, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] ARM: dts: at91: sama5d2 Xplained: add QSPI0 + SPI NOR memory nodes
2018-12-10 17:15 [PATCH] ARM: dts: at91: sama5d2 Xplained: add QSPI0 + SPI NOR memory nodes Tudor.Ambarus
2018-12-10 21:35 ` Alexandre Belloni
@ 2018-12-11 14:40 ` Boris Brezillon
2018-12-11 14:48 ` Ludovic Desroches
2018-12-11 14:49 ` Tudor.Ambarus
1 sibling, 2 replies; 8+ messages in thread
From: Boris Brezillon @ 2018-12-11 14:40 UTC (permalink / raw)
To: Tudor.Ambarus
Cc: Nicolas.Ferre, alexandre.belloni, Ludovic.Desroches, robh+dt,
mark.rutland, Cyrille.Pitchen, linux-arm-kernel, devicetree,
linux-kernel, linux-mtd, broonie, linux-spi
On Mon, 10 Dec 2018 17:15:29 +0000
<Tudor.Ambarus@microchip.com> wrote:
> From: Cyrille Pitchen <cyrille.pitchen@microchip.com>
>
> This patch configures the QSPI0 controller pin muxing and declares
> a jedec,spi-nor memory.
>
> sama5d2 Xplained RevB and RevC use the Macronix MX25L25673G flash
> memory which advertises a maximum frequency of 80MHz for Quad IO
> Fast Read. Set the spi-max-frequency to 80MHz knowing that actually
> the QSPI drver will set the SPI bus clock to 166MHz / 3 = 55.3MHz.
>
> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@microchip.com>
> [tudor.ambarus@microchip.com:
> - drop partitions,
> - add spi-rx/tx-bus-width
> - change spi-max-frequency to match the 80MHz limit advertised by
> MX25L25673G for Quad IO Fast Read,
> - reword commit message and subject.]
> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
> ---
> arch/arm/boot/dts/at91-sama5d2_xplained.dts | 31 +++++++++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
>
> diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> index 518e2b095ccf..171bc82cfbbf 100644
> --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> @@ -108,6 +108,21 @@
> };
>
> apb {
> + qspi0: spi@f0020000 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_qspi0_default>;
> + /* status = "okay"; */ /* conflict with sdmmc1 */
> +
> + flash@0 {
> + compatible = "jedec,spi-nor";
> + reg = <0>;
> + spi-max-frequency = <80000000>;
> + spi-tx-bus-width = <4>;
> + spi-rx-bus-width = <4>;
> + m25p,fast-read;
> + };
I'm a bit lost. What's the point of defining this if the QSPI
controller is not enabled?
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] ARM: dts: at91: sama5d2 Xplained: add QSPI0 + SPI NOR memory nodes
2018-12-11 14:40 ` Boris Brezillon
@ 2018-12-11 14:48 ` Ludovic Desroches
2018-12-11 14:49 ` Tudor.Ambarus
1 sibling, 0 replies; 8+ messages in thread
From: Ludovic Desroches @ 2018-12-11 14:48 UTC (permalink / raw)
To: Boris Brezillon
Cc: Tudor.Ambarus, Nicolas.Ferre, alexandre.belloni, robh+dt,
mark.rutland, Cyrille.Pitchen, linux-arm-kernel, devicetree,
linux-kernel, linux-mtd, broonie, linux-spi
On Tue, Dec 11, 2018 at 03:40:33PM +0100, Boris Brezillon wrote:
> On Mon, 10 Dec 2018 17:15:29 +0000
> <Tudor.Ambarus@microchip.com> wrote:
>
> > From: Cyrille Pitchen <cyrille.pitchen@microchip.com>
> >
> > This patch configures the QSPI0 controller pin muxing and declares
> > a jedec,spi-nor memory.
> >
> > sama5d2 Xplained RevB and RevC use the Macronix MX25L25673G flash
> > memory which advertises a maximum frequency of 80MHz for Quad IO
> > Fast Read. Set the spi-max-frequency to 80MHz knowing that actually
> > the QSPI drver will set the SPI bus clock to 166MHz / 3 = 55.3MHz.
> >
> > Signed-off-by: Cyrille Pitchen <cyrille.pitchen@microchip.com>
> > [tudor.ambarus@microchip.com:
> > - drop partitions,
> > - add spi-rx/tx-bus-width
> > - change spi-max-frequency to match the 80MHz limit advertised by
> > MX25L25673G for Quad IO Fast Read,
> > - reword commit message and subject.]
> > Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
> > ---
> > arch/arm/boot/dts/at91-sama5d2_xplained.dts | 31 +++++++++++++++++++++++++++++
> > 1 file changed, 31 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> > index 518e2b095ccf..171bc82cfbbf 100644
> > --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> > +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> > @@ -108,6 +108,21 @@
> > };
> >
> > apb {
> > + qspi0: spi@f0020000 {
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_qspi0_default>;
> > + /* status = "okay"; */ /* conflict with sdmmc1 */
> > +
> > + flash@0 {
> > + compatible = "jedec,spi-nor";
> > + reg = <0>;
> > + spi-max-frequency = <80000000>;
> > + spi-tx-bus-width = <4>;
> > + spi-rx-bus-width = <4>;
> > + m25p,fast-read;
> > + };
>
> I'm a bit lost. What's the point of defining this if the QSPI
> controller is not enabled?
It's a way to avoid customer struggling with the device tree. If he
doesn't care about sdmmc1, he can easily enable the qpsi controller and
get access to the memory.
Regards
Ludovic
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] ARM: dts: at91: sama5d2 Xplained: add QSPI0 + SPI NOR memory nodes
2018-12-11 14:40 ` Boris Brezillon
2018-12-11 14:48 ` Ludovic Desroches
@ 2018-12-11 14:49 ` Tudor.Ambarus
1 sibling, 0 replies; 8+ messages in thread
From: Tudor.Ambarus @ 2018-12-11 14:49 UTC (permalink / raw)
To: boris.brezillon
Cc: Nicolas.Ferre, alexandre.belloni, Ludovic.Desroches, robh+dt,
mark.rutland, Cyrille.Pitchen, linux-arm-kernel, devicetree,
linux-kernel, linux-mtd, broonie, linux-spi
Hi, Boris,
On 12/11/2018 04:40 PM, Boris Brezillon wrote:
> On Mon, 10 Dec 2018 17:15:29 +0000
> <Tudor.Ambarus@microchip.com> wrote:
>
>> From: Cyrille Pitchen <cyrille.pitchen@microchip.com>
>>
>> This patch configures the QSPI0 controller pin muxing and declares
>> a jedec,spi-nor memory.
>>
>> sama5d2 Xplained RevB and RevC use the Macronix MX25L25673G flash
>> memory which advertises a maximum frequency of 80MHz for Quad IO
>> Fast Read. Set the spi-max-frequency to 80MHz knowing that actually
>> the QSPI drver will set the SPI bus clock to 166MHz / 3 = 55.3MHz.
s/drver/driver
>>
>> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@microchip.com>
>> [tudor.ambarus@microchip.com:
>> - drop partitions,
>> - add spi-rx/tx-bus-width
>> - change spi-max-frequency to match the 80MHz limit advertised by
>> MX25L25673G for Quad IO Fast Read,
>> - reword commit message and subject.]
>> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
>> ---
>> arch/arm/boot/dts/at91-sama5d2_xplained.dts | 31 +++++++++++++++++++++++++++++
>> 1 file changed, 31 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
>> index 518e2b095ccf..171bc82cfbbf 100644
>> --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
>> +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
>> @@ -108,6 +108,21 @@
>> };
>>
>> apb {
>> + qspi0: spi@f0020000 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_qspi0_default>;
>> + /* status = "okay"; */ /* conflict with sdmmc1 */
>> +
>> + flash@0 {
>> + compatible = "jedec,spi-nor";
>> + reg = <0>;
>> + spi-max-frequency = <80000000>;
>> + spi-tx-bus-width = <4>;
>> + spi-rx-bus-width = <4>;
>> + m25p,fast-read;
>> + };
>
> I'm a bit lost. What's the point of defining this if the QSPI
> controller is not enabled?
You can enable qspi if you disable sdmmc1. I thought of having all described
together and choose one or another depending on needs.
ta
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] ARM: dts: at91: sama5d2 Xplained: add QSPI0 + SPI NOR memory nodes
2018-12-11 14:35 ` Alexandre Belloni
@ 2018-12-11 14:50 ` Ludovic Desroches
0 siblings, 0 replies; 8+ messages in thread
From: Ludovic Desroches @ 2018-12-11 14:50 UTC (permalink / raw)
To: Alexandre Belloni
Cc: Tudor.Ambarus, Nicolas.Ferre, robh+dt, mark.rutland,
Cyrille.Pitchen, linux-arm-kernel, devicetree, linux-kernel,
boris.brezillon, linux-mtd, broonie, linux-spi
On Tue, Dec 11, 2018 at 03:35:45PM +0100, Alexandre Belloni wrote:
> On 11/12/2018 12:32:40+0000, Tudor.Ambarus@microchip.com wrote:
> > Hi, Alexandre,
> >
> > On 12/10/2018 11:35 PM, Alexandre Belloni wrote:
> > > Hi,
> > >
> > > On 10/12/2018 17:15:29+0000, Tudor.Ambarus@microchip.com wrote:
> > >> From: Cyrille Pitchen <cyrille.pitchen@microchip.com>
> > >>
> > >> This patch configures the QSPI0 controller pin muxing and declares
> > >> a jedec,spi-nor memory.
> > >>
> > >> sama5d2 Xplained RevB and RevC use the Macronix MX25L25673G flash
> > >> memory which advertises a maximum frequency of 80MHz for Quad IO
> > >> Fast Read. Set the spi-max-frequency to 80MHz knowing that actually
> > >> the QSPI drver will set the SPI bus clock to 166MHz / 3 = 55.3MHz.
> > >>
> > >> Signed-off-by: Cyrille Pitchen <cyrille.pitchen@microchip.com>
> > >> [tudor.ambarus@microchip.com:
> > >> - drop partitions,
> > >> - add spi-rx/tx-bus-width
> > >> - change spi-max-frequency to match the 80MHz limit advertised by
> > >> MX25L25673G for Quad IO Fast Read,
> > >> - reword commit message and subject.]
> > >> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
> > >> ---
> > >> arch/arm/boot/dts/at91-sama5d2_xplained.dts | 31 +++++++++++++++++++++++++++++
> > >> 1 file changed, 31 insertions(+)
> > >>
> > >> diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> > >> index 518e2b095ccf..171bc82cfbbf 100644
> > >> --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> > >> +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts
> > >> @@ -108,6 +108,21 @@
> > >> };
> > >>
> > >> apb {
> > >> + qspi0: spi@f0020000 {
> > >> + pinctrl-names = "default";
> > >> + pinctrl-0 = <&pinctrl_qspi0_default>;
> > >> + /* status = "okay"; */ /* conflict with sdmmc1 */
> > >
> > > Isn't that conflicting then because I think the default is okay.
> > qspi0 is disabled in sama5d2.dtsi.
> >
>
> Ok, then maybe that comment is not necessary at all.
Usually we do it the other way around:
status = "disabled"; /* conflict with ... */
Regards
Ludovic
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2018-12-11 14:50 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-12-10 17:15 [PATCH] ARM: dts: at91: sama5d2 Xplained: add QSPI0 + SPI NOR memory nodes Tudor.Ambarus
2018-12-10 21:35 ` Alexandre Belloni
2018-12-11 12:32 ` Tudor.Ambarus
2018-12-11 14:35 ` Alexandre Belloni
2018-12-11 14:50 ` Ludovic Desroches
2018-12-11 14:40 ` Boris Brezillon
2018-12-11 14:48 ` Ludovic Desroches
2018-12-11 14:49 ` Tudor.Ambarus
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