* [PATCH] spi/fsl-espi: fix support for all available clock rates
@ 2016-08-02 17:38 Paulo Zaneti
[not found] ` <1470159485-7926-1-git-send-email-paulo.zaneti-rCUF4CxDseZknzVnJbg3IA@public.gmane.org>
0 siblings, 1 reply; 2+ messages in thread
From: Paulo Zaneti @ 2016-08-02 17:38 UTC (permalink / raw)
To: linux-spi-u79uwXL29TY76Z2rM5mHXA; +Cc: Paulo Zaneti
According to NXP ESPI datasheet, the SPI clock rate is:
spi_clk = System_Clock / ( 2 * DIV16 * ( 1 + PM ) )
Where System_Clock is the platform clock divided by 2,
DIV16 may be 1 or 16, and PM is a 4 bits integer (0 to 15).
Isolating PM on the expression, we get:
PM = (System_Clock / ( 2 * DIV16 * spi_clk ) ) - 1
Where System_Clock = mpc8xxx_spi->spibrg / 2, spi_clk = hz,
and DIV16 = 1 or DIV16 = 16. So,
PM = (mpc8xxx_spi->spibrg / ( 4 * hz) ) - 1
or
PM = (mpc8xxx_spi->spibrg / ( 16 * 4 * hz) ) - 1
Current spi-fsl-espi driver can't configure the HW for all
supported clock rates. It filters out clock rates for PM = 0
and PM = 1.
This patch allows all range of supported clock rates to be
configured on the ESPI controller.
Signed-off-by: Paulo Zaneti <paulo.zaneti-rCUF4CxDseZknzVnJbg3IA@public.gmane.org>
---
drivers/spi/spi-fsl-espi.c | 22 +++++++++-------------
1 file changed, 9 insertions(+), 13 deletions(-)
diff --git a/drivers/spi/spi-fsl-espi.c b/drivers/spi/spi-fsl-espi.c
index 8d85a3c..947ded2 100644
--- a/drivers/spi/spi-fsl-espi.c
+++ b/drivers/spi/spi-fsl-espi.c
@@ -136,7 +136,7 @@ static int fsl_espi_setup_transfer(struct spi_device *spi,
{
struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
int bits_per_word = 0;
- u8 pm;
+ u32 pm;
u32 hz = 0;
struct spi_mpc8xxx_cs *cs = spi->controller_state;
@@ -176,22 +176,18 @@ static int fsl_espi_setup_transfer(struct spi_device *spi,
cs->hw_mode |= CSMODE_LEN(bits_per_word);
- if ((mpc8xxx_spi->spibrg / hz) > 64) {
+ pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4) - 1;
+
+ if (pm > 15) {
cs->hw_mode |= CSMODE_DIV16;
- pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4);
+ pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4) - 1;
- WARN_ONCE(pm > 33, "%s: Requested speed is too low: %d Hz. "
+ WARN_ONCE(pm > 15, "%s: Requested speed is too low: %d Hz. "
"Will use %d Hz instead.\n", dev_name(&spi->dev),
- hz, mpc8xxx_spi->spibrg / (4 * 16 * (32 + 1)));
- if (pm > 33)
- pm = 33;
- } else {
- pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4);
+ hz, mpc8xxx_spi->spibrg / (4 * 16 * (15 + 1)));
+ if (pm > 15)
+ pm = 15;
}
- if (pm)
- pm--;
- if (pm < 2)
- pm = 2;
cs->hw_mode |= CSMODE_PM(pm);
--
1.9.1
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* Re: [PATCH] spi/fsl-espi: fix support for all available clock rates
[not found] ` <1470159485-7926-1-git-send-email-paulo.zaneti-rCUF4CxDseZknzVnJbg3IA@public.gmane.org>
@ 2016-08-15 19:59 ` Heiner Kallweit
0 siblings, 0 replies; 2+ messages in thread
From: Heiner Kallweit @ 2016-08-15 19:59 UTC (permalink / raw)
To: Paulo Zaneti, Mark Brown; +Cc: linux-spi-u79uwXL29TY76Z2rM5mHXA
Am 02.08.2016 um 19:38 schrieb Paulo Zaneti:
> According to NXP ESPI datasheet, the SPI clock rate is:
>
> spi_clk = System_Clock / ( 2 * DIV16 * ( 1 + PM ) )
>
> Where System_Clock is the platform clock divided by 2,
> DIV16 may be 1 or 16, and PM is a 4 bits integer (0 to 15).
>
> Isolating PM on the expression, we get:
>
> PM = (System_Clock / ( 2 * DIV16 * spi_clk ) ) - 1
>
> Where System_Clock = mpc8xxx_spi->spibrg / 2, spi_clk = hz,
> and DIV16 = 1 or DIV16 = 16. So,
>
> PM = (mpc8xxx_spi->spibrg / ( 4 * hz) ) - 1
> or
> PM = (mpc8xxx_spi->spibrg / ( 16 * 4 * hz) ) - 1
>
> Current spi-fsl-espi driver can't configure the HW for all
> supported clock rates. It filters out clock rates for PM = 0
> and PM = 1.
>
> This patch allows all range of supported clock rates to be
> configured on the ESPI controller.
>
> Signed-off-by: Paulo Zaneti <paulo.zaneti-rCUF4CxDseZknzVnJbg3IA@public.gmane.org>
> ---
> drivers/spi/spi-fsl-espi.c | 22 +++++++++-------------
> 1 file changed, 9 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/spi/spi-fsl-espi.c b/drivers/spi/spi-fsl-espi.c
> index 8d85a3c..947ded2 100644
> --- a/drivers/spi/spi-fsl-espi.c
> +++ b/drivers/spi/spi-fsl-espi.c
> @@ -136,7 +136,7 @@ static int fsl_espi_setup_transfer(struct spi_device *spi,
> {
> struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
> int bits_per_word = 0;
> - u8 pm;
> + u32 pm;
> u32 hz = 0;
> struct spi_mpc8xxx_cs *cs = spi->controller_state;
>
> @@ -176,22 +176,18 @@ static int fsl_espi_setup_transfer(struct spi_device *spi,
>
> cs->hw_mode |= CSMODE_LEN(bits_per_word);
>
> - if ((mpc8xxx_spi->spibrg / hz) > 64) {
> + pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4) - 1;
> +
> + if (pm > 15) {
> cs->hw_mode |= CSMODE_DIV16;
> - pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4);
> + pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4) - 1;
>
> - WARN_ONCE(pm > 33, "%s: Requested speed is too low: %d Hz. "
> + WARN_ONCE(pm > 15, "%s: Requested speed is too low: %d Hz. "
> "Will use %d Hz instead.\n", dev_name(&spi->dev),
> - hz, mpc8xxx_spi->spibrg / (4 * 16 * (32 + 1)));
> - if (pm > 33)
> - pm = 33;
> - } else {
> - pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4);
> + hz, mpc8xxx_spi->spibrg / (4 * 16 * (15 + 1)));
> + if (pm > 15)
> + pm = 15;
> }
> - if (pm)
> - pm--;
> - if (pm < 2)
> - pm = 2;
>
> cs->hw_mode |= CSMODE_PM(pm);
>
>
You missed to address your patch to Mark as SPI maintainer.
The patch looks fine to me based on the chip spec and works ok on a P1014 FSL SoC.
Rgds, Heiner
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2016-08-02 17:38 [PATCH] spi/fsl-espi: fix support for all available clock rates Paulo Zaneti
[not found] ` <1470159485-7926-1-git-send-email-paulo.zaneti-rCUF4CxDseZknzVnJbg3IA@public.gmane.org>
2016-08-15 19:59 ` Heiner Kallweit
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