* [PATCH v3 0/2] spi: Add Renesas R-Car Gen3 RPC SPI driver
@ 2018-12-07 11:13 Mason Yang
2018-12-07 11:13 ` [PATCH v3 1/2] spi: Add Renesas R-Car Gen3 RPC SPI controller driver Mason Yang
` (2 more replies)
0 siblings, 3 replies; 15+ messages in thread
From: Mason Yang @ 2018-12-07 11:13 UTC (permalink / raw)
To: broonie, marek.vasut, linux-kernel, linux-spi, boris.brezillon,
linux-renesas-soc, Geert Uytterhoeven
Cc: juliensu, Simon Horman, zhengxunli, Mason Yang
Hi Mark,
This Renesas R-Car Gen3 RPC SPI driver is based on Boris's new
spi-mem direct mapping read/write mode [1][2].
v3 patch is according to Marek and Geert's comments including:
1) soc_device_mach() to set up RPC_PHYCNT_STRTIM.
2) get_unaligned()
3) rpc-mode for rpi-spi-flash or rpc-hyperflash.
4) coding style and so on.
v2 patch including:
1) remove RPC clock enable/dis-able control,
2) patch run time PM,
3) add RPC module software reset,
4) add regmap,
5) other coding style and so on.
thanks for your review.
best regards,
Mason
[1] https://patchwork.kernel.org/patch/10670753
[2] https://patchwork.kernel.org/patch/10670747
Mason Yang (2):
spi: Add Renesas R-Car Gen3 RPC SPI controller driver
dt-binding: spi: Document Renesas R-Car Gen3 RPC controller bindings
.../devicetree/bindings/spi/spi-renesas-rpc.txt | 38 +
drivers/spi/Kconfig | 6 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-renesas-rpc.c | 776 +++++++++++++++++++++
4 files changed, 821 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/spi-renesas-rpc.txt
create mode 100644 drivers/spi/spi-renesas-rpc.c
--
1.9.1
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH v3 1/2] spi: Add Renesas R-Car Gen3 RPC SPI controller driver 2018-12-07 11:13 [PATCH v3 0/2] spi: Add Renesas R-Car Gen3 RPC SPI driver Mason Yang @ 2018-12-07 11:13 ` Mason Yang 2018-12-08 16:14 ` kbuild test robot ` (2 more replies) 2018-12-07 11:13 ` [PATCH v3 2/2] dt-binding: spi: Document Renesas R-Car Gen3 RPC controller bindings Mason Yang 2018-12-09 15:37 ` [PATCH v3 0/2] spi: Add Renesas R-Car Gen3 RPC SPI driver Sergei Shtylyov 2 siblings, 3 replies; 15+ messages in thread From: Mason Yang @ 2018-12-07 11:13 UTC (permalink / raw) To: broonie, marek.vasut, linux-kernel, linux-spi, boris.brezillon, linux-renesas-soc, Geert Uytterhoeven Cc: juliensu, Simon Horman, zhengxunli, Mason Yang Add a driver for Renesas R-Car Gen3 RPC SPI controller. Signed-off-by: Mason Yang <masonccyang@mxic.com.tw> --- drivers/spi/Kconfig | 6 + drivers/spi/Makefile | 1 + drivers/spi/spi-renesas-rpc.c | 776 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 783 insertions(+) create mode 100644 drivers/spi/spi-renesas-rpc.c diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig index 7d3a5c9..54b40f8 100644 --- a/drivers/spi/Kconfig +++ b/drivers/spi/Kconfig @@ -528,6 +528,12 @@ config SPI_RSPI help SPI driver for Renesas RSPI and QSPI blocks. +config SPI_RENESAS_RPC + tristate "Renesas R-Car Gen3 RPC SPI controller" + depends on ARCH_RENESAS || COMPILE_TEST + help + SPI driver for Renesas R-Car Gen3 RPC. + config SPI_QCOM_QSPI tristate "QTI QSPI controller" depends on ARCH_QCOM diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 3575205..5d5c523 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -81,6 +81,7 @@ obj-$(CONFIG_SPI_QUP) += spi-qup.o obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o obj-$(CONFIG_SPI_RSPI) += spi-rspi.o +obj-$(CONFIG_SPI_RENESAS_RPC) += spi-renesas-rpc.o obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o spi-s3c24xx-hw-y := spi-s3c24xx.o spi-s3c24xx-hw-$(CONFIG_SPI_S3C24XX_FIQ) += spi-s3c24xx-fiq.o diff --git a/drivers/spi/spi-renesas-rpc.c b/drivers/spi/spi-renesas-rpc.c new file mode 100644 index 0000000..cec5669 --- /dev/null +++ b/drivers/spi/spi-renesas-rpc.c @@ -0,0 +1,776 @@ +// SPDX-License-Identifier: GPL-2.0 +// +// Copyright (C) 2018 ~ 2019 Renesas Solutions Corp. +// Copyright (C) 2018 Macronix International Co., Ltd. +// +// R-Car Gen3 RPC SPI/QSPI/Octa driver +// +// Authors: +// Mason Yang <masonccyang@mxic.com.tw> +// + +#include <linux/clk.h> +#include <linux/io.h> +#include <linux/iopoll.h> +#include <linux/module.h> +#include <linux/platform_device.h> +#include <linux/pm_runtime.h> +#include <linux/of.h> +#include <linux/regmap.h> +#include <linux/reset.h> +#include <linux/spi/spi.h> +#include <linux/spi/spi-mem.h> +#include <linux/sys_soc.h> + +#include <asm/unaligned.h> + +#define RPC_CMNCR 0x0000 /* R/W */ +#define RPC_CMNCR_MD BIT(31) +#define RPC_CMNCR_SFDE BIT(24) +#define RPC_CMNCR_MOIIO3(val) (((val) & 0x3) << 22) +#define RPC_CMNCR_MOIIO2(val) (((val) & 0x3) << 20) +#define RPC_CMNCR_MOIIO1(val) (((val) & 0x3) << 18) +#define RPC_CMNCR_MOIIO0(val) (((val) & 0x3) << 16) +#define RPC_CMNCR_MOIIO_HIZ (RPC_CMNCR_MOIIO0(3) | RPC_CMNCR_MOIIO1(3) | \ + RPC_CMNCR_MOIIO2(3) | RPC_CMNCR_MOIIO3(3)) +#define RPC_CMNCR_IO3FV(val) (((val) & 0x3) << 14) +#define RPC_CMNCR_IO2FV(val) (((val) & 0x3) << 12) +#define RPC_CMNCR_IO0FV(val) (((val) & 0x3) << 8) +#define RPC_CMNCR_IOFV_HIZ (RPC_CMNCR_IO0FV(3) | RPC_CMNCR_IO2FV(3) | \ + RPC_CMNCR_IO3FV(3)) +#define RPC_CMNCR_CPHAT BIT(6) +#define RPC_CMNCR_CPHAR BIT(5) +#define RPC_CMNCR_SSLP BIT(4) +#define RPC_CMNCR_CPOL BIT(3) +#define RPC_CMNCR_BSZ(val) (((val) & 0x3) << 0) + +#define RPC_SSLDR 0x0004 /* R/W */ +#define RPC_SSLDR_SPNDL(d) (((d) & 0x7) << 16) +#define RPC_SSLDR_SLNDL(d) (((d) & 0x7) << 8) +#define RPC_SSLDR_SCKDL(d) (((d) & 0x7) << 0) + +#define RPC_DRCR 0x000C /* R/W */ +#define RPC_DRCR_SSLN BIT(24) +#define RPC_DRCR_RBURST(v) (((v) & 0x1F) << 16) +#define RPC_DRCR_RCF BIT(9) +#define RPC_DRCR_RBE BIT(8) +#define RPC_DRCR_SSLE BIT(0) + +#define RPC_DRCMR 0x0010 /* R/W */ +#define RPC_DRCMR_CMD(c) (((c) & 0xFF) << 16) +#define RPC_DRCMR_OCMD(c) (((c) & 0xFF) << 0) + +#define RPC_DREAR 0x0014 /* R/W */ +#define RPC_DREAR_EAC BIT(0) + +#define RPC_DROPR 0x0018 /* R/W */ + +#define RPC_DRENR 0x001C /* R/W */ +#define RPC_DRENR_CDB(o) (u32)((((o) & 0x3) << 30)) +#define RPC_DRENR_OCDB(o) (((o) & 0x3) << 28) +#define RPC_DRENR_ADB(o) (((o) & 0x3) << 24) +#define RPC_DRENR_OPDB(o) (((o) & 0x3) << 20) +#define RPC_DRENR_SPIDB(o) (((o) & 0x3) << 16) +#define RPC_DRENR_DME BIT(15) +#define RPC_DRENR_CDE BIT(14) +#define RPC_DRENR_OCDE BIT(12) +#define RPC_DRENR_ADE(v) (((v) & 0xF) << 8) +#define RPC_DRENR_OPDE(v) (((v) & 0xF) << 4) + +#define RPC_SMCR 0x0020 /* R/W */ +#define RPC_SMCR_SSLKP BIT(8) +#define RPC_SMCR_SPIRE BIT(2) +#define RPC_SMCR_SPIWE BIT(1) +#define RPC_SMCR_SPIE BIT(0) + +#define RPC_SMCMR 0x0024 /* R/W */ +#define RPC_SMCMR_CMD(c) (((c) & 0xFF) << 16) +#define RPC_SMCMR_OCMD(c) (((c) & 0xFF) << 0) + +#define RPC_SMADR 0x0028 /* R/W */ +#define RPC_SMOPR 0x002C /* R/W */ +#define RPC_SMOPR_OPD0(o) (((o) & 0xFF) << 0) +#define RPC_SMOPR_OPD1(o) (((o) & 0xFF) << 8) +#define RPC_SMOPR_OPD2(o) (((o) & 0xFF) << 16) +#define RPC_SMOPR_OPD3(o) (((o) & 0xFF) << 24) + +#define RPC_SMENR 0x0030 /* R/W */ +#define RPC_SMENR_CDB(o) (((o) & 0x2) << 30) +#define RPC_SMENR_OCDB(o) (((o) & 0x2) << 28) +#define RPC_SMENR_ADB(o) (((o) & 0x2) << 24) +#define RPC_SMENR_OPDB(o) (((o) & 0x2) << 20) +#define RPC_SMENR_SPIDB(o) (((o) & 0x2) << 16) +#define RPC_SMENR_DME BIT(15) +#define RPC_SMENR_CDE BIT(14) +#define RPC_SMENR_OCDE BIT(12) +#define RPC_SMENR_ADE(v) (((v) & 0xF) << 8) +#define RPC_SMENR_OPDE(v) (((v) & 0xF) << 4) +#define RPC_SMENR_SPIDE(v) (((v) & 0xF) << 0) + +#define RPC_SMRDR0 0x0038 /* R */ +#define RPC_SMRDR1 0x003C /* R */ +#define RPC_SMWDR0 0x0040 /* W */ +#define RPC_SMWDR1 0x0044 /* W */ + +#define RPC_CMNSR 0x0048 /* R */ +#define RPC_CMNSR_SSLF BIT(1) +#define RPC_CMNSR_TEND BIT(0) + +#define RPC_DRDMCR 0x0058 /* R/W */ +#define RPC_DRDRENR 0x005C /* R/W */ + +#define RPC_SMDMCR 0x0060 /* R/W */ +#define RPC_SMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0) + +#define RPC_SMDRENR 0x0064 /* R/W */ +#define RPC_SMDRENR_HYPE (0x5 << 12) +#define RPC_SMDRENR_ADDRE BIT(8) +#define RPC_SMDRENR_OPDRE BIT(4) +#define RPC_SMDRENR_SPIDRE BIT(0) + +#define RPC_PHYCNT 0x007C /* R/W */ +#define RPC_PHYCNT_CAL BIT(31) +#define PRC_PHYCNT_OCTA_AA BIT(22) +#define PRC_PHYCNT_OCTA_SA BIT(23) +#define PRC_PHYCNT_EXDS BIT(21) +#define RPC_PHYCNT_OCT BIT(20) +#define RPC_PHYCNT_STRTIM(v) (((v) & 0x7) << 15) +#define RPC_PHYCNT_WBUF2 BIT(4) +#define RPC_PHYCNT_WBUF BIT(2) +#define RPC_PHYCNT_MEM(v) (((v) & 0x3) << 0) + +#define RPC_PHYOFFSET1 0x0080 /* R/W */ +#define RPC_PHYOFFSET2 0x0084 /* R/W */ + +#define RPC_WBUF 0x8000 /* Write Buffer */ +#define RPC_WBUF_SIZE 256 /* Write Buffer size */ + +struct rpc_spi { + struct clk *clk_rpc; + void __iomem *base; + void __iomem *dirmap; + struct regmap *regmap; + u32 cur_speed_hz; + u32 cmd; + u32 addr; + u32 dummy; + u32 smcr; + u32 smenr; + u32 xferlen; + u32 totalxferlen; + enum spi_mem_data_dir xfer_dir; + struct reset_control *rstc; +}; + +static int rpc_spi_set_freq(struct rpc_spi *rpc, unsigned long freq) +{ + int ret; + + if (rpc->cur_speed_hz == freq) + return 0; + + ret = clk_set_rate(rpc->clk_rpc, freq); + if (ret) + return ret; + + rpc->cur_speed_hz = freq; + return ret; +} + +static const struct soc_device_attribute r8a7795es1[] __initconst = { + { .soc_id = "r8a7795", .revision = "ES1.*" }, + { /* sentinel */ } +}; + +static void rpc_spi_hw_init(struct rpc_spi *rpc) +{ + int strtim; + /* + * NOTE: The 0x260 are undocumented bits, but they must be set. + * RPC_PHYCNT_STRTIM is strobe timing adjustment bit, + * 0x0 : the delay is biggest, + * 0x1 : the delay is 2nd biggest, + * On H3 ES1.x, the value should be 0, while on others, + * the value should be 6. + */ + if (soc_device_match(r8a7795es1)) + strtim = 0; + else + strtim = 6; + + regmap_write(rpc->regmap, RPC_PHYCNT, RPC_PHYCNT_CAL | + RPC_PHYCNT_STRTIM(strtim) | 0x260); + + /* + * NOTE: The 0x31511144 and 0x431 are undocumented bits, + * but they must be set for RPC_PHYOFFSET1 & RPC_PHYOFFSET2. + */ + regmap_write(rpc->regmap, RPC_PHYOFFSET1, 0x31511144); + regmap_write(rpc->regmap, RPC_PHYOFFSET2, 0x431); + + regmap_write(rpc->regmap, RPC_SSLDR, RPC_SSLDR_SPNDL(7) | + RPC_SSLDR_SLNDL(7) | RPC_SSLDR_SCKDL(7)); +} + +static int rpc_spi_do_reset(struct rpc_spi *rpc) +{ + int ret; + + ret = reset_control_reset(rpc->rstc); + if (ret) + return ret; + + return 0; +} + +static int wait_msg_xfer_end(struct rpc_spi *rpc) +{ + u32 sts; + + return regmap_read_poll_timeout(rpc->regmap, RPC_CMNSR, sts, + sts & RPC_CMNSR_TEND, 0, USEC_PER_SEC); +} + +static u8 rpc_bits_set(u32 nbytes) +{ + nbytes = clamp(nbytes, 1U, 4U); + + return GENMASK(3, 4 - nbytes); +} + +static int rpc_spi_io_xfer(struct rpc_spi *rpc, + const void *tx_buf, void *rx_buf) +{ + u32 smenr, smcr, data, pos = 0; + int ret = 0; + + regmap_write(rpc->regmap, RPC_CMNCR, RPC_CMNCR_MD | RPC_CMNCR_SFDE | + RPC_CMNCR_MOIIO_HIZ | RPC_CMNCR_IOFV_HIZ | + RPC_CMNCR_BSZ(0)); + regmap_write(rpc->regmap, RPC_SMDRENR, 0x0); + regmap_write(rpc->regmap, RPC_SMCMR, rpc->cmd); + regmap_write(rpc->regmap, RPC_SMDMCR, rpc->dummy); + regmap_write(rpc->regmap, RPC_SMADR, rpc->addr); + + if (tx_buf) { + smenr = rpc->smenr; + + while (pos < rpc->xferlen) { + u32 nbytes = rpc->xferlen - pos; + + regmap_write(rpc->regmap, RPC_SMWDR0, + get_unaligned((u32 *)(tx_buf + pos))); + + if (nbytes > 4) { + nbytes = 4; + smcr = rpc->smcr | + RPC_SMCR_SPIE | RPC_SMCR_SSLKP; + } else { + smcr = rpc->smcr | RPC_SMCR_SPIE; + } + + regmap_write(rpc->regmap, RPC_SMENR, smenr); + regmap_write(rpc->regmap, RPC_SMCR, smcr); + ret = wait_msg_xfer_end(rpc); + if (ret) + goto out; + + pos += nbytes; + smenr = rpc->smenr & ~RPC_SMENR_CDE & + ~RPC_SMENR_ADE(0xf); + } + } else if (rx_buf) { + while (pos < rpc->xferlen) { + u32 nbytes = rpc->xferlen - pos; + + if (nbytes > 4) + nbytes = 4; + + regmap_write(rpc->regmap, RPC_SMENR, rpc->smenr); + regmap_write(rpc->regmap, RPC_SMCR, + rpc->smcr | RPC_SMCR_SPIE); + ret = wait_msg_xfer_end(rpc); + if (ret) + goto out; + + regmap_read(rpc->regmap, RPC_SMRDR0, &data); + memcpy_fromio(rx_buf + pos, (void *)&data, nbytes); + pos += nbytes; + regmap_write(rpc->regmap, RPC_SMCMR, rpc->cmd); + regmap_write(rpc->regmap, RPC_SMDMCR, rpc->dummy); + regmap_write(rpc->regmap, RPC_SMADR, rpc->addr + pos); + } + } else { + regmap_write(rpc->regmap, RPC_SMENR, rpc->smenr); + regmap_write(rpc->regmap, RPC_SMCR, rpc->smcr | RPC_SMCR_SPIE); + ret = wait_msg_xfer_end(rpc); + if (ret) + goto out; + } + + return ret; +out: + return rpc_spi_do_reset(rpc); +} + +static void rpc_spi_mem_set_prep_op_cfg(struct spi_device *spi, + const struct spi_mem_op *op, + u64 *offs, size_t *len) +{ + struct rpc_spi *rpc = spi_master_get_devdata(spi->master); + + rpc->cmd = RPC_SMCMR_CMD(op->cmd.opcode); + rpc->smenr = RPC_SMENR_CDE | + RPC_SMENR_CDB(fls(op->cmd.buswidth >> 1)); + rpc->totalxferlen = 1; + rpc->xfer_dir = SPI_MEM_NO_DATA; + rpc->xferlen = 0; + rpc->addr = 0; + + if (op->addr.nbytes) { + rpc->smenr |= RPC_SMENR_ADB(fls(op->addr.buswidth >> 1)); + if (op->addr.nbytes == 4) + rpc->smenr |= RPC_SMENR_ADE(0xf); + else + rpc->smenr |= RPC_SMENR_ADE(0x7); + + if (offs && len) + rpc->addr = *offs; + else + rpc->addr = op->addr.val; + rpc->totalxferlen += op->addr.nbytes; + } + + if (op->dummy.nbytes) { + rpc->smenr |= RPC_SMENR_DME; + rpc->dummy = RPC_SMDMCR_DMCYC(op->dummy.nbytes); + rpc->totalxferlen += op->dummy.nbytes; + } + + if (op->data.nbytes || (offs && len)) { + if (op->data.dir == SPI_MEM_DATA_IN) { + rpc->smcr = RPC_SMCR_SPIRE; + rpc->xfer_dir = SPI_MEM_DATA_IN; + } else if (op->data.dir == SPI_MEM_DATA_OUT) { + rpc->smcr = RPC_SMCR_SPIWE; + rpc->xfer_dir = SPI_MEM_DATA_OUT; + } + + if (offs && len) { + rpc->smenr |= + RPC_SMENR_SPIDE(rpc_bits_set(*len)) | + RPC_SMENR_SPIDB(fls(op->data.buswidth >> 1)); + rpc->xferlen = *len; + rpc->totalxferlen += *len; + } else { + rpc->smenr |= + RPC_SMENR_SPIDE(rpc_bits_set(op->data.nbytes)) | + RPC_SMENR_SPIDB(fls(op->data.buswidth >> 1)); + rpc->xferlen = op->data.nbytes; + rpc->totalxferlen += op->data.nbytes; + } + } +} + +static bool rpc_spi_mem_supports_op(struct spi_mem *mem, + const struct spi_mem_op *op) +{ + if (op->data.buswidth > 4 || op->addr.buswidth > 4 || + op->dummy.buswidth > 4 || op->cmd.buswidth > 4 || + op->addr.nbytes > 4) + return false; + + return true; +} + +static ssize_t rpc_spi_mem_dirmap_read(struct spi_mem_dirmap_desc *desc, + u64 offs, size_t len, void *buf) +{ + struct rpc_spi *rpc = spi_master_get_devdata(desc->mem->spi->master); + int ret; + + if (WARN_ON(offs + desc->info.offset + len > U32_MAX)) + return -EINVAL; + + ret = rpc_spi_set_freq(rpc, desc->mem->spi->max_speed_hz); + if (ret) + return ret; + + rpc_spi_mem_set_prep_op_cfg(desc->mem->spi, + &desc->info.op_tmpl, &offs, &len); + + regmap_write(rpc->regmap, RPC_CMNCR, RPC_CMNCR_SFDE | + RPC_CMNCR_MOIIO_HIZ | RPC_CMNCR_IOFV_HIZ | + RPC_CMNCR_BSZ(0)); + regmap_write(rpc->regmap, RPC_DRCR, RPC_DRCR_RBURST(0x1f) | + RPC_DRCR_RBE); + regmap_write(rpc->regmap, RPC_DRCMR, rpc->cmd); + regmap_write(rpc->regmap, RPC_DREAR, RPC_DREAR_EAC); + regmap_write(rpc->regmap, RPC_DROPR, 0); + regmap_write(rpc->regmap, RPC_DRENR, rpc->smenr); + regmap_write(rpc->regmap, RPC_DRDMCR, rpc->dummy); + regmap_write(rpc->regmap, RPC_DRDRENR, 0); + + memcpy_fromio(buf, rpc->dirmap + desc->info.offset + offs, len); + + return len; +} + +static ssize_t rpc_spi_mem_dirmap_write(struct spi_mem_dirmap_desc *desc, + u64 offs, size_t len, const void *buf) +{ + struct rpc_spi *rpc = spi_master_get_devdata(desc->mem->spi->master); + int ret; + + if (WARN_ON(offs + desc->info.offset + len > U32_MAX)) + return -EINVAL; + + if (WARN_ON(len > RPC_WBUF_SIZE)) + return -EIO; + + ret = rpc_spi_set_freq(rpc, desc->mem->spi->max_speed_hz); + if (ret) + return ret; + + rpc_spi_mem_set_prep_op_cfg(desc->mem->spi, + &desc->info.op_tmpl, &offs, &len); + + regmap_write(rpc->regmap, RPC_CMNCR, RPC_CMNCR_MD | RPC_CMNCR_SFDE | + RPC_CMNCR_MOIIO_HIZ | RPC_CMNCR_IOFV_HIZ | + RPC_CMNCR_BSZ(0)); + regmap_write(rpc->regmap, RPC_SMDRENR, 0); + regmap_write(rpc->regmap, RPC_PHYCNT, RPC_PHYCNT_CAL | 0x260 | + RPC_PHYCNT_WBUF2 | RPC_PHYCNT_WBUF); + + memcpy_toio(rpc->base + RPC_WBUF, buf, len); + + regmap_write(rpc->regmap, RPC_SMCMR, rpc->cmd); + regmap_write(rpc->regmap, RPC_SMADR, offs); + regmap_write(rpc->regmap, RPC_SMENR, rpc->smenr); + regmap_write(rpc->regmap, RPC_SMCR, rpc->smcr | RPC_SMCR_SPIE); + ret = wait_msg_xfer_end(rpc); + if (ret) + goto out; + + regmap_write(rpc->regmap, RPC_DRCR, RPC_DRCR_RCF); + regmap_write(rpc->regmap, RPC_PHYCNT, RPC_PHYCNT_CAL | + RPC_PHYCNT_STRTIM(6) | 0x260); + + return len; +out: + return rpc_spi_do_reset(rpc); +} + +static int rpc_spi_mem_dirmap_create(struct spi_mem_dirmap_desc *desc) +{ + struct rpc_spi *rpc = spi_master_get_devdata(desc->mem->spi->master); + + if (desc->info.offset + desc->info.length > U32_MAX) + return -ENOTSUPP; + + if (!rpc_spi_mem_supports_op(desc->mem, &desc->info.op_tmpl)) + return -ENOTSUPP; + + if (!rpc->dirmap && + desc->info.op_tmpl.data.dir == SPI_MEM_DATA_IN) + return -ENOTSUPP; + + return 0; +} + +static int rpc_spi_mem_exec_op(struct spi_mem *mem, + const struct spi_mem_op *op) +{ + struct rpc_spi *rpc = spi_master_get_devdata(mem->spi->master); + int ret; + + ret = rpc_spi_set_freq(rpc, mem->spi->max_speed_hz); + if (ret) + return ret; + + rpc_spi_mem_set_prep_op_cfg(mem->spi, op, NULL, NULL); + + ret = rpc_spi_io_xfer(rpc, + op->data.dir == SPI_MEM_DATA_OUT ? + op->data.buf.out : NULL, + op->data.dir == SPI_MEM_DATA_IN ? + op->data.buf.in : NULL); + + return ret; +} + +static const struct spi_controller_mem_ops rpc_spi_mem_ops = { + .supports_op = rpc_spi_mem_supports_op, + .exec_op = rpc_spi_mem_exec_op, + .dirmap_create = rpc_spi_mem_dirmap_create, + .dirmap_read = rpc_spi_mem_dirmap_read, + .dirmap_write = rpc_spi_mem_dirmap_write, +}; + +static void rpc_spi_transfer_setup(struct rpc_spi *rpc, + struct spi_message *msg) +{ + struct spi_transfer *t, xfer[4] = { }; + u32 i, xfercnt, xferpos = 0; + + rpc->totalxferlen = 0; + rpc->xfer_dir = SPI_MEM_NO_DATA; + + list_for_each_entry(t, &msg->transfers, transfer_list) { + if (t->tx_buf) { + xfer[xferpos].tx_buf = t->tx_buf; + xfer[xferpos].tx_nbits = t->tx_nbits; + } + + if (t->rx_buf) { + xfer[xferpos].rx_buf = t->rx_buf; + xfer[xferpos].rx_nbits = t->rx_nbits; + } + + if (t->len) { + xfer[xferpos++].len = t->len; + rpc->totalxferlen += t->len; + } + + if (list_is_last(&t->transfer_list, &msg->transfers)) { + if (xferpos > 1 && t->rx_buf) { + rpc->xfer_dir = SPI_MEM_DATA_IN; + rpc->smcr = RPC_SMCR_SPIRE; + } else if (xferpos > 1 && t->tx_buf) { + rpc->xfer_dir = SPI_MEM_DATA_OUT; + rpc->smcr = RPC_SMCR_SPIWE; + } + } + } + + xfercnt = xferpos; + rpc->xferlen = xfer[--xferpos].len; + rpc->cmd = RPC_SMCMR_CMD(((u8 *)xfer[0].tx_buf)[0]); + rpc->smenr = RPC_SMENR_CDE | RPC_SMENR_CDB(fls(xfer[0].tx_nbits >> 1)); + rpc->addr = 0; + + if (xfercnt > 2 && xfer[1].len && xfer[1].tx_buf) { + rpc->smenr |= RPC_SMENR_ADB(fls(xfer[1].tx_nbits >> 1)); + for (i = 0; i < xfer[1].len; i++) + rpc->addr |= ((u8 *)xfer[1].tx_buf)[i] + << (8 * (xfer[1].len - i - 1)); + + if (xfer[1].len == 4) + rpc->smenr |= RPC_SMENR_ADE(0xf); + else + rpc->smenr |= RPC_SMENR_ADE(0x7); + } + + if (xfercnt > 3 && xfer[2].len && xfer[2].tx_buf) { + rpc->smenr |= RPC_SMENR_DME; + rpc->dummy = RPC_SMDMCR_DMCYC(xfer[2].len); + } + + for (i = xfercnt - 1; i < xfercnt && xfercnt > 1; i++) { + if (xfer[i].rx_buf) { + rpc->smenr |= + RPC_SMENR_SPIDE(rpc_bits_set(xfer[i].len)) | + RPC_SMENR_SPIDB(fls(xfer[i].rx_nbits >> 1)); + } else if (xfer[i].tx_buf) { + rpc->smenr |= + RPC_SMENR_SPIDE(rpc_bits_set(xfer[i].len)) | + RPC_SMENR_SPIDB(fls(xfer[i].tx_nbits >> 1)); + } + } +} + +static int rpc_spi_xfer_message(struct rpc_spi *rpc, struct spi_transfer *t) +{ + int ret; + + ret = rpc_spi_set_freq(rpc, t->speed_hz); + if (ret) + return ret; + + ret = rpc_spi_io_xfer(rpc, + rpc->xfer_dir == SPI_MEM_DATA_OUT ? + t->tx_buf : NULL, + rpc->xfer_dir == SPI_MEM_DATA_IN ? + t->rx_buf : NULL); + + return ret; +} + +static int rpc_spi_transfer_one_message(struct spi_master *master, + struct spi_message *msg) +{ + struct rpc_spi *rpc = spi_master_get_devdata(master); + struct spi_transfer *t; + int ret; + + rpc_spi_transfer_setup(rpc, msg); + + list_for_each_entry(t, &msg->transfers, transfer_list) { + if (!list_is_last(&t->transfer_list, &msg->transfers)) + continue; + ret = rpc_spi_xfer_message(rpc, t); + if (ret) + goto out; + } + + msg->status = 0; + msg->actual_length = rpc->totalxferlen; +out: + spi_finalize_current_message(master); + return 0; +} + +static const struct regmap_range rpc_spi_volatile_ranges[] = { + regmap_reg_range(RPC_SMRDR0, RPC_SMRDR0), + regmap_reg_range(RPC_SMWDR0, RPC_SMWDR0), + regmap_reg_range(RPC_CMNSR, RPC_CMNSR), +}; + +static const struct regmap_access_table rpc_spi_volatile_table = { + .yes_ranges = rpc_spi_volatile_ranges, + .n_yes_ranges = ARRAY_SIZE(rpc_spi_volatile_ranges), +}; + +static const struct regmap_config rpc_spi_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, + .fast_io = true, + .max_register = RPC_WBUF + RPC_WBUF_SIZE, + .volatile_table = &rpc_spi_volatile_table, +}; + +static int rpc_spi_probe(struct platform_device *pdev) +{ + struct spi_master *master; + struct resource *res; + struct rpc_spi *rpc; + const struct regmap_config *regmap_config; + const char *mode; + int ret; + + ret = of_property_read_string(pdev->dev.of_node, "rpc-mode", &mode); + if (ret < 0) + return ret; + + if (strcasecmp(mode, "rpc-spi-flash")) + return -ENODEV; + + master = spi_alloc_master(&pdev->dev, sizeof(*rpc)); + if (!master) + return -ENOMEM; + + platform_set_drvdata(pdev, master); + + rpc = spi_master_get_devdata(master); + + master->dev.of_node = pdev->dev.of_node; + + rpc->clk_rpc = devm_clk_get(&pdev->dev, "clk_rpc"); + if (IS_ERR(rpc->clk_rpc)) + return PTR_ERR(rpc->clk_rpc); + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rpc_regs"); + rpc->base = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(rpc->base)) + return PTR_ERR(rpc->base); + + regmap_config = &rpc_spi_regmap_config; + rpc->regmap = devm_regmap_init_mmio(&pdev->dev, rpc->base, + regmap_config); + if (IS_ERR(rpc->regmap)) { + dev_err(&pdev->dev, "failed to init regmap %ld for rpc-spi\n", + PTR_ERR(rpc->regmap)); + return PTR_ERR(rpc->regmap); + } + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dirmap"); + rpc->dirmap = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(rpc->dirmap)) + rpc->dirmap = NULL; + + rpc->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL); + if (IS_ERR(rpc->rstc)) + return PTR_ERR(rpc->rstc); + + pm_runtime_enable(&pdev->dev); + master->auto_runtime_pm = true; + + master->num_chipselect = 1; + master->mem_ops = &rpc_spi_mem_ops; + master->transfer_one_message = rpc_spi_transfer_one_message; + + master->bits_per_word_mask = SPI_BPW_MASK(8); + master->mode_bits = SPI_CPOL | SPI_CPHA | + SPI_RX_DUAL | SPI_TX_DUAL | + SPI_RX_QUAD | SPI_TX_QUAD; + + rpc_spi_hw_init(rpc); + + ret = spi_register_master(master); + if (ret) { + dev_err(&pdev->dev, "spi_register_master failed\n"); + goto err_put_master; + } + return 0; + +err_put_master: + spi_master_put(master); + pm_runtime_disable(&pdev->dev); + + return ret; +} + +static int rpc_spi_remove(struct platform_device *pdev) +{ + struct spi_master *master = platform_get_drvdata(pdev); + + pm_runtime_disable(&pdev->dev); + spi_unregister_master(master); + + return 0; +} + +static const struct of_device_id rpc_spi_of_ids[] = { + { .compatible = "renesas,r8a77995-rpc", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, rpc_spi_of_ids); + +#ifdef CONFIG_PM_SLEEP +static int rpc_spi_suspend(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct spi_master *master = platform_get_drvdata(pdev); + + return spi_master_suspend(master); +} + +static int rpc_spi_resume(struct device *dev) +{ + struct platform_device *pdev = to_platform_device(dev); + struct spi_master *master = platform_get_drvdata(pdev); + + return spi_master_resume(master); +} + +static SIMPLE_DEV_PM_OPS(rpc_spi_pm_ops, rpc_spi_suspend, rpc_spi_resume); +#define DEV_PM_OPS (&rpc_spi_pm_ops) +#else +#define DEV_PM_OPS NULL +#endif + +static struct platform_driver rpc_spi_driver = { + .probe = rpc_spi_probe, + .remove = rpc_spi_remove, + .driver = { + .name = "rpc-spi", + .of_match_table = rpc_spi_of_ids, + .pm = DEV_PM_OPS, + }, +}; +module_platform_driver(rpc_spi_driver); + +MODULE_AUTHOR("Mason Yang <masonccyang@mxic.com.tw>"); +MODULE_DESCRIPTION("Renesas R-Car Gen3 RPC SPI controller driver"); +MODULE_LICENSE("GPL v2"); -- 1.9.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v3 1/2] spi: Add Renesas R-Car Gen3 RPC SPI controller driver 2018-12-07 11:13 ` [PATCH v3 1/2] spi: Add Renesas R-Car Gen3 RPC SPI controller driver Mason Yang @ 2018-12-08 16:14 ` kbuild test robot 2018-12-11 19:45 ` Sergei Shtylyov 2018-12-13 19:48 ` Sergei Shtylyov 2 siblings, 0 replies; 15+ messages in thread From: kbuild test robot @ 2018-12-08 16:14 UTC (permalink / raw) To: Mason Yang Cc: kbuild-all, broonie, marek.vasut, linux-kernel, linux-spi, boris.brezillon, linux-renesas-soc, Geert Uytterhoeven, juliensu, Simon Horman, zhengxunli, Mason Yang [-- Attachment #1: Type: text/plain, Size: 1201 bytes --] Hi Mason, Thank you for the patch! Perhaps something to improve: [auto build test WARNING on spi/for-next] [also build test WARNING on next-20181207] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] url: https://github.com/0day-ci/linux/commits/Mason-Yang/spi-Add-Renesas-R-Car-Gen3-RPC-SPI-controller-driver/20181208-081244 base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next config: i386-allmodconfig (attached as .config) compiler: gcc-7 (Debian 7.3.0-1) 7.3.0 reproduce: # save the attached .config to linux build tree make ARCH=i386 All warnings (new ones prefixed by >>): >> WARNING: drivers/spi/spi-renesas-rpc.o(.text+0xabd): Section mismatch in reference from the function rpc_spi_probe() to the variable .init.rodata:r8a7795es1 The function rpc_spi_probe() references the variable __initconst r8a7795es1. This is often because rpc_spi_probe lacks a __initconst annotation or the annotation of r8a7795es1 is wrong. --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation [-- Attachment #2: .config.gz --] [-- Type: application/gzip, Size: 66067 bytes --] ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 1/2] spi: Add Renesas R-Car Gen3 RPC SPI controller driver 2018-12-07 11:13 ` [PATCH v3 1/2] spi: Add Renesas R-Car Gen3 RPC SPI controller driver Mason Yang 2018-12-08 16:14 ` kbuild test robot @ 2018-12-11 19:45 ` Sergei Shtylyov [not found] ` <OFC335F545.7543A0F2-ON4825836A.0007E65A-4825836A.0008428D@mxic.com.tw> 2018-12-13 19:48 ` Sergei Shtylyov 2 siblings, 1 reply; 15+ messages in thread From: Sergei Shtylyov @ 2018-12-11 19:45 UTC (permalink / raw) To: Mason Yang, broonie, marek.vasut, linux-kernel, linux-spi, boris.brezillon, linux-renesas-soc, Geert Uytterhoeven Cc: juliensu, Simon Horman, zhengxunli On 12/07/2018 02:13 PM, Mason Yang wrote: > Add a driver for Renesas R-Car Gen3 RPC SPI controller. > > Signed-off-by: Mason Yang <masonccyang@mxic.com.tw> [...] > diff --git a/drivers/spi/spi-renesas-rpc.c b/drivers/spi/spi-renesas-rpc.c > new file mode 100644 > index 0000000..cec5669 > --- /dev/null > +++ b/drivers/spi/spi-renesas-rpc.c > @@ -0,0 +1,776 @@ [...] > +static const struct soc_device_attribute r8a7795es1[] __initconst = { This __initconst shouldn't be there, it causes a build warning. > + { .soc_id = "r8a7795", .revision = "ES1.*" }, Wait, the driver doesn't really probe on R8A7795 yet! > + { /* sentinel */ } > +}; > + > +static void rpc_spi_hw_init(struct rpc_spi *rpc) > +{ > + int strtim; > + /* > + * NOTE: The 0x260 are undocumented bits, but they must be set. > + * RPC_PHYCNT_STRTIM is strobe timing adjustment bit, > + * 0x0 : the delay is biggest, > + * 0x1 : the delay is 2nd biggest, > + * On H3 ES1.x, the value should be 0, while on others, > + * the value should be 6. > + */ > + if (soc_device_match(r8a7795es1)) > + strtim = 0; > + else > + strtim = 6; [...] > +static const struct of_device_id rpc_spi_of_ids[] = { > + { .compatible = "renesas,r8a77995-rpc", }, We only support R8A77995 now. > + { /* sentinel */ } > +}; > +MODULE_DEVICE_TABLE(of, rpc_spi_of_ids); [...] MBR, Sergei ^ permalink raw reply [flat|nested] 15+ messages in thread
[parent not found: <OFC335F545.7543A0F2-ON4825836A.0007E65A-4825836A.0008428D@mxic.com.tw>]
* Re: [PATCH v3 1/2] spi: Add Renesas R-Car Gen3 RPC SPI controller driver [not found] ` <OFC335F545.7543A0F2-ON4825836A.0007E65A-4825836A.0008428D@mxic.com.tw> @ 2018-12-21 10:22 ` Sergei Shtylyov 0 siblings, 0 replies; 15+ messages in thread From: Sergei Shtylyov @ 2018-12-21 10:22 UTC (permalink / raw) To: masonccyang Cc: boris.brezillon, broonie, Geert Uytterhoeven, Simon Horman, juliensu, linux-kernel, linux-renesas-soc, linux-spi, marek.vasut, zhengxunli Hello! On 12/21/2018 04:30 AM, masonccyang@mxic.com.tw wrote: >> > diff --git a/drivers/spi/spi-renesas-rpc.c b/drivers/spi/spi-renesas-rpc.c >> > new file mode 100644 >> > index 0000000..cec5669 >> > --- /dev/null >> > +++ b/drivers/spi/spi-renesas-rpc.c >> > @@ -0,0 +1,776 @@ >> [...] >> > +static const struct soc_device_attribute r8a7795es1[] __initconst = { >> >> This __initconst shouldn't be there, it causes a build warning. >> >> > + { .soc_id = "r8a7795", .revision = "ES1.*" }, >> >> Wait, the driver doesn't really probe on R8A7795 yet! > > yup, this is for RPC_PHYCNT_STRTIM setting by Marek's comments. > > On H3 ES1.x, the value should be 0, while on others, the value should be 6. > > ES1.x is r8a7795. Why care if we don't support H3 yet? Add this when the R8A77950 support is added. >> > + { /* sentinel */ } >> > +}; >> > + >> > +static void rpc_spi_hw_init(struct rpc_spi *rpc) >> > +{ >> > + int strtim; >> > + /* >> > + * NOTE: The 0x260 are undocumented bits, but they must be set. >> > + * RPC_PHYCNT_STRTIM is strobe timing adjustment bit, >> > + * 0x0 : the delay is biggest, >> > + * 0x1 : the delay is 2nd biggest, >> > + * On H3 ES1.x, the value should be 0, while on others, >> > + * the value should be 6. >> > + */ >> > + if (soc_device_match(r8a7795es1)) >> > + strtim = 0; >> > + else >> > + strtim = 6; >> [...] >> > +static const struct of_device_id rpc_spi_of_ids[] = { >> > + { .compatible = "renesas,r8a77995-rpc", }, >> >> We only support R8A77995 now. > > see above ! There's difference between R8A77995 and R8A77950, right? [...] > thanks & best regards, > Mason MBR, Sergei ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 1/2] spi: Add Renesas R-Car Gen3 RPC SPI controller driver 2018-12-07 11:13 ` [PATCH v3 1/2] spi: Add Renesas R-Car Gen3 RPC SPI controller driver Mason Yang 2018-12-08 16:14 ` kbuild test robot 2018-12-11 19:45 ` Sergei Shtylyov @ 2018-12-13 19:48 ` Sergei Shtylyov [not found] ` <OFAE786891.A102E46D-ON48258366.002779D7-48258366.002A5C36@mxic.com.tw> 2 siblings, 1 reply; 15+ messages in thread From: Sergei Shtylyov @ 2018-12-13 19:48 UTC (permalink / raw) To: Mason Yang, broonie, marek.vasut, linux-kernel, linux-spi, boris.brezillon, linux-renesas-soc, Geert Uytterhoeven Cc: juliensu, Simon Horman, zhengxunli On 12/07/2018 02:13 PM, Mason Yang wrote: > Add a driver for Renesas R-Car Gen3 RPC SPI controller. > > Signed-off-by: Mason Yang <masonccyang@mxic.com.tw> > --- > drivers/spi/Kconfig | 6 + > drivers/spi/Makefile | 1 + > drivers/spi/spi-renesas-rpc.c | 776 ++++++++++++++++++++++++++++++++++++++++++ > 3 files changed, 783 insertions(+) > create mode 100644 drivers/spi/spi-renesas-rpc.c > > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig > index 7d3a5c9..54b40f8 100644 > --- a/drivers/spi/Kconfig > +++ b/drivers/spi/Kconfig [...] > diff --git a/drivers/spi/spi-renesas-rpc.c b/drivers/spi/spi-renesas-rpc.c > new file mode 100644 > index 0000000..cec5669 > --- /dev/null > +++ b/drivers/spi/spi-renesas-rpc.c > @@ -0,0 +1,776 @@ [...] > +static int rpc_spi_do_reset(struct rpc_spi *rpc) > +{ > + int ret; > + > + ret = reset_control_reset(rpc->rstc); > + if (ret) > + return ret; > + > + return 0; This degrades to: { return reset_control_reset(rpc->rstc); } So, we hardly need this function now... [...] > +static int rpc_spi_io_xfer(struct rpc_spi *rpc, > + const void *tx_buf, void *rx_buf) > +{ > + u32 smenr, smcr, data, pos = 0; > + int ret = 0; > + > + regmap_write(rpc->regmap, RPC_CMNCR, RPC_CMNCR_MD | RPC_CMNCR_SFDE | > + RPC_CMNCR_MOIIO_HIZ | RPC_CMNCR_IOFV_HIZ | > + RPC_CMNCR_BSZ(0)); > + regmap_write(rpc->regmap, RPC_SMDRENR, 0x0); > + regmap_write(rpc->regmap, RPC_SMCMR, rpc->cmd); > + regmap_write(rpc->regmap, RPC_SMDMCR, rpc->dummy); > + regmap_write(rpc->regmap, RPC_SMADR, rpc->addr); > + > + if (tx_buf) { > + smenr = rpc->smenr; > + > + while (pos < rpc->xferlen) { > + u32 nbytes = rpc->xferlen - pos; > + > + regmap_write(rpc->regmap, RPC_SMWDR0, > + get_unaligned((u32 *)(tx_buf + pos))); > + > + if (nbytes > 4) { > + nbytes = 4; > + smcr = rpc->smcr | > + RPC_SMCR_SPIE | RPC_SMCR_SSLKP; > + } else { > + smcr = rpc->smcr | RPC_SMCR_SPIE; > + } > + > + regmap_write(rpc->regmap, RPC_SMENR, smenr); > + regmap_write(rpc->regmap, RPC_SMCR, smcr); > + ret = wait_msg_xfer_end(rpc); > + if (ret) > + goto out; > + > + pos += nbytes; > + smenr = rpc->smenr & ~RPC_SMENR_CDE & > + ~RPC_SMENR_ADE(0xf); > + } > + } else if (rx_buf) { > + while (pos < rpc->xferlen) { > + u32 nbytes = rpc->xferlen - pos; > + > + if (nbytes > 4) > + nbytes = 4; > + > + regmap_write(rpc->regmap, RPC_SMENR, rpc->smenr); > + regmap_write(rpc->regmap, RPC_SMCR, > + rpc->smcr | RPC_SMCR_SPIE); Hm... our flash chip (Spansion S25FS512S) doesn't get detected; it sends JEDEC ID bytes 0..3 repeatedly, unless I copy the SSLKP logic from the writing branch above... > + ret = wait_msg_xfer_end(rpc); > + if (ret) > + goto out; > + > + regmap_read(rpc->regmap, RPC_SMRDR0, &data); > + memcpy_fromio(rx_buf + pos, (void *)&data, nbytes); > + pos += nbytes; ... and it skips byte 4 unless I copy the code from the end of the writing branch, clearing CDE/ADE. But even then the byte 4 reads as 0x03 instead of 0. > + regmap_write(rpc->regmap, RPC_SMCMR, rpc->cmd); > + regmap_write(rpc->regmap, RPC_SMDMCR, rpc->dummy); > + regmap_write(rpc->regmap, RPC_SMADR, rpc->addr + pos); > + } > + } else { > + regmap_write(rpc->regmap, RPC_SMENR, rpc->smenr); > + regmap_write(rpc->regmap, RPC_SMCR, rpc->smcr | RPC_SMCR_SPIE); > + ret = wait_msg_xfer_end(rpc); > + if (ret) > + goto out; > + } > + > + return ret; > +out: > + return rpc_spi_do_reset(rpc); > +} [...] MBR, Sergei ^ permalink raw reply [flat|nested] 15+ messages in thread
[parent not found: <OFAE786891.A102E46D-ON48258366.002779D7-48258366.002A5C36@mxic.com.tw>]
* Re: [PATCH v3 1/2] spi: Add Renesas R-Car Gen3 RPC SPI controller driver [not found] ` <OFAE786891.A102E46D-ON48258366.002779D7-48258366.002A5C36@mxic.com.tw> @ 2018-12-17 13:23 ` Marek Vasut 2018-12-17 18:55 ` Sergei Shtylyov 2018-12-18 16:45 ` Sergei Shtylyov 2 siblings, 0 replies; 15+ messages in thread From: Marek Vasut @ 2018-12-17 13:23 UTC (permalink / raw) To: masonccyang, Sergei Shtylyov Cc: boris.brezillon, broonie, Geert Uytterhoeven, Simon Horman, juliensu, linux-kernel, linux-renesas-soc, linux-spi, zhengxunli On 12/17/2018 08:42 AM, masonccyang@mxic.com.tw wrote: > Hi Sergei, > > >> > +static int rpc_spi_io_xfer(struct rpc_spi *rpc, >> > + const void *tx_buf, void *rx_buf) >> > +{ >> > + u32 smenr, smcr, data, pos = 0; >> > + int ret = 0; >> > + >> > + regmap_write(rpc->regmap, RPC_CMNCR, RPC_CMNCR_MD | RPC_CMNCR_SFDE | >> > + RPC_CMNCR_MOIIO_HIZ | RPC_CMNCR_IOFV_HIZ | >> > + RPC_CMNCR_BSZ(0)); >> > + regmap_write(rpc->regmap, RPC_SMDRENR, 0x0); >> > + regmap_write(rpc->regmap, RPC_SMCMR, rpc->cmd); >> > + regmap_write(rpc->regmap, RPC_SMDMCR, rpc->dummy); >> > + regmap_write(rpc->regmap, RPC_SMADR, rpc->addr); >> > + >> > + if (tx_buf) { >> > + smenr = rpc->smenr; >> > + >> > + while (pos < rpc->xferlen) { >> > + u32 nbytes = rpc->xferlen - pos; >> > + >> > + regmap_write(rpc->regmap, RPC_SMWDR0, >> > + get_unaligned((u32 *)(tx_buf + pos))); >> > + >> > + if (nbytes > 4) { >> > + nbytes = 4; >> > + smcr = rpc->smcr | >> > + RPC_SMCR_SPIE | RPC_SMCR_SSLKP; >> > + } else { >> > + smcr = rpc->smcr | RPC_SMCR_SPIE; >> > + } >> > + >> > + regmap_write(rpc->regmap, RPC_SMENR, smenr); >> > + regmap_write(rpc->regmap, RPC_SMCR, smcr); >> > + ret = wait_msg_xfer_end(rpc); >> > + if (ret) >> > + goto out; >> > + >> > + pos += nbytes; >> > + smenr = rpc->smenr & ~RPC_SMENR_CDE & >> > + ~RPC_SMENR_ADE(0xf); >> > + } >> > + } else if (rx_buf) { >> > + while (pos < rpc->xferlen) { >> > + u32 nbytes = rpc->xferlen - pos; >> > + >> > + if (nbytes > 4) >> > + nbytes = 4; >> > + >> > + regmap_write(rpc->regmap, RPC_SMENR, rpc->smenr); >> > + regmap_write(rpc->regmap, RPC_SMCR, >> > + rpc->smcr | RPC_SMCR_SPIE); >> >> Hm... our flash chip (Spansion S25FS512S) doesn't get detected; it > sends >> JEDEC ID bytes 0..3 repeatedly, unless I copy the SSLKP logic from the > writing >> branch above... > > Do you switch the SW1, SW2, SW3, SW13, SW31 and SW10 to on-board QSPI > mode ? > Because R-Car D3 Draak board default is booting from HyperFlsah. So this puts us back to the original discussion -- the driver should support HF mode as well IMO. > what follows is my booting log, FYI. > ------------------------------------------------------------------ > [ 1.625053] m25p80 spi5.0: s25fl129p1 (16384 Kbytes) > [ 1.634391] 12 fixed-partitions partitions found on MTD device spi5.0 > [ 1.642198] Creating 12 MTD partitions on "spi5.0": > [ 1.647598] 0x000000000000-0x000000040000 : "Bank 1 - Boot parameter" > [ 1.660893] 0x000000040000-0x000000180000 : "Bank 1 - Loader-BL2" > [ 1.671287] 0x000000180000-0x0000001c0000 : "Bank 1 - Certification" > ----------------------------------------------------------------------- > >> >> > + ret = wait_msg_xfer_end(rpc); >> > + if (ret) >> > + goto out; >> > + >> > + regmap_read(rpc->regmap, RPC_SMRDR0, &data); >> > + memcpy_fromio(rx_buf + pos, (void *)&data, nbytes); >> > + pos += nbytes; >> >> ... and it skips byte 4 unless I copy the code from the end of the > writing >> branch, clearing CDE/ADE. But even then the byte 4 reads as 0x03 > instead of 0. > > yup, I think this is some kind of RPC HW limitation, > in RPC manual I/O mode, it only could read 4 bytes data w/ one command. > > That is, one command + read 4 bytes data + read 4 bytes data + read 4 > bytes data + ... > will get the incorrect data. > > That's why RPC in manual I/O mode, driver only could do, > one command + read 4 bytes data; one command + read 4 bytes data and so on. > > But RPC in external address space read mode(here we call it direct > mapping read mode) > is ok for one command + read 4 bytes data + read 4 bytes data + .... I think the U-Boot driver solves those problems, since it works in both RPC and HF mode on all of Gen3 boards , not just D3 in non-standard SPI boot configuration. Please take a look. -- Best regards, Marek Vasut ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 1/2] spi: Add Renesas R-Car Gen3 RPC SPI controller driver [not found] ` <OFAE786891.A102E46D-ON48258366.002779D7-48258366.002A5C36@mxic.com.tw> 2018-12-17 13:23 ` Marek Vasut @ 2018-12-17 18:55 ` Sergei Shtylyov 2018-12-18 16:45 ` Sergei Shtylyov 2 siblings, 0 replies; 15+ messages in thread From: Sergei Shtylyov @ 2018-12-17 18:55 UTC (permalink / raw) To: masonccyang Cc: boris.brezillon, broonie, Geert Uytterhoeven, Simon Horman, juliensu, linux-kernel, linux-renesas-soc, linux-spi, marek.vasut, zhengxunli Hello! On 12/17/2018 10:42 AM, masonccyang@mxic.com.tw wrote: >> > +static int rpc_spi_io_xfer(struct rpc_spi *rpc, >> > + const void *tx_buf, void *rx_buf) >> > +{ >> > + u32 smenr, smcr, data, pos = 0; >> > + int ret = 0; >> > + >> > + regmap_write(rpc->regmap, RPC_CMNCR, RPC_CMNCR_MD | RPC_CMNCR_SFDE | >> > + RPC_CMNCR_MOIIO_HIZ | RPC_CMNCR_IOFV_HIZ | >> > + RPC_CMNCR_BSZ(0)); >> > + regmap_write(rpc->regmap, RPC_SMDRENR, 0x0); >> > + regmap_write(rpc->regmap, RPC_SMCMR, rpc->cmd); >> > + regmap_write(rpc->regmap, RPC_SMDMCR, rpc->dummy); >> > + regmap_write(rpc->regmap, RPC_SMADR, rpc->addr); >> > + >> > + if (tx_buf) { >> > + smenr = rpc->smenr; >> > + >> > + while (pos < rpc->xferlen) { >> > + u32 nbytes = rpc->xferlen - pos; >> > + >> > + regmap_write(rpc->regmap, RPC_SMWDR0, >> > + get_unaligned((u32 *)(tx_buf + pos))); >> > + >> > + if (nbytes > 4) { >> > + nbytes = 4; >> > + smcr = rpc->smcr | >> > + RPC_SMCR_SPIE | RPC_SMCR_SSLKP; >> > + } else { >> > + smcr = rpc->smcr | RPC_SMCR_SPIE; >> > + } >> > + >> > + regmap_write(rpc->regmap, RPC_SMENR, smenr); >> > + regmap_write(rpc->regmap, RPC_SMCR, smcr); >> > + ret = wait_msg_xfer_end(rpc); >> > + if (ret) >> > + goto out; >> > + >> > + pos += nbytes; >> > + smenr = rpc->smenr & ~RPC_SMENR_CDE & >> > + ~RPC_SMENR_ADE(0xf); >> > + } >> > + } else if (rx_buf) { >> > + while (pos < rpc->xferlen) { >> > + u32 nbytes = rpc->xferlen - pos; >> > + >> > + if (nbytes > 4) >> > + nbytes = 4; >> > + >> > + regmap_write(rpc->regmap, RPC_SMENR, rpc->smenr); >> > + regmap_write(rpc->regmap, RPC_SMCR, >> > + rpc->smcr | RPC_SMCR_SPIE); >> >> Hm... our flash chip (Spansion S25FS512S) doesn't get detected; it sends >> JEDEC ID bytes 0..3 repeatedly, unless I copy the SSLKP logic from the writing >> branch above... > > Do you switch the SW1, SW2, SW3, SW13, SW31 and SW10 to on-board QSPI mode ? > Because R-Car D3 Draak board default is booting from HyperFlsah. I was testing your patch on the V3H-based Condor and Starter Kit boards -- it should have worked without much ado... It works with *our* driver, living under drivers/mtd/spi-nor/ (which makes it outdated, AFAIU) and I was going to push it upstream before I learned about your driver. :-) > what follows is my booting log, FYI. > ------------------------------------------------------------------ > [ 1.625053] m25p80 spi5.0: s25fl129p1 (16384 Kbytes) So another Spansion flash? > [ 1.634391] 12 fixed-partitions partitions found on MTD device spi5.0 > [ 1.642198] Creating 12 MTD partitions on "spi5.0": > [ 1.647598] 0x000000000000-0x000000040000 : "Bank 1 - Boot parameter" > [ 1.660893] 0x000000040000-0x000000180000 : "Bank 1 - Loader-BL2" > [ 1.671287] 0x000000180000-0x0000001c0000 : "Bank 1 - Certification" > ----------------------------------------------------------------------- > >> >> > + ret = wait_msg_xfer_end(rpc); >> > + if (ret) >> > + goto out; >> > + >> > + regmap_read(rpc->regmap, RPC_SMRDR0, &data); >> > + memcpy_fromio(rx_buf + pos, (void *)&data, nbytes); >> > + pos += nbytes; >> >> ... and it skips byte 4 unless I copy the code from the end of the writing >> branch, clearing CDE/ADE. But even then the byte 4 reads as 0x03 instead of 0. > > yup, I think this is some kind of RPC HW limitation, > in RPC manual I/O mode, it only could read 4 bytes data w/ one command. Thank for the info -- seems worth a comment though... > That is, one command + read 4 bytes data + read 4 bytes data + read 4 bytes data + ... > will get the incorrect data. What if we want to read less than 4 bytes (the ID read requests SPI_NOR_MAX_ID_LEN (6) bytes, i.e. 4 + 2)? You seem to always expect 4 bytes... > That's why RPC in manual I/O mode, driver only could do, > one command + read 4 bytes data; one command + read 4 bytes data and so on. The question is why it just duplicates the ID bytes 0..3 on the 2nd iteration in our case... > But RPC in external address space read mode(here we call it direct mapping read mode) > is ok for one command + read 4 bytes data + read 4 bytes data + .... Sounds promising... if only we could make the probing work. :-) > thanks & best regards, > Mason MBR, Sergei ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 1/2] spi: Add Renesas R-Car Gen3 RPC SPI controller driver [not found] ` <OFAE786891.A102E46D-ON48258366.002779D7-48258366.002A5C36@mxic.com.tw> 2018-12-17 13:23 ` Marek Vasut 2018-12-17 18:55 ` Sergei Shtylyov @ 2018-12-18 16:45 ` Sergei Shtylyov 2 siblings, 0 replies; 15+ messages in thread From: Sergei Shtylyov @ 2018-12-18 16:45 UTC (permalink / raw) To: masonccyang Cc: boris.brezillon, broonie, Geert Uytterhoeven, Simon Horman, juliensu, linux-kernel, linux-renesas-soc, linux-spi, marek.vasut, zhengxunli On 12/17/2018 10:42 AM, masonccyang@mxic.com.tw wrote: >> > +static int rpc_spi_io_xfer(struct rpc_spi *rpc, >> > + const void *tx_buf, void *rx_buf) >> > +{ >> > + u32 smenr, smcr, data, pos = 0; >> > + int ret = 0; >> > + >> > + regmap_write(rpc->regmap, RPC_CMNCR, RPC_CMNCR_MD | RPC_CMNCR_SFDE | >> > + RPC_CMNCR_MOIIO_HIZ | RPC_CMNCR_IOFV_HIZ | >> > + RPC_CMNCR_BSZ(0)); >> > + regmap_write(rpc->regmap, RPC_SMDRENR, 0x0); >> > + regmap_write(rpc->regmap, RPC_SMCMR, rpc->cmd); >> > + regmap_write(rpc->regmap, RPC_SMDMCR, rpc->dummy); >> > + regmap_write(rpc->regmap, RPC_SMADR, rpc->addr); >> > + >> > + if (tx_buf) { >> > + smenr = rpc->smenr; >> > + >> > + while (pos < rpc->xferlen) { >> > + u32 nbytes = rpc->xferlen - pos; >> > + >> > + regmap_write(rpc->regmap, RPC_SMWDR0, >> > + get_unaligned((u32 *)(tx_buf + pos))); >> > + >> > + if (nbytes > 4) { >> > + nbytes = 4; >> > + smcr = rpc->smcr | >> > + RPC_SMCR_SPIE | RPC_SMCR_SSLKP; >> > + } else { >> > + smcr = rpc->smcr | RPC_SMCR_SPIE; >> > + } >> > + >> > + regmap_write(rpc->regmap, RPC_SMENR, smenr); >> > + regmap_write(rpc->regmap, RPC_SMCR, smcr); >> > + ret = wait_msg_xfer_end(rpc); >> > + if (ret) >> > + goto out; >> > + >> > + pos += nbytes; >> > + smenr = rpc->smenr & ~RPC_SMENR_CDE & >> > + ~RPC_SMENR_ADE(0xf); >> > + } >> > + } else if (rx_buf) { >> > + while (pos < rpc->xferlen) { >> > + u32 nbytes = rpc->xferlen - pos; >> > + >> > + if (nbytes > 4) >> > + nbytes = 4; >> > + >> > + regmap_write(rpc->regmap, RPC_SMENR, rpc->smenr); >> > + regmap_write(rpc->regmap, RPC_SMCR, >> > + rpc->smcr | RPC_SMCR_SPIE); >> >> Hm... our flash chip (Spansion S25FS512S) doesn't get detected; it sends >> JEDEC ID bytes 0..3 repeatedly, unless I copy the SSLKP logic from the writing >> branch above... [...] > what follows is my booting log, FYI. > ------------------------------------------------------------------ > [ 1.625053] m25p80 spi5.0: s25fl129p1 (16384 Kbytes) Looking at the spi_nor_ids[], this chip has 0x01 in both byte 0 and byte 4... > [ 1.634391] 12 fixed-partitions partitions found on MTD device spi5.0 > [ 1.642198] Creating 12 MTD partitions on "spi5.0": > [ 1.647598] 0x000000000000-0x000000040000 : "Bank 1 - Boot parameter" > [ 1.660893] 0x000000040000-0x000000180000 : "Bank 1 - Loader-BL2" > [ 1.671287] 0x000000180000-0x0000001c0000 : "Bank 1 - Certification" > ----------------------------------------------------------------------- > >> >> > + ret = wait_msg_xfer_end(rpc); >> > + if (ret) >> > + goto out; >> > + >> > + regmap_read(rpc->regmap, RPC_SMRDR0, &data); >> > + memcpy_fromio(rx_buf + pos, (void *)&data, nbytes); >> > + pos += nbytes; >> >> ... and it skips byte 4 unless I copy the code from the end of the writing >> branch, clearing CDE/ADE. But even then the byte 4 reads as 0x03 instead of 0. > > yup, I think this is some kind of RPC HW limitation, > in RPC manual I/O mode, it only could read 4 bytes data w/ one command. > > That is, one command + read 4 bytes data + read 4 bytes data + read 4 bytes data + ... > will get the incorrect data. > > That's why RPC in manual I/O mode, driver only could do, > one command + read 4 bytes data; one command + read 4 bytes data and so on. Yes. But the problem is you can't work around by reading 4 bytes at most for the RDID command -- it has no address phase. Every time you "restart" reading, you get bytes 0..3 again, like me. It seems that this approach works for you only by chance... > thanks & best regards, > Mason MBR, Sergei ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 2/2] dt-binding: spi: Document Renesas R-Car Gen3 RPC controller bindings 2018-12-07 11:13 [PATCH v3 0/2] spi: Add Renesas R-Car Gen3 RPC SPI driver Mason Yang 2018-12-07 11:13 ` [PATCH v3 1/2] spi: Add Renesas R-Car Gen3 RPC SPI controller driver Mason Yang @ 2018-12-07 11:13 ` Mason Yang 2018-12-07 16:03 ` Sergei Shtylyov ` (2 more replies) 2018-12-09 15:37 ` [PATCH v3 0/2] spi: Add Renesas R-Car Gen3 RPC SPI driver Sergei Shtylyov 2 siblings, 3 replies; 15+ messages in thread From: Mason Yang @ 2018-12-07 11:13 UTC (permalink / raw) To: broonie, marek.vasut, linux-kernel, linux-spi, boris.brezillon, linux-renesas-soc, Geert Uytterhoeven Cc: juliensu, Simon Horman, zhengxunli, Mason Yang Document the bindings used by the Renesas R-Car Gen3 RPC controller. Signed-off-by: Mason Yang <masonccyang@mxic.com.tw> --- .../devicetree/bindings/spi/spi-renesas-rpc.txt | 38 ++++++++++++++++++++++ 1 file changed, 38 insertions(+) create mode 100644 Documentation/devicetree/bindings/spi/spi-renesas-rpc.txt diff --git a/Documentation/devicetree/bindings/spi/spi-renesas-rpc.txt b/Documentation/devicetree/bindings/spi/spi-renesas-rpc.txt new file mode 100644 index 0000000..a191f70 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spi-renesas-rpc.txt @@ -0,0 +1,38 @@ +Renesas R-Car Gen3 RPC controller Device Tree Bindings +------------------------------------------------------ + +Required properties: +- compatible: should be "renesas,r8a77995-rpc" +- #address-cells: should be 1 +- #size-cells: should be 0 +- reg: should contain 2 entries, one for the registers and one for the direct + mapping area +- reg-names: should contain "rpc_regs" and "dirmap" +- interrupts: interrupt line connected to the RPC controller +- clock-names: should contain "clk_rpc" +- clocks: should contain 1 entries for the module's clock +- rpc-mode: should contain "rpc-spi-flash" for rpc spi mode or + "rpc-hyperflash" for rpc hyerflash mode. + +Example: + + rpc: rpc@ee200000 { + compatible = "renesas,r8a77995-rpc"; + reg = <0 0xee200000 0 0x8100>, <0 0x08000000 0 0x4000000>; + reg-names = "rpc_regs", "dirmap"; + clocks = <&cpg CPG_MOD 917>; + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; + resets = <&cpg 917>; + clock-names = "clk_rpc"; + rpc-mode = "rpc-spi-flash"; + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <40000000>; + spi-tx-bus-width = <1>; + spi-rx-bus-width = <1>; + }; + }; -- 1.9.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v3 2/2] dt-binding: spi: Document Renesas R-Car Gen3 RPC controller bindings 2018-12-07 11:13 ` [PATCH v3 2/2] dt-binding: spi: Document Renesas R-Car Gen3 RPC controller bindings Mason Yang @ 2018-12-07 16:03 ` Sergei Shtylyov 2018-12-07 16:31 ` Marek Vasut 2018-12-12 16:41 ` Sergei Shtylyov 2018-12-12 17:47 ` Sergei Shtylyov 2 siblings, 1 reply; 15+ messages in thread From: Sergei Shtylyov @ 2018-12-07 16:03 UTC (permalink / raw) To: Mason Yang, broonie, marek.vasut, linux-kernel, linux-spi, boris.brezillon, linux-renesas-soc, Geert Uytterhoeven Cc: juliensu, Simon Horman, zhengxunli Hello! On 12/07/2018 02:13 PM, Mason Yang wrote: > Document the bindings used by the Renesas R-Car Gen3 RPC controller. > > Signed-off-by: Mason Yang <masonccyang@mxic.com.tw> > --- > .../devicetree/bindings/spi/spi-renesas-rpc.txt | 38 ++++++++++++++++++++++ > 1 file changed, 38 insertions(+) > create mode 100644 Documentation/devicetree/bindings/spi/spi-renesas-rpc.txt > > diff --git a/Documentation/devicetree/bindings/spi/spi-renesas-rpc.txt b/Documentation/devicetree/bindings/spi/spi-renesas-rpc.txt > new file mode 100644 > index 0000000..a191f70 > --- /dev/null > +++ b/Documentation/devicetree/bindings/spi/spi-renesas-rpc.txt > @@ -0,0 +1,38 @@ > +Renesas R-Car Gen3 RPC controller Device Tree Bindings > +------------------------------------------------------ > + > +Required properties: > +- compatible: should be "renesas,r8a77995-rpc" > +- #address-cells: should be 1 > +- #size-cells: should be 0 > +- reg: should contain 2 entries, one for the registers and one for the direct > + mapping area > +- reg-names: should contain "rpc_regs" and "dirmap" Please drop this "rpc_" thing, I think "regs" should be enough. > +- interrupts: interrupt line connected to the RPC controller > +- clock-names: should contain "clk_rpc" Please drop this "clk_" thing. BTW, what's with the RPCD2 clock? > +- clocks: should contain 1 entries for the module's clock > +- rpc-mode: should contain "rpc-spi-flash" for rpc spi mode or > + "rpc-hyperflash" for rpc hyerflash mode. I think the prop should be called "renesas,rpc-mode" and the values should be just "spi" and "hyperflash". [...] MBR, Sergei ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 2/2] dt-binding: spi: Document Renesas R-Car Gen3 RPC controller bindings 2018-12-07 16:03 ` Sergei Shtylyov @ 2018-12-07 16:31 ` Marek Vasut 0 siblings, 0 replies; 15+ messages in thread From: Marek Vasut @ 2018-12-07 16:31 UTC (permalink / raw) To: Sergei Shtylyov, Mason Yang, broonie, linux-kernel, linux-spi, boris.brezillon, linux-renesas-soc, Geert Uytterhoeven Cc: juliensu, Simon Horman, zhengxunli On 12/07/2018 05:03 PM, Sergei Shtylyov wrote: > Hello! > > On 12/07/2018 02:13 PM, Mason Yang wrote: > >> Document the bindings used by the Renesas R-Car Gen3 RPC controller. >> >> Signed-off-by: Mason Yang <masonccyang@mxic.com.tw> >> --- >> .../devicetree/bindings/spi/spi-renesas-rpc.txt | 38 ++++++++++++++++++++++ >> 1 file changed, 38 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/spi/spi-renesas-rpc.txt >> >> diff --git a/Documentation/devicetree/bindings/spi/spi-renesas-rpc.txt b/Documentation/devicetree/bindings/spi/spi-renesas-rpc.txt >> new file mode 100644 >> index 0000000..a191f70 >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/spi/spi-renesas-rpc.txt >> @@ -0,0 +1,38 @@ >> +Renesas R-Car Gen3 RPC controller Device Tree Bindings >> +------------------------------------------------------ >> + >> +Required properties: >> +- compatible: should be "renesas,r8a77995-rpc" >> +- #address-cells: should be 1 >> +- #size-cells: should be 0 >> +- reg: should contain 2 entries, one for the registers and one for the direct >> + mapping area >> +- reg-names: should contain "rpc_regs" and "dirmap" > > Please drop this "rpc_" thing, I think "regs" should be enough. > >> +- interrupts: interrupt line connected to the RPC controller >> +- clock-names: should contain "clk_rpc" > > Please drop this "clk_" thing. BTW, what's with the RPCD2 clock? > >> +- clocks: should contain 1 entries for the module's clock >> +- rpc-mode: should contain "rpc-spi-flash" for rpc spi mode or >> + "rpc-hyperflash" for rpc hyerflash mode. > > I think the prop should be called "renesas,rpc-mode" and the values should be > just "spi" and "hyperflash". Like I said before, you can determine the mode from the subnode attached to the controller, we don't need special prop for that. -- Best regards, Marek Vasut ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 2/2] dt-binding: spi: Document Renesas R-Car Gen3 RPC controller bindings 2018-12-07 11:13 ` [PATCH v3 2/2] dt-binding: spi: Document Renesas R-Car Gen3 RPC controller bindings Mason Yang 2018-12-07 16:03 ` Sergei Shtylyov @ 2018-12-12 16:41 ` Sergei Shtylyov 2018-12-12 17:47 ` Sergei Shtylyov 2 siblings, 0 replies; 15+ messages in thread From: Sergei Shtylyov @ 2018-12-12 16:41 UTC (permalink / raw) To: Mason Yang, broonie, marek.vasut, linux-kernel, linux-spi, boris.brezillon, linux-renesas-soc, Geert Uytterhoeven Cc: juliensu, Simon Horman, zhengxunli Hello! Should be "dt-bindings: " in the subject... MBR, Sergei ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 2/2] dt-binding: spi: Document Renesas R-Car Gen3 RPC controller bindings 2018-12-07 11:13 ` [PATCH v3 2/2] dt-binding: spi: Document Renesas R-Car Gen3 RPC controller bindings Mason Yang 2018-12-07 16:03 ` Sergei Shtylyov 2018-12-12 16:41 ` Sergei Shtylyov @ 2018-12-12 17:47 ` Sergei Shtylyov 2 siblings, 0 replies; 15+ messages in thread From: Sergei Shtylyov @ 2018-12-12 17:47 UTC (permalink / raw) To: Mason Yang, broonie, marek.vasut, linux-kernel, linux-spi, boris.brezillon, linux-renesas-soc, Geert Uytterhoeven Cc: juliensu, Simon Horman, zhengxunli On 12/07/2018 02:13 PM, Mason Yang wrote: > Document the bindings used by the Renesas R-Car Gen3 RPC controller. > > Signed-off-by: Mason Yang <masonccyang@mxic.com.tw> > --- > .../devicetree/bindings/spi/spi-renesas-rpc.txt | 38 ++++++++++++++++++++++ > 1 file changed, 38 insertions(+) > create mode 100644 Documentation/devicetree/bindings/spi/spi-renesas-rpc.txt > > diff --git a/Documentation/devicetree/bindings/spi/spi-renesas-rpc.txt b/Documentation/devicetree/bindings/spi/spi-renesas-rpc.txt > new file mode 100644 > index 0000000..a191f70 > --- /dev/null > +++ b/Documentation/devicetree/bindings/spi/spi-renesas-rpc.txt > @@ -0,0 +1,38 @@ > +Renesas R-Car Gen3 RPC controller Device Tree Bindings > +------------------------------------------------------ > + > +Required properties: > +- compatible: should be "renesas,r8a77995-rpc" > +- #address-cells: should be 1 > +- #size-cells: should be 0 > +- reg: should contain 2 entries, one for the registers and one for the direct > + mapping area > +- reg-names: should contain "rpc_regs" and "dirmap" > +- interrupts: interrupt line connected to the RPC controller Required prop but it's missing in your example below... > +- clock-names: should contain "clk_rpc" > +- clocks: should contain 1 entries for the module's clock > +- rpc-mode: should contain "rpc-spi-flash" for rpc spi mode or > + "rpc-hyperflash" for rpc hyerflash mode. > + > +Example: > + > + rpc: rpc@ee200000 { > + compatible = "renesas,r8a77995-rpc"; > + reg = <0 0xee200000 0 0x8100>, <0 0x08000000 0 0x4000000>; > + reg-names = "rpc_regs", "dirmap"; > + clocks = <&cpg CPG_MOD 917>; > + power-domains = <&sysc R8A77995_PD_ALWAYS_ON>; > + resets = <&cpg 917>; > + clock-names = "clk_rpc"; > + rpc-mode = "rpc-spi-flash"; > + #address-cells = <1>; > + #size-cells = <0>; [...] MBR, Sergei ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 0/2] spi: Add Renesas R-Car Gen3 RPC SPI driver 2018-12-07 11:13 [PATCH v3 0/2] spi: Add Renesas R-Car Gen3 RPC SPI driver Mason Yang 2018-12-07 11:13 ` [PATCH v3 1/2] spi: Add Renesas R-Car Gen3 RPC SPI controller driver Mason Yang 2018-12-07 11:13 ` [PATCH v3 2/2] dt-binding: spi: Document Renesas R-Car Gen3 RPC controller bindings Mason Yang @ 2018-12-09 15:37 ` Sergei Shtylyov 2 siblings, 0 replies; 15+ messages in thread From: Sergei Shtylyov @ 2018-12-09 15:37 UTC (permalink / raw) To: Mason Yang, broonie, marek.vasut, linux-kernel, linux-spi, boris.brezillon, linux-renesas-soc, Geert Uytterhoeven Cc: juliensu, Simon Horman, zhengxunli On 12/07/2018 02:13 PM, Mason Yang wrote: > This Renesas R-Car Gen3 RPC SPI driver is based on Boris's new > spi-mem direct mapping read/write mode [1][2]. > > v3 patch is according to Marek and Geert's comments including: > 1) soc_device_mach() to set up RPC_PHYCNT_STRTIM. > 2) get_unaligned() > 3) rpc-mode for rpi-spi-flash or rpc-hyperflash. > 4) coding style and so on. > > > v2 patch including: > 1) remove RPC clock enable/dis-able control, > 2) patch run time PM, > 3) add RPC module software reset, > 4) add regmap, > 5) other coding style and so on. > > thanks for your review. > > best regards, > Mason > > [1] https://patchwork.kernel.org/patch/10670753 > [2] https://patchwork.kernel.org/patch/10670747 > > > Mason Yang (2): > spi: Add Renesas R-Car Gen3 RPC SPI controller driver > dt-binding: spi: Document Renesas R-Car Gen3 RPC controller bindings Probably a stupid question: how did you test this driver (especially the dirmap related parts)? MBR, Sergei ^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2018-12-21 10:22 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
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2018-12-07 11:13 [PATCH v3 0/2] spi: Add Renesas R-Car Gen3 RPC SPI driver Mason Yang
2018-12-07 11:13 ` [PATCH v3 1/2] spi: Add Renesas R-Car Gen3 RPC SPI controller driver Mason Yang
2018-12-08 16:14 ` kbuild test robot
2018-12-11 19:45 ` Sergei Shtylyov
[not found] ` <OFC335F545.7543A0F2-ON4825836A.0007E65A-4825836A.0008428D@mxic.com.tw>
2018-12-21 10:22 ` Sergei Shtylyov
2018-12-13 19:48 ` Sergei Shtylyov
[not found] ` <OFAE786891.A102E46D-ON48258366.002779D7-48258366.002A5C36@mxic.com.tw>
2018-12-17 13:23 ` Marek Vasut
2018-12-17 18:55 ` Sergei Shtylyov
2018-12-18 16:45 ` Sergei Shtylyov
2018-12-07 11:13 ` [PATCH v3 2/2] dt-binding: spi: Document Renesas R-Car Gen3 RPC controller bindings Mason Yang
2018-12-07 16:03 ` Sergei Shtylyov
2018-12-07 16:31 ` Marek Vasut
2018-12-12 16:41 ` Sergei Shtylyov
2018-12-12 17:47 ` Sergei Shtylyov
2018-12-09 15:37 ` [PATCH v3 0/2] spi: Add Renesas R-Car Gen3 RPC SPI driver Sergei Shtylyov
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