From: Vignesh Raghavendra <vigneshr@ti.com>
To: "Ramuthevar,
Vadivel MuruganX" <vadivel.muruganx.ramuthevar@linux.intel.com>,
<broonie@kernel.org>, <linux-spi@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Cc: <robh+dt@kernel.org>, <dan.carpenter@oracle.com>,
<cheol.yong.kim@intel.com>, <qi-ming.wu@intel.com>
Subject: Re: [PATCH v6 2/2] spi: cadence-quadpsi: Add support for the Cadence QSPI controller
Date: Wed, 8 Jan 2020 10:44:26 +0530 [thread overview]
Message-ID: <9b95a30f-6d2d-2202-248a-24186d5ddb2a@ti.com> (raw)
In-Reply-To: <66b9f427-83c2-f56c-3d38-fa955429118d@linux.intel.com>
On 06/01/20 4:49 pm, Ramuthevar, Vadivel MuruganX wrote:
> Hi,
>
> Thank you for the review comments.
>
> On 6/1/2020 6:40 PM, Vignesh Raghavendra wrote:
>> Hi,
>>
>> On 30/12/19 1:11 pm, Ramuthevar,Vadivel MuruganX wrote:
>> [...]
>>> +static u32 cqspi_cmd2addr(const unsigned char *addr_buf, u32
>>> addr_width)
>>> +{
>>> + unsigned int addr = 0;
>>> + int i;
>>> +
>>> + /* Invalid address return zero. */
>>> + if (addr_width > 4)
>>> + return 0;
>>> +
>>> + for (i = 0; i < addr_width; i++) {
>>> + addr = addr << 8;
>>> + addr |= addr_buf[i];
>>> + }
>>> +
>>> + return addr;
>>> +}
>>> +
>> [...]
>>> +static int cqspi_apb_read_setup(struct struct_cqspi *cqspi,
>>> + const struct spi_mem_op *op,
>>> + const u8 *addrbuf)
>>> +{
>>> + void __iomem *reg_base = cqspi->iobase;
>>> + size_t addrlen = op->addr.nbytes;
>>> + size_t dummy_bytes = op->dummy.nbytes;
>>> + unsigned int addr_value, dummy_clk, reg;
>>> +
>>> + if (addrlen) {
>>> + addr_value = cqspi_cmd2addr(&addrbuf[0], addrlen);
>>> + writel(addr_value, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
>>> + }
>>> +
>> Why do you need to swap the address bytes to SPI bus order?
> Yes , you are right to align with spi bus order swap is done .
>> You are
>> writing to a controller register that accepts 24 bit or 32 bit address.
> 32bit address.
There is no need to swap the address bytes. The current driver
(drivers/mtd/spi-nor/cadence-quadspi.c) does not swap the address to SPI
bus order, why does the new driver required to do so?
>>> + reg = op->cmd.opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
>>> + reg |= (op->data.buswidth & CQSPI_REG_RD_INSTR_TYPE_DATA_MASK) <<
>>> + CQSPI_REG_RD_INSTR_TYPE_DATA_LSB;
>>> +
>> This is wrong... op->data.buswidth's range is 1 to 8 whereas
>> CQSPI_REG_RD_INSTR_TYPE range is 0 to 3. I wonder whether you tested
>> dual/quad mode with this driver?
> Yes I have tested with Quad mode since Cadence-IP supports dual/quad on
> my platform, used to validate
> before sending the patch that's standard procedure here.
> please let me know if you have any further queries.
>
Then I have no idea how it works on your platform.. What you are
programming above overflows the assigned bit fields for bus width, right?
> ---
> Best Regards
> Vadivel
>> I am still unable to get this series to work on my platform. Will
>> continue to debug...
>>
--
Regards
Vignesh
next prev parent reply other threads:[~2020-01-08 5:14 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-30 7:41 [PATCH v6 0/2] spi: cadence-quadpsi: Add support for the Cadence QSPI controller Ramuthevar,Vadivel MuruganX
2019-12-30 7:41 ` [PATCH v6 1/2] dt-bindings: spi: Add schema for Cadence QSPI Controller driver Ramuthevar,Vadivel MuruganX
2019-12-30 7:41 ` [PATCH v6 2/2] spi: cadence-quadpsi: Add support for the Cadence QSPI controller Ramuthevar,Vadivel MuruganX
2020-01-06 10:40 ` Vignesh Raghavendra
2020-01-06 11:19 ` Ramuthevar, Vadivel MuruganX
2020-01-08 5:14 ` Vignesh Raghavendra [this message]
2020-01-08 5:44 ` Ramuthevar, Vadivel MuruganX
2020-01-08 5:25 ` Vignesh Raghavendra
2020-01-08 5:55 ` Ramuthevar, Vadivel MuruganX
[not found] ` <20191230074102.50982-1-vadivel.muruganx.ramuthevar-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
2020-01-15 6:13 ` [PATCH v6 0/2] " Vignesh Raghavendra
2020-01-15 6:21 ` Ramuthevar, Vadivel MuruganX
[not found] ` <1aa6033a-c9e1-579b-0916-25037c07654d-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
2020-01-21 11:47 ` Ramuthevar, Vadivel MuruganX
2020-01-23 8:18 ` Vignesh Raghavendra
[not found] ` <860aecbc-22d3-c9ce-3570-44115d6e81b2-l0cyMroinI0@public.gmane.org>
2020-01-23 7:24 ` [EXT] " Kuldeep Singh
2020-01-23 7:47 ` Vignesh Raghavendra
2020-01-23 11:37 ` Kuldeep Singh
[not found] ` <AM6PR0402MB35573B2313C7FB81D747ABA6E00F0-Dzj3fuf2f4AsyWmSStHLuo3W/0Ik+aLCnBOFsp37pqbUKgpGm//BTAC/G2K4zDHf@public.gmane.org>
2020-01-27 4:21 ` Vignesh Raghavendra
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=9b95a30f-6d2d-2202-248a-24186d5ddb2a@ti.com \
--to=vigneshr@ti.com \
--cc=broonie@kernel.org \
--cc=cheol.yong.kim@intel.com \
--cc=dan.carpenter@oracle.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-spi@vger.kernel.org \
--cc=qi-ming.wu@intel.com \
--cc=robh+dt@kernel.org \
--cc=vadivel.muruganx.ramuthevar@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).