From: Vignesh Raghavendra <vigneshr@ti.com>
To: "Ramuthevar,Vadivel MuruganX"
<vadivel.muruganx.ramuthevar@linux.intel.com>,
<broonie@kernel.org>, <linux-spi@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Cc: <robh+dt@kernel.org>, <dan.carpenter@oracle.com>,
<cheol.yong.kim@intel.com>, <qi-ming.wu@intel.com>
Subject: Re: [PATCH v6 2/2] spi: cadence-quadpsi: Add support for the Cadence QSPI controller
Date: Wed, 8 Jan 2020 10:55:51 +0530 [thread overview]
Message-ID: <ac26ecfe-d45c-db70-df8f-91da32c9925a@ti.com> (raw)
In-Reply-To: <20191230074102.50982-3-vadivel.muruganx.ramuthevar@linux.intel.com>
Hi,
[...]
On 30/12/19 1:11 pm, Ramuthevar,Vadivel MuruganX wrote:
> +static int cqspi_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct struct_cqspi *cqspi;
> + struct spi_master *master;
> + struct reset_control *rstc, *rstc_ocp;
> + const struct cqspi_driver_platdata *ddata;
> + struct cqspi_platform_data *pdata = NULL;
> + struct resource *res = NULL;
> + int ret;
> +
> + master = spi_alloc_master(&pdev->dev, sizeof(*cqspi));
> + if (!master) {
> + dev_err(&pdev->dev, "spi_alloc_master failed\n");
> + return -ENOMEM;
> + }
> + master->mode_bits = SPI_RX_QUAD | SPI_TX_DUAL | SPI_RX_DUAL |
> + SPI_RX_OCTAL;
> + master->setup = cqspi_setup;
> + master->mem_ops = &cqspi_mem_ops;
> + master->dev.of_node = pdev->dev.of_node;
> + cqspi = spi_master_get_devdata(master);
> + cqspi->pdev = pdev;
> +
> + pdata = devm_kmalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
devm_kzalloc()?
> + if (!pdata)
> + return -ENOMEM;
> +
> + pdev->dev.platform_data = pdata;
> +
> + /* Obtain QSPI clock. */
> + cqspi->clk = devm_clk_get(&pdev->dev, "qspi");
clock-name of "qspi" is not mandatory as per DT binding and current DT
files don't have clock-names property. This therefore cause probe to
fail. This should remain:
cqspi->clk = devm_clk_get(&pdev->dev, "NULL");
> + if (IS_ERR(cqspi->clk)) {
> + dev_err(&pdev->dev, "cannot get qspi clk\n");
> + return PTR_ERR(cqspi->clk);
> + }
> + pdata->master_ref_clk_hz = clk_get_rate(cqspi->clk);
> +
> + ret = clk_prepare_enable(cqspi->clk);
> + if (ret < 0) {
> + dev_err(&pdev->dev, "failed to enable qspi clock: %d\n", ret);
> + return ret;
> + }
> +
> + /* Obtain configuration from OF. */
> + ret = cqspi_of_get_pdata(pdev);
> + if (ret) {
> + dev_err(&pdev->dev, "Get platform data failed.\n");
> + return -ENODEV;
> + }
> +
> + cqspi->res = res;
> + /* Obtain and remap controller address. */
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + cqspi->iobase = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(cqspi->iobase)) {
> + dev_err(dev, "Cannot remap controller address.\n");
> + return PTR_ERR(cqspi->iobase);
> + }
> +
> + /* Obtain and remap AHB address. */
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> + cqspi->qspi_ahb_virt = devm_ioremap_resource(dev, res);
> + if (IS_ERR(cqspi->qspi_ahb_virt)) {
> + dev_err(dev, "Cannot remap AHB address.\n");
> + return PTR_ERR(cqspi->qspi_ahb_virt);
> + }
> + cqspi->ahbbase = res;
> + cqspi->ahb_size = resource_size(res);
> +
> + /* Obtain QSPI reset control */
> + rstc = devm_reset_control_get_optional_exclusive(dev, "qspi");
> + if (IS_ERR(rstc)) {
> + dev_err(dev, "Cannot get QSPI reset.\n");
> + return PTR_ERR(rstc);
> + }
> +
> + rstc_ocp = devm_reset_control_get_optional_exclusive(dev, "qspi-ocp");
> + if (IS_ERR(rstc_ocp)) {
> + dev_err(dev, "Cannot get QSPI OCP reset.\n");
> + return PTR_ERR(rstc_ocp);
> + }
> +
> + reset_control_assert(rstc);
> + reset_control_deassert(rstc);
> +
> + reset_control_assert(rstc_ocp);
> + reset_control_deassert(rstc_ocp);
> +
> + ddata = of_device_get_match_data(dev);
> + if (ddata && (ddata->quirks & CQSPI_NEEDS_WR_DELAY))
> + cqspi->wr_delay = 5 * DIV_ROUND_UP(NSEC_PER_SEC,
> + pdata->master_ref_clk_hz);
> +
> + if (ddata && (ddata->quirks & CQSPI_DISABLE_DAC_MODE))
> + cqspi->use_dac_mode = false;
> +
> + init_completion(&cqspi->transfer_complete);
> +
> + /* Obtain IRQ line. */
> + cqspi->irq = platform_get_irq(pdev, 0);
> + if (cqspi->irq < 0) {
> + dev_err(dev, "platform_get_irq failed.\n");
> + ret = -ENXIO;
> + }
> + ret = devm_request_irq(dev, cqspi->irq, cqspi_irq_handler, 0,
> + pdev->name, cqspi);
> + if (ret) {
> + dev_err(dev, "request_irq failed.\n");
> + goto out_clk_disable;
> + }
> +
> + master->bus_num = pdata->bus_num;
> + master->num_chipselect = pdata->num_chipselect;
Where is pdata->bus_num and pdata->num_chipselect initialized? This
causes devm_spi_register_master() to fail randomly as num_chipselect may
be 0.
> + mutex_init(&cqspi->lock);
> + platform_set_drvdata(pdev, master);
> + cqspi_controller_init(cqspi);
> + cqspi->current_cs = -1;
> +
> + ret = devm_spi_register_master(dev, master);
> + if (ret) {
> + dev_err(&pdev->dev, "devm_spi_register_master failed.\n");
> + goto err_of;
> + }
> +
> + return 0;
> +
> +out_clk_disable:
> + clk_disable_unprepare(cqspi->clk);
> +err_of:
> + spi_master_put(master);
> + dev_err(&pdev->dev, "Cadence QSPI controller probe failed\n");
> + return ret;
> +}
> +
--
Regards
Vignesh
next prev parent reply other threads:[~2020-01-08 5:25 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-12-30 7:41 [PATCH v6 0/2] spi: cadence-quadpsi: Add support for the Cadence QSPI controller Ramuthevar,Vadivel MuruganX
2019-12-30 7:41 ` [PATCH v6 1/2] dt-bindings: spi: Add schema for Cadence QSPI Controller driver Ramuthevar,Vadivel MuruganX
2019-12-30 7:41 ` [PATCH v6 2/2] spi: cadence-quadpsi: Add support for the Cadence QSPI controller Ramuthevar,Vadivel MuruganX
2020-01-06 10:40 ` Vignesh Raghavendra
2020-01-06 11:19 ` Ramuthevar, Vadivel MuruganX
2020-01-08 5:14 ` Vignesh Raghavendra
2020-01-08 5:44 ` Ramuthevar, Vadivel MuruganX
2020-01-08 5:25 ` Vignesh Raghavendra [this message]
2020-01-08 5:55 ` Ramuthevar, Vadivel MuruganX
[not found] ` <20191230074102.50982-1-vadivel.muruganx.ramuthevar-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
2020-01-15 6:13 ` [PATCH v6 0/2] " Vignesh Raghavendra
2020-01-15 6:21 ` Ramuthevar, Vadivel MuruganX
[not found] ` <1aa6033a-c9e1-579b-0916-25037c07654d-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
2020-01-21 11:47 ` Ramuthevar, Vadivel MuruganX
2020-01-23 8:18 ` Vignesh Raghavendra
[not found] ` <860aecbc-22d3-c9ce-3570-44115d6e81b2-l0cyMroinI0@public.gmane.org>
2020-01-23 7:24 ` [EXT] " Kuldeep Singh
2020-01-23 7:47 ` Vignesh Raghavendra
2020-01-23 11:37 ` Kuldeep Singh
[not found] ` <AM6PR0402MB35573B2313C7FB81D747ABA6E00F0-Dzj3fuf2f4AsyWmSStHLuo3W/0Ik+aLCnBOFsp37pqbUKgpGm//BTAC/G2K4zDHf@public.gmane.org>
2020-01-27 4:21 ` Vignesh Raghavendra
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