mcspi

mcspi

[maxim maxim]

 Hi guys,
 I'm working with omap 3 spi driver, in the base I have mcspi driver
for tach device(http://processors.wiki.ti.com/index.php/AM335x_McSPI_Driver's_Guide),
I want to add my insmod driver for ublox 6(gps device). From ublox6
datasheet I saw what I need some initial delay between chip select
activation and data sending, I didn't find a way how to do it from
Linux SPI Framework, because of this I tried to write directly to some
registers what mapped in mcspi driver I can accept their mapped
address from contoller_data , but unfortunately it didn't work, may be
here you could give me some avices how I can do it.

Thanks ,
Kol
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Re: mcspi

[Gerhard Sittig]

On Sat, 2014-04-05 at 16:05 +0300, maxim maxim wrote:
> 
>  I'm working with omap 3 spi driver, in the base I have mcspi driver
> for tach device(http://processors.wiki.ti.com/index.php/AM335x_McSPI_Driver's_Guide),
> I want to add my insmod driver for ublox 6(gps device). From ublox6
> datasheet I saw what I need some initial delay between chip select
> activation and data sending, I didn't find a way how to do it from
> Linux SPI Framework, because of this I tried to write directly to some
> registers what mapped in mcspi driver I can accept their mapped
> address from contoller_data , but unfortunately it didn't work, may be
> here you could give me some avices how I can do it.

You might create an SPI message from multiple transfers, where
the first has no data (length zero) but specifies a delay.  If
the SPI controller's driver is implemented correctly, or if it
uses the SPI subsystem's common logic, this should result in the
desired pause between CS assertion and data transfer.

If it doesn't work out for you (when the driver cuts corners,
violates the API semantics, or tries to outsmart you), you may
want to fix that and provide patches. :)


virtually yours
Gerhard Sittig
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DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr. 5, D-82194 Groebenzell, Germany
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Re: mcspi

[maxim maxim]

Thanks Gerhard, good idea,  it's working fine for me:)

Best Regards,
Kol

2014-04-07 15:53 GMT+03:00 Gerhard Sittig <gsi-ynQEQJNshbs@public.gmane.org>:
> On Sat, 2014-04-05 at 16:05 +0300, maxim maxim wrote:
>>
>>  I'm working with omap 3 spi driver, in the base I have mcspi driver
>> for tach device(http://processors.wiki.ti.com/index.php/AM335x_McSPI_Driver's_Guide),
>> I want to add my insmod driver for ublox 6(gps device). From ublox6
>> datasheet I saw what I need some initial delay between chip select
>> activation and data sending, I didn't find a way how to do it from
>> Linux SPI Framework, because of this I tried to write directly to some
>> registers what mapped in mcspi driver I can accept their mapped
>> address from contoller_data , but unfortunately it didn't work, may be
>> here you could give me some avices how I can do it.
>
> You might create an SPI message from multiple transfers, where
> the first has no data (length zero) but specifies a delay.  If
> the SPI controller's driver is implemented correctly, or if it
> uses the SPI subsystem's common logic, this should result in the
> desired pause between CS assertion and data transfer.
>
> If it doesn't work out for you (when the driver cuts corners,
> violates the API semantics, or tries to outsmart you), you may
> want to fix that and provide patches. :)
>
>
> virtually yours
> Gerhard Sittig
> --
> DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
> HRB 165235 Munich, Office: Kirchenstr. 5, D-82194 Groebenzell, Germany
> Phone: +49-8142-66989-0 Fax: +49-8142-66989-80  Email: office-ynQEQJNshbs@public.gmane.org
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Re: mcspi

[Geert Uytterhoeven]

On Wed, Apr 9, 2014 at 6:40 PM, maxim maxim <look2004il-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> When I'm using with spi_sync(), while the master writes to MOSI, at
> the same time reads from MISO, doesn't it?

Yes it does.

Gr{oetje,eeting}s,

                        Geert

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when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds
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mcspi

[maxim maxim]

Hi all,

When I'm using with spi_sync(), while the master writes to MOSI, at
the same time reads from MISO, doesn't it?


Best Regards,

Kol
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