From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Pratyush Yadav <p.yadav@ti.com>
Cc: Mark Brown <broonie@kernel.org>, "R, Vignesh" <vigneshr@ti.com>,
juliensu@mxic.com.tw, ycllin@mxic.com.tw,
linux-spi <linux-spi@vger.kernel.org>,
MTD Maling List <linux-mtd@lists.infradead.org>,
Miquel Raynal <miquel.raynal@bootlin.com>,
zhengxunli <zhengxunli@mxic.com.tw>
Subject: Re: [PATCH v2 1/2] mtd: spi-nor: macronix: add support for Macronix octaflash
Date: Tue, 23 Feb 2021 19:07:37 +0100 [thread overview]
Message-ID: <CAMuHMdVQUCaiBwdU=KdFOu=D71kYbGqoqp9V3pLsXXE0AAdCog@mail.gmail.com> (raw)
In-Reply-To: <20210223152504.jtq4uxfepz7bdxhl@ti.com>
Hi Pratyush,
On Tue, Feb 23, 2021 at 4:25 PM Pratyush Yadav <p.yadav@ti.com> wrote:
> On 23/02/21 01:36PM, Mark Brown wrote:
> > On Tue, Feb 23, 2021 at 02:13:44PM +0100, Miquel Raynal wrote:
> > > Pratyush Yadav <p.yadav@ti.com> wrote on Fri, 5 Feb 2021 19:04:04 +0530:
> >
> > > > [0] Since SPI NOR has no way of knowing what speed the controller is
> > > > running at, assume the fastest speed the flash can run at.
> >
> > > Ok, I am not entirely clear about what is available/not available from
> > > the SPI core.
> >
> > > If this is true then I guess we can't do better with the current code
> > > base and this can be improved in the future if needed. So I'm fine with
> > > the current implementation.
> >
> > For normal SPI operations you can set the speed (really, top speed) on a
> > per transfer basis.
>
> To select the optimal number of dummy cycles we need to know what speed
> the controller is running at, not the other way around. The flash would
> always set the top speed to its maximum (say 200 MHz). But if the
> controller is only capable of running at 50 MHz, you will end up wasting
> dummy cycles. I don't see any API to communicate speed from controller
> to flash.
spi_transfer.effective_speed_hz?
If the driver has filled this in (after the first transfer), you can optimize
dummy cycles before doing the next transfer. Note that effective_speed_hz
might not always be the same, if e.g. the SPI controller shares its parent
clock with another component.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
next prev parent reply other threads:[~2021-02-23 18:08 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-05 9:36 [PATCH v2 0/2] Add octal DTR support for Macronix flash zhengxunli
2021-02-05 9:36 ` [PATCH v2 1/2] mtd: spi-nor: macronix: add support for Macronix octaflash zhengxunli
2021-02-05 9:47 ` Miquel Raynal
2021-02-05 13:34 ` Pratyush Yadav
2021-02-05 13:50 ` Miquel Raynal
2021-02-23 13:13 ` Miquel Raynal
2021-02-23 13:36 ` Mark Brown
2021-02-23 15:25 ` Pratyush Yadav
2021-02-23 18:07 ` Geert Uytterhoeven [this message]
2021-02-23 18:14 ` Mark Brown
[not found] ` <OF5890F10B.27BC3B4B-ON482586A7.001FE05B-482586A7.0024305D@mxic.com.tw>
2021-04-05 4:41 ` Tudor.Ambarus
2021-02-05 9:36 ` [PATCH v2 2/2] spi: mxic: patch for octal DTR mode support zhengxunli
2021-02-19 5:58 ` zhengxunli
2021-02-23 13:28 ` Mark Brown
2021-08-09 13:06 ` (subset) [PATCH v2 0/2] Add octal DTR support for Macronix flash Mark Brown
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