* [PATCH 5.15 1/2] spi: cadence-quadspi: fix write completion support
2022-04-27 10:54 [PATCH 5.15 0/2] ARM: socfpga: fix broken QuadSPI support Ian Abbott
@ 2022-04-27 10:54 ` Ian Abbott
2022-04-27 10:54 ` [PATCH 5.15 2/2] ARM: dts: socfpga: change qspi to "intel,socfpga-qspi" Ian Abbott
2022-04-29 9:05 ` [PATCH 5.15 0/2] ARM: socfpga: fix broken QuadSPI support Greg KH
2 siblings, 0 replies; 4+ messages in thread
From: Ian Abbott @ 2022-04-27 10:54 UTC (permalink / raw)
To: stable
Cc: linux-spi, devicetree, Dinh Nguyen, Mark Brown, Rob Herring,
Pratyush Yadav, Ian Abbott
From: Dinh Nguyen <dinguyen@kernel.org>
commit 98d948eb833104a094517401ed8be26ba3ce9935 upstream.
Some versions of the Cadence QSPI controller does not have the write
completion register implemented(CQSPI_REG_WR_COMPLETION_CTRL). On the
Intel SoCFPGA platform the CQSPI_REG_WR_COMPLETION_CTRL register is
not configured.
Add a quirk to not write to the CQSPI_REG_WR_COMPLETION_CTRL register.
Fixes: 9cb2ff111712 ("spi: cadence-quadspi: Disable Auto-HW polling)
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
Link: https://lore.kernel.org/r/20211108200854.3616121-1-dinguyen@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
[IA: backported for linux=5.15.y]
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
---
drivers/spi/spi-cadence-quadspi.c | 24 +++++++++++++++++++++---
1 file changed, 21 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c
index 1a6294a06e72..f7419511f4f6 100644
--- a/drivers/spi/spi-cadence-quadspi.c
+++ b/drivers/spi/spi-cadence-quadspi.c
@@ -36,6 +36,7 @@
/* Quirks */
#define CQSPI_NEEDS_WR_DELAY BIT(0)
#define CQSPI_DISABLE_DAC_MODE BIT(1)
+#define CQSPI_NO_SUPPORT_WR_COMPLETION BIT(3)
/* Capabilities */
#define CQSPI_SUPPORTS_OCTAL BIT(0)
@@ -83,6 +84,7 @@ struct cqspi_st {
u32 wr_delay;
bool use_direct_mode;
struct cqspi_flash_pdata f_pdata[CQSPI_MAX_CHIPSELECT];
+ bool wr_completion;
};
struct cqspi_driver_platdata {
@@ -797,9 +799,11 @@ static int cqspi_write_setup(struct cqspi_flash_pdata *f_pdata,
* polling on the controller's side. spinand and spi-nor will take
* care of polling the status register.
*/
- reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
- reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL;
- writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
+ if (cqspi->wr_completion) {
+ reg = readl(reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
+ reg |= CQSPI_REG_WR_DISABLE_AUTO_POLL;
+ writel(reg, reg_base + CQSPI_REG_WR_COMPLETION_CTRL);
+ }
reg = readl(reg_base + CQSPI_REG_SIZE);
reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
@@ -1517,6 +1521,10 @@ static int cqspi_probe(struct platform_device *pdev)
cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk);
master->max_speed_hz = cqspi->master_ref_clk_hz;
+
+ /* write completion is supported by default */
+ cqspi->wr_completion = true;
+
ddata = of_device_get_match_data(dev);
if (ddata) {
if (ddata->quirks & CQSPI_NEEDS_WR_DELAY)
@@ -1526,6 +1534,8 @@ static int cqspi_probe(struct platform_device *pdev)
master->mode_bits |= SPI_RX_OCTAL | SPI_TX_OCTAL;
if (!(ddata->quirks & CQSPI_DISABLE_DAC_MODE))
cqspi->use_direct_mode = true;
+ if (ddata->quirks & CQSPI_NO_SUPPORT_WR_COMPLETION)
+ cqspi->wr_completion = false;
}
ret = devm_request_irq(dev, irq, cqspi_irq_handler, 0,
@@ -1634,6 +1644,10 @@ static const struct cqspi_driver_platdata intel_lgm_qspi = {
.quirks = CQSPI_DISABLE_DAC_MODE,
};
+static const struct cqspi_driver_platdata socfpga_qspi = {
+ .quirks = CQSPI_NO_SUPPORT_WR_COMPLETION,
+};
+
static const struct of_device_id cqspi_dt_ids[] = {
{
.compatible = "cdns,qspi-nor",
@@ -1651,6 +1665,10 @@ static const struct of_device_id cqspi_dt_ids[] = {
.compatible = "intel,lgm-qspi",
.data = &intel_lgm_qspi,
},
+ {
+ .compatible = "intel,socfpga-qspi",
+ .data = (void *)&socfpga_qspi,
+ },
{ /* end of table */ }
};
--
2.35.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH 5.15 2/2] ARM: dts: socfpga: change qspi to "intel,socfpga-qspi"
2022-04-27 10:54 [PATCH 5.15 0/2] ARM: socfpga: fix broken QuadSPI support Ian Abbott
2022-04-27 10:54 ` [PATCH 5.15 1/2] spi: cadence-quadspi: fix write completion support Ian Abbott
@ 2022-04-27 10:54 ` Ian Abbott
2022-04-29 9:05 ` [PATCH 5.15 0/2] ARM: socfpga: fix broken QuadSPI support Greg KH
2 siblings, 0 replies; 4+ messages in thread
From: Ian Abbott @ 2022-04-27 10:54 UTC (permalink / raw)
To: stable
Cc: linux-spi, devicetree, Dinh Nguyen, Mark Brown, Rob Herring, Ian Abbott
From: Dinh Nguyen <dinguyen@kernel.org>
commit 36de991e93908f7ad5c2a0eac9c4ecf8b723fa4a upstream.
Because of commit 9cb2ff111712 ("spi: cadence-quadspi: Disable Auto-HW polling"),
which does a write to the CQSPI_REG_WR_COMPLETION_CTRL register
regardless of any condition. Well, the Cadence QuadSPI controller on
Intel's SoCFPGA platforms does not implement the
CQSPI_REG_WR_COMPLETION_CTRL register, thus a write to this register
results in a crash!
So starting with v5.16, I introduced the patch
98d948eb833 ("spi: cadence-quadspi: fix write completion support"),
which adds the dts compatible "intel,socfpga-qspi" that is specific for
versions that doesn't have the CQSPI_REG_WR_COMPLETION_CTRL register implemented.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
[IA: submitted for linux-5.15.y]
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
---
v3: revert back to "intel,socfpga-qspi"
v2: use both "cdns,qspi-nor" and "cdns,qspi-nor-0010"
---
arch/arm/boot/dts/socfpga.dtsi | 2 +-
arch/arm/boot/dts/socfpga_arria10.dtsi | 2 +-
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 2 +-
arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 0b021eef0b53..7c1d6423d7f8 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -782,7 +782,7 @@ ocram: sram@ffff0000 {
};
qspi: spi@ff705000 {
- compatible = "cdns,qspi-nor";
+ compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xff705000 0x1000>,
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index a574ea91d9d3..3ba431dfa8c9 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -756,7 +756,7 @@ usb0-ecc@ff8c8800 {
};
qspi: spi@ff809000 {
- compatible = "cdns,qspi-nor";
+ compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xff809000 0x100>,
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index d301ac0d406b..3ec301bd08a9 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -594,7 +594,7 @@ emac0-tx-ecc@ff8c0400 {
};
qspi: spi@ff8d2000 {
- compatible = "cdns,qspi-nor";
+ compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xff8d2000 0x100>,
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
index de1e98c99ec5..f4270cf18996 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
@@ -628,7 +628,7 @@ sdmmca-ecc@ff8c8c00 {
};
qspi: spi@ff8d2000 {
- compatible = "cdns,qspi-nor";
+ compatible = "intel,socfpga-qspi", "cdns,qspi-nor";
#address-cells = <1>;
#size-cells = <0>;
reg = <0xff8d2000 0x100>,
--
2.35.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH 5.15 0/2] ARM: socfpga: fix broken QuadSPI support
2022-04-27 10:54 [PATCH 5.15 0/2] ARM: socfpga: fix broken QuadSPI support Ian Abbott
2022-04-27 10:54 ` [PATCH 5.15 1/2] spi: cadence-quadspi: fix write completion support Ian Abbott
2022-04-27 10:54 ` [PATCH 5.15 2/2] ARM: dts: socfpga: change qspi to "intel,socfpga-qspi" Ian Abbott
@ 2022-04-29 9:05 ` Greg KH
2 siblings, 0 replies; 4+ messages in thread
From: Greg KH @ 2022-04-29 9:05 UTC (permalink / raw)
To: Ian Abbott
Cc: stable, linux-spi, devicetree, Dinh Nguyen, Mark Brown, Rob Herring
On Wed, Apr 27, 2022 at 11:54:05AM +0100, Ian Abbott wrote:
> Write support on the Cadence QSPI controller on the Intel SoCFPGA
> platform was broken by 9cb2ff111712 ("spi: cadence-quadspi: Disable
> Auto-HW polling) and fixed by 98d948eb8331 ("spi: cadence-quadspi: fix
> write completion support") and 36de991e9390 ("ARM: dts: socfpga: change
> qspi to "intel,socfpga-qspi").
>
> 1) spi: cadence-quadspi: fix write completion support
> 2) ARM: dts: socfpga: change qspi to "intel,socfpga-qspi"
>
> arch/arm/boot/dts/socfpga.dtsi | 2 +-
> arch/arm/boot/dts/socfpga_arria10.dtsi | 2 +-
> arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 2 +-
> arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 2 +-
> drivers/spi/spi-cadence-quadspi.c | 24 ++++++++++++++++++++---
> 5 files changed, 25 insertions(+), 7 deletions(-)
>
Both now queued up, thanks.
greg k-h
^ permalink raw reply [flat|nested] 4+ messages in thread