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From: Samuel Holland <samuel@sholland.org>
To: Chen-Yu Tsai <wens@csie.org>, Jernej Skrabec <jernej.skrabec@gmail.com>
Cc: Samuel Holland <samuel@sholland.org>,
	Gregory CLEMENT <gregory.clement@bootlin.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Rob Herring <robh+dt@kernel.org>,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-i2c@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-sunxi@lists.linux.dev
Subject: [PATCH 3/3] arm64: dts: allwinner: a100: Add I2C DMA requests
Date: Mon, 29 Aug 2022 21:08:24 -0500	[thread overview]
Message-ID: <20220830020824.62288-4-samuel@sholland.org> (raw)
In-Reply-To: <20220830020824.62288-1-samuel@sholland.org>

The I2C controllers in the A100 SoC are all connected to the DMA engine.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---

 arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
index 5453a3bb7d81..97e3e6907acd 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a100.dtsi
@@ -221,6 +221,8 @@ i2c0: i2c@5002000 {
 			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_BUS_I2C0>;
 			resets = <&ccu RST_BUS_I2C0>;
+			dmas = <&dma 43>, <&dma 43>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -234,6 +236,8 @@ i2c1: i2c@5002400 {
 			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_BUS_I2C1>;
 			resets = <&ccu RST_BUS_I2C1>;
+			dmas = <&dma 44>, <&dma 44>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -247,6 +251,8 @@ i2c2: i2c@5002800 {
 			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_BUS_I2C2>;
 			resets = <&ccu RST_BUS_I2C2>;
+			dmas = <&dma 45>, <&dma 45>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -260,6 +266,8 @@ i2c3: i2c@5002c00 {
 			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&ccu CLK_BUS_I2C3>;
 			resets = <&ccu RST_BUS_I2C3>;
+			dmas = <&dma 46>, <&dma 46>;
+			dma-names = "rx", "tx";
 			status = "disabled";
 			#address-cells = <1>;
 			#size-cells = <0>;
@@ -337,6 +345,8 @@ r_i2c0: i2c@7081400 {
 			interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&r_ccu CLK_R_APB2_I2C0>;
 			resets = <&r_ccu RST_R_APB2_I2C0>;
+			dmas = <&dma 50>, <&dma 50>;
+			dma-names = "rx", "tx";
 			pinctrl-names = "default";
 			pinctrl-0 = <&r_i2c0_pins>;
 			status = "disabled";
@@ -352,6 +362,8 @@ r_i2c1: i2c@7081800 {
 			interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&r_ccu CLK_R_APB2_I2C1>;
 			resets = <&r_ccu RST_R_APB2_I2C1>;
+			dmas = <&dma 51>, <&dma 51>;
+			dma-names = "rx", "tx";
 			pinctrl-names = "default";
 			pinctrl-0 = <&r_i2c1_pins>;
 			status = "disabled";
-- 
2.35.1


  parent reply	other threads:[~2022-08-30  2:08 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-30  2:08 [PATCH 0/3] DMA binding for Allwinner V536/newer I2C Samuel Holland
2022-08-30  2:08 ` [PATCH 1/3] dt-bindings: i2c: mv64xxx: Document DMA properties Samuel Holland
2022-08-30  9:36   ` Krzysztof Kozlowski
2022-08-30 13:10     ` Samuel Holland
2022-08-30 13:23       ` Krzysztof Kozlowski
2022-09-07 20:02   ` Wolfram Sang
2022-08-30  2:08 ` [PATCH 2/3] arm64: dts: allwinner: a100: Add device node for DMA controller Samuel Holland
2022-09-06 21:09   ` Jernej Škrabec
2022-09-08 20:01     ` Jernej Škrabec
2022-08-30  2:08 ` Samuel Holland [this message]
2022-09-06 21:11   ` [PATCH 3/3] arm64: dts: allwinner: a100: Add I2C DMA requests Jernej Škrabec
2022-09-08 20:01     ` Jernej Škrabec

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