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From: Rob Herring <robh@kernel.org>
To: Bjorn Helgaas <bhelgaas@google.com>,
	Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
	Jingoo Han <jingoohan1@gmail.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Binghui Wang <wangbinghui@hisilicon.com>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Fabio Estevam <festevam@gmail.com>,
	Jesper Nilsson <jesper.nilsson@axis.com>,
	Jonathan Chocron <jonnyc@amazon.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Kevin Hilman <khilman@baylibre.com>,
	Kishon Vijay Abraham I <kishon@ti.com>,
	Krzysztof Kozlowski <krzk@kernel.org>,
	Kukjin Kim <kgene@kernel.org>,
	Kunihiko Hayashi <hayashi.kunihiko@socionext.com>,
	linux-amlogic@lists.infradead.org, linux-arm-kernel@axis.com,
	linux-arm-kernel@lists.infradead.org,
	linux-arm-msm@vger.kernel.org, linux-omap@vger.kernel.org,
	linux-pci@vger.kernel.org, linux-samsung-soc@vger.kernel.org,
	linux-tegra@vger.kernel.org, Lucas Stach <l.stach@pengutronix.de>,
	Masahiro Yamada <yamada.masahiro@socionext.com>,
	Murali Karicheri <m-karicheri2@ti.com>,
	NXP Linux Team <linux-imx@nxp.com>,
	Pengutronix Kernel Team <kernel@pengutronix.de>,
	Pratyush Anand <pratyush.anand@gmail.com>,
	Richard Zhu <hongxing.zhu@nxp.com>,
	Sascha Hauer <s.hauer@pengutronix.de>,
	Shawn Guo <shawnguo@kernel.org>,
	Stanimir Varbanov <svarbanov@mm-sol.com>,
	Thierry Reding <thierry.reding@gmail.com>,
	Xiaowei Song <songxiaowei@hisilicon.com>,
	Yue Wang <yue.wang@Amlogic.com>
Subject: [RFC 03/27] PCI: dwc: Allow overriding bridge pci_ops
Date: Mon,  3 Aug 2020 15:00:52 -0600	[thread overview]
Message-ID: <20200803210116.3132633-4-robh@kernel.org> (raw)
In-Reply-To: <20200803210116.3132633-1-robh@kernel.org>

In preparation to allow drivers to set their own root and child pci_ops
instead of using the DWC specific config space ops, we need to make
the pci_host_bridge pointer available and move setting the bridge->ops
and bridge->child_ops pointer to before the .host_init() hook.

Cc: Jingoo Han <jingoohan1@gmail.com>
Cc: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Rob Herring <robh@kernel.org>
---
 drivers/pci/controller/dwc/pcie-designware-host.c | 15 ++++++++++-----
 drivers/pci/controller/dwc/pcie-designware.h      |  1 +
 2 files changed, 11 insertions(+), 5 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index 6232aefbbdb4..7cd8c9528d4c 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -344,6 +344,8 @@ int dw_pcie_host_init(struct pcie_port *pp)
 	if (!bridge)
 		return -ENOMEM;
 
+	pp->bridge = bridge;
+
 	ret = pci_parse_request_of_pci_ranges(dev, &bridge->windows,
 					      &bridge->dma_ranges, NULL);
 	if (ret)
@@ -450,6 +452,10 @@ int dw_pcie_host_init(struct pcie_port *pp)
 		}
 	}
 
+	/* Set default bus ops */
+	bridge->ops = &dw_pcie_ops;
+	bridge->child_ops = &dw_pcie_ops;
+
 	if (pp->ops->host_init) {
 		ret = pp->ops->host_init(pp);
 		if (ret)
@@ -461,7 +467,6 @@ int dw_pcie_host_init(struct pcie_port *pp)
 	bridge->dev.parent = dev;
 	bridge->sysdata = pp;
 	bridge->busnr = pp->root_bus_nr;
-	bridge->ops = &dw_pcie_ops;
 	bridge->map_irq = of_irq_parse_and_map_pci;
 	bridge->swizzle_irq = pci_common_swizzle;
 
@@ -667,11 +672,11 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
 	dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
 
 	/*
-	 * If the platform provides ->rd_other_conf, it means the platform
-	 * uses its own address translation component rather than ATU, so
-	 * we should not program the ATU here.
+	 * If the platform provides its own child bus config accesses, it means
+	 * the platform uses its own address translation component rather than
+	 * ATU, so we should not program the ATU here.
 	 */
-	if (!pp->ops->rd_other_conf) {
+	if (pp->bridge->child_ops == &dw_pcie_ops && !pp->ops->rd_other_conf) {
 		dw_pcie_prog_outbound_atu(pci, PCIE_ATU_REGION_INDEX0,
 					  PCIE_ATU_TYPE_MEM, pp->mem_base,
 					  pp->mem_bus_addr, pp->mem_size);
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 656e00f8fbeb..bad3cddab28e 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -201,6 +201,7 @@ struct pcie_port {
 	u32			num_vectors;
 	u32			irq_mask[MAX_MSI_CTRLS];
 	struct pci_bus		*root_bus;
+	struct pci_host_bridge  *bridge;
 	raw_spinlock_t		lock;
 	DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS);
 };
-- 
2.25.1


  parent reply	other threads:[~2020-08-03 21:01 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-03 21:00 [RFC 00/27] PCI: dwc: Driver clean-ups Rob Herring
2020-08-03 21:00 ` [RFC 01/27] PCI: Allow root and child buses to have different pci_ops Rob Herring
2020-08-03 21:00 ` [RFC 02/27] PCI: dwc: Use DBI accessors instead of own config accessors Rob Herring
2020-08-03 21:00 ` Rob Herring [this message]
2020-08-03 21:00 ` [RFC 04/27] PCI: dwc: Add a default pci_ops.map_bus for root port Rob Herring
2020-08-03 21:00 ` [RFC 05/27] PCI: dwc: al: Use pci_ops for child config space accessors Rob Herring
2020-08-03 21:00 ` [RFC 06/27] PCI: dwc: keystone: Use pci_ops for " Rob Herring
2020-08-03 21:00 ` [RFC 07/27] PCI: dwc: tegra: Use pci_ops for root " Rob Herring
2020-08-03 21:00 ` [RFC 08/27] PCI: dwc: meson: " Rob Herring
2020-08-03 21:00 ` [RFC 09/27] PCI: dwc: kirin: " Rob Herring
2020-08-03 21:00 ` [RFC 10/27] PCI: dwc: exynos: " Rob Herring
2020-08-03 21:01 ` [RFC 11/27] PCI: dwc: histb: " Rob Herring
2020-08-03 21:01 ` [RFC 12/27] PCI: dwc: Remove dwc specific config accessor ops Rob Herring
2020-08-03 21:01 ` [RFC 13/27] PCI: dwc: Use generic config accessors Rob Herring
2020-08-03 21:01 ` [RFC 14/27] PCI: Also call .add_bus() callback for root bus Rob Herring
2020-08-03 21:01 ` [RFC 15/27] PCI: dwc: keystone: Convert .scan_bus() callback to use add_bus Rob Herring
2020-08-03 21:01 ` [RFC 16/27] PCI: dwc: Convert to use pci_host_probe() Rob Herring
2020-08-03 21:01 ` [RFC 17/27] PCI: dwc: Remove root_bus pointer Rob Herring
2020-08-03 21:01 ` [RFC 18/27] PCI: dwc: Remove storing of PCI resources Rob Herring
2020-08-03 21:01 ` [RFC 19/27] PCI: dwc: Simplify config space handling Rob Herring
2020-08-03 21:01 ` [RFC 20/27] PCI: dwc/keystone: Drop duplicated 'num-viewport' Rob Herring
2020-08-03 21:01 ` [RFC 21/27] PCI: dwc: Check CONFIG_PCI_MSI inside dw_pcie_msi_init() Rob Herring
2020-08-03 21:01 ` [RFC 22/27] PCI: dwc/imx6: Remove duplicate define PCIE_LINK_WIDTH_SPEED_CONTROL Rob Herring
2020-08-03 21:01 ` [RFC 23/27] PCI: dwc/meson: Drop unnecessary RC config space initialization Rob Herring
2020-08-03 21:01 ` [RFC 24/27] PCI: dwc/meson: Rework PCI config and DW port logic register accesses Rob Herring
2020-08-03 21:01 ` [RFC 25/27] PCI: dwc/qcom: Use common PCI register definitions Rob Herring
2020-08-03 21:01 ` [RFC 26/27] PCI: dwc: Remove hardcoded PCI_CAP_ID_EXP offset Rob Herring
2020-08-03 21:01 ` [RFC 27/27] PCI: dwc/tegra: Use common Designware port logic register definitions Rob Herring

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