[PATCH 1/7] dt-bindings: arm: tegra: pmc: Improve property descriptions

[PATCH 1/7] dt-bindings: arm: tegra: pmc: Improve property descriptions

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Reformat the description of various properties to make them more
consistent with existing ones. Make use of json-schema's ability to
provide a description for individual list items to make improve the
documentation further.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 .../arm/tegra/nvidia,tegra20-pmc.yaml         | 215 +++++++++---------
 1 file changed, 104 insertions(+), 111 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
index 89191cfdf619..a90f01678775 100644
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
@@ -21,17 +21,14 @@ properties:
 
   reg:
     maxItems: 1
-    description:
-      Offset and length of the register set for the device.
+    description: Offset and length of the register set for the device.
 
   clock-names:
     items:
+      # Tegra clock of the same name
       - const: pclk
+      # 32 KHz clock input
       - const: clk32k_in
-    description:
-      Must includes entries pclk and clk32k_in.
-      pclk is the Tegra clock of that name and clk32k_in is 32KHz clock
-      input to Tegra.
 
   clocks:
     maxItems: 2
@@ -41,105 +38,103 @@ properties:
 
   '#clock-cells':
     const: 1
-    description:
-      Tegra PMC has clk_out_1, clk_out_2, and clk_out_3.
-      PMC also has blink control which allows 32Khz clock output to
-      Tegra blink pad.
-      Consumer of PMC clock should specify the desired clock by having
-      the clock ID in its "clocks" phandle cell with pmc clock provider.
-      See include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC
-      clock IDs.
+    description: |
+      Tegra PMC has clk_out_1, clk_out_2, and clk_out_3. PMC also has blink
+      control which allows 32Khz clock output to Tegra blink pad.
+
+      Consumer of PMC clock should specify the desired clock by having the
+      clock ID in its "clocks" phandle cell with PMC clock provider. See
+      include/dt-bindings/soc/tegra-pmc.h for the list of Tegra PMC clock IDs.
 
   '#interrupt-cells':
     const: 2
-    description:
-      Specifies number of cells needed to encode an interrupt source.
-      The value must be 2.
+    description: Specifies number of cells needed to encode an interrupt
+      source.
 
   interrupt-controller: true
 
   nvidia,invert-interrupt:
     $ref: /schemas/types.yaml#/definitions/flag
-    description: Inverts the PMU interrupt signal.
-      The PMU is an external Power Management Unit, whose interrupt output
-      signal is fed into the PMC. This signal is optionally inverted, and
-      then fed into the ARM GIC. The PMC is not involved in the detection
-      or handling of this interrupt signal, merely its inversion.
+    description: Inverts the PMU interrupt signal. The PMU is an external Power
+      Management Unit, whose interrupt output signal is fed into the PMC. This
+      signal is optionally inverted, and then fed into the ARM GIC. The PMC is
+      not involved in the detection or handling of this interrupt signal,
+      merely its inversion.
 
   nvidia,core-power-req-active-high:
     $ref: /schemas/types.yaml#/definitions/flag
-    description: Core power request active-high.
+    description: core power request active-high
 
   nvidia,sys-clock-req-active-high:
     $ref: /schemas/types.yaml#/definitions/flag
-    description: System clock request active-high.
+    description: system clock request active-high
 
   nvidia,combined-power-req:
     $ref: /schemas/types.yaml#/definitions/flag
-    description: combined power request for CPU and Core.
+    description: combined power request for CPU and core
 
   nvidia,cpu-pwr-good-en:
     $ref: /schemas/types.yaml#/definitions/flag
-    description:
-      CPU power good signal from external PMIC to PMC is enabled.
+    description: CPU power good signal from external PMIC to PMC is enabled
 
   nvidia,suspend-mode:
     $ref: /schemas/types.yaml#/definitions/uint32
-    enum: [0, 1, 2]
-    description:
-      The suspend mode that the platform should use.
-      Mode 0 is for LP0, CPU + Core voltage off and DRAM in self-refresh
-      Mode 1 is for LP1, CPU voltage off and DRAM in self-refresh
-      Mode 2 is for LP2, CPU voltage off
+    description: the suspend mode that the platform should use
+    oneOf:
+      - description: LP0, CPU + Core voltage off and DRAM in self-refresh
+        const: 0
+      - description: LP1, CPU voltage off and DRAM in self-refresh
+        const: 1
+      - description: LP2, CPU voltage off
+        const: 2
 
   nvidia,cpu-pwr-good-time:
     $ref: /schemas/types.yaml#/definitions/uint32
-    description: CPU power good time in uSec.
+    description: CPU power good time in microseconds
 
   nvidia,cpu-pwr-off-time:
     $ref: /schemas/types.yaml#/definitions/uint32
-    description: CPU power off time in uSec.
+    description: CPU power off time in microseconds
 
   nvidia,core-pwr-good-time:
     $ref: /schemas/types.yaml#/definitions/uint32-array
-    description:
-      <Oscillator-stable-time Power-stable-time>
-      Core power good time in uSec.
+    description: core power good time in microseconds
+    items:
+      - description: oscillator stable time
+      - description: power stable time
 
   nvidia,core-pwr-off-time:
     $ref: /schemas/types.yaml#/definitions/uint32
-    description: Core power off time in uSec.
+    description: core power off time in microseconds
 
   nvidia,lp0-vec:
     $ref: /schemas/types.yaml#/definitions/uint32-array
-    description:
-      <start length> Starting address and length of LP0 vector.
-      The LP0 vector contains the warm boot code that is executed
-      by AVP when resuming from the LP0 state.
-      The AVP (Audio-Video Processor) is an ARM7 processor and
-      always being the first boot processor when chip is power on
-      or resume from deep sleep mode. When the system is resumed
-      from the deep sleep mode, the warm boot code will restore
-      some PLLs, clocks and then brings up CPU0 for resuming the
-      system.
+    description: |
+      Starting address and length of LP0 vector. The LP0 vector contains the
+      warm boot code that is executed by AVP when resuming from the LP0 state.
+      The AVP (Audio-Video Processor) is an ARM7 processor and always being
+      the first boot processor when chip is power on or resume from deep sleep
+      mode. When the system is resumed from the deep sleep mode, the warm boot
+      code will restore some PLLs, clocks and then brings up CPU0 for resuming
+      the system.
+    items:
+      - description: starting address of LP0 vector
+      - description: length of LP0 vector
 
   core-supply:
-    description:
-      Phandle to voltage regulator connected to the SoC Core power rail.
+    description: phandle to voltage regulator connected to the SoC core power
+      rail
 
   core-domain:
     type: object
-    description: |
-      The vast majority of hardware blocks of Tegra SoC belong to a
-      Core power domain, which has a dedicated voltage rail that powers
-      the blocks.
-
+    description: The vast majority of hardware blocks of Tegra SoC belong to a
+      core power domain, which has a dedicated voltage rail that powers the
+      blocks.
     properties:
       operating-points-v2:
-        description:
-          Should contain level, voltages and opp-supported-hw property.
-          The supported-hw is a bitfield indicating SoC speedo or process
-          ID mask.
+        description: Should contain level, voltages and opp-supported-hw
+          property. The supported-hw is a bitfield indicating SoC speedo or
+          process ID mask.
 
       "#power-domain-cells":
         const: 0
@@ -152,37 +147,32 @@ properties:
 
   i2c-thermtrip:
     type: object
-    description:
-      On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode exists,
-      hardware-triggered thermal reset will be enabled.
-
+    description: On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode
+      exists, hardware-triggered thermal reset will be enabled.
     properties:
       nvidia,i2c-controller-id:
         $ref: /schemas/types.yaml#/definitions/uint32
-        description:
-          ID of I2C controller to send poweroff command to PMU.
-          Valid values are described in section 9.2.148
-          "APBDEV_PMC_SCRATCH53_0" of the Tegra K1 Technical Reference
-          Manual.
+        description: ID of I2C controller to send poweroff command to PMU.
+          Valid values are described in section 9.2.148 "APBDEV_PMC_SCRATCH53_0"
+          of the Tegra K1 Technical Reference Manual.
 
       nvidia,bus-addr:
         $ref: /schemas/types.yaml#/definitions/uint32
-        description: Bus address of the PMU on the I2C bus.
+        description: bus address of the PMU on the I2C bus
 
       nvidia,reg-addr:
         $ref: /schemas/types.yaml#/definitions/uint32
-        description: PMU I2C register address to issue poweroff command.
+        description: PMU I2C register address to issue poweroff command
 
       nvidia,reg-data:
         $ref: /schemas/types.yaml#/definitions/uint32
-        description: Poweroff command to write to PMU.
+        description: power-off command to write to PMU
 
       nvidia,pinmux-id:
         $ref: /schemas/types.yaml#/definitions/uint32
-        description:
-          Pinmux used by the hardware when issuing Poweroff command.
-          Defaults to 0. Valid values are described in section 12.5.2
-          "Pinmux Support" of the Tegra4 Technical Reference Manual.
+        description: Pinmux used by the hardware when issuing power-off command.
+          Defaults to 0. Valid values are described in section 12.5.2 "Pinmux
+          Support" of the Tegra4 Technical Reference Manual.
 
     required:
       - nvidia,i2c-controller-id
@@ -195,41 +185,44 @@ properties:
   powergates:
     type: object
     description: |
-      This node contains a hierarchy of power domain nodes, which should
-      match the powergates on the Tegra SoC. Each powergate node
-      represents a power-domain on the Tegra SoC that can be power-gated
-      by the Tegra PMC.
-      Hardware blocks belonging to a power domain should contain
-      "power-domains" property that is a phandle pointing to corresponding
-      powergate node.
-      The name of the powergate node should be one of the below. Note that
-      not every powergate is applicable to all Tegra devices and the following
-      list shows which powergates are applicable to which devices.
-      Please refer to Tegra TRM for mode details on the powergate nodes to
-      use for each power-gate block inside Tegra.
-      Name		Description			            Devices Applicable
-      3d		  3D Graphics			            Tegra20/114/124/210
-      3d0		  3D Graphics 0		            Tegra30
-      3d1		  3D Graphics 1		            Tegra30
-      aud		  Audio				                Tegra210
-      dfd		  Debug				                Tegra210
-      dis		  Display A			              Tegra114/124/210
-      disb		Display B			              Tegra114/124/210
-      heg		  2D Graphics		            	Tegra30/114/124/210
-      iram		Internal RAM		            Tegra124/210
-      mpe		  MPEG Encode			            All
-      nvdec		NVIDIA Video Decode Engine	Tegra210
-      nvjpg		NVIDIA JPEG Engine		      Tegra210
-      pcie		PCIE				                Tegra20/30/124/210
-      sata		SATA				                Tegra30/124/210
-      sor		  Display interfaces       		Tegra124/210
-      ve2		  Video Encode Engine 2		    Tegra210
-      venc		Video Encode Engine		      All
-      vdec		Video Decode Engine		      Tegra20/30/114/124
-      vic		  Video Imaging Compositor	  Tegra124/210
-      xusba		USB Partition A			        Tegra114/124/210
-      xusbb		USB Partition B 		        Tegra114/124/210
-      xusbc		USB Partition C			        Tegra114/124/210
+      This node contains a hierarchy of power domain nodes, which should match
+      the powergates on the Tegra SoC. Each powergate node represents a power-
+      domain on the Tegra SoC that can be power-gated by the Tegra PMC.
+
+      Hardware blocks belonging to a power domain should contain "power-domains"
+      property that is a phandle pointing to corresponding powergate node.
+
+      The name of the powergate node should be one of the below. Note that not
+      every powergate is applicable to all Tegra devices and the following list
+      shows which powergates are applicable to which devices.
+
+      Please refer to Tegra TRM for mode details on the powergate nodes to use
+      for each power-gate block inside Tegra.
+
+        Name     Description                   Devices Applicable
+        --------------------------------------------------------------
+        3d       3D Graphics                   Tegra20/114/124/210
+        3d0      3D Graphics 0                 Tegra30
+        3d1      3D Graphics 1                 Tegra30
+        aud      Audio                         Tegra210
+        dfd      Debug                         Tegra210
+        dis      Display A                     Tegra114/124/210
+        disb     Display B                     Tegra114/124/210
+        heg      2D Graphics                   Tegra30/114/124/210
+        iram     Internal RAM                  Tegra124/210
+        mpe      MPEG Encode                   All
+        nvdec    NVIDIA Video Decode Engine    Tegra210
+        nvjpg    NVIDIA JPEG Engine            Tegra210
+        pcie     PCIE                          Tegra20/30/124/210
+        sata     SATA                          Tegra30/124/210
+        sor      Display interfaces            Tegra124/210
+        ve2      Video Encode Engine 2         Tegra210
+        venc     Video Encode Engine           All
+        vdec     Video Decode Engine           Tegra20/30/114/124
+        vic      Video Imaging Compositor      Tegra124/210
+        xusba    USB Partition A               Tegra114/124/210
+        xusbb    USB Partition B               Tegra114/124/210
+        xusbc    USB Partition C               Tegra114/124/210
 
     patternProperties:
       "^[a-z0-9]+$":
-- 
2.41.0

[PATCH 2/7] dt-bindings: arm: tegra: pmc: Remove useless boilerplate descriptions

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

The descriptions for the clocks and resets properties are no longer
useful in the context of json-schema, so drop them.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 .../bindings/arm/tegra/nvidia,tegra20-pmc.yaml        | 11 -----------
 1 file changed, 11 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
index a90f01678775..c5a1ae44c5e3 100644
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
@@ -32,9 +32,6 @@ properties:
 
   clocks:
     maxItems: 2
-    description:
-      Must contain an entry for each entry in clock-names.
-      See ../clocks/clocks-bindings.txt for details.
 
   '#clock-cells':
     const: 1
@@ -233,18 +230,10 @@ properties:
           clocks:
             minItems: 1
             maxItems: 8
-            description:
-              Must contain an entry for each clock required by the PMC
-              for controlling a power-gate.
-              See ../clocks/clock-bindings.txt document for more details.
 
           resets:
             minItems: 1
             maxItems: 8
-            description:
-              Must contain an entry for each reset required by the PMC
-              for controlling a power-gate.
-              See ../reset/reset.txt for more details.
 
           power-domains:
             maxItems: 1
-- 
2.41.0

[PATCH 3/7] dt-bindings: arm: tegra: pmc: Move additionalProperties

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

For indented subschemas it can be difficult to understand which block an
additionalProperties property belongs to. Moving it closer to the
beginning of a block is a good way to clarify this.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 .../bindings/arm/tegra/nvidia,tegra20-pmc.yaml         | 10 +++-------
 1 file changed, 3 insertions(+), 7 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
index c5a1ae44c5e3..1d8b99938323 100644
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
@@ -127,6 +127,7 @@ properties:
     description: The vast majority of hardware blocks of Tegra SoC belong to a
       core power domain, which has a dedicated voltage rail that powers the
       blocks.
+    additionalProperties: false
     properties:
       operating-points-v2:
         description: Should contain level, voltages and opp-supported-hw
@@ -140,12 +141,11 @@ properties:
       - operating-points-v2
       - "#power-domain-cells"
 
-    additionalProperties: false
-
   i2c-thermtrip:
     type: object
     description: On Tegra30, Tegra114 and Tegra124 if i2c-thermtrip subnode
       exists, hardware-triggered thermal reset will be enabled.
+    additionalProperties: false
     properties:
       nvidia,i2c-controller-id:
         $ref: /schemas/types.yaml#/definitions/uint32
@@ -177,10 +177,9 @@ properties:
       - nvidia,reg-addr
       - nvidia,reg-data
 
-    additionalProperties: false
-
   powergates:
     type: object
+    additionalProperties: false
     description: |
       This node contains a hierarchy of power domain nodes, which should match
       the powergates on the Tegra SoC. Each powergate node represents a power-
@@ -225,7 +224,6 @@ properties:
       "^[a-z0-9]+$":
         type: object
         additionalProperties: false
-
         properties:
           clocks:
             minItems: 1
@@ -247,8 +245,6 @@ properties:
           - resets
           - '#power-domain-cells'
 
-    additionalProperties: false
-
 patternProperties:
   "^[a-f0-9]+-[a-f0-9]+$":
     type: object
-- 
2.41.0

[PATCH 4/7] dt-bindings: arm: tegra: pmc: Increase maximum number of clocks per powergate

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Some powergate definitions need more than 8 clocks, so bump the number
up to 10, which is the current maximum in any known device tree file.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 .../devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml       | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
index 1d8b99938323..82070d47ac7c 100644
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
@@ -227,7 +227,7 @@ properties:
         properties:
           clocks:
             minItems: 1
-            maxItems: 8
+            maxItems: 10
 
           resets:
             minItems: 1
-- 
2.41.0

[PATCH 5/7] dt-bindings: arm: tegra: pmc: Restructure pad configuration node schema

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

The pad configuration node schema in its current form can accidentally
match other properties as well. Restructure the schema to better match
how the device trees are using these.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 .../arm/tegra/nvidia,tegra20-pmc.yaml         | 181 ++++++++++++------
 1 file changed, 120 insertions(+), 61 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
index 82070d47ac7c..271aa8f80a65 100644
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
@@ -245,69 +245,82 @@ properties:
           - resets
           - '#power-domain-cells'
 
-patternProperties:
-  "^[a-f0-9]+-[a-f0-9]+$":
+  pinmux:
     type: object
-    description:
-      This is a Pad configuration node. On Tegra SOCs a pad is a set of
-      pins which are configured as a group. The pin grouping is a fixed
-      attribute of the hardware. The PMC can be used to set pad power state
-      and signaling voltage. A pad can be either in active or power down mode.
-      The support for power state and signaling voltage configuration varies
-      depending on the pad in question. 3.3V and 1.8V signaling voltages
-      are supported on pins where software controllable signaling voltage
-      switching is available.
-
-      The pad configuration state nodes are placed under the pmc node and they
-      are referred to by the pinctrl client properties. For more information
-      see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
-      The pad name should be used as the value of the pins property in pin
-      configuration nodes.
-
-      The following pads are present on Tegra124 and Tegra132
-      audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi, hsic,
-      hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, pex-cntrl,
-      sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2, usb_bias.
-
-      The following pads are present on Tegra210
-      audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg,
-      debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, hdmi,
-      hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
-      sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias.
-
     properties:
-      pins:
-        $ref: /schemas/types.yaml#/definitions/string
-        description: Must contain name of the pad(s) to be configured.
-
-      low-power-enable:
-        $ref: /schemas/types.yaml#/definitions/flag
-        description: Configure the pad into power down mode.
-
-      low-power-disable:
-        $ref: /schemas/types.yaml#/definitions/flag
-        description: Configure the pad into active mode.
-
-      power-source:
-        $ref: /schemas/types.yaml#/definitions/uint32
-        description:
-          Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
-          TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
-          The values are defined in
-          include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
-          Power state can be configured on all Tegra124 and Tegra132
-          pads. None of the Tegra124 or Tegra132 pads support signaling
-          voltage switching.
-          All of the listed Tegra210 pads except pex-cntrl support power
-          state configuration. Signaling voltage switching is supported
-          on below Tegra210 pads.
-          audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1,
-          sdmmc3, spi, spi-hv, and uart.
-
-    required:
-      - pins
-
-    additionalProperties: false
+      status: true
+
+    additionalProperties:
+      type: object
+      description: |
+        This is a pad configuration node. On Tegra SoCs a pad is a set of pins
+        which are configured as a group. The pin grouping is a fixed attribute
+        of the hardware. The PMC can be used to set pad power state and
+        signaling voltage. A pad can be either in active or power down mode.
+        The support for power state and signaling voltage configuration varies
+        depending on the pad in question. 3.3V and 1.8V signaling voltages are
+        supported on pins where software controllable signaling voltage
+        switching is available.
+
+        The pad configuration state nodes are placed under the pmc node and
+        they are referred to by the pinctrl client properties. For more
+        information see:
+
+          Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
+
+        The pad name should be used as the value of the pins property in pin
+        configuration nodes.
+
+        The following pads are present on Tegra124 and Tegra132:
+
+          audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi,
+          hsic, hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2,
+          pex-cntrl, sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2,
+          usb_bias
+
+        The following pads are present on Tegra210:
+
+          audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg,
+          debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio,
+          hdmi, hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl,
+          sdmmc1, sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias
+      additionalProperties: false
+      properties:
+        pins:
+          $ref: /schemas/types.yaml#/definitions/string-array
+          description: Must contain name of the pad(s) to be configured.
+
+        low-power-enable:
+          $ref: /schemas/types.yaml#/definitions/flag
+          description: Configure the pad into power down mode.
+
+        low-power-disable:
+          $ref: /schemas/types.yaml#/definitions/flag
+          description: Configure the pad into active mode.
+
+        power-source:
+          $ref: /schemas/types.yaml#/definitions/uint32
+          description: |
+            Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
+            TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages. The
+            values are defined in:
+
+              include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h
+
+            Power state can be configured on all Tegra124 and Tegra132 pads.
+            None of the Tegra124 or Tegra132 pads support signaling voltage
+            switching. All of the listed Tegra210 pads except pex-cntrl support
+            power state configuration. Signaling voltage switching is supported
+            on the following Tegra210 pads:
+
+              audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1, sdmmc3,
+              spi, spi-hv, uart
+
+        phandle:
+          $ref: /schemas/types.yaml#/definitions/uint32
+
+      required:
+        - pins
 
 required:
   - compatible
@@ -316,6 +329,52 @@ required:
   - clocks
   - '#clock-cells'
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: nvidia,tegra124-pmc
+    then:
+      properties:
+        pinmux:
+          properties:
+            status: true
+
+          additionalProperties:
+            type: object
+            properties:
+              pins:
+                items:
+                  enum: [ audio, bb, cam, comp, csia, csb, cse, dsi, dsib,
+                          dsic, dsid, hdmi, hsic, hv, lvds, mipi-bias, nand,
+                          pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
+                          sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2,
+                          usb_bias ]
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: nvidia,tegra210-pmc
+    then:
+      properties:
+        pinmux:
+          properties:
+            status: true
+
+          additionalProperties:
+            type: object
+            properties:
+              pins:
+                items:
+                  enum: [ audio, audio-hv, cam, csia, csib, csic, csid, csie,
+                          csif, dbg, debug-nonao, dmic, dp, dsi, dsib, dsic,
+                          dsid, emmc, emmc2, gpio, hdmi, hsic, lvds, mipi-bias,
+                          pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
+                          sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3,
+                          usb-bias ]
+
 additionalProperties: false
 
 dependencies:
-- 
2.41.0

[PATCH 6/7] dt-bindings: arm: tegra: pmc: Reformat example

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Reformat the example using 4 spaces for indentation.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 .../arm/tegra/nvidia,tegra20-pmc.yaml         | 77 +++++++++----------
 1 file changed, 38 insertions(+), 39 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
index 271aa8f80a65..f709a4a0853c 100644
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
+++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
@@ -384,47 +384,46 @@ dependencies:
 
 examples:
   - |
-
     #include <dt-bindings/clock/tegra210-car.h>
     #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
     #include <dt-bindings/soc/tegra-pmc.h>
 
-    tegra_pmc: pmc@7000e400 {
-              compatible = "nvidia,tegra210-pmc";
-              reg = <0x7000e400 0x400>;
-              core-supply = <&regulator>;
-              clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
-              clock-names = "pclk", "clk32k_in";
-              #clock-cells = <1>;
-
-              nvidia,invert-interrupt;
-              nvidia,suspend-mode = <0>;
-              nvidia,cpu-pwr-good-time = <0>;
-              nvidia,cpu-pwr-off-time = <0>;
-              nvidia,core-pwr-good-time = <4587 3876>;
-              nvidia,core-pwr-off-time = <39065>;
-              nvidia,core-power-req-active-high;
-              nvidia,sys-clock-req-active-high;
-
-              pd_core: core-domain {
-                      operating-points-v2 = <&core_opp_table>;
-                      #power-domain-cells = <0>;
-              };
-
-              powergates {
-                    pd_audio: aud {
-                            clocks = <&tegra_car TEGRA210_CLK_APE>,
-                                     <&tegra_car TEGRA210_CLK_APB2APE>;
-                            resets = <&tegra_car 198>;
-                            power-domains = <&pd_core>;
-                            #power-domain-cells = <0>;
-                    };
-
-                    pd_xusbss: xusba {
-                            clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
-                            resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
-                            power-domains = <&pd_core>;
-                            #power-domain-cells = <0>;
-                    };
-              };
+    pmc@7000e400 {
+        compatible = "nvidia,tegra210-pmc";
+        reg = <0x7000e400 0x400>;
+        core-supply = <&regulator>;
+        clocks = <&tegra_car TEGRA210_CLK_PCLK>, <&clk32k_in>;
+        clock-names = "pclk", "clk32k_in";
+        #clock-cells = <1>;
+
+        nvidia,invert-interrupt;
+        nvidia,suspend-mode = <0>;
+        nvidia,cpu-pwr-good-time = <0>;
+        nvidia,cpu-pwr-off-time = <0>;
+        nvidia,core-pwr-good-time = <4587 3876>;
+        nvidia,core-pwr-off-time = <39065>;
+        nvidia,core-power-req-active-high;
+        nvidia,sys-clock-req-active-high;
+
+        pd_core: core-domain {
+            operating-points-v2 = <&core_opp_table>;
+            #power-domain-cells = <0>;
+        };
+
+        powergates {
+            pd_audio: aud {
+                clocks = <&tegra_car TEGRA210_CLK_APE>,
+                         <&tegra_car TEGRA210_CLK_APB2APE>;
+                resets = <&tegra_car 198>;
+                power-domains = <&pd_core>;
+                #power-domain-cells = <0>;
+            };
+
+            pd_xusbss: xusba {
+                clocks = <&tegra_car TEGRA210_CLK_XUSB_SS>;
+                resets = <&tegra_car TEGRA210_CLK_XUSB_SS>;
+                power-domains = <&pd_core>;
+                #power-domain-cells = <0>;
+            };
+        };
     };
-- 
2.41.0

[PATCH 7/7] dt-bindings: arm: tegra: pmc: Relicense and move into soc/tegra directory

[Thierry Reding]

From: Thierry Reding <treding@nvidia.com>

Dual-license this binding for consistency with other Tegra bindings and
move it into the soc/tegra directory.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 .../bindings/{arm => soc}/tegra/nvidia,tegra20-pmc.yaml       | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
 rename Documentation/devicetree/bindings/{arm => soc}/tegra/nvidia,tegra20-pmc.yaml (99%)

diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-pmc.yaml
similarity index 99%
rename from Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
rename to Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-pmc.yaml
index f709a4a0853c..ef42f07e0572 100644
--- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
+++ b/Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-pmc.yaml
@@ -1,7 +1,7 @@
-# SPDX-License-Identifier: GPL-2.0
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra20-pmc.yaml#
+$id: http://devicetree.org/schemas/soc/tegra/nvidia,tegra20-pmc.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: Tegra Power Management Controller (PMC)
-- 
2.41.0

Re: [PATCH 1/7] dt-bindings: arm: tegra: pmc: Improve property descriptions

[Rob Herring]

On Fri, Jul 07, 2023 at 03:17:05PM +0200, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> Reformat the description of various properties to make them more
> consistent with existing ones. Make use of json-schema's ability to
> provide a description for individual list items to make improve the
> documentation further.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  .../arm/tegra/nvidia,tegra20-pmc.yaml         | 215 +++++++++---------
>  1 file changed, 104 insertions(+), 111 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
> index 89191cfdf619..a90f01678775 100644
> --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
> +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
> @@ -21,17 +21,14 @@ properties:
>  
>    reg:
>      maxItems: 1
> -    description:
> -      Offset and length of the register set for the device.
> +    description: Offset and length of the register set for the device.

nit: I'd add this to patch 2.

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH 2/7] dt-bindings: arm: tegra: pmc: Remove useless boilerplate descriptions

[Rob Herring]

On Fri, 07 Jul 2023 15:17:06 +0200, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> The descriptions for the clocks and resets properties are no longer
> useful in the context of json-schema, so drop them.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  .../bindings/arm/tegra/nvidia,tegra20-pmc.yaml        | 11 -----------
>  1 file changed, 11 deletions(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH 3/7] dt-bindings: arm: tegra: pmc: Move additionalProperties

[Rob Herring]

On Fri, 07 Jul 2023 15:17:07 +0200, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> For indented subschemas it can be difficult to understand which block an
> additionalProperties property belongs to. Moving it closer to the
> beginning of a block is a good way to clarify this.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  .../bindings/arm/tegra/nvidia,tegra20-pmc.yaml         | 10 +++-------
>  1 file changed, 3 insertions(+), 7 deletions(-)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH 4/7] dt-bindings: arm: tegra: pmc: Increase maximum number of clocks per powergate

[Rob Herring]

On Fri, 07 Jul 2023 15:17:08 +0200, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> Some powergate definitions need more than 8 clocks, so bump the number
> up to 10, which is the current maximum in any known device tree file.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  .../devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml       | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH 5/7] dt-bindings: arm: tegra: pmc: Restructure pad configuration node schema

[Rob Herring]

On Fri, Jul 07, 2023 at 03:17:09PM +0200, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> The pad configuration node schema in its current form can accidentally
> match other properties as well. Restructure the schema to better match
> how the device trees are using these.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  .../arm/tegra/nvidia,tegra20-pmc.yaml         | 181 ++++++++++++------
>  1 file changed, 120 insertions(+), 61 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
> index 82070d47ac7c..271aa8f80a65 100644
> --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
> +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
> @@ -245,69 +245,82 @@ properties:
>            - resets
>            - '#power-domain-cells'
>  
> -patternProperties:
> -  "^[a-f0-9]+-[a-f0-9]+$":
> +  pinmux:
>      type: object
> -    description:
> -      This is a Pad configuration node. On Tegra SOCs a pad is a set of
> -      pins which are configured as a group. The pin grouping is a fixed
> -      attribute of the hardware. The PMC can be used to set pad power state
> -      and signaling voltage. A pad can be either in active or power down mode.
> -      The support for power state and signaling voltage configuration varies
> -      depending on the pad in question. 3.3V and 1.8V signaling voltages
> -      are supported on pins where software controllable signaling voltage
> -      switching is available.
> -
> -      The pad configuration state nodes are placed under the pmc node and they
> -      are referred to by the pinctrl client properties. For more information
> -      see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
> -      The pad name should be used as the value of the pins property in pin
> -      configuration nodes.
> -
> -      The following pads are present on Tegra124 and Tegra132
> -      audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi, hsic,
> -      hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, pex-cntrl,
> -      sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2, usb_bias.
> -
> -      The following pads are present on Tegra210
> -      audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg,
> -      debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, hdmi,
> -      hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
> -      sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias.
> -
>      properties:
> -      pins:
> -        $ref: /schemas/types.yaml#/definitions/string
> -        description: Must contain name of the pad(s) to be configured.
> -
> -      low-power-enable:
> -        $ref: /schemas/types.yaml#/definitions/flag
> -        description: Configure the pad into power down mode.
> -
> -      low-power-disable:
> -        $ref: /schemas/types.yaml#/definitions/flag
> -        description: Configure the pad into active mode.
> -
> -      power-source:
> -        $ref: /schemas/types.yaml#/definitions/uint32
> -        description:
> -          Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
> -          TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
> -          The values are defined in
> -          include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
> -          Power state can be configured on all Tegra124 and Tegra132
> -          pads. None of the Tegra124 or Tegra132 pads support signaling
> -          voltage switching.
> -          All of the listed Tegra210 pads except pex-cntrl support power
> -          state configuration. Signaling voltage switching is supported
> -          on below Tegra210 pads.
> -          audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1,
> -          sdmmc3, spi, spi-hv, and uart.
> -
> -    required:
> -      - pins
> -
> -    additionalProperties: false
> +      status: true

If you need this, that's a bug in dtschema.

> +
> +    additionalProperties:
> +      type: object
> +      description: |
> +        This is a pad configuration node. On Tegra SoCs a pad is a set of pins
> +        which are configured as a group. The pin grouping is a fixed attribute
> +        of the hardware. The PMC can be used to set pad power state and
> +        signaling voltage. A pad can be either in active or power down mode.
> +        The support for power state and signaling voltage configuration varies
> +        depending on the pad in question. 3.3V and 1.8V signaling voltages are
> +        supported on pins where software controllable signaling voltage
> +        switching is available.
> +
> +        The pad configuration state nodes are placed under the pmc node and
> +        they are referred to by the pinctrl client properties. For more
> +        information see:
> +
> +          Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
> +
> +        The pad name should be used as the value of the pins property in pin
> +        configuration nodes.
> +
> +        The following pads are present on Tegra124 and Tegra132:
> +
> +          audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi,
> +          hsic, hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2,
> +          pex-cntrl, sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2,
> +          usb_bias
> +
> +        The following pads are present on Tegra210:
> +
> +          audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg,
> +          debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio,
> +          hdmi, hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl,
> +          sdmmc1, sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias
> +      additionalProperties: false
> +      properties:
> +        pins:
> +          $ref: /schemas/types.yaml#/definitions/string-array
> +          description: Must contain name of the pad(s) to be configured.
> +
> +        low-power-enable:
> +          $ref: /schemas/types.yaml#/definitions/flag
> +          description: Configure the pad into power down mode.
> +
> +        low-power-disable:
> +          $ref: /schemas/types.yaml#/definitions/flag
> +          description: Configure the pad into active mode.
> +
> +        power-source:
> +          $ref: /schemas/types.yaml#/definitions/uint32
> +          description: |
> +            Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
> +            TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages. The
> +            values are defined in:
> +
> +              include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h
> +
> +            Power state can be configured on all Tegra124 and Tegra132 pads.
> +            None of the Tegra124 or Tegra132 pads support signaling voltage
> +            switching. All of the listed Tegra210 pads except pex-cntrl support
> +            power state configuration. Signaling voltage switching is supported
> +            on the following Tegra210 pads:
> +
> +              audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1, sdmmc3,
> +              spi, spi-hv, uart
> +
> +        phandle:
> +          $ref: /schemas/types.yaml#/definitions/uint32

ditto

> +
> +      required:
> +        - pins
>  
>  required:
>    - compatible
> @@ -316,6 +329,52 @@ required:
>    - clocks
>    - '#clock-cells'
>  
> +allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: nvidia,tegra124-pmc
> +    then:
> +      properties:
> +        pinmux:
> +          properties:
> +            status: true
> +
> +          additionalProperties:
> +            type: object
> +            properties:
> +              pins:
> +                items:
> +                  enum: [ audio, bb, cam, comp, csia, csb, cse, dsi, dsib,
> +                          dsic, dsid, hdmi, hsic, hv, lvds, mipi-bias, nand,
> +                          pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
> +                          sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2,
> +                          usb_bias ]
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            const: nvidia,tegra210-pmc
> +    then:
> +      properties:
> +        pinmux:
> +          properties:
> +            status: true
> +
> +          additionalProperties:
> +            type: object
> +            properties:
> +              pins:
> +                items:
> +                  enum: [ audio, audio-hv, cam, csia, csib, csic, csid, csie,
> +                          csif, dbg, debug-nonao, dmic, dp, dsi, dsib, dsic,
> +                          dsid, emmc, emmc2, gpio, hdmi, hsic, lvds, mipi-bias,
> +                          pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
> +                          sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3,
> +                          usb-bias ]
> +
>  additionalProperties: false
>  
>  dependencies:
> -- 
> 2.41.0
> 

Re: [PATCH 6/7] dt-bindings: arm: tegra: pmc: Reformat example

[Rob Herring]

On Fri, 07 Jul 2023 15:17:10 +0200, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> Reformat the example using 4 spaces for indentation.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  .../arm/tegra/nvidia,tegra20-pmc.yaml         | 77 +++++++++----------
>  1 file changed, 38 insertions(+), 39 deletions(-)
> 

Acked-by: Rob Herring <robh@kernel.org>

Re: [PATCH 7/7] dt-bindings: arm: tegra: pmc: Relicense and move into soc/tegra directory

[Rob Herring]

On Fri, 07 Jul 2023 15:17:11 +0200, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> Dual-license this binding for consistency with other Tegra bindings and
> move it into the soc/tegra directory.
> 
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
>  .../bindings/{arm => soc}/tegra/nvidia,tegra20-pmc.yaml       | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>  rename Documentation/devicetree/bindings/{arm => soc}/tegra/nvidia,tegra20-pmc.yaml (99%)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH 1/7] dt-bindings: arm: tegra: pmc: Improve property descriptions

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 1364 bytes --]

On Fri, Jul 07, 2023 at 04:29:41PM -0600, Rob Herring wrote:
> On Fri, Jul 07, 2023 at 03:17:05PM +0200, Thierry Reding wrote:
> > From: Thierry Reding <treding@nvidia.com>
> > 
> > Reformat the description of various properties to make them more
> > consistent with existing ones. Make use of json-schema's ability to
> > provide a description for individual list items to make improve the
> > documentation further.
> > 
> > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > ---
> >  .../arm/tegra/nvidia,tegra20-pmc.yaml         | 215 +++++++++---------
> >  1 file changed, 104 insertions(+), 111 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
> > index 89191cfdf619..a90f01678775 100644
> > --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
> > +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
> > @@ -21,17 +21,14 @@ properties:
> >  
> >    reg:
> >      maxItems: 1
> > -    description:
> > -      Offset and length of the register set for the device.
> > +    description: Offset and length of the register set for the device.
> 
> nit: I'd add this to patch 2.
> 
> Reviewed-by: Rob Herring <robh@kernel.org>

Indeed, makes sense.

Thierry

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

Re: [PATCH 5/7] dt-bindings: arm: tegra: pmc: Restructure pad configuration node schema

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 9483 bytes --]

On Fri, Jul 07, 2023 at 04:35:03PM -0600, Rob Herring wrote:
> On Fri, Jul 07, 2023 at 03:17:09PM +0200, Thierry Reding wrote:
> > From: Thierry Reding <treding@nvidia.com>
> > 
> > The pad configuration node schema in its current form can accidentally
> > match other properties as well. Restructure the schema to better match
> > how the device trees are using these.
> > 
> > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > ---
> >  .../arm/tegra/nvidia,tegra20-pmc.yaml         | 181 ++++++++++++------
> >  1 file changed, 120 insertions(+), 61 deletions(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
> > index 82070d47ac7c..271aa8f80a65 100644
> > --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
> > +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
> > @@ -245,69 +245,82 @@ properties:
> >            - resets
> >            - '#power-domain-cells'
> >  
> > -patternProperties:
> > -  "^[a-f0-9]+-[a-f0-9]+$":
> > +  pinmux:
> >      type: object
> > -    description:
> > -      This is a Pad configuration node. On Tegra SOCs a pad is a set of
> > -      pins which are configured as a group. The pin grouping is a fixed
> > -      attribute of the hardware. The PMC can be used to set pad power state
> > -      and signaling voltage. A pad can be either in active or power down mode.
> > -      The support for power state and signaling voltage configuration varies
> > -      depending on the pad in question. 3.3V and 1.8V signaling voltages
> > -      are supported on pins where software controllable signaling voltage
> > -      switching is available.
> > -
> > -      The pad configuration state nodes are placed under the pmc node and they
> > -      are referred to by the pinctrl client properties. For more information
> > -      see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
> > -      The pad name should be used as the value of the pins property in pin
> > -      configuration nodes.
> > -
> > -      The following pads are present on Tegra124 and Tegra132
> > -      audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi, hsic,
> > -      hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, pex-cntrl,
> > -      sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2, usb_bias.
> > -
> > -      The following pads are present on Tegra210
> > -      audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg,
> > -      debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, hdmi,
> > -      hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
> > -      sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias.
> > -
> >      properties:
> > -      pins:
> > -        $ref: /schemas/types.yaml#/definitions/string
> > -        description: Must contain name of the pad(s) to be configured.
> > -
> > -      low-power-enable:
> > -        $ref: /schemas/types.yaml#/definitions/flag
> > -        description: Configure the pad into power down mode.
> > -
> > -      low-power-disable:
> > -        $ref: /schemas/types.yaml#/definitions/flag
> > -        description: Configure the pad into active mode.
> > -
> > -      power-source:
> > -        $ref: /schemas/types.yaml#/definitions/uint32
> > -        description:
> > -          Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
> > -          TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
> > -          The values are defined in
> > -          include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
> > -          Power state can be configured on all Tegra124 and Tegra132
> > -          pads. None of the Tegra124 or Tegra132 pads support signaling
> > -          voltage switching.
> > -          All of the listed Tegra210 pads except pex-cntrl support power
> > -          state configuration. Signaling voltage switching is supported
> > -          on below Tegra210 pads.
> > -          audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1,
> > -          sdmmc3, spi, spi-hv, and uart.
> > -
> > -    required:
> > -      - pins
> > -
> > -    additionalProperties: false
> > +      status: true
> 
> If you need this, that's a bug in dtschema.

Looks like I don't need it here...

> 
> > +
> > +    additionalProperties:
> > +      type: object
> > +      description: |
> > +        This is a pad configuration node. On Tegra SoCs a pad is a set of pins
> > +        which are configured as a group. The pin grouping is a fixed attribute
> > +        of the hardware. The PMC can be used to set pad power state and
> > +        signaling voltage. A pad can be either in active or power down mode.
> > +        The support for power state and signaling voltage configuration varies
> > +        depending on the pad in question. 3.3V and 1.8V signaling voltages are
> > +        supported on pins where software controllable signaling voltage
> > +        switching is available.
> > +
> > +        The pad configuration state nodes are placed under the pmc node and
> > +        they are referred to by the pinctrl client properties. For more
> > +        information see:
> > +
> > +          Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
> > +
> > +        The pad name should be used as the value of the pins property in pin
> > +        configuration nodes.
> > +
> > +        The following pads are present on Tegra124 and Tegra132:
> > +
> > +          audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi,
> > +          hsic, hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2,
> > +          pex-cntrl, sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2,
> > +          usb_bias
> > +
> > +        The following pads are present on Tegra210:
> > +
> > +          audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg,
> > +          debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio,
> > +          hdmi, hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl,
> > +          sdmmc1, sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias
> > +      additionalProperties: false
> > +      properties:
> > +        pins:
> > +          $ref: /schemas/types.yaml#/definitions/string-array
> > +          description: Must contain name of the pad(s) to be configured.
> > +
> > +        low-power-enable:
> > +          $ref: /schemas/types.yaml#/definitions/flag
> > +          description: Configure the pad into power down mode.
> > +
> > +        low-power-disable:
> > +          $ref: /schemas/types.yaml#/definitions/flag
> > +          description: Configure the pad into active mode.
> > +
> > +        power-source:
> > +          $ref: /schemas/types.yaml#/definitions/uint32
> > +          description: |
> > +            Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
> > +            TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages. The
> > +            values are defined in:
> > +
> > +              include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h
> > +
> > +            Power state can be configured on all Tegra124 and Tegra132 pads.
> > +            None of the Tegra124 or Tegra132 pads support signaling voltage
> > +            switching. All of the listed Tegra210 pads except pex-cntrl support
> > +            power state configuration. Signaling voltage switching is supported
> > +            on the following Tegra210 pads:
> > +
> > +              audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1, sdmmc3,
> > +              spi, spi-hv, uart
> > +
> > +        phandle:
> > +          $ref: /schemas/types.yaml#/definitions/uint32
> 
> ditto

... and not this either. Might be some leftovers from testing with
earlier versions of dtschema. I've dropped them now.

> 
> > +
> > +      required:
> > +        - pins
> >  
> >  required:
> >    - compatible
> > @@ -316,6 +329,52 @@ required:
> >    - clocks
> >    - '#clock-cells'
> >  
> > +allOf:
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            const: nvidia,tegra124-pmc
> > +    then:
> > +      properties:
> > +        pinmux:
> > +          properties:
> > +            status: true

However I do get complaints if I drop this one:

	Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-pmc.yaml: allOf:0:then:properties:pinmux: 'anyOf' conditional failed, one must be fixed:
		'type' is a required property
		'properties' is a required property
		'patternProperties' is a required property
		hint: 'additionalProperties' depends on 'properties' or 'patternProperties'
		from schema $id: http://devicetree.org/meta-schemas/core.yaml#
	Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-pmc.yaml: allOf:1:then:properties:pinmux: 'anyOf' conditional failed, one must be fixed:
		'type' is a required property
		'properties' is a required property
		'patternProperties' is a required property
		hint: 'additionalProperties' depends on 'properties' or 'patternProperties'
		from schema $id: http://devicetree.org/meta-schemas/core.yaml#

Would you consider that a bug in dtschema as well that I should try to
fix or is that expected?

Thanks,
Thierry

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

Re: [PATCH 5/7] dt-bindings: arm: tegra: pmc: Restructure pad configuration node schema

[Thierry Reding]

[-- Attachment #1: Type: text/plain, Size: 10846 bytes --]

On Mon, Jul 10, 2023 at 03:57:53PM +0200, Thierry Reding wrote:
> On Fri, Jul 07, 2023 at 04:35:03PM -0600, Rob Herring wrote:
> > On Fri, Jul 07, 2023 at 03:17:09PM +0200, Thierry Reding wrote:
> > > From: Thierry Reding <treding@nvidia.com>
> > > 
> > > The pad configuration node schema in its current form can accidentally
> > > match other properties as well. Restructure the schema to better match
> > > how the device trees are using these.
> > > 
> > > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > > ---
> > >  .../arm/tegra/nvidia,tegra20-pmc.yaml         | 181 ++++++++++++------
> > >  1 file changed, 120 insertions(+), 61 deletions(-)
> > > 
> > > diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
> > > index 82070d47ac7c..271aa8f80a65 100644
> > > --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
> > > +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-pmc.yaml
> > > @@ -245,69 +245,82 @@ properties:
> > >            - resets
> > >            - '#power-domain-cells'
> > >  
> > > -patternProperties:
> > > -  "^[a-f0-9]+-[a-f0-9]+$":
> > > +  pinmux:
> > >      type: object
> > > -    description:
> > > -      This is a Pad configuration node. On Tegra SOCs a pad is a set of
> > > -      pins which are configured as a group. The pin grouping is a fixed
> > > -      attribute of the hardware. The PMC can be used to set pad power state
> > > -      and signaling voltage. A pad can be either in active or power down mode.
> > > -      The support for power state and signaling voltage configuration varies
> > > -      depending on the pad in question. 3.3V and 1.8V signaling voltages
> > > -      are supported on pins where software controllable signaling voltage
> > > -      switching is available.
> > > -
> > > -      The pad configuration state nodes are placed under the pmc node and they
> > > -      are referred to by the pinctrl client properties. For more information
> > > -      see Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt.
> > > -      The pad name should be used as the value of the pins property in pin
> > > -      configuration nodes.
> > > -
> > > -      The following pads are present on Tegra124 and Tegra132
> > > -      audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi, hsic,
> > > -      hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2, pex-cntrl,
> > > -      sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2, usb_bias.
> > > -
> > > -      The following pads are present on Tegra210
> > > -      audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg,
> > > -      debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio, hdmi,
> > > -      hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl, sdmmc1,
> > > -      sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias.
> > > -
> > >      properties:
> > > -      pins:
> > > -        $ref: /schemas/types.yaml#/definitions/string
> > > -        description: Must contain name of the pad(s) to be configured.
> > > -
> > > -      low-power-enable:
> > > -        $ref: /schemas/types.yaml#/definitions/flag
> > > -        description: Configure the pad into power down mode.
> > > -
> > > -      low-power-disable:
> > > -        $ref: /schemas/types.yaml#/definitions/flag
> > > -        description: Configure the pad into active mode.
> > > -
> > > -      power-source:
> > > -        $ref: /schemas/types.yaml#/definitions/uint32
> > > -        description:
> > > -          Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
> > > -          TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages.
> > > -          The values are defined in
> > > -          include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h.
> > > -          Power state can be configured on all Tegra124 and Tegra132
> > > -          pads. None of the Tegra124 or Tegra132 pads support signaling
> > > -          voltage switching.
> > > -          All of the listed Tegra210 pads except pex-cntrl support power
> > > -          state configuration. Signaling voltage switching is supported
> > > -          on below Tegra210 pads.
> > > -          audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1,
> > > -          sdmmc3, spi, spi-hv, and uart.
> > > -
> > > -    required:
> > > -      - pins
> > > -
> > > -    additionalProperties: false
> > > +      status: true
> > 
> > If you need this, that's a bug in dtschema.
> 
> Looks like I don't need it here...
> 
> > 
> > > +
> > > +    additionalProperties:
> > > +      type: object
> > > +      description: |
> > > +        This is a pad configuration node. On Tegra SoCs a pad is a set of pins
> > > +        which are configured as a group. The pin grouping is a fixed attribute
> > > +        of the hardware. The PMC can be used to set pad power state and
> > > +        signaling voltage. A pad can be either in active or power down mode.
> > > +        The support for power state and signaling voltage configuration varies
> > > +        depending on the pad in question. 3.3V and 1.8V signaling voltages are
> > > +        supported on pins where software controllable signaling voltage
> > > +        switching is available.
> > > +
> > > +        The pad configuration state nodes are placed under the pmc node and
> > > +        they are referred to by the pinctrl client properties. For more
> > > +        information see:
> > > +
> > > +          Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
> > > +
> > > +        The pad name should be used as the value of the pins property in pin
> > > +        configuration nodes.
> > > +
> > > +        The following pads are present on Tegra124 and Tegra132:
> > > +
> > > +          audio, bb, cam, comp, csia, csb, cse, dsi, dsib, dsic, dsid, hdmi,
> > > +          hsic, hv, lvds, mipi-bias, nand, pex-bias, pex-clk1, pex-clk2,
> > > +          pex-cntrl, sdmmc1, sdmmc3, sdmmc4, sys_ddc, uart, usb0, usb1, usb2,
> > > +          usb_bias
> > > +
> > > +        The following pads are present on Tegra210:
> > > +
> > > +          audio, audio-hv, cam, csia, csib, csic, csid, csie, csif, dbg,
> > > +          debug-nonao, dmic, dp, dsi, dsib, dsic, dsid, emmc, emmc2, gpio,
> > > +          hdmi, hsic, lvds, mipi-bias, pex-bias, pex-clk1, pex-clk2, pex-cntrl,
> > > +          sdmmc1, sdmmc3, spi, spi-hv, uart, usb0, usb1, usb2, usb3, usb-bias
> > > +      additionalProperties: false
> > > +      properties:
> > > +        pins:
> > > +          $ref: /schemas/types.yaml#/definitions/string-array
> > > +          description: Must contain name of the pad(s) to be configured.
> > > +
> > > +        low-power-enable:
> > > +          $ref: /schemas/types.yaml#/definitions/flag
> > > +          description: Configure the pad into power down mode.
> > > +
> > > +        low-power-disable:
> > > +          $ref: /schemas/types.yaml#/definitions/flag
> > > +          description: Configure the pad into active mode.
> > > +
> > > +        power-source:
> > > +          $ref: /schemas/types.yaml#/definitions/uint32
> > > +          description: |
> > > +            Must contain either TEGRA_IO_PAD_VOLTAGE_1V8 or
> > > +            TEGRA_IO_PAD_VOLTAGE_3V3 to select between signaling voltages. The
> > > +            values are defined in:
> > > +
> > > +              include/dt-bindings/pinctrl/pinctrl-tegra-io-pad.h
> > > +
> > > +            Power state can be configured on all Tegra124 and Tegra132 pads.
> > > +            None of the Tegra124 or Tegra132 pads support signaling voltage
> > > +            switching. All of the listed Tegra210 pads except pex-cntrl support
> > > +            power state configuration. Signaling voltage switching is supported
> > > +            on the following Tegra210 pads:
> > > +
> > > +              audio, audio-hv, cam, dbg, dmic, gpio, pex-cntrl, sdmmc1, sdmmc3,
> > > +              spi, spi-hv, uart
> > > +
> > > +        phandle:
> > > +          $ref: /schemas/types.yaml#/definitions/uint32
> > 
> > ditto
> 
> ... and not this either. Might be some leftovers from testing with
> earlier versions of dtschema. I've dropped them now.

[Quoting the above in full for reference]

Scratch that. This isn't triggered by the example, but I do see a
warning when trying to validate DTS files that have pad configuration
nodes that are referenced by phandle. You can see this in various board
DTS files derived from tegra210.dtsi.

One slight improvement to this might be to do:

	phandle: true

instead. However, given that this is completely standard, maybe that's
not what we want.

Any idea what might be causing this to be required? We do have
additionalProperties: false, but I thought the likes of phandle, status,
etc. were exempt from that.

> > > +      required:
> > > +        - pins
> > >  
> > >  required:
> > >    - compatible
> > > @@ -316,6 +329,52 @@ required:
> > >    - clocks
> > >    - '#clock-cells'
> > >  
> > > +allOf:
> > > +  - if:
> > > +      properties:
> > > +        compatible:
> > > +          contains:
> > > +            const: nvidia,tegra124-pmc
> > > +    then:
> > > +      properties:
> > > +        pinmux:
> > > +          properties:
> > > +            status: true
> 
> However I do get complaints if I drop this one:
> 
> 	Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-pmc.yaml: allOf:0:then:properties:pinmux: 'anyOf' conditional failed, one must be fixed:
> 		'type' is a required property
> 		'properties' is a required property
> 		'patternProperties' is a required property
> 		hint: 'additionalProperties' depends on 'properties' or 'patternProperties'
> 		from schema $id: http://devicetree.org/meta-schemas/core.yaml#
> 	Documentation/devicetree/bindings/soc/tegra/nvidia,tegra20-pmc.yaml: allOf:1:then:properties:pinmux: 'anyOf' conditional failed, one must be fixed:
> 		'type' is a required property
> 		'properties' is a required property
> 		'patternProperties' is a required property
> 		hint: 'additionalProperties' depends on 'properties' or 'patternProperties'
> 		from schema $id: http://devicetree.org/meta-schemas/core.yaml#
> 
> Would you consider that a bug in dtschema as well that I should try to
> fix or is that expected?

I guess this is a special case in a way because typically we would use
patternProperties for this. However, there really aren't any rules as to
what's valid here as a name or not. We could of course make something up
but this is description that most closely reflects reality.

Thierry

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]