* [Patch v3 0/2] memory: tegra: Skip restricted register access from Guest
@ 2024-04-12 13:05 Sumit Gupta
2024-04-12 13:05 ` [Patch v3 1/2] dt-bindings: make sid and broadcast reg optional Sumit Gupta
2024-04-12 13:05 ` [Patch v3 2/2] memory: tegra: make sid and broadcast regions optional Sumit Gupta
0 siblings, 2 replies; 22+ messages in thread
From: Sumit Gupta @ 2024-04-12 13:05 UTC (permalink / raw)
To: krzysztof.kozlowski, robh, conor+dt, maz, mark.rutland, treding,
jonathanh
Cc: devicetree, linux-kernel, linux-tegra, amhetre, bbasu, sumitg
MC SID and Broadbast channel register access is restricted for Guest VM.
But the Tegra MC driver is considering both these regions as mandatory
and causes error on access. Change that to consider both the regions as
optional in SoC's from Tegra186 onwards. Then skip access to the
restricted registers from Guest if its region is not present in Guest DT
and hence not mapped.
Previously, the solution in [1] was not accepted. Now, handled the
problem with this alternate solution.
---
v2[2] -> v3:
- fix the yaml error.
- add null check for ch_regs in mc_ch_readl() causing error in old SoC's
- remove unused populate label reported by kernel test robot.
- fix existing compile warning about length of name in tegra186_mc_probe.
v1[1] -> v2:
- consider broadcast channel registers also as restricted along with sid
- make sid and broadcast regions optional and access if present in dt.
- update the yaml file.
Sumit Gupta (2):
dt-bindings: make sid and broadcast reg optional
memory: tegra: make sid and broadcast regions optional
.../nvidia,tegra186-mc.yaml | 95 ++++++++++---------
drivers/memory/tegra/mc.c | 9 +-
drivers/memory/tegra/mc.h | 22 +++--
drivers/memory/tegra/tegra186.c | 25 ++---
4 files changed, 82 insertions(+), 69 deletions(-)
[1]https://lore.kernel.org/lkml/20240206114852.8472-1-sumitg@nvidia.com/
[2]https://lore.kernel.org/lkml/20240402132626.24693-1-sumitg@nvidia.com/
--
2.17.1
^ permalink raw reply [flat|nested] 22+ messages in thread
* [Patch v3 1/2] dt-bindings: make sid and broadcast reg optional
2024-04-12 13:05 [Patch v3 0/2] memory: tegra: Skip restricted register access from Guest Sumit Gupta
@ 2024-04-12 13:05 ` Sumit Gupta
2024-04-22 7:02 ` Krzysztof Kozlowski
2024-04-25 7:52 ` Krzysztof Kozlowski
2024-04-12 13:05 ` [Patch v3 2/2] memory: tegra: make sid and broadcast regions optional Sumit Gupta
1 sibling, 2 replies; 22+ messages in thread
From: Sumit Gupta @ 2024-04-12 13:05 UTC (permalink / raw)
To: krzysztof.kozlowski, robh, conor+dt, maz, mark.rutland, treding,
jonathanh
Cc: devicetree, linux-kernel, linux-tegra, amhetre, bbasu, sumitg
MC SID and Broadbast channel register access is restricted for Guest VM.
Make both the regions as optional for SoC's from Tegra186 onwards.
Tegra MC driver will skip access to the restricted registers from Guest
if the respective regions are not present in the memory-controller node
of Guest DT.
Suggested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
---
.../nvidia,tegra186-mc.yaml | 95 ++++++++++---------
1 file changed, 49 insertions(+), 46 deletions(-)
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
index 935d63d181d9..e0bd013ecca3 100644
--- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
@@ -34,11 +34,11 @@ properties:
- nvidia,tegra234-mc
reg:
- minItems: 6
+ minItems: 4
maxItems: 18
reg-names:
- minItems: 6
+ minItems: 4
maxItems: 18
interrupts:
@@ -151,12 +151,13 @@ allOf:
reg-names:
items:
- - const: sid
- - const: broadcast
- - const: ch0
- - const: ch1
- - const: ch2
- - const: ch3
+ enum:
+ - sid
+ - broadcast
+ - ch0
+ - ch1
+ - ch2
+ - ch3
- if:
properties:
@@ -165,29 +166,30 @@ allOf:
then:
properties:
reg:
- minItems: 18
+ minItems: 16
description: 17 memory controller channels and 1 for stream-id registers
reg-names:
items:
- - const: sid
- - const: broadcast
- - const: ch0
- - const: ch1
- - const: ch2
- - const: ch3
- - const: ch4
- - const: ch5
- - const: ch6
- - const: ch7
- - const: ch8
- - const: ch9
- - const: ch10
- - const: ch11
- - const: ch12
- - const: ch13
- - const: ch14
- - const: ch15
+ enum:
+ - sid
+ - broadcast
+ - ch0
+ - ch1
+ - ch2
+ - ch3
+ - ch4
+ - ch5
+ - ch6
+ - ch7
+ - ch8
+ - ch9
+ - ch10
+ - ch11
+ - ch12
+ - ch13
+ - ch14
+ - ch15
- if:
properties:
@@ -196,29 +198,30 @@ allOf:
then:
properties:
reg:
- minItems: 18
+ minItems: 16
description: 17 memory controller channels and 1 for stream-id registers
reg-names:
items:
- - const: sid
- - const: broadcast
- - const: ch0
- - const: ch1
- - const: ch2
- - const: ch3
- - const: ch4
- - const: ch5
- - const: ch6
- - const: ch7
- - const: ch8
- - const: ch9
- - const: ch10
- - const: ch11
- - const: ch12
- - const: ch13
- - const: ch14
- - const: ch15
+ enum:
+ - sid
+ - broadcast
+ - ch0
+ - ch1
+ - ch2
+ - ch3
+ - ch4
+ - ch5
+ - ch6
+ - ch7
+ - ch8
+ - ch9
+ - ch10
+ - ch11
+ - ch12
+ - ch13
+ - ch14
+ - ch15
additionalProperties: false
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Patch v3 2/2] memory: tegra: make sid and broadcast regions optional
2024-04-12 13:05 [Patch v3 0/2] memory: tegra: Skip restricted register access from Guest Sumit Gupta
2024-04-12 13:05 ` [Patch v3 1/2] dt-bindings: make sid and broadcast reg optional Sumit Gupta
@ 2024-04-12 13:05 ` Sumit Gupta
2024-04-22 7:12 ` Krzysztof Kozlowski
1 sibling, 1 reply; 22+ messages in thread
From: Sumit Gupta @ 2024-04-12 13:05 UTC (permalink / raw)
To: krzysztof.kozlowski, robh, conor+dt, maz, mark.rutland, treding,
jonathanh
Cc: devicetree, linux-kernel, linux-tegra, amhetre, bbasu, sumitg
MC SID and Broadbast channel register access is restricted for Guest VM.
In Tegra MC driver, consider both the regions as optional and skip
access to restricted registers from Guest if a region is not present
in Guest DT.
Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
---
drivers/memory/tegra/mc.c | 9 ++++++++-
drivers/memory/tegra/mc.h | 22 ++++++++++++----------
drivers/memory/tegra/tegra186.c | 25 +++++++++++++------------
3 files changed, 33 insertions(+), 23 deletions(-)
diff --git a/drivers/memory/tegra/mc.c b/drivers/memory/tegra/mc.c
index 224b488794e5..d819dab1b223 100644
--- a/drivers/memory/tegra/mc.c
+++ b/drivers/memory/tegra/mc.c
@@ -899,6 +899,7 @@ static void tegra_mc_num_channel_enabled(struct tegra_mc *mc)
static int tegra_mc_probe(struct platform_device *pdev)
{
+ struct resource *res;
struct tegra_mc *mc;
u64 mask;
int err;
@@ -923,7 +924,13 @@ static int tegra_mc_probe(struct platform_device *pdev)
/* length of MC tick in nanoseconds */
mc->tick = 30;
- mc->regs = devm_platform_ioremap_resource(pdev, 0);
+ if (mc->soc->num_channels) {
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "sid");
+ if (res)
+ mc->regs = devm_ioremap_resource(&pdev->dev, res);
+ } else {
+ mc->regs = devm_platform_ioremap_resource(pdev, 0);
+ }
if (IS_ERR(mc->regs))
return PTR_ERR(mc->regs);
diff --git a/drivers/memory/tegra/mc.h b/drivers/memory/tegra/mc.h
index c3f6655bec60..7e7bd3e09cdc 100644
--- a/drivers/memory/tegra/mc.h
+++ b/drivers/memory/tegra/mc.h
@@ -112,25 +112,27 @@ icc_provider_to_tegra_mc(struct icc_provider *provider)
static inline u32 mc_ch_readl(const struct tegra_mc *mc, int ch,
unsigned long offset)
{
- if (!mc->bcast_ch_regs)
- return 0;
-
- if (ch == MC_BROADCAST_CHANNEL)
+ if (ch == MC_BROADCAST_CHANNEL) {
+ if (!mc->bcast_ch_regs)
+ return 0;
return readl_relaxed(mc->bcast_ch_regs + offset);
+ } else if (mc->ch_regs) {
+ return readl_relaxed(mc->ch_regs[ch] + offset);
+ }
- return readl_relaxed(mc->ch_regs[ch] + offset);
+ return 0;
}
static inline void mc_ch_writel(const struct tegra_mc *mc, int ch,
u32 value, unsigned long offset)
{
- if (!mc->bcast_ch_regs)
- return;
-
- if (ch == MC_BROADCAST_CHANNEL)
+ if (ch == MC_BROADCAST_CHANNEL) {
+ if (!mc->bcast_ch_regs)
+ return;
writel_relaxed(value, mc->bcast_ch_regs + offset);
- else
+ } else if (mc->ch_regs) {
writel_relaxed(value, mc->ch_regs[ch] + offset);
+ }
}
static inline u32 mc_readl(const struct tegra_mc *mc, unsigned long offset)
diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c
index 1b3183951bfe..716582255eeb 100644
--- a/drivers/memory/tegra/tegra186.c
+++ b/drivers/memory/tegra/tegra186.c
@@ -26,20 +26,16 @@
static int tegra186_mc_probe(struct tegra_mc *mc)
{
struct platform_device *pdev = to_platform_device(mc->dev);
+ struct resource *res;
unsigned int i;
- char name[8];
+ char name[14];
int err;
- mc->bcast_ch_regs = devm_platform_ioremap_resource_byname(pdev, "broadcast");
- if (IS_ERR(mc->bcast_ch_regs)) {
- if (PTR_ERR(mc->bcast_ch_regs) == -EINVAL) {
- dev_warn(&pdev->dev,
- "Broadcast channel is missing, please update your device-tree\n");
- mc->bcast_ch_regs = NULL;
- goto populate;
- }
-
- return PTR_ERR(mc->bcast_ch_regs);
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "broadcast");
+ if (res) {
+ mc->bcast_ch_regs = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(mc->bcast_ch_regs))
+ return PTR_ERR(mc->bcast_ch_regs);
}
mc->ch_regs = devm_kcalloc(mc->dev, mc->soc->num_channels, sizeof(*mc->ch_regs),
@@ -55,7 +51,6 @@ static int tegra186_mc_probe(struct tegra_mc *mc)
return PTR_ERR(mc->ch_regs[i]);
}
-populate:
err = of_platform_populate(mc->dev->of_node, NULL, NULL, mc->dev);
if (err < 0)
return err;
@@ -121,6 +116,9 @@ static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev)
if (!tegra_dev_iommu_get_stream_id(dev, &sid))
return 0;
+ if (!mc->regs)
+ return 0;
+
while (!of_parse_phandle_with_args(dev->of_node, "interconnects", "#interconnect-cells",
index, &args)) {
if (args.np == mc->dev->of_node && args.args_count != 0) {
@@ -146,6 +144,9 @@ static int tegra186_mc_resume(struct tegra_mc *mc)
#if IS_ENABLED(CONFIG_IOMMU_API)
unsigned int i;
+ if (!mc->regs)
+ return 0;
+
for (i = 0; i < mc->soc->num_clients; i++) {
const struct tegra_mc_client *client = &mc->soc->clients[i];
--
2.17.1
^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [Patch v3 1/2] dt-bindings: make sid and broadcast reg optional
2024-04-12 13:05 ` [Patch v3 1/2] dt-bindings: make sid and broadcast reg optional Sumit Gupta
@ 2024-04-22 7:02 ` Krzysztof Kozlowski
2024-04-24 16:26 ` Thierry Reding
2024-04-25 7:52 ` Krzysztof Kozlowski
1 sibling, 1 reply; 22+ messages in thread
From: Krzysztof Kozlowski @ 2024-04-22 7:02 UTC (permalink / raw)
To: Sumit Gupta, robh, conor+dt, maz, mark.rutland, treding, jonathanh
Cc: devicetree, linux-kernel, linux-tegra, amhetre, bbasu
On 12/04/2024 15:05, Sumit Gupta wrote:
> MC SID and Broadbast channel register access is restricted for Guest VM.
Broadcast
> Make both the regions as optional for SoC's from Tegra186 onwards.
onward?
> Tegra MC driver will skip access to the restricted registers from Guest
> if the respective regions are not present in the memory-controller node
> of Guest DT.
>
> Suggested-by: Thierry Reding <treding@nvidia.com>
> Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
> ---
> .../nvidia,tegra186-mc.yaml | 95 ++++++++++---------
> 1 file changed, 49 insertions(+), 46 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> index 935d63d181d9..e0bd013ecca3 100644
> --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> @@ -34,11 +34,11 @@ properties:
> - nvidia,tegra234-mc
>
> reg:
> - minItems: 6
> + minItems: 4
> maxItems: 18
>
> reg-names:
> - minItems: 6
> + minItems: 4
> maxItems: 18
>
> interrupts:
> @@ -151,12 +151,13 @@ allOf:
>
> reg-names:
> items:
> - - const: sid
> - - const: broadcast
> - - const: ch0
> - - const: ch1
> - - const: ch2
> - - const: ch3
> + enum:
> + - sid
> + - broadcast
> + - ch0
> + - ch1
> + - ch2
> + - ch3
I understand why sid and broadcast are becoming optional, but why order
of the rest is now fully flexible?
This does not even make sid/broadcast optional, but ch0!
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Patch v3 2/2] memory: tegra: make sid and broadcast regions optional
2024-04-12 13:05 ` [Patch v3 2/2] memory: tegra: make sid and broadcast regions optional Sumit Gupta
@ 2024-04-22 7:12 ` Krzysztof Kozlowski
2024-04-22 14:36 ` Sumit Gupta
0 siblings, 1 reply; 22+ messages in thread
From: Krzysztof Kozlowski @ 2024-04-22 7:12 UTC (permalink / raw)
To: Sumit Gupta, robh, conor+dt, maz, mark.rutland, treding, jonathanh
Cc: devicetree, linux-kernel, linux-tegra, amhetre, bbasu
On 12/04/2024 15:05, Sumit Gupta wrote:
> MC SID and Broadbast channel register access is restricted for Guest VM.
Same typo
> In Tegra MC driver, consider both the regions as optional and skip
> access to restricted registers from Guest if a region is not present
> in Guest DT.
>
...
>
> static inline u32 mc_readl(const struct tegra_mc *mc, unsigned long offset)
> diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c
> index 1b3183951bfe..716582255eeb 100644
> --- a/drivers/memory/tegra/tegra186.c
> +++ b/drivers/memory/tegra/tegra186.c
> @@ -26,20 +26,16 @@
> static int tegra186_mc_probe(struct tegra_mc *mc)
> {
> struct platform_device *pdev = to_platform_device(mc->dev);
> + struct resource *res;
> unsigned int i;
> - char name[8];
> + char name[14];
How is it relevant? I don't see this being used in your diff.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Patch v3 2/2] memory: tegra: make sid and broadcast regions optional
2024-04-22 7:12 ` Krzysztof Kozlowski
@ 2024-04-22 14:36 ` Sumit Gupta
2024-04-23 14:41 ` Krzysztof Kozlowski
0 siblings, 1 reply; 22+ messages in thread
From: Sumit Gupta @ 2024-04-22 14:36 UTC (permalink / raw)
To: Krzysztof Kozlowski, robh, conor+dt, maz, mark.rutland, treding,
jonathanh
Cc: devicetree, linux-kernel, linux-tegra, amhetre, bbasu, Sumit Gupta
> On 12/04/2024 15:05, Sumit Gupta wrote:
>> MC SID and Broadbast channel register access is restricted for Guest VM.
>
> Same typo
>
Thank you for catching. Will correct in v4.
>> In Tegra MC driver, consider both the regions as optional and skip
>> access to restricted registers from Guest if a region is not present
>> in Guest DT.
>>
>
> ...
>
>>
>> static inline u32 mc_readl(const struct tegra_mc *mc, unsigned long offset)
>> diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c
>> index 1b3183951bfe..716582255eeb 100644
>> --- a/drivers/memory/tegra/tegra186.c
>> +++ b/drivers/memory/tegra/tegra186.c
>> @@ -26,20 +26,16 @@
>> static int tegra186_mc_probe(struct tegra_mc *mc)
>> {
>> struct platform_device *pdev = to_platform_device(mc->dev);
>> + struct resource *res;
>> unsigned int i;
>> - char name[8];
>> + char name[14];
>
> How is it relevant? I don't see this being used in your diff.
>
>
> Best regards,
> Krzysztof
>
Did this change for below warning coming with 'W=1'.
../drivers/memory/tegra/tegra186.c: In function tegra186_mc_probe:
../drivers/memory/tegra/tegra186.c:51:49: warning: %u directive output
may be truncated writing between 1 and 10 bytes into a region of size 6
[8;;https://gc
c.gnu.org/onlinedocs/gcc/Warning-Options.html#index-Wformat-truncation=-Wformat-truncation=8;;]
51 | snprintf(name, sizeof(name), "ch%u", i);
| ^~
../drivers/memory/tegra/tegra186.c:51:46: note: directive argument in
the range [0, 4294967294]
51 | snprintf(name, sizeof(name), "ch%u", i);
| ^~~~~~
../drivers/memory/tegra/tegra186.c:51:17: note: snprintf output between
4 and 13 bytes into a destination of size 8
51 | snprintf(name, sizeof(name), "ch%u", i);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Thank you,
Sumit Gupta
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Patch v3 2/2] memory: tegra: make sid and broadcast regions optional
2024-04-22 14:36 ` Sumit Gupta
@ 2024-04-23 14:41 ` Krzysztof Kozlowski
2024-04-23 19:46 ` Sumit Gupta
0 siblings, 1 reply; 22+ messages in thread
From: Krzysztof Kozlowski @ 2024-04-23 14:41 UTC (permalink / raw)
To: Sumit Gupta, robh, conor+dt, maz, mark.rutland, treding, jonathanh
Cc: devicetree, linux-kernel, linux-tegra, amhetre, bbasu
On 22/04/2024 16:36, Sumit Gupta wrote:
>
>> On 12/04/2024 15:05, Sumit Gupta wrote:
>>> MC SID and Broadbast channel register access is restricted for Guest VM.
>>
>> Same typo
>>
> Thank you for catching. Will correct in v4.
>
>>> In Tegra MC driver, consider both the regions as optional and skip
>>> access to restricted registers from Guest if a region is not present
>>> in Guest DT.
>>>
>>
>> ...
>>
>>>
>>> static inline u32 mc_readl(const struct tegra_mc *mc, unsigned long offset)
>>> diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c
>>> index 1b3183951bfe..716582255eeb 100644
>>> --- a/drivers/memory/tegra/tegra186.c
>>> +++ b/drivers/memory/tegra/tegra186.c
>>> @@ -26,20 +26,16 @@
>>> static int tegra186_mc_probe(struct tegra_mc *mc)
>>> {
>>> struct platform_device *pdev = to_platform_device(mc->dev);
>>> + struct resource *res;
>>> unsigned int i;
>>> - char name[8];
>>> + char name[14];
>>
>> How is it relevant? I don't see this being used in your diff.
>>
>>
>> Best regards,
>> Krzysztof
>>
>
> Did this change for below warning coming with 'W=1'.
>
> ../drivers/memory/tegra/tegra186.c: In function tegra186_mc_probe:
> ../drivers/memory/tegra/tegra186.c:51:49: warning: %u directive output
> may be truncated writing between 1 and 10 bytes into a region of size 6
> [8;;https://gc
> c.gnu.org/onlinedocs/gcc/Warning-Options.html#index-Wformat-truncation=-Wformat-truncation=8;;]
> 51 | snprintf(name, sizeof(name), "ch%u", i);
> | ^~
> ../drivers/memory/tegra/tegra186.c:51:46: note: directive argument in
> the range [0, 4294967294]
> 51 | snprintf(name, sizeof(name), "ch%u", i);
> | ^~~~~~
> ../drivers/memory/tegra/tegra186.c:51:17: note: snprintf output between
> 4 and 13 bytes into a destination of size 8
> 51 | snprintf(name, sizeof(name), "ch%u", i);
> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
I asked how this is relevant to this change and you answer there is a
warning. If the warning was there, your answer is really just deflecting
the topic, so obviously this is new warning. Which part of code uses
longer name?
BTW, really, such answers do not make review of your code smoother.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Patch v3 2/2] memory: tegra: make sid and broadcast regions optional
2024-04-23 14:41 ` Krzysztof Kozlowski
@ 2024-04-23 19:46 ` Sumit Gupta
2024-04-24 4:09 ` Krzysztof Kozlowski
0 siblings, 1 reply; 22+ messages in thread
From: Sumit Gupta @ 2024-04-23 19:46 UTC (permalink / raw)
To: Krzysztof Kozlowski, robh, conor+dt, maz, mark.rutland, treding,
jonathanh
Cc: devicetree, linux-kernel, linux-tegra, amhetre, bbasu, Sumit Gupta
>>>>
>>>> static inline u32 mc_readl(const struct tegra_mc *mc, unsigned long offset)
>>>> diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c
>>>> index 1b3183951bfe..716582255eeb 100644
>>>> --- a/drivers/memory/tegra/tegra186.c
>>>> +++ b/drivers/memory/tegra/tegra186.c
>>>> @@ -26,20 +26,16 @@
>>>> static int tegra186_mc_probe(struct tegra_mc *mc)
>>>> {
>>>> struct platform_device *pdev = to_platform_device(mc->dev);
>>>> + struct resource *res;
>>>> unsigned int i;
>>>> - char name[8];
>>>> + char name[14];
>>>
>>> How is it relevant? I don't see this being used in your diff.
>>>
>>>
>>> Best regards,
>>> Krzysztof
>>>
>>
>> Did this change for below warning coming with 'W=1'.
>>
>> ../drivers/memory/tegra/tegra186.c: In function tegra186_mc_probe:
>> ../drivers/memory/tegra/tegra186.c:51:49: warning: %u directive output
>> may be truncated writing between 1 and 10 bytes into a region of size 6
>> [8;;https://gc
>> c.gnu.org/onlinedocs/gcc/Warning-Options.html#index-Wformat-truncation=-Wformat-truncation=8;;]
>> 51 | snprintf(name, sizeof(name), "ch%u", i);
>> | ^~
>> ../drivers/memory/tegra/tegra186.c:51:46: note: directive argument in
>> the range [0, 4294967294]
>> 51 | snprintf(name, sizeof(name), "ch%u", i);
>> | ^~~~~~
>> ../drivers/memory/tegra/tegra186.c:51:17: note: snprintf output between
>> 4 and 13 bytes into a destination of size 8
>> 51 | snprintf(name, sizeof(name), "ch%u", i);
>> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>
> I asked how this is relevant to this change and you answer there is a
> warning. If the warning was there, your answer is really just deflecting
> the topic, so obviously this is new warning. Which part of code uses
> longer name?
>
> BTW, really, such answers do not make review of your code smoother.
>
> Best regards,
> Krzysztof
>
Apologies for not explaining it earlier.
I increased the buffer size to suppress a static check warning in the
existing code due to big range of 'unsigned int i', if copied to small
name buffer.
Seems like the warning is harmless as the maximum value of num_channels
is 16. I will remove it and keep the buffer size as 8 in the next
version.
Thank you,
Sumit Gupta
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Patch v3 2/2] memory: tegra: make sid and broadcast regions optional
2024-04-23 19:46 ` Sumit Gupta
@ 2024-04-24 4:09 ` Krzysztof Kozlowski
2024-04-24 5:27 ` Sumit Gupta
0 siblings, 1 reply; 22+ messages in thread
From: Krzysztof Kozlowski @ 2024-04-24 4:09 UTC (permalink / raw)
To: Sumit Gupta, robh, conor+dt, maz, mark.rutland, treding, jonathanh
Cc: devicetree, linux-kernel, linux-tegra, amhetre, bbasu
On 23/04/2024 21:46, Sumit Gupta wrote:
>
>
>
>>>>>
>>>>> static inline u32 mc_readl(const struct tegra_mc *mc, unsigned long offset)
>>>>> diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c
>>>>> index 1b3183951bfe..716582255eeb 100644
>>>>> --- a/drivers/memory/tegra/tegra186.c
>>>>> +++ b/drivers/memory/tegra/tegra186.c
>>>>> @@ -26,20 +26,16 @@
>>>>> static int tegra186_mc_probe(struct tegra_mc *mc)
>>>>> {
>>>>> struct platform_device *pdev = to_platform_device(mc->dev);
>>>>> + struct resource *res;
>>>>> unsigned int i;
>>>>> - char name[8];
>>>>> + char name[14];
>>>>
>>>> How is it relevant? I don't see this being used in your diff.
>>>>
>>>>
>>>> Best regards,
>>>> Krzysztof
>>>>
>>>
>>> Did this change for below warning coming with 'W=1'.
>>>
>>> ../drivers/memory/tegra/tegra186.c: In function tegra186_mc_probe:
>>> ../drivers/memory/tegra/tegra186.c:51:49: warning: %u directive output
>>> may be truncated writing between 1 and 10 bytes into a region of size 6
>>> [8;;https://gc
>>> c.gnu.org/onlinedocs/gcc/Warning-Options.html#index-Wformat-truncation=-Wformat-truncation=8;;]
>>> 51 | snprintf(name, sizeof(name), "ch%u", i);
>>> | ^~
>>> ../drivers/memory/tegra/tegra186.c:51:46: note: directive argument in
>>> the range [0, 4294967294]
>>> 51 | snprintf(name, sizeof(name), "ch%u", i);
>>> | ^~~~~~
>>> ../drivers/memory/tegra/tegra186.c:51:17: note: snprintf output between
>>> 4 and 13 bytes into a destination of size 8
>>> 51 | snprintf(name, sizeof(name), "ch%u", i);
>>> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>>
>> I asked how this is relevant to this change and you answer there is a
>> warning. If the warning was there, your answer is really just deflecting
>> the topic, so obviously this is new warning. Which part of code uses
>> longer name?
>>
>> BTW, really, such answers do not make review of your code smoother.
>>
>> Best regards,
>> Krzysztof
>>
>
> Apologies for not explaining it earlier.
>
> I increased the buffer size to suppress a static check warning in the
> existing code due to big range of 'unsigned int i', if copied to small
> name buffer.
>
> Seems like the warning is harmless as the maximum value of num_channels
> is 16. I will remove it and keep the buffer size as 8 in the next
> version.
>
That's not the point. For the third time: how is it relevant to this
change here? Was or was not the warning before?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Patch v3 2/2] memory: tegra: make sid and broadcast regions optional
2024-04-24 4:09 ` Krzysztof Kozlowski
@ 2024-04-24 5:27 ` Sumit Gupta
2024-04-24 5:44 ` Krzysztof Kozlowski
0 siblings, 1 reply; 22+ messages in thread
From: Sumit Gupta @ 2024-04-24 5:27 UTC (permalink / raw)
To: Krzysztof Kozlowski, robh, conor+dt, maz, mark.rutland,
Thierry Reding, Jon Hunter
Cc: devicetree, linux-kernel, linux-tegra, Ashish Mhetre, Bibek Basu,
Sumit Gupta
>>
>>>>>>
>>>>>> static inline u32 mc_readl(const struct tegra_mc *mc, unsigned long offset)
>>>>>> diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c
>>>>>> index 1b3183951bfe..716582255eeb 100644
>>>>>> --- a/drivers/memory/tegra/tegra186.c
>>>>>> +++ b/drivers/memory/tegra/tegra186.c
>>>>>> @@ -26,20 +26,16 @@
>>>>>> static int tegra186_mc_probe(struct tegra_mc *mc)
>>>>>> {
>>>>>> struct platform_device *pdev = to_platform_device(mc->dev);
>>>>>> + struct resource *res;
>>>>>> unsigned int i;
>>>>>> - char name[8];
>>>>>> + char name[14];
>>>>>
>>>>> How is it relevant? I don't see this being used in your diff.
>>>>>
>>>>>
>>>>> Best regards,
>>>>> Krzysztof
>>>>>
>>>>
>>>> Did this change for below warning coming with 'W=1'.
>>>>
>>>> ../drivers/memory/tegra/tegra186.c: In function tegra186_mc_probe:
>>>> ../drivers/memory/tegra/tegra186.c:51:49: warning: %u directive output
>>>> may be truncated writing between 1 and 10 bytes into a region of size 6
>>>> [8;;https://gc
>>>> c.gnu.org/onlinedocs/gcc/Warning-Options.html#index-Wformat-truncation=-Wformat-truncation=8;;]
>>>> 51 | snprintf(name, sizeof(name), "ch%u", i);
>>>> | ^~
>>>> ../drivers/memory/tegra/tegra186.c:51:46: note: directive argument in
>>>> the range [0, 4294967294]
>>>> 51 | snprintf(name, sizeof(name), "ch%u", i);
>>>> | ^~~~~~
>>>> ../drivers/memory/tegra/tegra186.c:51:17: note: snprintf output between
>>>> 4 and 13 bytes into a destination of size 8
>>>> 51 | snprintf(name, sizeof(name), "ch%u", i);
>>>> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>>>
>>> I asked how this is relevant to this change and you answer there is a
>>> warning. If the warning was there, your answer is really just deflecting
>>> the topic, so obviously this is new warning. Which part of code uses
>>> longer name?
>>>
>>> BTW, really, such answers do not make review of your code smoother.
>>>
>>> Best regards,
>>> Krzysztof
>>>
>>
>> Apologies for not explaining it earlier.
>>
>> I increased the buffer size to suppress a static check warning in the
>> existing code due to big range of 'unsigned int i', if copied to small
>> name buffer.
>>
>> Seems like the warning is harmless as the maximum value of num_channels
>> is 16. I will remove it and keep the buffer size as 8 in the next
>> version.
>>
>
> That's not the point. For the third time: how is it relevant to this
> change here? Was or was not the warning before?
>
This is not relevant to the change here. The warning was before as well.
Thank you,
Sumit Gupta
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Patch v3 2/2] memory: tegra: make sid and broadcast regions optional
2024-04-24 5:27 ` Sumit Gupta
@ 2024-04-24 5:44 ` Krzysztof Kozlowski
2024-04-24 6:27 ` Sumit Gupta
0 siblings, 1 reply; 22+ messages in thread
From: Krzysztof Kozlowski @ 2024-04-24 5:44 UTC (permalink / raw)
To: Sumit Gupta, robh, conor+dt, maz, mark.rutland, Thierry Reding,
Jon Hunter
Cc: devicetree, linux-kernel, linux-tegra, Ashish Mhetre, Bibek Basu
On 24/04/2024 07:27, Sumit Gupta wrote:
>
>
>>>
>>>>>>>
>>>>>>> static inline u32 mc_readl(const struct tegra_mc *mc, unsigned long offset)
>>>>>>> diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c
>>>>>>> index 1b3183951bfe..716582255eeb 100644
>>>>>>> --- a/drivers/memory/tegra/tegra186.c
>>>>>>> +++ b/drivers/memory/tegra/tegra186.c
>>>>>>> @@ -26,20 +26,16 @@
>>>>>>> static int tegra186_mc_probe(struct tegra_mc *mc)
>>>>>>> {
>>>>>>> struct platform_device *pdev = to_platform_device(mc->dev);
>>>>>>> + struct resource *res;
>>>>>>> unsigned int i;
>>>>>>> - char name[8];
>>>>>>> + char name[14];
>>>>>>
>>>>>> How is it relevant? I don't see this being used in your diff.
>>>>>>
>>>>>>
>>>>>> Best regards,
>>>>>> Krzysztof
>>>>>>
>>>>>
>>>>> Did this change for below warning coming with 'W=1'.
>>>>>
>>>>> ../drivers/memory/tegra/tegra186.c: In function tegra186_mc_probe:
>>>>> ../drivers/memory/tegra/tegra186.c:51:49: warning: %u directive output
>>>>> may be truncated writing between 1 and 10 bytes into a region of size 6
>>>>> [8;;https://gc
>>>>> c.gnu.org/onlinedocs/gcc/Warning-Options.html#index-Wformat-truncation=-Wformat-truncation=8;;]
>>>>> 51 | snprintf(name, sizeof(name), "ch%u", i);
>>>>> | ^~
>>>>> ../drivers/memory/tegra/tegra186.c:51:46: note: directive argument in
>>>>> the range [0, 4294967294]
>>>>> 51 | snprintf(name, sizeof(name), "ch%u", i);
>>>>> | ^~~~~~
>>>>> ../drivers/memory/tegra/tegra186.c:51:17: note: snprintf output between
>>>>> 4 and 13 bytes into a destination of size 8
>>>>> 51 | snprintf(name, sizeof(name), "ch%u", i);
>>>>> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>>>>
>>>> I asked how this is relevant to this change and you answer there is a
>>>> warning. If the warning was there, your answer is really just deflecting
>>>> the topic, so obviously this is new warning. Which part of code uses
>>>> longer name?
>>>>
>>>> BTW, really, such answers do not make review of your code smoother.
>>>>
>>>> Best regards,
>>>> Krzysztof
>>>>
>>>
>>> Apologies for not explaining it earlier.
>>>
>>> I increased the buffer size to suppress a static check warning in the
>>> existing code due to big range of 'unsigned int i', if copied to small
>>> name buffer.
>>>
>>> Seems like the warning is harmless as the maximum value of num_channels
>>> is 16. I will remove it and keep the buffer size as 8 in the next
>>> version.
>>>
>>
>> That's not the point. For the third time: how is it relevant to this
>> change here? Was or was not the warning before?
>>
>
> This is not relevant to the change here. The warning was before as well.
OK, fixing the warning is always a good idea, but this *must* be always
separate patch, with its own explanation and rationale, and warning message.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Patch v3 2/2] memory: tegra: make sid and broadcast regions optional
2024-04-24 5:44 ` Krzysztof Kozlowski
@ 2024-04-24 6:27 ` Sumit Gupta
0 siblings, 0 replies; 22+ messages in thread
From: Sumit Gupta @ 2024-04-24 6:27 UTC (permalink / raw)
To: Krzysztof Kozlowski, robh, conor+dt, maz, mark.rutland,
Thierry Reding, Jon Hunter
Cc: devicetree, linux-kernel, linux-tegra, Ashish Mhetre, Bibek Basu,
Sumit Gupta
>>>>>>>>
>>>>>>>> static inline u32 mc_readl(const struct tegra_mc *mc, unsigned long offset)
>>>>>>>> diff --git a/drivers/memory/tegra/tegra186.c b/drivers/memory/tegra/tegra186.c
>>>>>>>> index 1b3183951bfe..716582255eeb 100644
>>>>>>>> --- a/drivers/memory/tegra/tegra186.c
>>>>>>>> +++ b/drivers/memory/tegra/tegra186.c
>>>>>>>> @@ -26,20 +26,16 @@
>>>>>>>> static int tegra186_mc_probe(struct tegra_mc *mc)
>>>>>>>> {
>>>>>>>> struct platform_device *pdev = to_platform_device(mc->dev);
>>>>>>>> + struct resource *res;
>>>>>>>> unsigned int i;
>>>>>>>> - char name[8];
>>>>>>>> + char name[14];
>>>>>>>
>>>>>>> How is it relevant? I don't see this being used in your diff.
>>>>>>>
>>>>>>>
>>>>>>> Best regards,
>>>>>>> Krzysztof
>>>>>>>
>>>>>>
>>>>>> Did this change for below warning coming with 'W=1'.
>>>>>>
>>>>>> ../drivers/memory/tegra/tegra186.c: In function tegra186_mc_probe:
>>>>>> ../drivers/memory/tegra/tegra186.c:51:49: warning: %u directive output
>>>>>> may be truncated writing between 1 and 10 bytes into a region of size 6
>>>>>> [8;;https://gc
>>>>>> c.gnu.org/onlinedocs/gcc/Warning-Options.html#index-Wformat-truncation=-Wformat-truncation=8;;]
>>>>>> 51 | snprintf(name, sizeof(name), "ch%u", i);
>>>>>> | ^~
>>>>>> ../drivers/memory/tegra/tegra186.c:51:46: note: directive argument in
>>>>>> the range [0, 4294967294]
>>>>>> 51 | snprintf(name, sizeof(name), "ch%u", i);
>>>>>> | ^~~~~~
>>>>>> ../drivers/memory/tegra/tegra186.c:51:17: note: snprintf output between
>>>>>> 4 and 13 bytes into a destination of size 8
>>>>>> 51 | snprintf(name, sizeof(name), "ch%u", i);
>>>>>> | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>>>>>
>>>>> I asked how this is relevant to this change and you answer there is a
>>>>> warning. If the warning was there, your answer is really just deflecting
>>>>> the topic, so obviously this is new warning. Which part of code uses
>>>>> longer name?
>>>>>
>>>>> BTW, really, such answers do not make review of your code smoother.
>>>>>
>>>>> Best regards,
>>>>> Krzysztof
>>>>>
>>>>
>>>> Apologies for not explaining it earlier.
>>>>
>>>> I increased the buffer size to suppress a static check warning in the
>>>> existing code due to big range of 'unsigned int i', if copied to small
>>>> name buffer.
>>>>
>>>> Seems like the warning is harmless as the maximum value of num_channels
>>>> is 16. I will remove it and keep the buffer size as 8 in the next
>>>> version.
>>>>
>>>
>>> That's not the point. For the third time: how is it relevant to this
>>> change here? Was or was not the warning before?
>>>
>>
>> This is not relevant to the change here. The warning was before as well.
>
> OK, fixing the warning is always a good idea, but this *must* be always
> separate patch, with its own explanation and rationale, and warning message.
>
Sure, will submit a separate patch for the warning and spin a v4 for
this patch series after incorporating all review comments.
Thank you,
Sumit Gupta
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Patch v3 1/2] dt-bindings: make sid and broadcast reg optional
2024-04-22 7:02 ` Krzysztof Kozlowski
@ 2024-04-24 16:26 ` Thierry Reding
2024-04-24 17:04 ` Thierry Reding
2024-04-25 7:51 ` Krzysztof Kozlowski
0 siblings, 2 replies; 22+ messages in thread
From: Thierry Reding @ 2024-04-24 16:26 UTC (permalink / raw)
To: Krzysztof Kozlowski, Sumit Gupta, robh, conor+dt, maz,
mark.rutland, treding, jonathanh
Cc: devicetree, linux-kernel, linux-tegra, amhetre, bbasu
[-- Attachment #1: Type: text/plain, Size: 2644 bytes --]
On Mon Apr 22, 2024 at 9:02 AM CEST, Krzysztof Kozlowski wrote:
> On 12/04/2024 15:05, Sumit Gupta wrote:
> > MC SID and Broadbast channel register access is restricted for Guest VM.
>
> Broadcast
>
> > Make both the regions as optional for SoC's from Tegra186 onwards.
>
> onward?
>
> > Tegra MC driver will skip access to the restricted registers from Guest
> > if the respective regions are not present in the memory-controller node
> > of Guest DT.
> >
> > Suggested-by: Thierry Reding <treding@nvidia.com>
> > Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
> > ---
> > .../nvidia,tegra186-mc.yaml | 95 ++++++++++---------
> > 1 file changed, 49 insertions(+), 46 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> > index 935d63d181d9..e0bd013ecca3 100644
> > --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> > +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> > @@ -34,11 +34,11 @@ properties:
> > - nvidia,tegra234-mc
> >
> > reg:
> > - minItems: 6
> > + minItems: 4
> > maxItems: 18
> >
> > reg-names:
> > - minItems: 6
> > + minItems: 4
> > maxItems: 18
> >
> > interrupts:
> > @@ -151,12 +151,13 @@ allOf:
> >
> > reg-names:
> > items:
> > - - const: sid
> > - - const: broadcast
> > - - const: ch0
> > - - const: ch1
> > - - const: ch2
> > - - const: ch3
> > + enum:
> > + - sid
> > + - broadcast
> > + - ch0
> > + - ch1
> > + - ch2
> > + - ch3
>
> I understand why sid and broadcast are becoming optional, but why order
> of the rest is now fully flexible?
The reason why the order of the rest doesn't matter is because we have
both reg and reg-names properties and so the order in which they appear
in the list doesn't matter. The only thing that matters is that the
entries of the reg and reg-names properties match.
> This does not even make sid/broadcast optional, but ch0!
Yeah, this ends up making all entries optional, which isn't what we
want. I don't know of a way to accurately express this in json-schema,
though. Do you?
If not, then maybe we need to resort to something like this and also
mention explicitly in some comment that it is sid and broadcast that are
optional.
Thierry
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Patch v3 1/2] dt-bindings: make sid and broadcast reg optional
2024-04-24 16:26 ` Thierry Reding
@ 2024-04-24 17:04 ` Thierry Reding
2024-04-25 7:52 ` Krzysztof Kozlowski
2024-04-25 7:51 ` Krzysztof Kozlowski
1 sibling, 1 reply; 22+ messages in thread
From: Thierry Reding @ 2024-04-24 17:04 UTC (permalink / raw)
To: Thierry Reding, Krzysztof Kozlowski, Sumit Gupta, robh, conor+dt,
maz, mark.rutland, treding, jonathanh
Cc: devicetree, linux-kernel, linux-tegra, amhetre, bbasu
[-- Attachment #1: Type: text/plain, Size: 7184 bytes --]
On Wed Apr 24, 2024 at 6:26 PM CEST, Thierry Reding wrote:
> On Mon Apr 22, 2024 at 9:02 AM CEST, Krzysztof Kozlowski wrote:
> > On 12/04/2024 15:05, Sumit Gupta wrote:
> > > MC SID and Broadbast channel register access is restricted for Guest VM.
> >
> > Broadcast
> >
> > > Make both the regions as optional for SoC's from Tegra186 onwards.
> >
> > onward?
> >
> > > Tegra MC driver will skip access to the restricted registers from Guest
> > > if the respective regions are not present in the memory-controller node
> > > of Guest DT.
> > >
> > > Suggested-by: Thierry Reding <treding@nvidia.com>
> > > Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
> > > ---
> > > .../nvidia,tegra186-mc.yaml | 95 ++++++++++---------
> > > 1 file changed, 49 insertions(+), 46 deletions(-)
> > >
> > > diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> > > index 935d63d181d9..e0bd013ecca3 100644
> > > --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> > > +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> > > @@ -34,11 +34,11 @@ properties:
> > > - nvidia,tegra234-mc
> > >
> > > reg:
> > > - minItems: 6
> > > + minItems: 4
> > > maxItems: 18
> > >
> > > reg-names:
> > > - minItems: 6
> > > + minItems: 4
> > > maxItems: 18
> > >
> > > interrupts:
> > > @@ -151,12 +151,13 @@ allOf:
> > >
> > > reg-names:
> > > items:
> > > - - const: sid
> > > - - const: broadcast
> > > - - const: ch0
> > > - - const: ch1
> > > - - const: ch2
> > > - - const: ch3
> > > + enum:
> > > + - sid
> > > + - broadcast
> > > + - ch0
> > > + - ch1
> > > + - ch2
> > > + - ch3
> >
> > I understand why sid and broadcast are becoming optional, but why order
> > of the rest is now fully flexible?
>
> The reason why the order of the rest doesn't matter is because we have
> both reg and reg-names properties and so the order in which they appear
> in the list doesn't matter. The only thing that matters is that the
> entries of the reg and reg-names properties match.
>
> > This does not even make sid/broadcast optional, but ch0!
>
> Yeah, this ends up making all entries optional, which isn't what we
> want. I don't know of a way to accurately express this in json-schema,
> though. Do you?
>
> If not, then maybe we need to resort to something like this and also
> mention explicitly in some comment that it is sid and broadcast that are
> optional.
Actually, here's another variant that is a bit closer to what we want:
--- >8 ---
diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
index 935d63d181d9..86f1475926e4 100644
--- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
@@ -34,11 +34,11 @@ properties:
- nvidia,tegra234-mc
reg:
- minItems: 6
+ minItems: 4
maxItems: 18
reg-names:
- minItems: 6
+ minItems: 4
maxItems: 18
interrupts:
@@ -146,17 +146,21 @@ allOf:
then:
properties:
reg:
+ minItems: 4
maxItems: 6
description: 5 memory controller channels and 1 for stream-id registers
reg-names:
- items:
- - const: sid
- - const: broadcast
- - const: ch0
- - const: ch1
- - const: ch2
- - const: ch3
+ anyOf:
+ - items:
+ enum: [ sid, broadcast, ch0, ch1, ch2, ch3 ]
+ uniqueItems: true
+ minItems: 6
+
+ - items:
+ enum: [ ch0, ch1, ch2, ch3 ]
+ uniqueItems: true
+ minItems: 4
- if:
properties:
@@ -165,29 +169,22 @@ allOf:
then:
properties:
reg:
- minItems: 18
+ minItems: 16
description: 17 memory controller channels and 1 for stream-id registers
reg-names:
- items:
- - const: sid
- - const: broadcast
- - const: ch0
- - const: ch1
- - const: ch2
- - const: ch3
- - const: ch4
- - const: ch5
- - const: ch6
- - const: ch7
- - const: ch8
- - const: ch9
- - const: ch10
- - const: ch11
- - const: ch12
- - const: ch13
- - const: ch14
- - const: ch15
+ anyOf:
+ - items:
+ enum: [ sid, broadcast, ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7,
+ ch8, ch9, ch10, ch11, ch12, ch13, ch14, ch15 ]
+ minItems: 18
+ uniqueItems: true
+
+ - items:
+ enum: [ ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7, ch8, ch9, ch10,
+ ch11, ch12, ch13, ch14, ch15 ]
+ minItems: 16
+ uniqueItems: true
- if:
properties:
@@ -196,29 +193,22 @@ allOf:
then:
properties:
reg:
- minItems: 18
+ minItems: 16
description: 17 memory controller channels and 1 for stream-id registers
reg-names:
- items:
- - const: sid
- - const: broadcast
- - const: ch0
- - const: ch1
- - const: ch2
- - const: ch3
- - const: ch4
- - const: ch5
- - const: ch6
- - const: ch7
- - const: ch8
- - const: ch9
- - const: ch10
- - const: ch11
- - const: ch12
- - const: ch13
- - const: ch14
- - const: ch15
+ anyOf:
+ - items:
+ enum: [ sid, broadcast, ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7,
+ ch8, ch9, ch10, ch11, ch12, ch13, ch14, ch15 ]
+ minItems: 18
+ uniqueItems: true
+
+ - items:
+ enum: [ ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7, ch8, ch9, ch10,
+ ch11, ch12, ch13, ch14, ch15 ]
+ minItems: 16
+ uniqueItems: true
additionalProperties: false
--- >8 ---
The one restriction that it has is that "sid" and "broadcast" must be
optional together. So you can't have just "sid" or "broadcast", but they
either must both be there, or they must both not be there.
I suppose we could technically make that work by adding more
alternatives, but perhaps it can be avoided for sanity?
Thierry
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^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [Patch v3 1/2] dt-bindings: make sid and broadcast reg optional
2024-04-24 16:26 ` Thierry Reding
2024-04-24 17:04 ` Thierry Reding
@ 2024-04-25 7:51 ` Krzysztof Kozlowski
1 sibling, 0 replies; 22+ messages in thread
From: Krzysztof Kozlowski @ 2024-04-25 7:51 UTC (permalink / raw)
To: Thierry Reding, Sumit Gupta, robh, conor+dt, maz, mark.rutland,
treding, jonathanh
Cc: devicetree, linux-kernel, linux-tegra, amhetre, bbasu
On 24/04/2024 18:26, Thierry Reding wrote:
> On Mon Apr 22, 2024 at 9:02 AM CEST, Krzysztof Kozlowski wrote:
>> On 12/04/2024 15:05, Sumit Gupta wrote:
>>> MC SID and Broadbast channel register access is restricted for Guest VM.
>>
>> Broadcast
>>
>>> Make both the regions as optional for SoC's from Tegra186 onwards.
>>
>> onward?
>>
>>> Tegra MC driver will skip access to the restricted registers from Guest
>>> if the respective regions are not present in the memory-controller node
>>> of Guest DT.
>>>
>>> Suggested-by: Thierry Reding <treding@nvidia.com>
>>> Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
>>> ---
>>> .../nvidia,tegra186-mc.yaml | 95 ++++++++++---------
>>> 1 file changed, 49 insertions(+), 46 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
>>> index 935d63d181d9..e0bd013ecca3 100644
>>> --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
>>> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
>>> @@ -34,11 +34,11 @@ properties:
>>> - nvidia,tegra234-mc
>>>
>>> reg:
>>> - minItems: 6
>>> + minItems: 4
>>> maxItems: 18
>>>
>>> reg-names:
>>> - minItems: 6
>>> + minItems: 4
>>> maxItems: 18
>>>
>>> interrupts:
>>> @@ -151,12 +151,13 @@ allOf:
>>>
>>> reg-names:
>>> items:
>>> - - const: sid
>>> - - const: broadcast
>>> - - const: ch0
>>> - - const: ch1
>>> - - const: ch2
>>> - - const: ch3
>>> + enum:
>>> + - sid
>>> + - broadcast
>>> + - ch0
>>> + - ch1
>>> + - ch2
>>> + - ch3
>>
>> I understand why sid and broadcast are becoming optional, but why order
>> of the rest is now fully flexible?
>
> The reason why the order of the rest doesn't matter is because we have
> both reg and reg-names properties and so the order in which they appear
> in the list doesn't matter. The only thing that matters is that the
> entries of the reg and reg-names properties match.
No, that's not true. Client/implementation can pick up by indices and
order always matters, at least as much as possible.
If the reason is "we have reg-names", then the answer is: no. That's not
valid argument. The reason could be that entries are so
fragmented/randomly distributed that order by indices is impossible.
>
>> This does not even make sid/broadcast optional, but ch0!
>
> Yeah, this ends up making all entries optional, which isn't what we
> want. I don't know of a way to accurately express this in json-schema,
> though. Do you?
I think oneOf: with two cases. Depends what is exactly optional. The
commit msg is quite poor here. I expect proper rationale and description
of driver. Is sid optional? broadcast? Both? Any? And what does it mean
optional? The address is reserved or address is not existing? Or maybe
address is there, but can be ignored?
>
> If not, then maybe we need to resort to something like this and also
> mention explicitly in some comment that it is sid and broadcast that are
> optional.
>
> Thierry
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Patch v3 1/2] dt-bindings: make sid and broadcast reg optional
2024-04-24 17:04 ` Thierry Reding
@ 2024-04-25 7:52 ` Krzysztof Kozlowski
2024-04-25 9:39 ` Thierry Reding
0 siblings, 1 reply; 22+ messages in thread
From: Krzysztof Kozlowski @ 2024-04-25 7:52 UTC (permalink / raw)
To: Thierry Reding, Sumit Gupta, robh, conor+dt, maz, mark.rutland,
treding, jonathanh
Cc: devicetree, linux-kernel, linux-tegra, amhetre, bbasu
On 24/04/2024 19:04, Thierry Reding wrote:
> On Wed Apr 24, 2024 at 6:26 PM CEST, Thierry Reding wrote:
>> On Mon Apr 22, 2024 at 9:02 AM CEST, Krzysztof Kozlowski wrote:
>>> On 12/04/2024 15:05, Sumit Gupta wrote:
>>>> MC SID and Broadbast channel register access is restricted for Guest VM.
>>>
>>> Broadcast
>>>
>>>> Make both the regions as optional for SoC's from Tegra186 onwards.
>>>
>>> onward?
>>>
>>>> Tegra MC driver will skip access to the restricted registers from Guest
>>>> if the respective regions are not present in the memory-controller node
>>>> of Guest DT.
>>>>
>>>> Suggested-by: Thierry Reding <treding@nvidia.com>
>>>> Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
>>>> ---
>>>> .../nvidia,tegra186-mc.yaml | 95 ++++++++++---------
>>>> 1 file changed, 49 insertions(+), 46 deletions(-)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
>>>> index 935d63d181d9..e0bd013ecca3 100644
>>>> --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
>>>> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
>>>> @@ -34,11 +34,11 @@ properties:
>>>> - nvidia,tegra234-mc
>>>>
>>>> reg:
>>>> - minItems: 6
>>>> + minItems: 4
>>>> maxItems: 18
>>>>
>>>> reg-names:
>>>> - minItems: 6
>>>> + minItems: 4
>>>> maxItems: 18
>>>>
>>>> interrupts:
>>>> @@ -151,12 +151,13 @@ allOf:
>>>>
>>>> reg-names:
>>>> items:
>>>> - - const: sid
>>>> - - const: broadcast
>>>> - - const: ch0
>>>> - - const: ch1
>>>> - - const: ch2
>>>> - - const: ch3
>>>> + enum:
>>>> + - sid
>>>> + - broadcast
>>>> + - ch0
>>>> + - ch1
>>>> + - ch2
>>>> + - ch3
>>>
>>> I understand why sid and broadcast are becoming optional, but why order
>>> of the rest is now fully flexible?
>>
>> The reason why the order of the rest doesn't matter is because we have
>> both reg and reg-names properties and so the order in which they appear
>> in the list doesn't matter. The only thing that matters is that the
>> entries of the reg and reg-names properties match.
>>
>>> This does not even make sid/broadcast optional, but ch0!
>>
>> Yeah, this ends up making all entries optional, which isn't what we
>> want. I don't know of a way to accurately express this in json-schema,
>> though. Do you?
>>
>> If not, then maybe we need to resort to something like this and also
>> mention explicitly in some comment that it is sid and broadcast that are
>> optional.
>
> Actually, here's another variant that is a bit closer to what we want:
>
> --- >8 ---
> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> index 935d63d181d9..86f1475926e4 100644
> --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> @@ -34,11 +34,11 @@ properties:
> - nvidia,tegra234-mc
>
> reg:
> - minItems: 6
> + minItems: 4
> maxItems: 18
>
> reg-names:
> - minItems: 6
> + minItems: 4
> maxItems: 18
>
> interrupts:
> @@ -146,17 +146,21 @@ allOf:
> then:
> properties:
> reg:
> + minItems: 4
> maxItems: 6
> description: 5 memory controller channels and 1 for stream-id registers
>
> reg-names:
> - items:
> - - const: sid
> - - const: broadcast
> - - const: ch0
> - - const: ch1
> - - const: ch2
> - - const: ch3
> + anyOf:
> + - items:
> + enum: [ sid, broadcast, ch0, ch1, ch2, ch3 ]
> + uniqueItems: true
> + minItems: 6
> +
> + - items:
> + enum: [ ch0, ch1, ch2, ch3 ]
> + uniqueItems: true
> + minItems: 4
>
> - if:
> properties:
> @@ -165,29 +169,22 @@ allOf:
> then:
> properties:
> reg:
> - minItems: 18
> + minItems: 16
> description: 17 memory controller channels and 1 for stream-id registers
>
> reg-names:
> - items:
> - - const: sid
> - - const: broadcast
> - - const: ch0
> - - const: ch1
> - - const: ch2
> - - const: ch3
> - - const: ch4
> - - const: ch5
> - - const: ch6
> - - const: ch7
> - - const: ch8
> - - const: ch9
> - - const: ch10
> - - const: ch11
> - - const: ch12
> - - const: ch13
> - - const: ch14
> - - const: ch15
> + anyOf:
> + - items:
> + enum: [ sid, broadcast, ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7,
> + ch8, ch9, ch10, ch11, ch12, ch13, ch14, ch15 ]
> + minItems: 18
> + uniqueItems: true
> +
> + - items:
> + enum: [ ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7, ch8, ch9, ch10,
> + ch11, ch12, ch13, ch14, ch15 ]
> + minItems: 16
> + uniqueItems: true
No, because order is strict.
...
>
> The one restriction that it has is that "sid" and "broadcast" must be
> optional together. So you can't have just "sid" or "broadcast", but they
> either must both be there, or they must both not be there.
>
This must be explained in commit msg.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Patch v3 1/2] dt-bindings: make sid and broadcast reg optional
2024-04-12 13:05 ` [Patch v3 1/2] dt-bindings: make sid and broadcast reg optional Sumit Gupta
2024-04-22 7:02 ` Krzysztof Kozlowski
@ 2024-04-25 7:52 ` Krzysztof Kozlowski
1 sibling, 0 replies; 22+ messages in thread
From: Krzysztof Kozlowski @ 2024-04-25 7:52 UTC (permalink / raw)
To: Sumit Gupta, robh, conor+dt, maz, mark.rutland, treding, jonathanh
Cc: devicetree, linux-kernel, linux-tegra, amhetre, bbasu
On 12/04/2024 15:05, Sumit Gupta wrote:
> MC SID and Broadbast channel register access is restricted for Guest VM.
> Make both the regions as optional for SoC's from Tegra186 onwards.
> Tegra MC driver will skip access to the restricted registers from Guest
> if the respective regions are not present in the memory-controller node
> of Guest DT.
>
> Suggested-by: Thierry Reding <treding@nvidia.com>
> Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
> ---
One more thing:
Please use subject prefixes matching the subsystem. You can get them for
example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
your patch is touching.
The current prefix is just terrible... are you changing all bindings in
entire kernel repository?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Patch v3 1/2] dt-bindings: make sid and broadcast reg optional
2024-04-25 7:52 ` Krzysztof Kozlowski
@ 2024-04-25 9:39 ` Thierry Reding
2024-04-25 9:45 ` Krzysztof Kozlowski
0 siblings, 1 reply; 22+ messages in thread
From: Thierry Reding @ 2024-04-25 9:39 UTC (permalink / raw)
To: Krzysztof Kozlowski, Sumit Gupta, robh, conor+dt, maz,
mark.rutland, treding, jonathanh
Cc: devicetree, linux-kernel, linux-tegra, amhetre, bbasu
[-- Attachment #1: Type: text/plain, Size: 6630 bytes --]
On Thu Apr 25, 2024 at 9:52 AM CEST, Krzysztof Kozlowski wrote:
> On 24/04/2024 19:04, Thierry Reding wrote:
> > On Wed Apr 24, 2024 at 6:26 PM CEST, Thierry Reding wrote:
> >> On Mon Apr 22, 2024 at 9:02 AM CEST, Krzysztof Kozlowski wrote:
> >>> On 12/04/2024 15:05, Sumit Gupta wrote:
> >>>> MC SID and Broadbast channel register access is restricted for Guest VM.
> >>>
> >>> Broadcast
> >>>
> >>>> Make both the regions as optional for SoC's from Tegra186 onwards.
> >>>
> >>> onward?
> >>>
> >>>> Tegra MC driver will skip access to the restricted registers from Guest
> >>>> if the respective regions are not present in the memory-controller node
> >>>> of Guest DT.
> >>>>
> >>>> Suggested-by: Thierry Reding <treding@nvidia.com>
> >>>> Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
> >>>> ---
> >>>> .../nvidia,tegra186-mc.yaml | 95 ++++++++++---------
> >>>> 1 file changed, 49 insertions(+), 46 deletions(-)
> >>>>
> >>>> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> >>>> index 935d63d181d9..e0bd013ecca3 100644
> >>>> --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> >>>> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> >>>> @@ -34,11 +34,11 @@ properties:
> >>>> - nvidia,tegra234-mc
> >>>>
> >>>> reg:
> >>>> - minItems: 6
> >>>> + minItems: 4
> >>>> maxItems: 18
> >>>>
> >>>> reg-names:
> >>>> - minItems: 6
> >>>> + minItems: 4
> >>>> maxItems: 18
> >>>>
> >>>> interrupts:
> >>>> @@ -151,12 +151,13 @@ allOf:
> >>>>
> >>>> reg-names:
> >>>> items:
> >>>> - - const: sid
> >>>> - - const: broadcast
> >>>> - - const: ch0
> >>>> - - const: ch1
> >>>> - - const: ch2
> >>>> - - const: ch3
> >>>> + enum:
> >>>> + - sid
> >>>> + - broadcast
> >>>> + - ch0
> >>>> + - ch1
> >>>> + - ch2
> >>>> + - ch3
> >>>
> >>> I understand why sid and broadcast are becoming optional, but why order
> >>> of the rest is now fully flexible?
> >>
> >> The reason why the order of the rest doesn't matter is because we have
> >> both reg and reg-names properties and so the order in which they appear
> >> in the list doesn't matter. The only thing that matters is that the
> >> entries of the reg and reg-names properties match.
> >>
> >>> This does not even make sid/broadcast optional, but ch0!
> >>
> >> Yeah, this ends up making all entries optional, which isn't what we
> >> want. I don't know of a way to accurately express this in json-schema,
> >> though. Do you?
> >>
> >> If not, then maybe we need to resort to something like this and also
> >> mention explicitly in some comment that it is sid and broadcast that are
> >> optional.
> >
> > Actually, here's another variant that is a bit closer to what we want:
> >
> > --- >8 ---
> > diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> > index 935d63d181d9..86f1475926e4 100644
> > --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> > +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> > @@ -34,11 +34,11 @@ properties:
> > - nvidia,tegra234-mc
> >
> > reg:
> > - minItems: 6
> > + minItems: 4
> > maxItems: 18
> >
> > reg-names:
> > - minItems: 6
> > + minItems: 4
> > maxItems: 18
> >
> > interrupts:
> > @@ -146,17 +146,21 @@ allOf:
> > then:
> > properties:
> > reg:
> > + minItems: 4
> > maxItems: 6
> > description: 5 memory controller channels and 1 for stream-id registers
> >
> > reg-names:
> > - items:
> > - - const: sid
> > - - const: broadcast
> > - - const: ch0
> > - - const: ch1
> > - - const: ch2
> > - - const: ch3
> > + anyOf:
> > + - items:
> > + enum: [ sid, broadcast, ch0, ch1, ch2, ch3 ]
> > + uniqueItems: true
> > + minItems: 6
> > +
> > + - items:
> > + enum: [ ch0, ch1, ch2, ch3 ]
> > + uniqueItems: true
> > + minItems: 4
> >
> > - if:
> > properties:
> > @@ -165,29 +169,22 @@ allOf:
> > then:
> > properties:
> > reg:
> > - minItems: 18
> > + minItems: 16
> > description: 17 memory controller channels and 1 for stream-id registers
> >
> > reg-names:
> > - items:
> > - - const: sid
> > - - const: broadcast
> > - - const: ch0
> > - - const: ch1
> > - - const: ch2
> > - - const: ch3
> > - - const: ch4
> > - - const: ch5
> > - - const: ch6
> > - - const: ch7
> > - - const: ch8
> > - - const: ch9
> > - - const: ch10
> > - - const: ch11
> > - - const: ch12
> > - - const: ch13
> > - - const: ch14
> > - - const: ch15
> > + anyOf:
> > + - items:
> > + enum: [ sid, broadcast, ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7,
> > + ch8, ch9, ch10, ch11, ch12, ch13, ch14, ch15 ]
> > + minItems: 18
> > + uniqueItems: true
> > +
> > + - items:
> > + enum: [ ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7, ch8, ch9, ch10,
> > + ch11, ch12, ch13, ch14, ch15 ]
> > + minItems: 16
> > + uniqueItems: true
>
> No, because order is strict.
Why? I realize that prior to this the order was indeed strict and it's
common to have these listed in strict order in the DTS files. However,
this is an arbitrary restriction that was introduced in the patch that
added reg-names. However, */*-names properties have always assumed the
ordering to be non-strict because each entry from the * property gets
matched up with the corresponding entry in the *-names property, so the
ordering is completely irrelevant.
Thierry
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Patch v3 1/2] dt-bindings: make sid and broadcast reg optional
2024-04-25 9:39 ` Thierry Reding
@ 2024-04-25 9:45 ` Krzysztof Kozlowski
2024-04-25 15:03 ` Thierry Reding
0 siblings, 1 reply; 22+ messages in thread
From: Krzysztof Kozlowski @ 2024-04-25 9:45 UTC (permalink / raw)
To: Thierry Reding, Sumit Gupta, robh, conor+dt, maz, mark.rutland,
treding, jonathanh
Cc: devicetree, linux-kernel, linux-tegra, amhetre, bbasu
On 25/04/2024 11:39, Thierry Reding wrote:
> On Thu Apr 25, 2024 at 9:52 AM CEST, Krzysztof Kozlowski wrote:
>> On 24/04/2024 19:04, Thierry Reding wrote:
>>> On Wed Apr 24, 2024 at 6:26 PM CEST, Thierry Reding wrote:
>>>> On Mon Apr 22, 2024 at 9:02 AM CEST, Krzysztof Kozlowski wrote:
>>>>> On 12/04/2024 15:05, Sumit Gupta wrote:
>>>>>> MC SID and Broadbast channel register access is restricted for Guest VM.
>>>>>
>>>>> Broadcast
>>>>>
>>>>>> Make both the regions as optional for SoC's from Tegra186 onwards.
>>>>>
>>>>> onward?
>>>>>
>>>>>> Tegra MC driver will skip access to the restricted registers from Guest
>>>>>> if the respective regions are not present in the memory-controller node
>>>>>> of Guest DT.
>>>>>>
>>>>>> Suggested-by: Thierry Reding <treding@nvidia.com>
>>>>>> Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
>>>>>> ---
>>>>>> .../nvidia,tegra186-mc.yaml | 95 ++++++++++---------
>>>>>> 1 file changed, 49 insertions(+), 46 deletions(-)
>>>>>>
>>>>>> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
>>>>>> index 935d63d181d9..e0bd013ecca3 100644
>>>>>> --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
>>>>>> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
>>>>>> @@ -34,11 +34,11 @@ properties:
>>>>>> - nvidia,tegra234-mc
>>>>>>
>>>>>> reg:
>>>>>> - minItems: 6
>>>>>> + minItems: 4
>>>>>> maxItems: 18
>>>>>>
>>>>>> reg-names:
>>>>>> - minItems: 6
>>>>>> + minItems: 4
>>>>>> maxItems: 18
>>>>>>
>>>>>> interrupts:
>>>>>> @@ -151,12 +151,13 @@ allOf:
>>>>>>
>>>>>> reg-names:
>>>>>> items:
>>>>>> - - const: sid
>>>>>> - - const: broadcast
>>>>>> - - const: ch0
>>>>>> - - const: ch1
>>>>>> - - const: ch2
>>>>>> - - const: ch3
>>>>>> + enum:
>>>>>> + - sid
>>>>>> + - broadcast
>>>>>> + - ch0
>>>>>> + - ch1
>>>>>> + - ch2
>>>>>> + - ch3
>>>>>
>>>>> I understand why sid and broadcast are becoming optional, but why order
>>>>> of the rest is now fully flexible?
>>>>
>>>> The reason why the order of the rest doesn't matter is because we have
>>>> both reg and reg-names properties and so the order in which they appear
>>>> in the list doesn't matter. The only thing that matters is that the
>>>> entries of the reg and reg-names properties match.
>>>>
>>>>> This does not even make sid/broadcast optional, but ch0!
>>>>
>>>> Yeah, this ends up making all entries optional, which isn't what we
>>>> want. I don't know of a way to accurately express this in json-schema,
>>>> though. Do you?
>>>>
>>>> If not, then maybe we need to resort to something like this and also
>>>> mention explicitly in some comment that it is sid and broadcast that are
>>>> optional.
>>>
>>> Actually, here's another variant that is a bit closer to what we want:
>>>
>>> --- >8 ---
>>> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
>>> index 935d63d181d9..86f1475926e4 100644
>>> --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
>>> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
>>> @@ -34,11 +34,11 @@ properties:
>>> - nvidia,tegra234-mc
>>>
>>> reg:
>>> - minItems: 6
>>> + minItems: 4
>>> maxItems: 18
>>>
>>> reg-names:
>>> - minItems: 6
>>> + minItems: 4
>>> maxItems: 18
>>>
>>> interrupts:
>>> @@ -146,17 +146,21 @@ allOf:
>>> then:
>>> properties:
>>> reg:
>>> + minItems: 4
>>> maxItems: 6
>>> description: 5 memory controller channels and 1 for stream-id registers
>>>
>>> reg-names:
>>> - items:
>>> - - const: sid
>>> - - const: broadcast
>>> - - const: ch0
>>> - - const: ch1
>>> - - const: ch2
>>> - - const: ch3
>>> + anyOf:
>>> + - items:
>>> + enum: [ sid, broadcast, ch0, ch1, ch2, ch3 ]
>>> + uniqueItems: true
>>> + minItems: 6
>>> +
>>> + - items:
>>> + enum: [ ch0, ch1, ch2, ch3 ]
>>> + uniqueItems: true
>>> + minItems: 4
>>>
>>> - if:
>>> properties:
>>> @@ -165,29 +169,22 @@ allOf:
>>> then:
>>> properties:
>>> reg:
>>> - minItems: 18
>>> + minItems: 16
>>> description: 17 memory controller channels and 1 for stream-id registers
>>>
>>> reg-names:
>>> - items:
>>> - - const: sid
>>> - - const: broadcast
>>> - - const: ch0
>>> - - const: ch1
>>> - - const: ch2
>>> - - const: ch3
>>> - - const: ch4
>>> - - const: ch5
>>> - - const: ch6
>>> - - const: ch7
>>> - - const: ch8
>>> - - const: ch9
>>> - - const: ch10
>>> - - const: ch11
>>> - - const: ch12
>>> - - const: ch13
>>> - - const: ch14
>>> - - const: ch15
>>> + anyOf:
>>> + - items:
>>> + enum: [ sid, broadcast, ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7,
>>> + ch8, ch9, ch10, ch11, ch12, ch13, ch14, ch15 ]
>>> + minItems: 18
>>> + uniqueItems: true
>>> +
>>> + - items:
>>> + enum: [ ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7, ch8, ch9, ch10,
>>> + ch11, ch12, ch13, ch14, ch15 ]
>>> + minItems: 16
>>> + uniqueItems: true
>>
>> No, because order is strict.
>
> Why? I realize that prior to this the order was indeed strict and it's
That's the policy for entire Devicetree. I said why in other email:
because any bindings consumer can take it via indices.
> common to have these listed in strict order in the DTS files. However,
> this is an arbitrary restriction that was introduced in the patch that
> added reg-names. However, */*-names properties have always assumed the
> ordering to be non-strict because each entry from the * property gets
> matched up with the corresponding entry in the *-names property, so the
> ordering is completely irrelevant.
This was raised so many times... reg-names is just a helper. It does not
change the fact that order should be strict and if binding defined the
order, it is an ABI.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Patch v3 1/2] dt-bindings: make sid and broadcast reg optional
2024-04-25 9:45 ` Krzysztof Kozlowski
@ 2024-04-25 15:03 ` Thierry Reding
2024-04-25 15:16 ` Krzysztof Kozlowski
0 siblings, 1 reply; 22+ messages in thread
From: Thierry Reding @ 2024-04-25 15:03 UTC (permalink / raw)
To: Krzysztof Kozlowski, Sumit Gupta, robh, conor+dt, maz,
mark.rutland, treding, jonathanh
Cc: devicetree, linux-kernel, linux-tegra, amhetre, bbasu
[-- Attachment #1: Type: text/plain, Size: 8298 bytes --]
On Thu Apr 25, 2024 at 11:45 AM CEST, Krzysztof Kozlowski wrote:
> On 25/04/2024 11:39, Thierry Reding wrote:
> > On Thu Apr 25, 2024 at 9:52 AM CEST, Krzysztof Kozlowski wrote:
> >> On 24/04/2024 19:04, Thierry Reding wrote:
> >>> On Wed Apr 24, 2024 at 6:26 PM CEST, Thierry Reding wrote:
> >>>> On Mon Apr 22, 2024 at 9:02 AM CEST, Krzysztof Kozlowski wrote:
> >>>>> On 12/04/2024 15:05, Sumit Gupta wrote:
> >>>>>> MC SID and Broadbast channel register access is restricted for Guest VM.
> >>>>>
> >>>>> Broadcast
> >>>>>
> >>>>>> Make both the regions as optional for SoC's from Tegra186 onwards.
> >>>>>
> >>>>> onward?
> >>>>>
> >>>>>> Tegra MC driver will skip access to the restricted registers from Guest
> >>>>>> if the respective regions are not present in the memory-controller node
> >>>>>> of Guest DT.
> >>>>>>
> >>>>>> Suggested-by: Thierry Reding <treding@nvidia.com>
> >>>>>> Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
> >>>>>> ---
> >>>>>> .../nvidia,tegra186-mc.yaml | 95 ++++++++++---------
> >>>>>> 1 file changed, 49 insertions(+), 46 deletions(-)
> >>>>>>
> >>>>>> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> >>>>>> index 935d63d181d9..e0bd013ecca3 100644
> >>>>>> --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> >>>>>> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> >>>>>> @@ -34,11 +34,11 @@ properties:
> >>>>>> - nvidia,tegra234-mc
> >>>>>>
> >>>>>> reg:
> >>>>>> - minItems: 6
> >>>>>> + minItems: 4
> >>>>>> maxItems: 18
> >>>>>>
> >>>>>> reg-names:
> >>>>>> - minItems: 6
> >>>>>> + minItems: 4
> >>>>>> maxItems: 18
> >>>>>>
> >>>>>> interrupts:
> >>>>>> @@ -151,12 +151,13 @@ allOf:
> >>>>>>
> >>>>>> reg-names:
> >>>>>> items:
> >>>>>> - - const: sid
> >>>>>> - - const: broadcast
> >>>>>> - - const: ch0
> >>>>>> - - const: ch1
> >>>>>> - - const: ch2
> >>>>>> - - const: ch3
> >>>>>> + enum:
> >>>>>> + - sid
> >>>>>> + - broadcast
> >>>>>> + - ch0
> >>>>>> + - ch1
> >>>>>> + - ch2
> >>>>>> + - ch3
> >>>>>
> >>>>> I understand why sid and broadcast are becoming optional, but why order
> >>>>> of the rest is now fully flexible?
> >>>>
> >>>> The reason why the order of the rest doesn't matter is because we have
> >>>> both reg and reg-names properties and so the order in which they appear
> >>>> in the list doesn't matter. The only thing that matters is that the
> >>>> entries of the reg and reg-names properties match.
> >>>>
> >>>>> This does not even make sid/broadcast optional, but ch0!
> >>>>
> >>>> Yeah, this ends up making all entries optional, which isn't what we
> >>>> want. I don't know of a way to accurately express this in json-schema,
> >>>> though. Do you?
> >>>>
> >>>> If not, then maybe we need to resort to something like this and also
> >>>> mention explicitly in some comment that it is sid and broadcast that are
> >>>> optional.
> >>>
> >>> Actually, here's another variant that is a bit closer to what we want:
> >>>
> >>> --- >8 ---
> >>> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> >>> index 935d63d181d9..86f1475926e4 100644
> >>> --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> >>> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> >>> @@ -34,11 +34,11 @@ properties:
> >>> - nvidia,tegra234-mc
> >>>
> >>> reg:
> >>> - minItems: 6
> >>> + minItems: 4
> >>> maxItems: 18
> >>>
> >>> reg-names:
> >>> - minItems: 6
> >>> + minItems: 4
> >>> maxItems: 18
> >>>
> >>> interrupts:
> >>> @@ -146,17 +146,21 @@ allOf:
> >>> then:
> >>> properties:
> >>> reg:
> >>> + minItems: 4
> >>> maxItems: 6
> >>> description: 5 memory controller channels and 1 for stream-id registers
> >>>
> >>> reg-names:
> >>> - items:
> >>> - - const: sid
> >>> - - const: broadcast
> >>> - - const: ch0
> >>> - - const: ch1
> >>> - - const: ch2
> >>> - - const: ch3
> >>> + anyOf:
> >>> + - items:
> >>> + enum: [ sid, broadcast, ch0, ch1, ch2, ch3 ]
> >>> + uniqueItems: true
> >>> + minItems: 6
> >>> +
> >>> + - items:
> >>> + enum: [ ch0, ch1, ch2, ch3 ]
> >>> + uniqueItems: true
> >>> + minItems: 4
> >>>
> >>> - if:
> >>> properties:
> >>> @@ -165,29 +169,22 @@ allOf:
> >>> then:
> >>> properties:
> >>> reg:
> >>> - minItems: 18
> >>> + minItems: 16
> >>> description: 17 memory controller channels and 1 for stream-id registers
> >>>
> >>> reg-names:
> >>> - items:
> >>> - - const: sid
> >>> - - const: broadcast
> >>> - - const: ch0
> >>> - - const: ch1
> >>> - - const: ch2
> >>> - - const: ch3
> >>> - - const: ch4
> >>> - - const: ch5
> >>> - - const: ch6
> >>> - - const: ch7
> >>> - - const: ch8
> >>> - - const: ch9
> >>> - - const: ch10
> >>> - - const: ch11
> >>> - - const: ch12
> >>> - - const: ch13
> >>> - - const: ch14
> >>> - - const: ch15
> >>> + anyOf:
> >>> + - items:
> >>> + enum: [ sid, broadcast, ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7,
> >>> + ch8, ch9, ch10, ch11, ch12, ch13, ch14, ch15 ]
> >>> + minItems: 18
> >>> + uniqueItems: true
> >>> +
> >>> + - items:
> >>> + enum: [ ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7, ch8, ch9, ch10,
> >>> + ch11, ch12, ch13, ch14, ch15 ]
> >>> + minItems: 16
> >>> + uniqueItems: true
> >>
> >> No, because order is strict.
> >
> > Why? I realize that prior to this the order was indeed strict and it's
>
> That's the policy for entire Devicetree. I said why in other email:
> because any bindings consumer can take it via indices.
>
> > common to have these listed in strict order in the DTS files. However,
> > this is an arbitrary restriction that was introduced in the patch that
> > added reg-names. However, */*-names properties have always assumed the
> > ordering to be non-strict because each entry from the * property gets
> > matched up with the corresponding entry in the *-names property, so the
> > ordering is completely irrelevant.
>
> This was raised so many times... reg-names is just a helper. It does not
> change the fact that order should be strict and if binding defined the
> order, it is an ABI.
Sorry, but that's not how we've dealt with this in the past. Even though
this was now ten or more years ago, I distinctly recall that when we
started adding these *-names properties and at the time it was very much
implied that the order didn't matter.
The only use-case that I know of where order was always meant to matter
is backwards-compatibility for devices that used to have a single entry
(hence drivers couldn't rely on *-names to resolve the index) and then
had additional entries added. The *-names entry for that previously
single entry would now obviously have to always be first in the list to
preserve backwards-compatibility.
Besides, if reg-names was really only a helper, then it would also be
completely redundant. Many device tree bindings have *-names properties
marked as "required" precisely because of the role that they serve.
Thierry
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Patch v3 1/2] dt-bindings: make sid and broadcast reg optional
2024-04-25 15:03 ` Thierry Reding
@ 2024-04-25 15:16 ` Krzysztof Kozlowski
2024-04-25 15:51 ` Thierry Reding
0 siblings, 1 reply; 22+ messages in thread
From: Krzysztof Kozlowski @ 2024-04-25 15:16 UTC (permalink / raw)
To: Thierry Reding, Sumit Gupta, robh, conor+dt, maz, mark.rutland,
treding, jonathanh
Cc: devicetree, linux-kernel, linux-tegra, amhetre, bbasu
On 25/04/2024 17:03, Thierry Reding wrote:
> On Thu Apr 25, 2024 at 11:45 AM CEST, Krzysztof Kozlowski wrote:
>> On 25/04/2024 11:39, Thierry Reding wrote:
>>> On Thu Apr 25, 2024 at 9:52 AM CEST, Krzysztof Kozlowski wrote:
>>>> On 24/04/2024 19:04, Thierry Reding wrote:
>>>>> On Wed Apr 24, 2024 at 6:26 PM CEST, Thierry Reding wrote:
>>>>>> On Mon Apr 22, 2024 at 9:02 AM CEST, Krzysztof Kozlowski wrote:
>>>>>>> On 12/04/2024 15:05, Sumit Gupta wrote:
>>>>>>>> MC SID and Broadbast channel register access is restricted for Guest VM.
>>>>>>>
>>>>>>> Broadcast
>>>>>>>
>>>>>>>> Make both the regions as optional for SoC's from Tegra186 onwards.
>>>>>>>
>>>>>>> onward?
>>>>>>>
>>>>>>>> Tegra MC driver will skip access to the restricted registers from Guest
>>>>>>>> if the respective regions are not present in the memory-controller node
>>>>>>>> of Guest DT.
>>>>>>>>
>>>>>>>> Suggested-by: Thierry Reding <treding@nvidia.com>
>>>>>>>> Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
>>>>>>>> ---
>>>>>>>> .../nvidia,tegra186-mc.yaml | 95 ++++++++++---------
>>>>>>>> 1 file changed, 49 insertions(+), 46 deletions(-)
>>>>>>>>
>>>>>>>> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
>>>>>>>> index 935d63d181d9..e0bd013ecca3 100644
>>>>>>>> --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
>>>>>>>> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
>>>>>>>> @@ -34,11 +34,11 @@ properties:
>>>>>>>> - nvidia,tegra234-mc
>>>>>>>>
>>>>>>>> reg:
>>>>>>>> - minItems: 6
>>>>>>>> + minItems: 4
>>>>>>>> maxItems: 18
>>>>>>>>
>>>>>>>> reg-names:
>>>>>>>> - minItems: 6
>>>>>>>> + minItems: 4
>>>>>>>> maxItems: 18
>>>>>>>>
>>>>>>>> interrupts:
>>>>>>>> @@ -151,12 +151,13 @@ allOf:
>>>>>>>>
>>>>>>>> reg-names:
>>>>>>>> items:
>>>>>>>> - - const: sid
>>>>>>>> - - const: broadcast
>>>>>>>> - - const: ch0
>>>>>>>> - - const: ch1
>>>>>>>> - - const: ch2
>>>>>>>> - - const: ch3
>>>>>>>> + enum:
>>>>>>>> + - sid
>>>>>>>> + - broadcast
>>>>>>>> + - ch0
>>>>>>>> + - ch1
>>>>>>>> + - ch2
>>>>>>>> + - ch3
>>>>>>>
>>>>>>> I understand why sid and broadcast are becoming optional, but why order
>>>>>>> of the rest is now fully flexible?
>>>>>>
>>>>>> The reason why the order of the rest doesn't matter is because we have
>>>>>> both reg and reg-names properties and so the order in which they appear
>>>>>> in the list doesn't matter. The only thing that matters is that the
>>>>>> entries of the reg and reg-names properties match.
>>>>>>
>>>>>>> This does not even make sid/broadcast optional, but ch0!
>>>>>>
>>>>>> Yeah, this ends up making all entries optional, which isn't what we
>>>>>> want. I don't know of a way to accurately express this in json-schema,
>>>>>> though. Do you?
>>>>>>
>>>>>> If not, then maybe we need to resort to something like this and also
>>>>>> mention explicitly in some comment that it is sid and broadcast that are
>>>>>> optional.
>>>>>
>>>>> Actually, here's another variant that is a bit closer to what we want:
>>>>>
>>>>> --- >8 ---
>>>>> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
>>>>> index 935d63d181d9..86f1475926e4 100644
>>>>> --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
>>>>> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
>>>>> @@ -34,11 +34,11 @@ properties:
>>>>> - nvidia,tegra234-mc
>>>>>
>>>>> reg:
>>>>> - minItems: 6
>>>>> + minItems: 4
>>>>> maxItems: 18
>>>>>
>>>>> reg-names:
>>>>> - minItems: 6
>>>>> + minItems: 4
>>>>> maxItems: 18
>>>>>
>>>>> interrupts:
>>>>> @@ -146,17 +146,21 @@ allOf:
>>>>> then:
>>>>> properties:
>>>>> reg:
>>>>> + minItems: 4
>>>>> maxItems: 6
>>>>> description: 5 memory controller channels and 1 for stream-id registers
>>>>>
>>>>> reg-names:
>>>>> - items:
>>>>> - - const: sid
>>>>> - - const: broadcast
>>>>> - - const: ch0
>>>>> - - const: ch1
>>>>> - - const: ch2
>>>>> - - const: ch3
>>>>> + anyOf:
>>>>> + - items:
>>>>> + enum: [ sid, broadcast, ch0, ch1, ch2, ch3 ]
>>>>> + uniqueItems: true
>>>>> + minItems: 6
>>>>> +
>>>>> + - items:
>>>>> + enum: [ ch0, ch1, ch2, ch3 ]
>>>>> + uniqueItems: true
>>>>> + minItems: 4
>>>>>
>>>>> - if:
>>>>> properties:
>>>>> @@ -165,29 +169,22 @@ allOf:
>>>>> then:
>>>>> properties:
>>>>> reg:
>>>>> - minItems: 18
>>>>> + minItems: 16
>>>>> description: 17 memory controller channels and 1 for stream-id registers
>>>>>
>>>>> reg-names:
>>>>> - items:
>>>>> - - const: sid
>>>>> - - const: broadcast
>>>>> - - const: ch0
>>>>> - - const: ch1
>>>>> - - const: ch2
>>>>> - - const: ch3
>>>>> - - const: ch4
>>>>> - - const: ch5
>>>>> - - const: ch6
>>>>> - - const: ch7
>>>>> - - const: ch8
>>>>> - - const: ch9
>>>>> - - const: ch10
>>>>> - - const: ch11
>>>>> - - const: ch12
>>>>> - - const: ch13
>>>>> - - const: ch14
>>>>> - - const: ch15
>>>>> + anyOf:
>>>>> + - items:
>>>>> + enum: [ sid, broadcast, ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7,
>>>>> + ch8, ch9, ch10, ch11, ch12, ch13, ch14, ch15 ]
>>>>> + minItems: 18
>>>>> + uniqueItems: true
>>>>> +
>>>>> + - items:
>>>>> + enum: [ ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7, ch8, ch9, ch10,
>>>>> + ch11, ch12, ch13, ch14, ch15 ]
>>>>> + minItems: 16
>>>>> + uniqueItems: true
>>>>
>>>> No, because order is strict.
>>>
>>> Why? I realize that prior to this the order was indeed strict and it's
>>
>> That's the policy for entire Devicetree. I said why in other email:
>> because any bindings consumer can take it via indices.
>>
>>> common to have these listed in strict order in the DTS files. However,
>>> this is an arbitrary restriction that was introduced in the patch that
>>> added reg-names. However, */*-names properties have always assumed the
>>> ordering to be non-strict because each entry from the * property gets
>>> matched up with the corresponding entry in the *-names property, so the
>>> ordering is completely irrelevant.
>>
>> This was raised so many times... reg-names is just a helper. It does not
>> change the fact that order should be strict and if binding defined the
>> order, it is an ABI.
>
> Sorry, but that's not how we've dealt with this in the past. Even though
> this was now ten or more years ago, I distinctly recall that when we
> started adding these *-names properties and at the time it was very much
> implied that the order didn't matter.
Then you added it wrong and Rob was expressing the purpose of names
multiple times. The names were for cases when you could not determine
the order.
The strict order was repeated so many times in the mailing list, I lost
track.
> The only use-case that I know of where order was always meant to matter
> is backwards-compatibility for devices that used to have a single entry
> (hence drivers couldn't rely on *-names to resolve the index) and then
> had additional entries added. The *-names entry for that previously
> single entry would now obviously have to always be first in the list to
> preserve backwards-compatibility.
>
> Besides, if reg-names was really only a helper, then it would also be
> completely redundant. Many device tree bindings have *-names properties
> marked as "required" precisely because of the role that they serve.
For most of the cases, so ones which do not have flexible order, it is
redundant and for that reason Qualcomm has been switching away from
xxx-names in several drivers.
However it is not entirely redundant, because it allows bindings
consumers to choose either index or name. Both are ABI, when documented
in the binding with strict order.
https://lore.kernel.org/all/CAL_JsqJSYAsotjzvOUy_f7ZRfsSrfZyuEzq7eRwwKk12FBgxYg@mail.gmail.com/
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Patch v3 1/2] dt-bindings: make sid and broadcast reg optional
2024-04-25 15:16 ` Krzysztof Kozlowski
@ 2024-04-25 15:51 ` Thierry Reding
0 siblings, 0 replies; 22+ messages in thread
From: Thierry Reding @ 2024-04-25 15:51 UTC (permalink / raw)
To: Krzysztof Kozlowski, Sumit Gupta, robh, conor+dt, maz,
mark.rutland, treding, jonathanh
Cc: devicetree, linux-kernel, linux-tegra, amhetre, bbasu
[-- Attachment #1: Type: text/plain, Size: 10139 bytes --]
On Thu Apr 25, 2024 at 5:16 PM CEST, Krzysztof Kozlowski wrote:
> On 25/04/2024 17:03, Thierry Reding wrote:
> > On Thu Apr 25, 2024 at 11:45 AM CEST, Krzysztof Kozlowski wrote:
> >> On 25/04/2024 11:39, Thierry Reding wrote:
> >>> On Thu Apr 25, 2024 at 9:52 AM CEST, Krzysztof Kozlowski wrote:
> >>>> On 24/04/2024 19:04, Thierry Reding wrote:
> >>>>> On Wed Apr 24, 2024 at 6:26 PM CEST, Thierry Reding wrote:
> >>>>>> On Mon Apr 22, 2024 at 9:02 AM CEST, Krzysztof Kozlowski wrote:
> >>>>>>> On 12/04/2024 15:05, Sumit Gupta wrote:
> >>>>>>>> MC SID and Broadbast channel register access is restricted for Guest VM.
> >>>>>>>
> >>>>>>> Broadcast
> >>>>>>>
> >>>>>>>> Make both the regions as optional for SoC's from Tegra186 onwards.
> >>>>>>>
> >>>>>>> onward?
> >>>>>>>
> >>>>>>>> Tegra MC driver will skip access to the restricted registers from Guest
> >>>>>>>> if the respective regions are not present in the memory-controller node
> >>>>>>>> of Guest DT.
> >>>>>>>>
> >>>>>>>> Suggested-by: Thierry Reding <treding@nvidia.com>
> >>>>>>>> Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
> >>>>>>>> ---
> >>>>>>>> .../nvidia,tegra186-mc.yaml | 95 ++++++++++---------
> >>>>>>>> 1 file changed, 49 insertions(+), 46 deletions(-)
> >>>>>>>>
> >>>>>>>> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> >>>>>>>> index 935d63d181d9..e0bd013ecca3 100644
> >>>>>>>> --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> >>>>>>>> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> >>>>>>>> @@ -34,11 +34,11 @@ properties:
> >>>>>>>> - nvidia,tegra234-mc
> >>>>>>>>
> >>>>>>>> reg:
> >>>>>>>> - minItems: 6
> >>>>>>>> + minItems: 4
> >>>>>>>> maxItems: 18
> >>>>>>>>
> >>>>>>>> reg-names:
> >>>>>>>> - minItems: 6
> >>>>>>>> + minItems: 4
> >>>>>>>> maxItems: 18
> >>>>>>>>
> >>>>>>>> interrupts:
> >>>>>>>> @@ -151,12 +151,13 @@ allOf:
> >>>>>>>>
> >>>>>>>> reg-names:
> >>>>>>>> items:
> >>>>>>>> - - const: sid
> >>>>>>>> - - const: broadcast
> >>>>>>>> - - const: ch0
> >>>>>>>> - - const: ch1
> >>>>>>>> - - const: ch2
> >>>>>>>> - - const: ch3
> >>>>>>>> + enum:
> >>>>>>>> + - sid
> >>>>>>>> + - broadcast
> >>>>>>>> + - ch0
> >>>>>>>> + - ch1
> >>>>>>>> + - ch2
> >>>>>>>> + - ch3
> >>>>>>>
> >>>>>>> I understand why sid and broadcast are becoming optional, but why order
> >>>>>>> of the rest is now fully flexible?
> >>>>>>
> >>>>>> The reason why the order of the rest doesn't matter is because we have
> >>>>>> both reg and reg-names properties and so the order in which they appear
> >>>>>> in the list doesn't matter. The only thing that matters is that the
> >>>>>> entries of the reg and reg-names properties match.
> >>>>>>
> >>>>>>> This does not even make sid/broadcast optional, but ch0!
> >>>>>>
> >>>>>> Yeah, this ends up making all entries optional, which isn't what we
> >>>>>> want. I don't know of a way to accurately express this in json-schema,
> >>>>>> though. Do you?
> >>>>>>
> >>>>>> If not, then maybe we need to resort to something like this and also
> >>>>>> mention explicitly in some comment that it is sid and broadcast that are
> >>>>>> optional.
> >>>>>
> >>>>> Actually, here's another variant that is a bit closer to what we want:
> >>>>>
> >>>>> --- >8 ---
> >>>>> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> >>>>> index 935d63d181d9..86f1475926e4 100644
> >>>>> --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> >>>>> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml
> >>>>> @@ -34,11 +34,11 @@ properties:
> >>>>> - nvidia,tegra234-mc
> >>>>>
> >>>>> reg:
> >>>>> - minItems: 6
> >>>>> + minItems: 4
> >>>>> maxItems: 18
> >>>>>
> >>>>> reg-names:
> >>>>> - minItems: 6
> >>>>> + minItems: 4
> >>>>> maxItems: 18
> >>>>>
> >>>>> interrupts:
> >>>>> @@ -146,17 +146,21 @@ allOf:
> >>>>> then:
> >>>>> properties:
> >>>>> reg:
> >>>>> + minItems: 4
> >>>>> maxItems: 6
> >>>>> description: 5 memory controller channels and 1 for stream-id registers
> >>>>>
> >>>>> reg-names:
> >>>>> - items:
> >>>>> - - const: sid
> >>>>> - - const: broadcast
> >>>>> - - const: ch0
> >>>>> - - const: ch1
> >>>>> - - const: ch2
> >>>>> - - const: ch3
> >>>>> + anyOf:
> >>>>> + - items:
> >>>>> + enum: [ sid, broadcast, ch0, ch1, ch2, ch3 ]
> >>>>> + uniqueItems: true
> >>>>> + minItems: 6
> >>>>> +
> >>>>> + - items:
> >>>>> + enum: [ ch0, ch1, ch2, ch3 ]
> >>>>> + uniqueItems: true
> >>>>> + minItems: 4
> >>>>>
> >>>>> - if:
> >>>>> properties:
> >>>>> @@ -165,29 +169,22 @@ allOf:
> >>>>> then:
> >>>>> properties:
> >>>>> reg:
> >>>>> - minItems: 18
> >>>>> + minItems: 16
> >>>>> description: 17 memory controller channels and 1 for stream-id registers
> >>>>>
> >>>>> reg-names:
> >>>>> - items:
> >>>>> - - const: sid
> >>>>> - - const: broadcast
> >>>>> - - const: ch0
> >>>>> - - const: ch1
> >>>>> - - const: ch2
> >>>>> - - const: ch3
> >>>>> - - const: ch4
> >>>>> - - const: ch5
> >>>>> - - const: ch6
> >>>>> - - const: ch7
> >>>>> - - const: ch8
> >>>>> - - const: ch9
> >>>>> - - const: ch10
> >>>>> - - const: ch11
> >>>>> - - const: ch12
> >>>>> - - const: ch13
> >>>>> - - const: ch14
> >>>>> - - const: ch15
> >>>>> + anyOf:
> >>>>> + - items:
> >>>>> + enum: [ sid, broadcast, ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7,
> >>>>> + ch8, ch9, ch10, ch11, ch12, ch13, ch14, ch15 ]
> >>>>> + minItems: 18
> >>>>> + uniqueItems: true
> >>>>> +
> >>>>> + - items:
> >>>>> + enum: [ ch0, ch1, ch2, ch3, ch4, ch5, ch6, ch7, ch8, ch9, ch10,
> >>>>> + ch11, ch12, ch13, ch14, ch15 ]
> >>>>> + minItems: 16
> >>>>> + uniqueItems: true
> >>>>
> >>>> No, because order is strict.
> >>>
> >>> Why? I realize that prior to this the order was indeed strict and it's
> >>
> >> That's the policy for entire Devicetree. I said why in other email:
> >> because any bindings consumer can take it via indices.
> >>
> >>> common to have these listed in strict order in the DTS files. However,
> >>> this is an arbitrary restriction that was introduced in the patch that
> >>> added reg-names. However, */*-names properties have always assumed the
> >>> ordering to be non-strict because each entry from the * property gets
> >>> matched up with the corresponding entry in the *-names property, so the
> >>> ordering is completely irrelevant.
> >>
> >> This was raised so many times... reg-names is just a helper. It does not
> >> change the fact that order should be strict and if binding defined the
> >> order, it is an ABI.
> >
> > Sorry, but that's not how we've dealt with this in the past. Even though
> > this was now ten or more years ago, I distinctly recall that when we
> > started adding these *-names properties and at the time it was very much
> > implied that the order didn't matter.
>
> Then you added it wrong and Rob was expressing the purpose of names
> multiple times. The names were for cases when you could not determine
> the order.
>
> The strict order was repeated so many times in the mailing list, I lost
> track.
Sorry, but this isn't true. Perhaps the device tree maintainers' stance
on this has changed over the years, but don't go around telling people
that they did things wrongly when all they were doing was follow what
was considered best practice at the time.
> > The only use-case that I know of where order was always meant to matter
> > is backwards-compatibility for devices that used to have a single entry
> > (hence drivers couldn't rely on *-names to resolve the index) and then
> > had additional entries added. The *-names entry for that previously
> > single entry would now obviously have to always be first in the list to
> > preserve backwards-compatibility.
> >
> > Besides, if reg-names was really only a helper, then it would also be
> > completely redundant. Many device tree bindings have *-names properties
> > marked as "required" precisely because of the role that they serve.
>
> For most of the cases, so ones which do not have flexible order, it is
> redundant and for that reason Qualcomm has been switching away from
> xxx-names in several drivers.
>
> However it is not entirely redundant, because it allows bindings
> consumers to choose either index or name. Both are ABI, when documented
> in the binding with strict order.
>
> https://lore.kernel.org/all/CAL_JsqJSYAsotjzvOUy_f7ZRfsSrfZyuEzq7eRwwKk12FBgxYg@mail.gmail.com/
You do realize that "flexible order" is entirely defined by the
bindings, right? There's nothing inherently strict in any of this. The
bindings define any order (or lack thereof) that entries should be
listed in and the drivers that implement the bindings need to respect
whatever the bindings specify.
Thierry
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^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2024-04-25 15:51 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-04-12 13:05 [Patch v3 0/2] memory: tegra: Skip restricted register access from Guest Sumit Gupta
2024-04-12 13:05 ` [Patch v3 1/2] dt-bindings: make sid and broadcast reg optional Sumit Gupta
2024-04-22 7:02 ` Krzysztof Kozlowski
2024-04-24 16:26 ` Thierry Reding
2024-04-24 17:04 ` Thierry Reding
2024-04-25 7:52 ` Krzysztof Kozlowski
2024-04-25 9:39 ` Thierry Reding
2024-04-25 9:45 ` Krzysztof Kozlowski
2024-04-25 15:03 ` Thierry Reding
2024-04-25 15:16 ` Krzysztof Kozlowski
2024-04-25 15:51 ` Thierry Reding
2024-04-25 7:51 ` Krzysztof Kozlowski
2024-04-25 7:52 ` Krzysztof Kozlowski
2024-04-12 13:05 ` [Patch v3 2/2] memory: tegra: make sid and broadcast regions optional Sumit Gupta
2024-04-22 7:12 ` Krzysztof Kozlowski
2024-04-22 14:36 ` Sumit Gupta
2024-04-23 14:41 ` Krzysztof Kozlowski
2024-04-23 19:46 ` Sumit Gupta
2024-04-24 4:09 ` Krzysztof Kozlowski
2024-04-24 5:27 ` Sumit Gupta
2024-04-24 5:44 ` Krzysztof Kozlowski
2024-04-24 6:27 ` Sumit Gupta
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