* [PATCH 0/3] Add DT bindings and DT nodes for USB in SC7280
@ 2021-03-17 11:01 Sandeep Maheswaram
2021-03-17 11:01 ` [PATCH 1/3] dt-bindings: usb: qcom,dwc3: Add bindings for SC7280 Sandeep Maheswaram
` (2 more replies)
0 siblings, 3 replies; 11+ messages in thread
From: Sandeep Maheswaram @ 2021-03-17 11:01 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Kishon Vijay Abraham I, Rob Herring,
Vinod Koul, Greg Kroah-Hartman, Wesley Cheng, Stephen Boyd,
Doug Anderson, Matthias Kaehlcke
Cc: linux-arm-msm, linux-kernel, devicetree, linux-phy, linux-usb,
Manu Gautam, Sandeep Maheswaram
This series includes usb controller and phy binding updates
for SC7280 SoC and DT chnages for SC7280 SoC and SC7280 IDP board.
The IDP board change dependency on the below patch series
https://patchwork.kernel.org/project/linux-arm-msm/list/?series=448321
Sandeep Maheswaram (3):
dt-bindings: usb: qcom,dwc3: Add bindings for SC7280
dt-bindings: phy: qcom,usb-snps-femto-v2: Add bindings for SC7280
arm64: dts: qcom: sc7280: Add USB related nodes
.../bindings/phy/qcom,usb-snps-femto-v2.yaml | 1 +
.../devicetree/bindings/usb/qcom,dwc3.yaml | 1 +
arch/arm64/boot/dts/qcom/sc7280-idp.dts | 39 ++++++
arch/arm64/boot/dts/qcom/sc7280.dtsi | 149 +++++++++++++++++++++
4 files changed, 190 insertions(+)
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 11+ messages in thread* [PATCH 1/3] dt-bindings: usb: qcom,dwc3: Add bindings for SC7280 2021-03-17 11:01 [PATCH 0/3] Add DT bindings and DT nodes for USB in SC7280 Sandeep Maheswaram @ 2021-03-17 11:01 ` Sandeep Maheswaram 2021-03-17 19:34 ` Matthias Kaehlcke ` (2 more replies) 2021-03-17 11:01 ` [PATCH 2/3] dt-bindings: phy: qcom,usb-snps-femto-v2: " Sandeep Maheswaram 2021-03-17 11:01 ` [PATCH 3/3] arm64: dts: qcom: sc7280: Add USB related nodes Sandeep Maheswaram 2 siblings, 3 replies; 11+ messages in thread From: Sandeep Maheswaram @ 2021-03-17 11:01 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Kishon Vijay Abraham I, Rob Herring, Vinod Koul, Greg Kroah-Hartman, Wesley Cheng, Stephen Boyd, Doug Anderson, Matthias Kaehlcke Cc: linux-arm-msm, linux-kernel, devicetree, linux-phy, linux-usb, Manu Gautam, Sandeep Maheswaram Add the compatible string for sc7280 SoC from Qualcomm. Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> --- Documentation/devicetree/bindings/usb/qcom,dwc3.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml index c3cbd1f..413299b 100644 --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml @@ -16,6 +16,7 @@ properties: - qcom,msm8996-dwc3 - qcom,msm8998-dwc3 - qcom,sc7180-dwc3 + - qcom,sc7280-dwc3 - qcom,sdm845-dwc3 - qcom,sdx55-dwc3 - qcom,sm8150-dwc3 -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] dt-bindings: usb: qcom,dwc3: Add bindings for SC7280 2021-03-17 11:01 ` [PATCH 1/3] dt-bindings: usb: qcom,dwc3: Add bindings for SC7280 Sandeep Maheswaram @ 2021-03-17 19:34 ` Matthias Kaehlcke 2021-03-23 21:01 ` Stephen Boyd 2021-03-26 0:22 ` Rob Herring 2 siblings, 0 replies; 11+ messages in thread From: Matthias Kaehlcke @ 2021-03-17 19:34 UTC (permalink / raw) To: Sandeep Maheswaram Cc: Andy Gross, Bjorn Andersson, Kishon Vijay Abraham I, Rob Herring, Vinod Koul, Greg Kroah-Hartman, Wesley Cheng, Stephen Boyd, Doug Anderson, linux-arm-msm, linux-kernel, devicetree, linux-phy, linux-usb, Manu Gautam On Wed, Mar 17, 2021 at 04:31:39PM +0530, Sandeep Maheswaram wrote: > Add the compatible string for sc7280 SoC from Qualcomm. > > Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> > --- > Documentation/devicetree/bindings/usb/qcom,dwc3.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml > index c3cbd1f..413299b 100644 > --- a/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml > +++ b/Documentation/devicetree/bindings/usb/qcom,dwc3.yaml > @@ -16,6 +16,7 @@ properties: > - qcom,msm8996-dwc3 > - qcom,msm8998-dwc3 > - qcom,sc7180-dwc3 > + - qcom,sc7280-dwc3 > - qcom,sdm845-dwc3 > - qcom,sdx55-dwc3 > - qcom,sm8150-dwc3 Reviewed-by: Matthias Kaehlcke <mka@chromium.org> ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] dt-bindings: usb: qcom,dwc3: Add bindings for SC7280 2021-03-17 11:01 ` [PATCH 1/3] dt-bindings: usb: qcom,dwc3: Add bindings for SC7280 Sandeep Maheswaram 2021-03-17 19:34 ` Matthias Kaehlcke @ 2021-03-23 21:01 ` Stephen Boyd 2021-03-26 0:22 ` Rob Herring 2 siblings, 0 replies; 11+ messages in thread From: Stephen Boyd @ 2021-03-23 21:01 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Doug Anderson, Greg Kroah-Hartman, Kishon Vijay Abraham I, Matthias Kaehlcke, Rob Herring, Sandeep Maheswaram, Vinod Koul, Wesley Cheng Cc: linux-arm-msm, linux-kernel, devicetree, linux-phy, linux-usb, Manu Gautam, Sandeep Maheswaram Quoting Sandeep Maheswaram (2021-03-17 04:01:39) > Add the compatible string for sc7280 SoC from Qualcomm. > > Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org> ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] dt-bindings: usb: qcom,dwc3: Add bindings for SC7280 2021-03-17 11:01 ` [PATCH 1/3] dt-bindings: usb: qcom,dwc3: Add bindings for SC7280 Sandeep Maheswaram 2021-03-17 19:34 ` Matthias Kaehlcke 2021-03-23 21:01 ` Stephen Boyd @ 2021-03-26 0:22 ` Rob Herring 2 siblings, 0 replies; 11+ messages in thread From: Rob Herring @ 2021-03-26 0:22 UTC (permalink / raw) To: Sandeep Maheswaram Cc: linux-phy, Stephen Boyd, Vinod Koul, Doug Anderson, linux-arm-msm, devicetree, Manu Gautam, linux-usb, Bjorn Andersson, Rob Herring, Andy Gross, Wesley Cheng, Matthias Kaehlcke, Kishon Vijay Abraham I, linux-kernel, Greg Kroah-Hartman On Wed, 17 Mar 2021 16:31:39 +0530, Sandeep Maheswaram wrote: > Add the compatible string for sc7280 SoC from Qualcomm. > > Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> > --- > Documentation/devicetree/bindings/usb/qcom,dwc3.yaml | 1 + > 1 file changed, 1 insertion(+) > Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 2/3] dt-bindings: phy: qcom,usb-snps-femto-v2: Add bindings for SC7280 2021-03-17 11:01 [PATCH 0/3] Add DT bindings and DT nodes for USB in SC7280 Sandeep Maheswaram 2021-03-17 11:01 ` [PATCH 1/3] dt-bindings: usb: qcom,dwc3: Add bindings for SC7280 Sandeep Maheswaram @ 2021-03-17 11:01 ` Sandeep Maheswaram 2021-03-17 20:03 ` Matthias Kaehlcke ` (2 more replies) 2021-03-17 11:01 ` [PATCH 3/3] arm64: dts: qcom: sc7280: Add USB related nodes Sandeep Maheswaram 2 siblings, 3 replies; 11+ messages in thread From: Sandeep Maheswaram @ 2021-03-17 11:01 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Kishon Vijay Abraham I, Rob Herring, Vinod Koul, Greg Kroah-Hartman, Wesley Cheng, Stephen Boyd, Doug Anderson, Matthias Kaehlcke Cc: linux-arm-msm, linux-kernel, devicetree, linux-phy, linux-usb, Manu Gautam, Sandeep Maheswaram Add the compatible string for sc7280 SoC from Qualcomm Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> --- Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml b/Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml index ee77c64..20203a8 100644 --- a/Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml @@ -16,6 +16,7 @@ properties: compatible: enum: - qcom,usb-snps-hs-7nm-phy + - qcom,sc7280-usb-hs-phy - qcom,sm8150-usb-hs-phy - qcom,sm8250-usb-hs-phy - qcom,sm8350-usb-hs-phy -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 2/3] dt-bindings: phy: qcom,usb-snps-femto-v2: Add bindings for SC7280 2021-03-17 11:01 ` [PATCH 2/3] dt-bindings: phy: qcom,usb-snps-femto-v2: " Sandeep Maheswaram @ 2021-03-17 20:03 ` Matthias Kaehlcke 2021-03-23 21:02 ` Stephen Boyd 2021-03-25 7:22 ` Vinod Koul 2 siblings, 0 replies; 11+ messages in thread From: Matthias Kaehlcke @ 2021-03-17 20:03 UTC (permalink / raw) To: Sandeep Maheswaram Cc: Andy Gross, Bjorn Andersson, Kishon Vijay Abraham I, Rob Herring, Vinod Koul, Greg Kroah-Hartman, Wesley Cheng, Stephen Boyd, Doug Anderson, linux-arm-msm, linux-kernel, devicetree, linux-phy, linux-usb, Manu Gautam On Wed, Mar 17, 2021 at 04:31:40PM +0530, Sandeep Maheswaram wrote: > Add the compatible string for sc7280 SoC from Qualcomm > > Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> > --- > Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml b/Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml > index ee77c64..20203a8 100644 > --- a/Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml > +++ b/Documentation/devicetree/bindings/phy/qcom,usb-snps-femto-v2.yaml > @@ -16,6 +16,7 @@ properties: > compatible: > enum: > - qcom,usb-snps-hs-7nm-phy > + - qcom,sc7280-usb-hs-phy > - qcom,sm8150-usb-hs-phy > - qcom,sm8250-usb-hs-phy > - qcom,sm8350-usb-hs-phy Reviewed-by: Matthias Kaehlcke <mka@chromium.org> ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/3] dt-bindings: phy: qcom,usb-snps-femto-v2: Add bindings for SC7280 2021-03-17 11:01 ` [PATCH 2/3] dt-bindings: phy: qcom,usb-snps-femto-v2: " Sandeep Maheswaram 2021-03-17 20:03 ` Matthias Kaehlcke @ 2021-03-23 21:02 ` Stephen Boyd 2021-03-25 7:22 ` Vinod Koul 2 siblings, 0 replies; 11+ messages in thread From: Stephen Boyd @ 2021-03-23 21:02 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Doug Anderson, Greg Kroah-Hartman, Kishon Vijay Abraham I, Matthias Kaehlcke, Rob Herring, Sandeep Maheswaram, Vinod Koul, Wesley Cheng Cc: linux-arm-msm, linux-kernel, devicetree, linux-phy, linux-usb, Manu Gautam, Sandeep Maheswaram Quoting Sandeep Maheswaram (2021-03-17 04:01:40) > Add the compatible string for sc7280 SoC from Qualcomm > > Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org> ^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/3] dt-bindings: phy: qcom,usb-snps-femto-v2: Add bindings for SC7280 2021-03-17 11:01 ` [PATCH 2/3] dt-bindings: phy: qcom,usb-snps-femto-v2: " Sandeep Maheswaram 2021-03-17 20:03 ` Matthias Kaehlcke 2021-03-23 21:02 ` Stephen Boyd @ 2021-03-25 7:22 ` Vinod Koul 2 siblings, 0 replies; 11+ messages in thread From: Vinod Koul @ 2021-03-25 7:22 UTC (permalink / raw) To: Sandeep Maheswaram Cc: Andy Gross, Bjorn Andersson, Kishon Vijay Abraham I, Rob Herring, Greg Kroah-Hartman, Wesley Cheng, Stephen Boyd, Doug Anderson, Matthias Kaehlcke, linux-arm-msm, linux-kernel, devicetree, linux-phy, linux-usb, Manu Gautam On 17-03-21, 16:31, Sandeep Maheswaram wrote: > Add the compatible string for sc7280 SoC from Qualcomm Applied, thanks -- ~Vinod ^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH 3/3] arm64: dts: qcom: sc7280: Add USB related nodes 2021-03-17 11:01 [PATCH 0/3] Add DT bindings and DT nodes for USB in SC7280 Sandeep Maheswaram 2021-03-17 11:01 ` [PATCH 1/3] dt-bindings: usb: qcom,dwc3: Add bindings for SC7280 Sandeep Maheswaram 2021-03-17 11:01 ` [PATCH 2/3] dt-bindings: phy: qcom,usb-snps-femto-v2: " Sandeep Maheswaram @ 2021-03-17 11:01 ` Sandeep Maheswaram 2021-03-18 19:03 ` Matthias Kaehlcke 2 siblings, 1 reply; 11+ messages in thread From: Sandeep Maheswaram @ 2021-03-17 11:01 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Kishon Vijay Abraham I, Rob Herring, Vinod Koul, Greg Kroah-Hartman, Wesley Cheng, Stephen Boyd, Doug Anderson, Matthias Kaehlcke Cc: linux-arm-msm, linux-kernel, devicetree, linux-phy, linux-usb, Manu Gautam, Sandeep Maheswaram Add nodes for DWC3 USB controller, QMP and HS USB PHYs. Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> --- arch/arm64/boot/dts/qcom/sc7280-idp.dts | 39 +++++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 149 ++++++++++++++++++++++++++++++++ 2 files changed, 188 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts index 54d2cb3..251a5b5 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts @@ -257,3 +257,42 @@ bias-pull-up; }; }; + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "host"; +}; + +&usb_1_hsphy { + status = "okay"; + + vdda-pll-supply = <&vreg_l10c_0p8>; + vdda33-supply = <&vreg_l2b_3p0>; + vdda18-supply = <&vreg_l1c_1p8>; +}; + +&usb_1_qmpphy { + status = "okay"; + + vdda-phy-supply = <&vreg_l6b_1p2>; + vdda-pll-supply = <&vreg_l1b_0p8>; +}; + +&usb_2 { + status = "okay"; +}; + +&usb_2_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_2_hsphy { + status = "okay"; + + vdda-pll-supply = <&vreg_l10c_0p8>; + vdda33-supply = <&vreg_l2b_3p0>; + vdda18-supply = <&vreg_l1c_1p8>; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 39cf0be..a785f65 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -305,6 +305,155 @@ }; }; + usb_1_hsphy: phy@88e3000 { + compatible = "qcom,sc7280-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg = <0 0x088e3000 0 0x400>; + status = "disabled"; + #phy-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + }; + + usb_2_hsphy: phy@88e4000 { + compatible = "qcom,sc7280-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; + reg = <0 0x088e4000 0 0x400>; + status = "disabled"; + #phy-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; + }; + + usb_1_qmpphy: phy@88e9000 { + compatible = "qcom,sm8250-qmp-usb3-phy"; + reg = <0 0x088e9000 0 0x200>, + <0 0x088e8000 0 0x20>; + reg-names = "reg-base", "dp_com"; + status = "disabled"; + #clock-cells = <1>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux", "ref_clk_src", "com_aux"; + + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, + <&gcc GCC_USB3_PHY_PRIM_BCR>; + reset-names = "phy", "common"; + + usb_1_ssphy: lanes@88e9200 { + reg = <0 0x088e9200 0 0x200>, + <0 0x088e9400 0 0x200>, + <0 0x088e9c00 0 0x400>, + <0 0x088e9600 0 0x200>, + <0 0x088e9800 0 0x200>, + <0 0x088e9a00 0 0x100>; + #phy-cells = <0>; + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "pipe0"; + clock-output-names = "usb3_phy_pipe_clk_src"; + }; + }; + + usb_2: usb@8cf8800 { + compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; + reg = <0 0x08cf8800 0 0x400>; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_SLEEP_CLK>; + clock-names = "cfg_noc", "core", "iface","mock_utmi", + "sleep"; + + assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_SEC_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 13 IRQ_TYPE_EDGE_RISING>, + <&pdc 12 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "hs_phy_irq", + "dm_hs_phy_irq", "dp_hs_phy_irq"; + + power-domains = <&gcc GCC_USB30_SEC_GDSC>; + + resets = <&gcc GCC_USB30_SEC_BCR>; + + usb_2_dwc3: dwc3@8c00000 { + compatible = "snps,dwc3"; + reg = <0 0x08c00000 0 0xe000>; + interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&apps_smmu 0xa0 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_2_hsphy>; + phy-names = "usb2-phy"; + maximum-speed = "high-speed"; + }; + }; + + usb_1: usb@a6f8800 { + compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; + reg = <0 0x0a6f8800 0 0x400>; + status = "disabled"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + dma-ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>; + + clock-names = "cfg_noc", "core", "iface", "mock_utmi", + "sleep"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", + "dm_hs_phy_irq", "ss_phy_irq"; + + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + usb_1_dwc3: dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0 0x0a600000 0 0xe000>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&apps_smmu 0xe0 0x0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_1_hsphy>, <&usb_1_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sc7280-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>; -- QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation ^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH 3/3] arm64: dts: qcom: sc7280: Add USB related nodes 2021-03-17 11:01 ` [PATCH 3/3] arm64: dts: qcom: sc7280: Add USB related nodes Sandeep Maheswaram @ 2021-03-18 19:03 ` Matthias Kaehlcke 0 siblings, 0 replies; 11+ messages in thread From: Matthias Kaehlcke @ 2021-03-18 19:03 UTC (permalink / raw) To: Sandeep Maheswaram Cc: Andy Gross, Bjorn Andersson, Kishon Vijay Abraham I, Rob Herring, Vinod Koul, Greg Kroah-Hartman, Wesley Cheng, Stephen Boyd, Doug Anderson, linux-arm-msm, linux-kernel, devicetree, linux-phy, linux-usb, Manu Gautam On Wed, Mar 17, 2021 at 04:31:41PM +0530, Sandeep Maheswaram wrote: > Add nodes for DWC3 USB controller, QMP and HS USB PHYs. > > Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org> > --- > arch/arm64/boot/dts/qcom/sc7280-idp.dts | 39 +++++++++ > arch/arm64/boot/dts/qcom/sc7280.dtsi | 149 ++++++++++++++++++++++++++++++++ > 2 files changed, 188 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dts b/arch/arm64/boot/dts/qcom/sc7280-idp.dts > index 54d2cb3..251a5b5 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dts > +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dts > @@ -257,3 +257,42 @@ > bias-pull-up; > }; > }; > + > +&usb_1 { > + status = "okay"; > +}; > + > +&usb_1_dwc3 { > + dr_mode = "host"; > +}; > + > +&usb_1_hsphy { > + status = "okay"; > + > + vdda-pll-supply = <&vreg_l10c_0p8>; > + vdda33-supply = <&vreg_l2b_3p0>; > + vdda18-supply = <&vreg_l1c_1p8>; > +}; > + > +&usb_1_qmpphy { > + status = "okay"; > + > + vdda-phy-supply = <&vreg_l6b_1p2>; > + vdda-pll-supply = <&vreg_l1b_0p8>; > +}; > + > +&usb_2 { > + status = "okay"; > +}; > + > +&usb_2_dwc3 { > + dr_mode = "peripheral"; > +}; > + > +&usb_2_hsphy { > + status = "okay"; > + > + vdda-pll-supply = <&vreg_l10c_0p8>; > + vdda33-supply = <&vreg_l2b_3p0>; > + vdda18-supply = <&vreg_l1c_1p8>; > +}; > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index 39cf0be..a785f65 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -305,6 +305,155 @@ > }; > }; > > + usb_1_hsphy: phy@88e3000 { > + compatible = "qcom,sc7280-usb-hs-phy", > + "qcom,usb-snps-hs-7nm-phy"; > + reg = <0 0x088e3000 0 0x400>; > + status = "disabled"; > + #phy-cells = <0>; > + > + clocks = <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "ref"; > + > + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; > + }; > + > + usb_2_hsphy: phy@88e4000 { > + compatible = "qcom,sc7280-usb-hs-phy", > + "qcom,usb-snps-hs-7nm-phy"; > + reg = <0 0x088e4000 0 0x400>; > + status = "disabled"; > + #phy-cells = <0>; > + > + clocks = <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "ref"; > + > + resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; > + }; > + > + usb_1_qmpphy: phy@88e9000 { > + compatible = "qcom,sm8250-qmp-usb3-phy"; > + reg = <0 0x088e9000 0 0x200>, > + <0 0x088e8000 0 0x20>; > + reg-names = "reg-base", "dp_com"; > + status = "disabled"; > + #clock-cells = <1>; IIUC this means that the PHY is a clock provider. Which clocks does it provide? How would a possible consumer specify the clock it wants to use? I couldn't find the corresponding definitions in the header of the binding > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, > + <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; > + clock-names = "aux", "ref_clk_src", "com_aux"; > + > + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, > + <&gcc GCC_USB3_PHY_PRIM_BCR>; > + reset-names = "phy", "common"; > + > + usb_1_ssphy: lanes@88e9200 { > + reg = <0 0x088e9200 0 0x200>, > + <0 0x088e9400 0 0x200>, > + <0 0x088e9c00 0 0x400>, > + <0 0x088e9600 0 0x200>, > + <0 0x088e9800 0 0x200>, > + <0 0x088e9a00 0 0x100>; > + #phy-cells = <0>; > + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; > + clock-names = "pipe0"; > + clock-output-names = "usb3_phy_pipe_clk_src"; > + }; > + }; > + > + usb_2: usb@8cf8800 { > + compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; > + reg = <0 0x08cf8800 0 0x400>; > + status = "disabled"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + dma-ranges; > + > + clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, > + <&gcc GCC_USB30_SEC_MASTER_CLK>, > + <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, > + <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, > + <&gcc GCC_USB30_SEC_SLEEP_CLK>; > + clock-names = "cfg_noc", "core", "iface","mock_utmi", > + "sleep"; > + > + assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, > + <&gcc GCC_USB30_SEC_MASTER_CLK>; > + assigned-clock-rates = <19200000>, <200000000>; > + > + interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 13 IRQ_TYPE_EDGE_RISING>, > + <&pdc 12 IRQ_TYPE_EDGE_RISING>; > + interrupt-names = "hs_phy_irq", > + "dm_hs_phy_irq", "dp_hs_phy_irq"; > + > + power-domains = <&gcc GCC_USB30_SEC_GDSC>; > + > + resets = <&gcc GCC_USB30_SEC_BCR>; > + > + usb_2_dwc3: dwc3@8c00000 { > + compatible = "snps,dwc3"; > + reg = <0 0x08c00000 0 0xe000>; > + interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; > + iommus = <&apps_smmu 0xa0 0x0>; > + snps,dis_u2_susphy_quirk; > + snps,dis_enblslpm_quirk; > + phys = <&usb_2_hsphy>; > + phy-names = "usb2-phy"; > + maximum-speed = "high-speed"; > + }; > + }; > + > + usb_1: usb@a6f8800 { > + compatible = "qcom,sc7280-dwc3", "qcom,dwc3"; > + reg = <0 0x0a6f8800 0 0x400>; > + status = "disabled"; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + dma-ranges; > + > + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, > + <&gcc GCC_USB30_PRIM_MASTER_CLK>, > + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, > + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, > + <&gcc GCC_USB30_PRIM_SLEEP_CLK>; > + > + clock-names = "cfg_noc", "core", "iface", "mock_utmi", > + "sleep"; > + > + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, > + <&gcc GCC_USB30_PRIM_MASTER_CLK>; > + assigned-clock-rates = <19200000>, <200000000>; > + > + interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, > + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, > + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "hs_phy_irq", "dp_hs_phy_irq", > + "dm_hs_phy_irq", "ss_phy_irq"; > + > + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; > + > + resets = <&gcc GCC_USB30_PRIM_BCR>; > + > + usb_1_dwc3: dwc3@a600000 { > + compatible = "snps,dwc3"; > + reg = <0 0x0a600000 0 0xe000>; > + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; > + iommus = <&apps_smmu 0xe0 0x0>; > + snps,dis_u2_susphy_quirk; > + snps,dis_enblslpm_quirk; > + phys = <&usb_1_hsphy>, <&usb_1_ssphy>; > + phy-names = "usb2-phy", "usb3-phy"; The 'maximum-speed' isn't specified in difference to the other controller. According to commit d3d245aee0b1 ("arm64: dts: qcom: sc7180: Add maximum speed property for DWC3 USB node") the max speed is used to configure the interconnect bandwidth. dwc3_qcom_interconnect_init() falls back to super speed if the max speed is unknown, so it should be fine to omit it, unless it is needed for something else. ^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2021-03-26 0:23 UTC | newest] Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-03-17 11:01 [PATCH 0/3] Add DT bindings and DT nodes for USB in SC7280 Sandeep Maheswaram 2021-03-17 11:01 ` [PATCH 1/3] dt-bindings: usb: qcom,dwc3: Add bindings for SC7280 Sandeep Maheswaram 2021-03-17 19:34 ` Matthias Kaehlcke 2021-03-23 21:01 ` Stephen Boyd 2021-03-26 0:22 ` Rob Herring 2021-03-17 11:01 ` [PATCH 2/3] dt-bindings: phy: qcom,usb-snps-femto-v2: " Sandeep Maheswaram 2021-03-17 20:03 ` Matthias Kaehlcke 2021-03-23 21:02 ` Stephen Boyd 2021-03-25 7:22 ` Vinod Koul 2021-03-17 11:01 ` [PATCH 3/3] arm64: dts: qcom: sc7280: Add USB related nodes Sandeep Maheswaram 2021-03-18 19:03 ` Matthias Kaehlcke
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