* [PATCH v2] usb: dwc2: Force 8bit UTMI width for Samsung Exynos SoCs
[not found] <CGME20190614065304eucas1p1ad98abc5c0f5e5e94fa43bed7e7d0e4f@eucas1p1.samsung.com>
@ 2019-06-14 6:52 ` Marek Szyprowski
0 siblings, 0 replies; only message in thread
From: Marek Szyprowski @ 2019-06-14 6:52 UTC (permalink / raw)
To: linux-usb, linux-samsung-soc, linux-kernel
Cc: Marek Szyprowski, Minas Harutyunyan, Felipe Balbi,
Bartlomiej Zolnierkiewicz, Jules Maselbas, Krzysztof Kozlowski
Samsung Exynos SoCs require to force UTMI width to 8bit, otherwise the
host side of the shared USB2 PHY doesn't work.
Reported-by: Krzysztof Kozlowski <krzk@kernel.org>
Fixes: 707d80f0a3c5 ("usb: dwc2: gadget: Replace phyif with phy_utmi_width")
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Acked-by: Minas Harutyunyan <hminas@synopsys.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Tested-by: Krzysztof Kozlowski <krzk@kernel.org>
---
v2:
- added collected tags
---
drivers/usb/dwc2/params.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/dwc2/params.c b/drivers/usb/dwc2/params.c
index 6900eea57526..9ece4affb9d4 100644
--- a/drivers/usb/dwc2/params.c
+++ b/drivers/usb/dwc2/params.c
@@ -76,6 +76,7 @@ static void dwc2_set_s3c6400_params(struct dwc2_hsotg *hsotg)
struct dwc2_core_params *p = &hsotg->params;
p->power_down = 0;
+ p->phy_utmi_width = 8;
}
static void dwc2_set_rk_params(struct dwc2_hsotg *hsotg)
--
2.17.1
^ permalink raw reply related [flat|nested] only message in thread
only message in thread, other threads:[~2019-06-14 6:53 UTC | newest]
Thread overview: (only message) (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
[not found] <CGME20190614065304eucas1p1ad98abc5c0f5e5e94fa43bed7e7d0e4f@eucas1p1.samsung.com>
2019-06-14 6:52 ` [PATCH v2] usb: dwc2: Force 8bit UTMI width for Samsung Exynos SoCs Marek Szyprowski
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).