* [PATCH 1/5] dt-bindings: usb: dwc3: Add a property to do a CGTL soft reset on mode switching
2019-09-25 23:42 [RFC][PATCH 0/5] dwc3: Changes for HiKey960 support John Stultz
@ 2019-09-25 23:42 ` John Stultz
2019-09-25 23:42 ` [PATCH 2/5] usb: dwc3: Execute GCTL Core Soft Reset while switch mode for Hisilicon Kirin Soc John Stultz
` (3 subsequent siblings)
4 siblings, 0 replies; 10+ messages in thread
From: John Stultz @ 2019-09-25 23:42 UTC (permalink / raw)
To: lkml
Cc: John Stultz, Greg Kroah-Hartman, Felipe Balbi, Andy Shevchenko,
Rob Herring, Mark Rutland, Yu Chen, Matthias Brugger,
Chunfeng Yun, linux-usb, devicetree
Provide a dt-binding for quirk needed to do a GCTL soft reset on mode
switching
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Felipe Balbi <balbi@kernel.org>
Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Yu Chen <chenyu56@huawei.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Cc: Chunfeng Yun <chunfeng.yun@mediatek.com>
Cc: linux-usb@vger.kernel.org
Cc: devicetree@vger.kernel.org
Signed-off-by: John Stultz <john.stultz@linaro.org>
---
Documentation/devicetree/bindings/usb/dwc3.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
index 66780a47ad85..cf4ef6c22fb3 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -77,6 +77,8 @@ Optional properties:
during HS transmit.
- snps,dis_metastability_quirk: when set, disable metastability workaround.
CAUTION: use only if you are absolutely sure of it.
+ - snps,gctl-reset-quirk: when set, GCTL soft reset will be executed on mode
+ switch.
- snps,is-utmi-l1-suspend: true when DWC3 asserts output signal
utmi_l1_suspend_n, false when asserts utmi_sleep_n
- snps,hird-threshold: HIRD threshold
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 2/5] usb: dwc3: Execute GCTL Core Soft Reset while switch mode for Hisilicon Kirin Soc
2019-09-25 23:42 [RFC][PATCH 0/5] dwc3: Changes for HiKey960 support John Stultz
2019-09-25 23:42 ` [PATCH 1/5] dt-bindings: usb: dwc3: Add a property to do a CGTL soft reset on mode switching John Stultz
@ 2019-09-25 23:42 ` John Stultz
2019-09-25 23:42 ` [PATCH 3/5] usb: dwc3: Increase timeout for CmdAct cleared by device controller John Stultz
` (2 subsequent siblings)
4 siblings, 0 replies; 10+ messages in thread
From: John Stultz @ 2019-09-25 23:42 UTC (permalink / raw)
To: lkml
Cc: Yu Chen, Greg Kroah-Hartman, Felipe Balbi, Andy Shevchenko,
Rob Herring, Mark Rutland, Matthias Brugger, Chunfeng Yun,
linux-usb, devicetree, John Stultz
From: Yu Chen <chenyu56@huawei.com>
A GCTL soft reset should be executed when switch mode for dwc3 core
of Hisilicon Kirin Soc.
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Felipe Balbi <balbi@kernel.org>
Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Yu Chen <chenyu56@huawei.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Cc: Chunfeng Yun <chunfeng.yun@mediatek.com>
Cc: linux-usb@vger.kernel.org
Cc: devicetree@vger.kernel.org
Signed-off-by: Yu Chen <chenyu56@huawei.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
---
drivers/usb/dwc3/core.c | 20 ++++++++++++++++++++
drivers/usb/dwc3/core.h | 3 +++
2 files changed, 23 insertions(+)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 999ce5e84d3c..440261432421 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -112,6 +112,19 @@ void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
dwc->current_dr_role = mode;
}
+static void dwc3_gctl_core_soft_reset(struct dwc3 *dwc)
+{
+ u32 reg;
+
+ reg = dwc3_readl(dwc->regs, DWC3_GCTL);
+ reg |= DWC3_GCTL_CORESOFTRESET;
+ dwc3_writel(dwc->regs, DWC3_GCTL, reg);
+
+ reg = dwc3_readl(dwc->regs, DWC3_GCTL);
+ reg &= ~DWC3_GCTL_CORESOFTRESET;
+ dwc3_writel(dwc->regs, DWC3_GCTL, reg);
+}
+
static void __dwc3_set_mode(struct work_struct *work)
{
struct dwc3 *dwc = work_to_dwc(work);
@@ -156,6 +169,10 @@ static void __dwc3_set_mode(struct work_struct *work)
dwc3_set_prtcap(dwc, dwc->desired_dr_role);
+ /* Execute a GCTL Core Soft Reset when switch mode */
+ if (dwc->gctl_reset_quirk)
+ dwc3_gctl_core_soft_reset(dwc);
+
spin_unlock_irqrestore(&dwc->lock, flags);
switch (dwc->desired_dr_role) {
@@ -1316,6 +1333,9 @@ static void dwc3_get_properties(struct dwc3 *dwc)
dwc->dis_metastability_quirk = device_property_read_bool(dev,
"snps,dis_metastability_quirk");
+ dwc->gctl_reset_quirk = device_property_read_bool(dev,
+ "snps,gctl-reset-quirk");
+
dwc->lpm_nyet_threshold = lpm_nyet_threshold;
dwc->tx_de_emphasis = tx_de_emphasis;
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index 1c8b349379af..b3cb6eec3f8f 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -1029,6 +1029,7 @@ struct dwc3_scratchpad_array {
* 2 - No de-emphasis
* 3 - Reserved
* @dis_metastability_quirk: set to disable metastability quirk.
+ * @gctl_reset_quirk: set to do a gctl soft-reset while switch operation mode.
* @imod_interval: set the interrupt moderation interval in 250ns
* increments or 0 to disable.
*/
@@ -1219,6 +1220,8 @@ struct dwc3 {
unsigned dis_metastability_quirk:1;
+ unsigned gctl_reset_quirk:1;
+
u16 imod_interval;
};
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 3/5] usb: dwc3: Increase timeout for CmdAct cleared by device controller
2019-09-25 23:42 [RFC][PATCH 0/5] dwc3: Changes for HiKey960 support John Stultz
2019-09-25 23:42 ` [PATCH 1/5] dt-bindings: usb: dwc3: Add a property to do a CGTL soft reset on mode switching John Stultz
2019-09-25 23:42 ` [PATCH 2/5] usb: dwc3: Execute GCTL Core Soft Reset while switch mode for Hisilicon Kirin Soc John Stultz
@ 2019-09-25 23:42 ` John Stultz
2019-09-25 23:42 ` [PATCH 4/5] dt-bindings: usb: dwc3: of-simple: add compatible for HiSi John Stultz
2019-09-25 23:42 ` [PATCH 5/5] usb: dwc3: dwc3-of-simple: Add support for dwc3 of Hisilicon Soc Platform John Stultz
4 siblings, 0 replies; 10+ messages in thread
From: John Stultz @ 2019-09-25 23:42 UTC (permalink / raw)
To: lkml
Cc: Yu Chen, Greg Kroah-Hartman, Felipe Balbi, Andy Shevchenko,
Rob Herring, Mark Rutland, Matthias Brugger, Chunfeng Yun,
linux-usb, devicetree, John Stultz
From: Yu Chen <chenyu56@huawei.com>
It needs more time for the device controller to clear the CmdAct of
DEPCMD on Hisilicon Kirin Soc.
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Felipe Balbi <balbi@kernel.org>
Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Yu Chen <chenyu56@huawei.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Cc: Chunfeng Yun <chunfeng.yun@mediatek.com>
Cc: linux-usb@vger.kernel.org
Cc: devicetree@vger.kernel.org
Signed-off-by: Yu Chen <chenyu56@huawei.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
---
drivers/usb/dwc3/gadget.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index 8adb59f8e4f1..81907e163252 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -270,7 +270,7 @@ int dwc3_send_gadget_ep_cmd(struct dwc3_ep *dep, unsigned cmd,
{
const struct usb_endpoint_descriptor *desc = dep->endpoint.desc;
struct dwc3 *dwc = dep->dwc;
- u32 timeout = 1000;
+ u32 timeout = 5000;
u32 saved_config = 0;
u32 reg;
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 4/5] dt-bindings: usb: dwc3: of-simple: add compatible for HiSi
2019-09-25 23:42 [RFC][PATCH 0/5] dwc3: Changes for HiKey960 support John Stultz
` (2 preceding siblings ...)
2019-09-25 23:42 ` [PATCH 3/5] usb: dwc3: Increase timeout for CmdAct cleared by device controller John Stultz
@ 2019-09-25 23:42 ` John Stultz
2019-09-26 1:34 ` Chunfeng Yun
2019-09-25 23:42 ` [PATCH 5/5] usb: dwc3: dwc3-of-simple: Add support for dwc3 of Hisilicon Soc Platform John Stultz
4 siblings, 1 reply; 10+ messages in thread
From: John Stultz @ 2019-09-25 23:42 UTC (permalink / raw)
To: lkml
Cc: John Stultz, Greg Kroah-Hartman, Felipe Balbi, Andy Shevchenko,
Rob Herring, Mark Rutland, Yu Chen, Matthias Brugger,
Chunfeng Yun, linux-usb, devicetree
Add necessary compatible flag for HiSi's DWC3 so
dwc3-of-simple will probe.
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Felipe Balbi <balbi@kernel.org>
Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Yu Chen <chenyu56@huawei.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Cc: Chunfeng Yun <chunfeng.yun@mediatek.com>
Cc: linux-usb@vger.kernel.org
Cc: devicetree@vger.kernel.org
Signed-off-by: John Stultz <john.stultz@linaro.org>
---
.../devicetree/bindings/usb/hisi,dwc3.txt | 52 +++++++++++++++++++
1 file changed, 52 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb/hisi,dwc3.txt
diff --git a/Documentation/devicetree/bindings/usb/hisi,dwc3.txt b/Documentation/devicetree/bindings/usb/hisi,dwc3.txt
new file mode 100644
index 000000000000..dc31b8a3c006
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/hisi,dwc3.txt
@@ -0,0 +1,52 @@
+HiSi SuperSpeed DWC3 USB SoC controller
+
+Required properties:
+- compatible: should contain "hisilicon,hi3660-dwc3" for HiSi SoC
+- clocks: A list of phandle + clock-specifier pairs for the
+ clocks listed in clock-names
+- clock-names: Should contain the following:
+ "clk_usb3phy_ref" Phy reference clk
+ "aclk_usb3otg" USB3 OTG aclk
+
+- assigned-clocks: Should be:
+ HI3660_ACLK_GATE_USB3OTG
+- assigned-clock-rates: Should be:
+ 229Mhz (229000000) for HI3660_ACLK_GATE_USB3OTG
+
+Optional properties:
+- resets: Phandle to reset control that resets core and wrapper.
+
+Required child node:
+A child node must exist to represent the core DWC3 IP block. The name of
+the node is not important. The content of the node is defined in dwc3.txt.
+
+Example device nodes:
+
+ usb3: hisi_dwc3 {
+ compatible = "hisilicon,hi3660-dwc3";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&crg_ctrl HI3660_CLK_ABB_USB>,
+ <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>;
+ clock-names = "clk_usb3phy_ref", "aclk_usb3otg";
+
+ assigned-clocks = <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>;
+ assigned-clock-rates = <229 000 000>;
+ resets = <&crg_rst 0x90 8>,
+ <&crg_rst 0x90 7>,
+ <&crg_rst 0x90 6>,
+ <&crg_rst 0x90 5>;
+
+ dwc3: dwc3@ff100000 {
+ compatible = "snps,dwc3";
+ reg = <0x0 0xff100000 0x0 0x100000>;
+ interrupts = <0 159 4>, <0 161 4>;
+ phys = <&usb_phy>;
+ phy-names = "usb3-phy";
+ dr_mode = "otg";
+
+ ...
+ };
+ };
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH 4/5] dt-bindings: usb: dwc3: of-simple: add compatible for HiSi
2019-09-25 23:42 ` [PATCH 4/5] dt-bindings: usb: dwc3: of-simple: add compatible for HiSi John Stultz
@ 2019-09-26 1:34 ` Chunfeng Yun
2019-09-26 4:06 ` John Stultz
0 siblings, 1 reply; 10+ messages in thread
From: Chunfeng Yun @ 2019-09-26 1:34 UTC (permalink / raw)
To: John Stultz
Cc: lkml, Greg Kroah-Hartman, Felipe Balbi, Andy Shevchenko,
Rob Herring, Mark Rutland, Yu Chen, Matthias Brugger, linux-usb,
devicetree
On Wed, 2019-09-25 at 23:42 +0000, John Stultz wrote:
> Add necessary compatible flag for HiSi's DWC3 so
> dwc3-of-simple will probe.
>
> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
> Cc: Felipe Balbi <balbi@kernel.org>
> Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Yu Chen <chenyu56@huawei.com>
> Cc: Matthias Brugger <matthias.bgg@gmail.com>
> Cc: Chunfeng Yun <chunfeng.yun@mediatek.com>
> Cc: linux-usb@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> Signed-off-by: John Stultz <john.stultz@linaro.org>
> ---
> .../devicetree/bindings/usb/hisi,dwc3.txt | 52 +++++++++++++++++++
> 1 file changed, 52 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/usb/hisi,dwc3.txt
>
> diff --git a/Documentation/devicetree/bindings/usb/hisi,dwc3.txt b/Documentation/devicetree/bindings/usb/hisi,dwc3.txt
> new file mode 100644
> index 000000000000..dc31b8a3c006
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/hisi,dwc3.txt
> @@ -0,0 +1,52 @@
> +HiSi SuperSpeed DWC3 USB SoC controller
> +
> +Required properties:
> +- compatible: should contain "hisilicon,hi3660-dwc3" for HiSi SoC
> +- clocks: A list of phandle + clock-specifier pairs for the
> + clocks listed in clock-names
> +- clock-names: Should contain the following:
> + "clk_usb3phy_ref" Phy reference clk
It's not good idea to apply phy's clock in dwc3's node
> + "aclk_usb3otg" USB3 OTG aclk
> +
> +- assigned-clocks: Should be:
> + HI3660_ACLK_GATE_USB3OTG
> +- assigned-clock-rates: Should be:
> + 229Mhz (229000000) for HI3660_ACLK_GATE_USB3OTG
> +
> +Optional properties:
> +- resets: Phandle to reset control that resets core and wrapper.
> +
> +Required child node:
> +A child node must exist to represent the core DWC3 IP block. The name of
> +the node is not important. The content of the node is defined in dwc3.txt.
> +
> +Example device nodes:
> +
> + usb3: hisi_dwc3 {
> + compatible = "hisilicon,hi3660-dwc3";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + clocks = <&crg_ctrl HI3660_CLK_ABB_USB>,
> + <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>;
> + clock-names = "clk_usb3phy_ref", "aclk_usb3otg";
> +
> + assigned-clocks = <&crg_ctrl HI3660_ACLK_GATE_USB3OTG>;
> + assigned-clock-rates = <229 000 000>;
> + resets = <&crg_rst 0x90 8>,
> + <&crg_rst 0x90 7>,
> + <&crg_rst 0x90 6>,
> + <&crg_rst 0x90 5>;
> +
> + dwc3: dwc3@ff100000 {
> + compatible = "snps,dwc3";
> + reg = <0x0 0xff100000 0x0 0x100000>;
> + interrupts = <0 159 4>, <0 161 4>;
> + phys = <&usb_phy>;
> + phy-names = "usb3-phy";
> + dr_mode = "otg";
> +
> + ...
> + };
> + };
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH 4/5] dt-bindings: usb: dwc3: of-simple: add compatible for HiSi
2019-09-26 1:34 ` Chunfeng Yun
@ 2019-09-26 4:06 ` John Stultz
2019-09-26 6:42 ` Chunfeng Yun
0 siblings, 1 reply; 10+ messages in thread
From: John Stultz @ 2019-09-26 4:06 UTC (permalink / raw)
To: Chunfeng Yun
Cc: lkml, Greg Kroah-Hartman, Felipe Balbi, Andy Shevchenko,
Rob Herring, Mark Rutland, Yu Chen, Matthias Brugger,
Linux USB List,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
On Wed, Sep 25, 2019 at 6:34 PM Chunfeng Yun <chunfeng.yun@mediatek.com> wrote:
> On Wed, 2019-09-25 at 23:42 +0000, John Stultz wrote:
> > +++ b/Documentation/devicetree/bindings/usb/hisi,dwc3.txt
> > @@ -0,0 +1,52 @@
> > +HiSi SuperSpeed DWC3 USB SoC controller
> > +
> > +Required properties:
> > +- compatible: should contain "hisilicon,hi3660-dwc3" for HiSi SoC
> > +- clocks: A list of phandle + clock-specifier pairs for the
> > + clocks listed in clock-names
> > +- clock-names: Should contain the following:
> > + "clk_usb3phy_ref" Phy reference clk
> It's not good idea to apply phy's clock in dwc3's node
Hey! Thanks for taking a look at this!
So first, my apologies, I'm not the driver author and I don't have any
real specs on the hardware other then what's in the source tree I'm
working on. Not the ideal person to be documenting the binding, but I
realized we still needed some binding documentation (although a few
other dwc-of-simple compat entries are undocumented), so this is my
rough stab at it. :/
Given the name clk_usb3phy_ref I'm assuming its a phy reference clock,
but I honestly don't know if I'm getting that wrong. It all seems to
be leveraging the fact that the dwc-of-simple driver batch enables and
disables all the clocks w/o really looking at the names.
Do you have a recommendation for what would be best here? I suspect
it's necessary to enable/disable the clk in a similar path(though I'm
unfortunately traveling this week so I can't validate that). Do I try
to move the clk_usb3phy_ref clock enable/disable handling to somewhere
else?
thanks
-john
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 4/5] dt-bindings: usb: dwc3: of-simple: add compatible for HiSi
2019-09-26 4:06 ` John Stultz
@ 2019-09-26 6:42 ` Chunfeng Yun
2019-10-02 20:45 ` John Stultz
0 siblings, 1 reply; 10+ messages in thread
From: Chunfeng Yun @ 2019-09-26 6:42 UTC (permalink / raw)
To: John Stultz
Cc: lkml, Greg Kroah-Hartman, Felipe Balbi, Andy Shevchenko,
Rob Herring, Mark Rutland, Yu Chen, Matthias Brugger,
Linux USB List,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
On Wed, 2019-09-25 at 21:06 -0700, John Stultz wrote:
> On Wed, Sep 25, 2019 at 6:34 PM Chunfeng Yun <chunfeng.yun@mediatek.com> wrote:
> > On Wed, 2019-09-25 at 23:42 +0000, John Stultz wrote:
> > > +++ b/Documentation/devicetree/bindings/usb/hisi,dwc3.txt
> > > @@ -0,0 +1,52 @@
> > > +HiSi SuperSpeed DWC3 USB SoC controller
> > > +
> > > +Required properties:
> > > +- compatible: should contain "hisilicon,hi3660-dwc3" for HiSi SoC
> > > +- clocks: A list of phandle + clock-specifier pairs for the
> > > + clocks listed in clock-names
> > > +- clock-names: Should contain the following:
> > > + "clk_usb3phy_ref" Phy reference clk
> > It's not good idea to apply phy's clock in dwc3's node
>
> Hey! Thanks for taking a look at this!
>
> So first, my apologies, I'm not the driver author and I don't have any
> real specs on the hardware other then what's in the source tree I'm
> working on. Not the ideal person to be documenting the binding, but I
> realized we still needed some binding documentation (although a few
> other dwc-of-simple compat entries are undocumented), so this is my
> rough stab at it. :/
>
> Given the name clk_usb3phy_ref I'm assuming its a phy reference clock,
> but I honestly don't know if I'm getting that wrong. It all seems to
> be leveraging the fact that the dwc-of-simple driver batch enables and
> disables all the clocks w/o really looking at the names.
>
> Do you have a recommendation for what would be best here? I suspect
> it's necessary to enable/disable the clk in a similar path(though I'm
> unfortunately traveling this week so I can't validate that). Do I try
> to move the clk_usb3phy_ref clock enable/disable handling to somewhere
> else?
If it's phy clock, we should enable/disable it in phy driver, maybe we'd
better ask for help from Yu Chen
>
> thanks
> -john
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH 4/5] dt-bindings: usb: dwc3: of-simple: add compatible for HiSi
2019-09-26 6:42 ` Chunfeng Yun
@ 2019-10-02 20:45 ` John Stultz
0 siblings, 0 replies; 10+ messages in thread
From: John Stultz @ 2019-10-02 20:45 UTC (permalink / raw)
To: Chunfeng Yun
Cc: lkml, Greg Kroah-Hartman, Felipe Balbi, Andy Shevchenko,
Rob Herring, Mark Rutland, Yu Chen, Matthias Brugger,
Linux USB List,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS
On Wed, Sep 25, 2019 at 11:42 PM Chunfeng Yun <chunfeng.yun@mediatek.com> wrote:
> On Wed, 2019-09-25 at 21:06 -0700, John Stultz wrote:
> > On Wed, Sep 25, 2019 at 6:34 PM Chunfeng Yun <chunfeng.yun@mediatek.com> wrote:
> > > On Wed, 2019-09-25 at 23:42 +0000, John Stultz wrote:
> > > > +++ b/Documentation/devicetree/bindings/usb/hisi,dwc3.txt
> > > > @@ -0,0 +1,52 @@
> > > > +HiSi SuperSpeed DWC3 USB SoC controller
> > > > +
> > > > +Required properties:
> > > > +- compatible: should contain "hisilicon,hi3660-dwc3" for HiSi SoC
> > > > +- clocks: A list of phandle + clock-specifier pairs for the
> > > > + clocks listed in clock-names
> > > > +- clock-names: Should contain the following:
> > > > + "clk_usb3phy_ref" Phy reference clk
> > > It's not good idea to apply phy's clock in dwc3's node
...
> > Given the name clk_usb3phy_ref I'm assuming its a phy reference clock,
> > but I honestly don't know if I'm getting that wrong. It all seems to
> > be leveraging the fact that the dwc-of-simple driver batch enables and
> > disables all the clocks w/o really looking at the names.
> >
...
> If it's phy clock, we should enable/disable it in phy driver, maybe we'd
> better ask for help from Yu Chen
So I've been looking around the existing code and I'm not sure how we
got to clk_usb3phy_ref here.
Really it is the HI3660_CLK_ABB_USB, who's name is "clk_abb_usb" and
who's parent is "clk_gate_usb_tcxo_en"
So I'm thinking just specifying clk_abb_usb is more accurate here?
Does that sound reasonable?
thanks
-john
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 5/5] usb: dwc3: dwc3-of-simple: Add support for dwc3 of Hisilicon Soc Platform
2019-09-25 23:42 [RFC][PATCH 0/5] dwc3: Changes for HiKey960 support John Stultz
` (3 preceding siblings ...)
2019-09-25 23:42 ` [PATCH 4/5] dt-bindings: usb: dwc3: of-simple: add compatible for HiSi John Stultz
@ 2019-09-25 23:42 ` John Stultz
4 siblings, 0 replies; 10+ messages in thread
From: John Stultz @ 2019-09-25 23:42 UTC (permalink / raw)
To: lkml
Cc: Yu Chen, Greg Kroah-Hartman, Felipe Balbi, Andy Shevchenko,
Rob Herring, Mark Rutland, Matthias Brugger, Chunfeng Yun,
linux-usb, devicetree, John Stultz
From: Yu Chen <chenyu56@huawei.com>
This patch adds support for the poweron and shutdown of dwc3 core
on Hisilicon Soc Platform.
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Felipe Balbi <balbi@kernel.org>
Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Yu Chen <chenyu56@huawei.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>
Cc: Chunfeng Yun <chunfeng.yun@mediatek.com>
Cc: linux-usb@vger.kernel.org
Cc: devicetree@vger.kernel.org
Signed-off-by: Yu Chen <chenyu56@huawei.com>
Signed-off-by: John Stultz <john.stultz@linaro.org>
---
drivers/usb/dwc3/dwc3-of-simple.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/dwc3-of-simple.c b/drivers/usb/dwc3/dwc3-of-simple.c
index bdac3e7d7b18..78617500edee 100644
--- a/drivers/usb/dwc3/dwc3-of-simple.c
+++ b/drivers/usb/dwc3/dwc3-of-simple.c
@@ -51,7 +51,8 @@ static int dwc3_of_simple_probe(struct platform_device *pdev)
* Some controllers need to toggle the usb3-otg reset before trying to
* initialize the PHY, otherwise the PHY times out.
*/
- if (of_device_is_compatible(np, "rockchip,rk3399-dwc3"))
+ if (of_device_is_compatible(np, "rockchip,rk3399-dwc3") ||
+ of_device_is_compatible(np, "hisilicon,hi3660-dwc3"))
simple->need_reset = true;
if (of_device_is_compatible(np, "amlogic,meson-axg-dwc3") ||
@@ -183,6 +184,7 @@ static const struct of_device_id of_dwc3_simple_match[] = {
{ .compatible = "amlogic,meson-axg-dwc3" },
{ .compatible = "amlogic,meson-gxl-dwc3" },
{ .compatible = "allwinner,sun50i-h6-dwc3" },
+ { .compatible = "hisilicon,hi3660-dwc3" },
{ /* Sentinel */ }
};
MODULE_DEVICE_TABLE(of, of_dwc3_simple_match);
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread