[PATCH 1/3] dt-bindings: usb: mtk-xhci: add support ip-sleep for mt8195

[PATCH 1/3] dt-bindings: usb: mtk-xhci: add support ip-sleep for mt8195

[Chunfeng Yun]

There are 4 USB controllers on MT8195, each controller's wakeup control is
different, add some spicific versions for them.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
 .../devicetree/bindings/usb/mediatek,mtk-xhci.yaml          | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml
index 11f7bacd4e2b..41efb51638d1 100644
--- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml
+++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml
@@ -146,7 +146,11 @@ properties:
             2 - used by mt2712 etc, revision 2 following IPM rule;
             101 - used by mt8183, specific 1.01;
             102 - used by mt8192, specific 1.02;
-          enum: [1, 2, 101, 102]
+            103 - used by mt8195, IP0, specific 1.03;
+            104 - used by mt8195, IP1, specific 1.04;
+            105 - used by mt8195, IP2, specific 1.05;
+            106 - used by mt8195, IP3, specific 1.06;
+          enum: [1, 2, 101, 102, 103, 104, 105, 106]
 
   mediatek,u3p-dis-msk:
     $ref: /schemas/types.yaml#/definitions/uint32
-- 
2.18.0

[PATCH 2/3] usb: xhci-mtk: add support ip-sleep wakeup for mt8195

[Chunfeng Yun]

Add support ip-sleep wakeup for mt8195, it's a specific revision for
each USB controller, and not following IPM rule.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
 drivers/usb/host/xhci-mtk.c | 37 +++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
index c53f6f276d5c..63f4b6984667 100644
--- a/drivers/usb/host/xhci-mtk.c
+++ b/drivers/usb/host/xhci-mtk.c
@@ -95,6 +95,19 @@
 #define WC0_SSUSB0_CDEN		BIT(6)
 #define WC0_IS_SPM_EN		BIT(1)
 
+/* mt8195 */
+#define PERI_WK_CTRL0_8195	0x04
+#define WC0_IS_P_95		BIT(30)	/* polarity */
+#define WC0_IS_C_95(x)		((u32)(((x) & 0x7) << 27))
+#define WC0_IS_EN_P3_95		BIT(26)
+#define WC0_IS_EN_P2_95		BIT(25)
+#define WC0_IS_EN_P1_95		BIT(24)
+
+#define PERI_WK_CTRL1_8195	0x20
+#define WC1_IS_C_95(x)		((u32)(((x) & 0xf) << 28))
+#define WC1_IS_P_95		BIT(12)
+#define WC1_IS_EN_P0_95		BIT(6)
+
 /* mt2712 etc */
 #define PERI_SSUSB_SPM_CTRL	0x0
 #define SSC_IP_SLEEP_EN	BIT(4)
@@ -105,6 +118,10 @@ enum ssusb_uwk_vers {
 	SSUSB_UWK_V2,
 	SSUSB_UWK_V1_1 = 101,	/* specific revision 1.01 */
 	SSUSB_UWK_V1_2,		/* specific revision 1.2 */
+	SSUSB_UWK_V1_3,		/* mt8195 IP0 */
+	SSUSB_UWK_V1_4,		/* mt8195 IP1 */
+	SSUSB_UWK_V1_5,		/* mt8195 IP2 */
+	SSUSB_UWK_V1_6,		/* mt8195 IP3 */
 };
 
 /*
@@ -307,6 +324,26 @@ static void usb_wakeup_ip_sleep_set(struct xhci_hcd_mtk *mtk, bool enable)
 		msk = WC0_SSUSB0_CDEN | WC0_IS_SPM_EN;
 		val = enable ? msk : 0;
 		break;
+	case SSUSB_UWK_V1_3:
+		reg = mtk->uwk_reg_base + PERI_WK_CTRL1_8195;
+		msk = WC1_IS_EN_P0_95 | WC1_IS_C_95(0xf) | WC1_IS_P_95;
+		val = enable ? (WC1_IS_EN_P0_95 | WC1_IS_C_95(0x1)) : 0;
+		break;
+	case SSUSB_UWK_V1_4:
+		reg = mtk->uwk_reg_base + PERI_WK_CTRL0_8195;
+		msk = WC0_IS_EN_P1_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95;
+		val = enable ? (WC0_IS_EN_P1_95 | WC0_IS_C_95(0x1)) : 0;
+		break;
+	case SSUSB_UWK_V1_5:
+		reg = mtk->uwk_reg_base + PERI_WK_CTRL0_8195;
+		msk = WC0_IS_EN_P2_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95;
+		val = enable ? (WC0_IS_EN_P2_95 | WC0_IS_C_95(0x1)) : 0;
+		break;
+	case SSUSB_UWK_V1_6:
+		reg = mtk->uwk_reg_base + PERI_WK_CTRL0_8195;
+		msk = WC0_IS_EN_P3_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95;
+		val = enable ? (WC0_IS_EN_P3_95 | WC0_IS_C_95(0x1)) : 0;
+		break;
 	case SSUSB_UWK_V2:
 		reg = mtk->uwk_reg_base + PERI_SSUSB_SPM_CTRL;
 		msk = SSC_IP_SLEEP_EN | SSC_SPM_INT_EN;
-- 
2.18.0

Re: [PATCH 2/3] usb: xhci-mtk: add support ip-sleep wakeup for mt8195

[Matthias Brugger]

On 02/11/2021 07:00, Chunfeng Yun wrote:
> Add support ip-sleep wakeup for mt8195, it's a specific revision for
> each USB controller, and not following IPM rule.
> 
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>

Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>

> ---
>   drivers/usb/host/xhci-mtk.c | 37 +++++++++++++++++++++++++++++++++++++
>   1 file changed, 37 insertions(+)
> 
> diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
> index c53f6f276d5c..63f4b6984667 100644
> --- a/drivers/usb/host/xhci-mtk.c
> +++ b/drivers/usb/host/xhci-mtk.c
> @@ -95,6 +95,19 @@
>   #define WC0_SSUSB0_CDEN		BIT(6)
>   #define WC0_IS_SPM_EN		BIT(1)
>   
> +/* mt8195 */
> +#define PERI_WK_CTRL0_8195	0x04
> +#define WC0_IS_P_95		BIT(30)	/* polarity */
> +#define WC0_IS_C_95(x)		((u32)(((x) & 0x7) << 27))
> +#define WC0_IS_EN_P3_95		BIT(26)
> +#define WC0_IS_EN_P2_95		BIT(25)
> +#define WC0_IS_EN_P1_95		BIT(24)
> +
> +#define PERI_WK_CTRL1_8195	0x20
> +#define WC1_IS_C_95(x)		((u32)(((x) & 0xf) << 28))
> +#define WC1_IS_P_95		BIT(12)
> +#define WC1_IS_EN_P0_95		BIT(6)
> +
>   /* mt2712 etc */
>   #define PERI_SSUSB_SPM_CTRL	0x0
>   #define SSC_IP_SLEEP_EN	BIT(4)
> @@ -105,6 +118,10 @@ enum ssusb_uwk_vers {
>   	SSUSB_UWK_V2,
>   	SSUSB_UWK_V1_1 = 101,	/* specific revision 1.01 */
>   	SSUSB_UWK_V1_2,		/* specific revision 1.2 */
> +	SSUSB_UWK_V1_3,		/* mt8195 IP0 */
> +	SSUSB_UWK_V1_4,		/* mt8195 IP1 */
> +	SSUSB_UWK_V1_5,		/* mt8195 IP2 */
> +	SSUSB_UWK_V1_6,		/* mt8195 IP3 */
>   };
>   
>   /*
> @@ -307,6 +324,26 @@ static void usb_wakeup_ip_sleep_set(struct xhci_hcd_mtk *mtk, bool enable)
>   		msk = WC0_SSUSB0_CDEN | WC0_IS_SPM_EN;
>   		val = enable ? msk : 0;
>   		break;
> +	case SSUSB_UWK_V1_3:
> +		reg = mtk->uwk_reg_base + PERI_WK_CTRL1_8195;
> +		msk = WC1_IS_EN_P0_95 | WC1_IS_C_95(0xf) | WC1_IS_P_95;
> +		val = enable ? (WC1_IS_EN_P0_95 | WC1_IS_C_95(0x1)) : 0;
> +		break;
> +	case SSUSB_UWK_V1_4:
> +		reg = mtk->uwk_reg_base + PERI_WK_CTRL0_8195;
> +		msk = WC0_IS_EN_P1_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95;
> +		val = enable ? (WC0_IS_EN_P1_95 | WC0_IS_C_95(0x1)) : 0;
> +		break;
> +	case SSUSB_UWK_V1_5:
> +		reg = mtk->uwk_reg_base + PERI_WK_CTRL0_8195;
> +		msk = WC0_IS_EN_P2_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95;
> +		val = enable ? (WC0_IS_EN_P2_95 | WC0_IS_C_95(0x1)) : 0;
> +		break;
> +	case SSUSB_UWK_V1_6:
> +		reg = mtk->uwk_reg_base + PERI_WK_CTRL0_8195;
> +		msk = WC0_IS_EN_P3_95 | WC0_IS_C_95(0x7) | WC0_IS_P_95;
> +		val = enable ? (WC0_IS_EN_P3_95 | WC0_IS_C_95(0x1)) : 0;
> +		break;
>   	case SSUSB_UWK_V2:
>   		reg = mtk->uwk_reg_base + PERI_SSUSB_SPM_CTRL;
>   		msk = SSC_IP_SLEEP_EN | SSC_SPM_INT_EN;
> 

Re: [PATCH 2/3] usb: xhci-mtk: add support ip-sleep wakeup for mt8195

[AngeloGioacchino Del Regno]

Il 02/11/21 07:00, Chunfeng Yun ha scritto:
> Add support ip-sleep wakeup for mt8195, it's a specific revision for
> each USB controller, and not following IPM rule.
> 
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>

Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>

[PATCH 3/3] arm64: dts: mediatek: Add USB xHCI controller for mt8195

[Chunfeng Yun]

Add all four USB xHCI controllers for MT8195

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 79 ++++++++++++++++++++++++
 1 file changed, 79 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index a59c0e9d1fc2..263eebfd2ea1 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -8,6 +8,7 @@
 #include <dt-bindings/clock/mt8195-clk.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
 #include <dt-bindings/power/mt8195-power.h>
 
 / {
@@ -823,6 +824,26 @@
 			status = "disabled";
 		};
 
+		xhci0: usb@11200000 {
+			compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";
+			reg = <0 0x11200000 0 0x1000>, <0 0x11203e00 0 0x0100>;
+			reg-names = "mac", "ippc";
+			interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
+			phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
+			assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
+					  <&topckgen CLK_TOP_SSUSB_XHCI>;
+			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+			clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>,
+				 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>,
+				 <&topckgen CLK_TOP_SSUSB_REF>,
+				 <&apmixedsys CLK_APMIXED_USB1PLL>;
+			clock-names = "sys_ck", "xhci_ck", "ref_ck", "mcu_ck";
+			mediatek,syscon-wakeup = <&pericfg 0x400 103>;
+			wakeup-source;
+			status = "disabled";
+		};
+
 		mmc0: mmc@11230000 {
 			compatible = "mediatek,mt8195-mmc", "mediatek,mt8192-mmc";
 			reg = <0 0x11230000 0 0x10000>,
@@ -843,6 +864,64 @@
 			status = "disabled";
 		};
 
+		xhci1: usb@11290000 {
+			compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";
+			reg = <0 0x11290000 0 0x1000>, <0 0x11293e00 0 0x0100>;
+			reg-names = "mac", "ippc";
+			interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;
+			phys = <&u2port1 PHY_TYPE_USB2>;
+			assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>,
+					  <&topckgen CLK_TOP_SSUSB_XHCI_1P>;
+			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+			clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>,
+				 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>,
+				 <&topckgen CLK_TOP_SSUSB_P1_REF>,
+				 <&apmixedsys CLK_APMIXED_USB1PLL>;
+			clock-names = "sys_ck", "xhci_ck", "ref_ck", "mcu_ck";
+			mediatek,syscon-wakeup = <&pericfg 0x400 104>;
+			wakeup-source;
+			status = "disabled";
+		};
+
+		xhci2: usb@112a0000 {
+			compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";
+			reg = <0 0x112a0000 0 0x1000>, <0 0x112a3e00 0 0x0100>;
+			reg-names = "mac", "ippc";
+			interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
+			phys = <&u2port2 PHY_TYPE_USB2>;
+			assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>,
+					  <&topckgen CLK_TOP_SSUSB_XHCI_2P>;
+			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+			clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>,
+				 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>,
+				 <&topckgen CLK_TOP_SSUSB_P2_REF>;
+			clock-names = "sys_ck", "xhci_ck", "ref_ck";
+			mediatek,syscon-wakeup = <&pericfg 0x400 105>;
+			status = "disabled";
+		};
+
+		xhci3: usb@112b0000 {
+			compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";
+			reg = <0 0x112b0000 0 0x1000>, <0 0x112b3e00 0 0x0100>;
+			reg-names = "mac", "ippc";
+			interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
+			phys = <&u2port3 PHY_TYPE_USB2>;
+			assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>,
+					  <&topckgen CLK_TOP_SSUSB_XHCI_3P>;
+			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+			clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>,
+				 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>,
+				 <&topckgen CLK_TOP_SSUSB_P3_REF>;
+			clock-names = "sys_ck", "xhci_ck", "ref_ck";
+			mediatek,syscon-wakeup = <&pericfg 0x400 106>;
+			wakeup-source;
+			usb2-lpm-disable;
+			status = "disabled";
+		};
+
 		nor_flash: nor@1132c000 {
 			compatible = "mediatek,mt8195-nor", "mediatek,mt8173-nor";
 			reg = <0 0x1132c000 0 0x1000>;
-- 
2.18.0

Re: [PATCH 3/3] arm64: dts: mediatek: Add USB xHCI controller for mt8195

[Matthias Brugger]

On 02/11/2021 07:00, Chunfeng Yun wrote:
> Add all four USB xHCI controllers for MT8195
> 
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>

Patch lookes good, I'll take it as soon as 1/3 and 2/3 is accepted.

Regards,
Matthias

> ---
>   arch/arm64/boot/dts/mediatek/mt8195.dtsi | 79 ++++++++++++++++++++++++
>   1 file changed, 79 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index a59c0e9d1fc2..263eebfd2ea1 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -8,6 +8,7 @@
>   #include <dt-bindings/clock/mt8195-clk.h>
>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>   #include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/phy/phy.h>
>   #include <dt-bindings/power/mt8195-power.h>
>   
>   / {
> @@ -823,6 +824,26 @@
>   			status = "disabled";
>   		};
>   
> +		xhci0: usb@11200000 {
> +			compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";
> +			reg = <0 0x11200000 0 0x1000>, <0 0x11203e00 0 0x0100>;
> +			reg-names = "mac", "ippc";
> +			interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
> +			phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
> +			assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
> +					  <&topckgen CLK_TOP_SSUSB_XHCI>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
> +						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
> +			clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>,
> +				 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>,
> +				 <&topckgen CLK_TOP_SSUSB_REF>,
> +				 <&apmixedsys CLK_APMIXED_USB1PLL>;
> +			clock-names = "sys_ck", "xhci_ck", "ref_ck", "mcu_ck";
> +			mediatek,syscon-wakeup = <&pericfg 0x400 103>;
> +			wakeup-source;
> +			status = "disabled";
> +		};
> +
>   		mmc0: mmc@11230000 {
>   			compatible = "mediatek,mt8195-mmc", "mediatek,mt8192-mmc";
>   			reg = <0 0x11230000 0 0x10000>,
> @@ -843,6 +864,64 @@
>   			status = "disabled";
>   		};
>   
> +		xhci1: usb@11290000 {
> +			compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";
> +			reg = <0 0x11290000 0 0x1000>, <0 0x11293e00 0 0x0100>;
> +			reg-names = "mac", "ippc";
> +			interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;
> +			phys = <&u2port1 PHY_TYPE_USB2>;
> +			assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>,
> +					  <&topckgen CLK_TOP_SSUSB_XHCI_1P>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
> +						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
> +			clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>,
> +				 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>,
> +				 <&topckgen CLK_TOP_SSUSB_P1_REF>,
> +				 <&apmixedsys CLK_APMIXED_USB1PLL>;
> +			clock-names = "sys_ck", "xhci_ck", "ref_ck", "mcu_ck";
> +			mediatek,syscon-wakeup = <&pericfg 0x400 104>;
> +			wakeup-source;
> +			status = "disabled";
> +		};
> +
> +		xhci2: usb@112a0000 {
> +			compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";
> +			reg = <0 0x112a0000 0 0x1000>, <0 0x112a3e00 0 0x0100>;
> +			reg-names = "mac", "ippc";
> +			interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
> +			phys = <&u2port2 PHY_TYPE_USB2>;
> +			assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>,
> +					  <&topckgen CLK_TOP_SSUSB_XHCI_2P>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
> +						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
> +			clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>,
> +				 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>,
> +				 <&topckgen CLK_TOP_SSUSB_P2_REF>;
> +			clock-names = "sys_ck", "xhci_ck", "ref_ck";
> +			mediatek,syscon-wakeup = <&pericfg 0x400 105>;
> +			status = "disabled";
> +		};
> +
> +		xhci3: usb@112b0000 {
> +			compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";
> +			reg = <0 0x112b0000 0 0x1000>, <0 0x112b3e00 0 0x0100>;
> +			reg-names = "mac", "ippc";
> +			interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
> +			phys = <&u2port3 PHY_TYPE_USB2>;
> +			assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>,
> +					  <&topckgen CLK_TOP_SSUSB_XHCI_3P>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
> +						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
> +			clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>,
> +				 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>,
> +				 <&topckgen CLK_TOP_SSUSB_P3_REF>;
> +			clock-names = "sys_ck", "xhci_ck", "ref_ck";
> +			mediatek,syscon-wakeup = <&pericfg 0x400 106>;
> +			wakeup-source;
> +			usb2-lpm-disable;
> +			status = "disabled";
> +		};
> +
>   		nor_flash: nor@1132c000 {
>   			compatible = "mediatek,mt8195-nor", "mediatek,mt8173-nor";
>   			reg = <0 0x1132c000 0 0x1000>;
> 

Re: [PATCH 3/3] arm64: dts: mediatek: Add USB xHCI controller for mt8195

[AngeloGioacchino Del Regno]

Il 02/11/21 07:00, Chunfeng Yun ha scritto:
> Add all four USB xHCI controllers for MT8195
> 
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
>   arch/arm64/boot/dts/mediatek/mt8195.dtsi | 79 ++++++++++++++++++++++++
>   1 file changed, 79 insertions(+)
> 

Hello!
Thanks for the patch! However, there is something to improve...

> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index a59c0e9d1fc2..263eebfd2ea1 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -8,6 +8,7 @@
>   #include <dt-bindings/clock/mt8195-clk.h>
>   #include <dt-bindings/interrupt-controller/arm-gic.h>
>   #include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/phy/phy.h>
>   #include <dt-bindings/power/mt8195-power.h>
>   
>   / {
> @@ -823,6 +824,26 @@
>   			status = "disabled";
>   		};
>   
> +		xhci0: usb@11200000 {
> +			compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";
> +			reg = <0 0x11200000 0 0x1000>, <0 0x11203e00 0 0x0100>;
> +			reg-names = "mac", "ippc";
> +			interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;

Here, and on the other xhci nodes (from what I know, xhci{0,1,3}), you should use
interrupts-extended and declare the wakeup interrupt on pio.

			interrupts-extended = <&gic GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>,

					      <&pio 219 IRQ_TYPE_LEVEL_LOW>;

			interrupt-names = "host", "wakeup";


> +			phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
> +			assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
> +					  <&topckgen CLK_TOP_SSUSB_XHCI>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
> +						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
> +			clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>,
> +				 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>,
> +				 <&topckgen CLK_TOP_SSUSB_REF>,
> +				 <&apmixedsys CLK_APMIXED_USB1PLL>;
> +			clock-names = "sys_ck", "xhci_ck", "ref_ck", "mcu_ck";
> +			mediatek,syscon-wakeup = <&pericfg 0x400 103>;
> +			wakeup-source;
> +			status = "disabled";
> +		};
> +
>   		mmc0: mmc@11230000 {
>   			compatible = "mediatek,mt8195-mmc", "mediatek,mt8192-mmc";
>   			reg = <0 0x11230000 0 0x10000>,
> @@ -843,6 +864,64 @@
>   			status = "disabled";
>   		};
>   
> +		xhci1: usb@11290000 {
> +			compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";
> +			reg = <0 0x11290000 0 0x1000>, <0 0x11293e00 0 0x0100>;
> +			reg-names = "mac", "ippc";
> +			interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;

			interrupts-extended = <&gic GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>,

					      <&pio 218 IRQ_TYPE_LEVEL_LOW>;

> +			phys = <&u2port1 PHY_TYPE_USB2>;
> +			assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>,
> +					  <&topckgen CLK_TOP_SSUSB_XHCI_1P>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
> +						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
> +			clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>,
> +				 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>,
> +				 <&topckgen CLK_TOP_SSUSB_P1_REF>,
> +				 <&apmixedsys CLK_APMIXED_USB1PLL>;
> +			clock-names = "sys_ck", "xhci_ck", "ref_ck", "mcu_ck";
> +			mediatek,syscon-wakeup = <&pericfg 0x400 104>;
> +			wakeup-source;
> +			status = "disabled";
> +		};
> +
> +		xhci2: usb@112a0000 {
> +			compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";
> +			reg = <0 0x112a0000 0 0x1000>, <0 0x112a3e00 0 0x0100>;
> +			reg-names = "mac", "ippc";
> +			interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
> +			phys = <&u2port2 PHY_TYPE_USB2>;
> +			assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>,
> +					  <&topckgen CLK_TOP_SSUSB_XHCI_2P>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
> +						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
> +			clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>,
> +				 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>,
> +				 <&topckgen CLK_TOP_SSUSB_P2_REF>;
> +			clock-names = "sys_ck", "xhci_ck", "ref_ck";
> +			mediatek,syscon-wakeup = <&pericfg 0x400 105>;
> +			status = "disabled";
> +		};
> +
> +		xhci3: usb@112b0000 {
> +			compatible = "mediatek,mt8195-xhci", "mediatek,mtk-xhci";
> +			reg = <0 0x112b0000 0 0x1000>, <0 0x112b3e00 0 0x0100>;
> +			reg-names = "mac", "ippc";
> +			interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;

			interrupts-extended = <&gic GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>,

					      <&pio 221 IRQ_TYPE_LEVEL_LOW>;

			interrupts-names = "host", "wakeup";

> +			phys = <&u2port3 PHY_TYPE_USB2>;
> +			assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>,
> +					  <&topckgen CLK_TOP_SSUSB_XHCI_3P>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
> +						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
> +			clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>,
> +				 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>,
> +				 <&topckgen CLK_TOP_SSUSB_P3_REF>;
> +			clock-names = "sys_ck", "xhci_ck", "ref_ck";
> +			mediatek,syscon-wakeup = <&pericfg 0x400 106>;
> +			wakeup-source;
> +			usb2-lpm-disable;
> +			status = "disabled";
> +		};
> +
>   		nor_flash: nor@1132c000 {
>   			compatible = "mediatek,mt8195-nor", "mediatek,mt8173-nor";
>   			reg = <0 0x1132c000 0 0x1000>;
> 

Regards,
- Angelo

Re: [PATCH 3/3] arm64: dts: mediatek: Add USB xHCI controller for mt8195

[Chunfeng Yun]

On Fri, 2021-11-26 at 11:36 +0100, AngeloGioacchino Del Regno wrote:
> Il 02/11/21 07:00, Chunfeng Yun ha scritto:
> > Add all four USB xHCI controllers for MT8195
> > 
> > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> > ---
> >   arch/arm64/boot/dts/mediatek/mt8195.dtsi | 79
> > ++++++++++++++++++++++++
> >   1 file changed, 79 insertions(+)
> > 
> 
> Hello!
> Thanks for the patch! However, there is something to improve...
> 
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > index a59c0e9d1fc2..263eebfd2ea1 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> > @@ -8,6 +8,7 @@
> >   #include <dt-bindings/clock/mt8195-clk.h>
> >   #include <dt-bindings/interrupt-controller/arm-gic.h>
> >   #include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/phy/phy.h>
> >   #include <dt-bindings/power/mt8195-power.h>
> >   
> >   / {
> > @@ -823,6 +824,26 @@
> >   			status = "disabled";
> >   		};
> >   
> > +		xhci0: usb@11200000 {
> > +			compatible = "mediatek,mt8195-xhci",
> > "mediatek,mtk-xhci";
> > +			reg = <0 0x11200000 0 0x1000>, <0 0x11203e00 0
> > 0x0100>;
> > +			reg-names = "mac", "ippc";
> > +			interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> 
> Here, and on the other xhci nodes (from what I know, xhci{0,1,3}),
> you should use
> interrupts-extended and declare the wakeup interrupt on pio.
> 
> 			interrupts-extended = <&gic GIC_SPI 129
> IRQ_TYPE_LEVEL_HIGH 0>,
> 
> 					      <&pio 219
> IRQ_TYPE_LEVEL_LOW>;
> 
> 			interrupt-names = "host", "wakeup";
Ok, this patch doesn't support runtime suspend, will add it in next
version, thanks a lot

> 
> 
> > +			phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0
> > PHY_TYPE_USB3>;
> > +			assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
> > +					  <&topckgen
> > CLK_TOP_SSUSB_XHCI>;
> > +			assigned-clock-parents = <&topckgen
> > CLK_TOP_UNIVPLL_D5_D4>,
> > +						 <&topckgen
> > CLK_TOP_UNIVPLL_D5_D4>;
> > +			clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>,
> > +				 <&infracfg_ao
> > CLK_INFRA_AO_SSUSB_XHCI>,
> > +				 <&topckgen CLK_TOP_SSUSB_REF>,
> > +				 <&apmixedsys CLK_APMIXED_USB1PLL>;
> > +			clock-names = "sys_ck", "xhci_ck", "ref_ck",
> > "mcu_ck";
> > +			mediatek,syscon-wakeup = <&pericfg 0x400 103>;
> > +			wakeup-source;
> > +			status = "disabled";
> > +		};
> > +
> >   		mmc0: mmc@11230000 {
> >   			compatible = "mediatek,mt8195-mmc",
> > "mediatek,mt8192-mmc";
> >   			reg = <0 0x11230000 0 0x10000>,
> > @@ -843,6 +864,64 @@
> >   			status = "disabled";
> >   		};
> >   
> > +		xhci1: usb@11290000 {
> > +			compatible = "mediatek,mt8195-xhci",
> > "mediatek,mtk-xhci";
> > +			reg = <0 0x11290000 0 0x1000>, <0 0x11293e00 0
> > 0x0100>;
> > +			reg-names = "mac", "ippc";
> > +			interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> 
> 			interrupts-extended = <&gic GIC_SPI 530
> IRQ_TYPE_LEVEL_HIGH 0>,
> 
> 					      <&pio 218
> IRQ_TYPE_LEVEL_LOW>;
> 
> > +			phys = <&u2port1 PHY_TYPE_USB2>;
> > +			assigned-clocks = <&topckgen
> > CLK_TOP_USB_TOP_1P>,
> > +					  <&topckgen
> > CLK_TOP_SSUSB_XHCI_1P>;
> > +			assigned-clock-parents = <&topckgen
> > CLK_TOP_UNIVPLL_D5_D4>,
> > +						 <&topckgen
> > CLK_TOP_UNIVPLL_D5_D4>;
> > +			clocks = <&pericfg_ao
> > CLK_PERI_AO_SSUSB_1P_BUS>,
> > +				 <&pericfg_ao
> > CLK_PERI_AO_SSUSB_1P_XHCI>,
> > +				 <&topckgen CLK_TOP_SSUSB_P1_REF>,
> > +				 <&apmixedsys CLK_APMIXED_USB1PLL>;
> > +			clock-names = "sys_ck", "xhci_ck", "ref_ck",
> > "mcu_ck";
> > +			mediatek,syscon-wakeup = <&pericfg 0x400 104>;
> > +			wakeup-source;
> > +			status = "disabled";
> > +		};
> > +
> > +		xhci2: usb@112a0000 {
> > +			compatible = "mediatek,mt8195-xhci",
> > "mediatek,mtk-xhci";
> > +			reg = <0 0x112a0000 0 0x1000>, <0 0x112a3e00 0
> > 0x0100>;
> > +			reg-names = "mac", "ippc";
> > +			interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> > +			phys = <&u2port2 PHY_TYPE_USB2>;
> > +			assigned-clocks = <&topckgen
> > CLK_TOP_USB_TOP_2P>,
> > +					  <&topckgen
> > CLK_TOP_SSUSB_XHCI_2P>;
> > +			assigned-clock-parents = <&topckgen
> > CLK_TOP_UNIVPLL_D5_D4>,
> > +						 <&topckgen
> > CLK_TOP_UNIVPLL_D5_D4>;
> > +			clocks = <&pericfg_ao
> > CLK_PERI_AO_SSUSB_2P_BUS>,
> > +				 <&pericfg_ao
> > CLK_PERI_AO_SSUSB_2P_XHCI>,
> > +				 <&topckgen CLK_TOP_SSUSB_P2_REF>;
> > +			clock-names = "sys_ck", "xhci_ck", "ref_ck";
> > +			mediatek,syscon-wakeup = <&pericfg 0x400 105>;
> > +			status = "disabled";
> > +		};
> > +
> > +		xhci3: usb@112b0000 {
> > +			compatible = "mediatek,mt8195-xhci",
> > "mediatek,mtk-xhci";
> > +			reg = <0 0x112b0000 0 0x1000>, <0 0x112b3e00 0
> > 0x0100>;
> > +			reg-names = "mac", "ippc";
> > +			interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH
> > 0>;
> 
> 			interrupts-extended = <&gic GIC_SPI 536
> IRQ_TYPE_LEVEL_HIGH 0>,
> 
> 					      <&pio 221
> IRQ_TYPE_LEVEL_LOW>;
> 
> 			interrupts-names = "host", "wakeup";
> 
> > +			phys = <&u2port3 PHY_TYPE_USB2>;
> > +			assigned-clocks = <&topckgen
> > CLK_TOP_USB_TOP_3P>,
> > +					  <&topckgen
> > CLK_TOP_SSUSB_XHCI_3P>;
> > +			assigned-clock-parents = <&topckgen
> > CLK_TOP_UNIVPLL_D5_D4>,
> > +						 <&topckgen
> > CLK_TOP_UNIVPLL_D5_D4>;
> > +			clocks = <&pericfg_ao
> > CLK_PERI_AO_SSUSB_3P_BUS>,
> > +				 <&pericfg_ao
> > CLK_PERI_AO_SSUSB_3P_XHCI>,
> > +				 <&topckgen CLK_TOP_SSUSB_P3_REF>;
> > +			clock-names = "sys_ck", "xhci_ck", "ref_ck";
> > +			mediatek,syscon-wakeup = <&pericfg 0x400 106>;
> > +			wakeup-source;
> > +			usb2-lpm-disable;
> > +			status = "disabled";
> > +		};
> > +
> >   		nor_flash: nor@1132c000 {
> >   			compatible = "mediatek,mt8195-nor",
> > "mediatek,mt8173-nor";
> >   			reg = <0 0x1132c000 0 0x1000>;
> > 
> 
> Regards,
> - Angelo

Re: [PATCH 1/3] dt-bindings: usb: mtk-xhci: add support ip-sleep for mt8195

[Rob Herring]

On Tue, Nov 02, 2021 at 02:00:47PM +0800, Chunfeng Yun wrote:
> There are 4 USB controllers on MT8195, each controller's wakeup control is
> different, add some spicific versions for them.

specific

> 
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
>  .../devicetree/bindings/usb/mediatek,mtk-xhci.yaml          | 6 +++++-
>  1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml
> index 11f7bacd4e2b..41efb51638d1 100644
> --- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml
> +++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml
> @@ -146,7 +146,11 @@ properties:
>              2 - used by mt2712 etc, revision 2 following IPM rule;
>              101 - used by mt8183, specific 1.01;
>              102 - used by mt8192, specific 1.02;
> -          enum: [1, 2, 101, 102]
> +            103 - used by mt8195, IP0, specific 1.03;
> +            104 - used by mt8195, IP1, specific 1.04;
> +            105 - used by mt8195, IP2, specific 1.05;
> +            106 - used by mt8195, IP3, specific 1.06;
> +          enum: [1, 2, 101, 102, 103, 104, 105, 106]
>  
>    mediatek,u3p-dis-msk:
>      $ref: /schemas/types.yaml#/definitions/uint32
> -- 
> 2.18.0
> 
> 

Re: [PATCH 1/3] dt-bindings: usb: mtk-xhci: add support ip-sleep for mt8195

[Chunfeng Yun]

On Fri, 2021-11-12 at 10:57 -0600, Rob Herring wrote:
> On Tue, Nov 02, 2021 at 02:00:47PM +0800, Chunfeng Yun wrote:
> > There are 4 USB controllers on MT8195, each controller's wakeup
> > control is
> > different, add some spicific versions for them.
> 
> specific
Will fix it, thanks

> 
> > 
> > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> > ---
> >  .../devicetree/bindings/usb/mediatek,mtk-xhci.yaml          | 6
> > +++++-
> >  1 file changed, 5 insertions(+), 1 deletion(-)
> > 
> > diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-
> > xhci.yaml b/Documentation/devicetree/bindings/usb/mediatek,mtk-
> > xhci.yaml
> > index 11f7bacd4e2b..41efb51638d1 100644
> > --- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml
> > +++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml
> > @@ -146,7 +146,11 @@ properties:
> >              2 - used by mt2712 etc, revision 2 following IPM rule;
> >              101 - used by mt8183, specific 1.01;
> >              102 - used by mt8192, specific 1.02;
> > -          enum: [1, 2, 101, 102]
> > +            103 - used by mt8195, IP0, specific 1.03;
> > +            104 - used by mt8195, IP1, specific 1.04;
> > +            105 - used by mt8195, IP2, specific 1.05;
> > +            106 - used by mt8195, IP3, specific 1.06;
> > +          enum: [1, 2, 101, 102, 103, 104, 105, 106]
> >  
> >    mediatek,u3p-dis-msk:
> >      $ref: /schemas/types.yaml#/definitions/uint32
> > -- 
> > 2.18.0
> > 
> > 

Re: [PATCH 1/3] dt-bindings: usb: mtk-xhci: add support ip-sleep for mt8195

[AngeloGioacchino Del Regno]

Il 02/11/21 07:00, Chunfeng Yun ha scritto:
> There are 4 USB controllers on MT8195, each controller's wakeup control is
> different, add some spicific versions for them.
> 
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>

Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>