From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
To: Geert Uytterhoeven <geert+renesas@glider.be>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Mark Brown <broonie@kernel.org>,
Wim Van Sebroeck <wim@linux-watchdog.org>,
Guenter Roeck <linux@roeck-us.net>
Cc: Fabrizio Castro <fabrizio.castro@bp.renesas.com>,
Bjorn Helgaas <bhelgaas@google.com>,
Simon Horman <horms@verge.net.au>,
Magnus Damm <magnus.damm@gmail.com>,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-spi@vger.kernel.org, linux-watchdog@vger.kernel.org,
linux-renesas-soc@vger.kernel.org,
Chris Paterson <Chris.Paterson2@renesas.com>,
Biju Das <biju.das@bp.renesas.com>,
Laurent Pinchart <laurent.pinchart@ideasonboard.com>,
Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>,
Jacopo Mondi <jacopo+renesas@jmondi.org>,
xu_shunji@hoperun.com
Subject: [PATCH 6/7] arm64: dts: renesas: r8a774b1: Add PCIe device nodes
Date: Fri, 4 Oct 2019 09:35:32 +0100 [thread overview]
Message-ID: <1570178133-21532-7-git-send-email-fabrizio.castro@bp.renesas.com> (raw)
In-Reply-To: <1570178133-21532-1-git-send-email-fabrizio.castro@bp.renesas.com>
This patch adds PCIe{0,1} device nodes for R8A774B1 SoC.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 42 +++++++++++++++++++++++++++++--
1 file changed, 40 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
index 3bd0b47..0163b284 100644
--- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
@@ -1304,19 +1304,57 @@
};
pciec0: pcie@fe000000 {
+ compatible = "renesas,pcie-r8a774b1",
+ "renesas,pcie-rcar-gen3";
reg = <0 0xfe000000 0 0x80000>;
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x00 0xff>;
- /* placeholder */
+ device_type = "pci";
+ ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
+ 0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
+ 0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
+ 0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+ clock-names = "pcie", "pcie_bus";
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ resets = <&cpg 319>;
+ status = "disabled";
};
pciec1: pcie@ee800000 {
+ compatible = "renesas,pcie-r8a774b1",
+ "renesas,pcie-rcar-gen3";
reg = <0 0xee800000 0 0x80000>;
#address-cells = <3>;
#size-cells = <2>;
bus-range = <0x00 0xff>;
- /* placeholder */
+ device_type = "pci";
+ ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000
+ 0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000
+ 0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000
+ 0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
+ /* Map all possible DDR as inbound ranges */
+ dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0>;
+ interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
+ clock-names = "pcie", "pcie_bus";
+ power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+ resets = <&cpg 318>;
+ status = "disabled";
};
fdp1@fe940000 {
--
2.7.4
next prev parent reply other threads:[~2019-10-04 8:36 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-04 8:35 [PATCH 0/7] Add RZ/G2N MSIOF/RWDT/PCIEC support Fabrizio Castro
2019-10-04 8:35 ` [PATCH 1/7] dt-bindings: watchdog: renesas-wdt: Document r8a774b1 support Fabrizio Castro
2019-10-04 13:12 ` Guenter Roeck
2019-10-07 11:28 ` Geert Uytterhoeven
2019-10-15 19:24 ` Rob Herring
2019-10-04 8:35 ` [PATCH 2/7] dt-bindings: spi: sh-msiof: Add " Fabrizio Castro
2019-10-07 11:27 ` Geert Uytterhoeven
2019-10-15 9:26 ` Applied "dt-bindings: spi: sh-msiof: Add r8a774b1 support" to the spi tree Mark Brown
2019-10-04 8:35 ` [PATCH 3/7] dt-bindings: PCI: rcar: Add device tree support for r8a774b1 Fabrizio Castro
2019-10-04 10:33 ` Andrew Murray
2019-10-07 11:29 ` Geert Uytterhoeven
2019-10-15 19:25 ` Rob Herring
2019-10-04 8:35 ` [PATCH 4/7] arm64: dts: renesas: r8a774b1: Add RWDT node Fabrizio Castro
2019-10-09 12:45 ` Geert Uytterhoeven
2019-10-04 8:35 ` [PATCH 5/7] arm64: dts: renesas: r8a774b1: Add all MSIOF nodes Fabrizio Castro
2019-10-09 12:46 ` Geert Uytterhoeven
2019-10-04 8:35 ` Fabrizio Castro [this message]
2019-10-04 10:32 ` [PATCH 6/7] arm64: dts: renesas: r8a774b1: Add PCIe device nodes Andrew Murray
2019-10-09 12:48 ` Geert Uytterhoeven
2019-10-04 8:35 ` [PATCH 7/7] arm64: dts: renesas: hihope-rzg2-ex: Let the board specific DT decide about pciec1 Fabrizio Castro
2019-10-09 15:28 ` Geert Uytterhoeven
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1570178133-21532-7-git-send-email-fabrizio.castro@bp.renesas.com \
--to=fabrizio.castro@bp.renesas.com \
--cc=Chris.Paterson2@renesas.com \
--cc=bhelgaas@google.com \
--cc=biju.das@bp.renesas.com \
--cc=broonie@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=geert+renesas@glider.be \
--cc=horms@verge.net.au \
--cc=jacopo+renesas@jmondi.org \
--cc=kieran.bingham+renesas@ideasonboard.com \
--cc=laurent.pinchart@ideasonboard.com \
--cc=linux-pci@vger.kernel.org \
--cc=linux-renesas-soc@vger.kernel.org \
--cc=linux-spi@vger.kernel.org \
--cc=linux-watchdog@vger.kernel.org \
--cc=linux@roeck-us.net \
--cc=magnus.damm@gmail.com \
--cc=mark.rutland@arm.com \
--cc=robh+dt@kernel.org \
--cc=wim@linux-watchdog.org \
--cc=xu_shunji@hoperun.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).