* [PATCH 01/15] mt76: mt7915: add comments about rx descriptor parsing
2021-08-11 21:44 [PATCH 00/15] mt7915 stats and debugging improvements greearb
@ 2021-08-11 21:44 ` greearb
2021-08-11 21:44 ` [PATCH 02/15] mt76: mt7915: print out hw revision greearb
` (13 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: greearb @ 2021-08-11 21:44 UTC (permalink / raw)
To: linux-wireless; +Cc: Ben Greear
From: Ben Greear <greearb@candelatech.com>
This is a tricky beast to understand, so add some notes for
next time someone is looking at this code and trying to compare
against documents.
Signed-off-by: Ben Greear <greearb@candelatech.com>
---
.../net/wireless/mediatek/mt76/mt7915/mac.c | 23 +++++++++++++++----
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
index 2c5b47766949..d836c665ddaf 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
@@ -410,6 +410,7 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
__le32 *rxd = (__le32 *)skb->data;
__le32 *rxv = NULL;
u32 mode = 0;
+ /* table "PP -> HOST / X-CPU" RX Format */
u32 rxd0 = le32_to_cpu(rxd[0]);
u32 rxd1 = le32_to_cpu(rxd[1]);
u32 rxd2 = le32_to_cpu(rxd[2]);
@@ -489,7 +490,7 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
rxd += 6;
if (rxd1 & MT_RXD1_NORMAL_GROUP_4) {
- u32 v0 = le32_to_cpu(rxd[0]);
+ u32 v0 = le32_to_cpu(rxd[0]); /* DW6 */
u32 v2 = le32_to_cpu(rxd[2]);
fc = cpu_to_le16(FIELD_GET(MT_RXD6_FRAME_CONTROL, v0));
@@ -502,6 +503,7 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
}
if (rxd1 & MT_RXD1_NORMAL_GROUP_1) {
+ /* DW10, assuming Group-4 enabled */
u8 *data = (u8 *)rxd;
if (status->flag & RX_FLAG_DECRYPTED) {
@@ -533,6 +535,7 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
}
if (rxd1 & MT_RXD1_NORMAL_GROUP_2) {
+ /* DW14, assuming group-1,4 */
status->timestamp = le32_to_cpu(rxd[0]);
status->flag |= RX_FLAG_MACTIME_START;
@@ -558,18 +561,22 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
if (rxd1 & MT_RXD1_NORMAL_GROUP_3) {
u32 v0, v1, v2;
- rxv = rxd;
+ rxv = rxd; /* DW16 assuming group 1,2,3,4 */
rxd += 2;
if ((u8 *)rxd - skb->data >= skb->len)
return -EINVAL;
- v0 = le32_to_cpu(rxv[0]);
+ v0 = le32_to_cpu(rxv[0]); /* DW16, P-VEC1 31:0 */
+ /* DW17, RX_RCPI copied over P-VEC 64:32 Per RX Format doc. */
v1 = le32_to_cpu(rxv[1]);
- v2 = le32_to_cpu(rxv[2]);
+ v2 = le32_to_cpu(rxv[2]); /* first DW of group-5, C-RXV */
if (v0 & MT_PRXV_HT_AD_CODE)
status->enc_flags |= RX_ENC_FLAG_LDPC;
+ /* TODO: When group-5 is enabled, use nss (and stbc) to
+ * calculate chains properly for this particular skb.
+ */
status->chains = mphy->antenna_mask;
status->chain_signal[0] = to_rssi(MT_PRXV_RCPI0, v1);
status->chain_signal[1] = to_rssi(MT_PRXV_RCPI1, v1);
@@ -581,12 +588,18 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
if (!(status->chains & BIT(i)))
continue;
+ /* TODO: Use db sum logic instead of max. */
status->signal = max(status->signal,
status->chain_signal[i]);
}
- /* RXD Group 5 - C-RXV */
+ /* RXD Group 5 - C-RXV.
+ * Group 5 Not currently enabled for 7915 except in
+ * monitor mode.
+ * See MT_DMA_DCR0_RXD_G5_EN
+ */
if (rxd1 & MT_RXD1_NORMAL_GROUP_5) {
+ /* See RXV document ... */
u8 stbc = FIELD_GET(MT_CRXV_HT_STBC, v2);
u8 gi = FIELD_GET(MT_CRXV_HT_SHORT_GI, v2);
bool cck = false;
--
2.20.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 02/15] mt76: mt7915: print out hw revision
2021-08-11 21:44 [PATCH 00/15] mt7915 stats and debugging improvements greearb
2021-08-11 21:44 ` [PATCH 01/15] mt76: mt7915: add comments about rx descriptor parsing greearb
@ 2021-08-11 21:44 ` greearb
2021-08-11 21:44 ` [PATCH 03/15] mt76: mt7915: tx_stats debugfs to read from mib greearb
` (12 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: greearb @ 2021-08-11 21:44 UTC (permalink / raw)
To: linux-wireless; +Cc: Ben Greear
From: Ben Greear <greearb@candelatech.com>
Help determine what version of silicon is in use.
Signed-off-by: Ben Greear <greearb@candelatech.com>
---
drivers/net/wireless/mediatek/mt76/mt7915/mmio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mmio.c b/drivers/net/wireless/mediatek/mt76/mt7915/mmio.c
index af712a936ef6..34febe09f071 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mmio.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mmio.c
@@ -144,7 +144,7 @@ int mt7915_mmio_init(struct mt76_dev *mdev, void __iomem *mem_base, int irq)
mdev->rev = (mt76_rr(dev, MT_HW_CHIPID) << 16) |
(mt76_rr(dev, MT_HW_REV) & 0xff);
- dev_dbg(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
+ dev_info(mdev->dev, "ASIC revision: %04x\n", mdev->rev);
mt76_wr(dev, MT_INT_MASK_CSR, 0);
--
2.20.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 03/15] mt76: mt7915: tx_stats debugfs to read from mib
2021-08-11 21:44 [PATCH 00/15] mt7915 stats and debugging improvements greearb
2021-08-11 21:44 ` [PATCH 01/15] mt76: mt7915: add comments about rx descriptor parsing greearb
2021-08-11 21:44 ` [PATCH 02/15] mt76: mt7915: print out hw revision greearb
@ 2021-08-11 21:44 ` greearb
2021-08-11 21:44 ` [PATCH 04/15] mt76: mt7915: support enabling rx group-5 status greearb
` (11 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: greearb @ 2021-08-11 21:44 UTC (permalink / raw)
To: linux-wireless; +Cc: Ben Greear
From: Ben Greear <greearb@candelatech.com>
Read from accumulated mib values instead of directly from
registers since registers are clear-on-read.
Signed-off-by: Ben Greear <greearb@candelatech.com>
---
.../wireless/mediatek/mt76/mt7915/debugfs.c | 20 ++++++++++---------
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c b/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c
index f2ff0d3f52cd..b48fda497ab6 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c
@@ -444,7 +444,9 @@ static int
mt7915_tx_stats_show(struct seq_file *file, void *data)
{
struct mt7915_dev *dev = file->private;
- int stat[8], i, n;
+ int i;
+ long n;
+ struct mib_stats *mib = &dev->phy.mib;
mt7915_ampdu_stat_read_phy(&dev->phy, file);
mt7915_txbf_stat_read_phy(&dev->phy, file);
@@ -454,16 +456,16 @@ mt7915_tx_stats_show(struct seq_file *file, void *data)
/* Tx amsdu info */
seq_puts(file, "Tx MSDU statistics:\n");
- for (i = 0, n = 0; i < ARRAY_SIZE(stat); i++) {
- stat[i] = mt76_rr(dev, MT_PLE_AMSDU_PACK_MSDU_CNT(i));
- n += stat[i];
- }
+ for (i = 0, n = 0; i < ARRAY_SIZE(mib->amsdu_pack_stats); i++)
+ n += mib->amsdu_pack_stats[i];
+
+ for (i = 0; i < ARRAY_SIZE(mib->amsdu_pack_stats); i++) {
+ long si = mib->amsdu_pack_stats[i];
- for (i = 0; i < ARRAY_SIZE(stat); i++) {
- seq_printf(file, "AMSDU pack count of %d MSDU in TXD: 0x%x ",
- i + 1, stat[i]);
+ seq_printf(file, "AMSDU pack count of %d MSDU in TXD: %ld ",
+ i + 1, si);
if (n != 0)
- seq_printf(file, "(%d%%)\n", stat[i] * 100 / n);
+ seq_printf(file, "(%ld%%)\n", si * 100 / n);
else
seq_puts(file, "\n");
}
--
2.20.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 04/15] mt76: mt7915: support enabling rx group-5 status
2021-08-11 21:44 [PATCH 00/15] mt7915 stats and debugging improvements greearb
` (2 preceding siblings ...)
2021-08-11 21:44 ` [PATCH 03/15] mt76: mt7915: tx_stats debugfs to read from mib greearb
@ 2021-08-11 21:44 ` greearb
2021-08-11 21:44 ` [PATCH 05/15] mt76: mt7915: use nss for calculating rx-chains greearb
` (10 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: greearb @ 2021-08-11 21:44 UTC (permalink / raw)
To: linux-wireless; +Cc: Ben Greear
From: Ben Greear <greearb@candelatech.com>
When enabled, this allows per-skb rx rate reporting.
Enabling this may degrade RX performance, so it remains
disabled by default.
Signed-off-by: Ben Greear <greearb@candelatech.com>
---
.../wireless/mediatek/mt76/mt7915/debugfs.c | 33 +++++++++++++++++++
.../net/wireless/mediatek/mt76/mt7915/init.c | 3 +-
.../net/wireless/mediatek/mt76/mt7915/mac.c | 3 +-
.../net/wireless/mediatek/mt76/mt7915/main.c | 3 +-
.../wireless/mediatek/mt76/mt7915/mt7915.h | 5 +++
5 files changed, 44 insertions(+), 3 deletions(-)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c b/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c
index b48fda497ab6..885c60ea2a71 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c
@@ -354,6 +354,38 @@ mt7915_txs_for_no_skb_get(void *data, u64 *val)
DEFINE_DEBUGFS_ATTRIBUTE(fops_txs_for_no_skb, mt7915_txs_for_no_skb_get,
mt7915_txs_for_no_skb_set, "%lld\n");
+static int
+mt7915_rx_group_5_enable_set(void *data, u64 val)
+{
+ struct mt7915_dev *dev = data;
+
+ mutex_lock(&dev->mt76.mutex);
+
+ dev->rx_group_5_enable = !!val;
+
+ /* Enabled if we requested enabled OR if monitor mode is enabled. */
+ mt76_rmw_field(dev, MT_DMA_DCR0(0), MT_DMA_DCR0_RXD_G5_EN,
+ dev->phy.is_monitor_mode || dev->rx_group_5_enable);
+ mt76_testmode_reset(dev->phy.mt76, true);
+
+ mutex_unlock(&dev->mt76.mutex);
+
+ return 0;
+}
+
+static int
+mt7915_rx_group_5_enable_get(void *data, u64 *val)
+{
+ struct mt7915_dev *dev = data;
+
+ *val = dev->rx_group_5_enable;
+
+ return 0;
+}
+
+DEFINE_DEBUGFS_ATTRIBUTE(fops_rx_group_5_enable, mt7915_rx_group_5_enable_get,
+ mt7915_rx_group_5_enable_set, "%lld\n");
+
static void
mt7915_ampdu_stat_read_phy(struct mt7915_phy *phy,
struct seq_file *file)
@@ -592,6 +624,7 @@ int mt7915_init_debugfs(struct mt7915_dev *dev)
debugfs_create_file("tx_stats", 0400, dir, dev, &mt7915_tx_stats_fops);
debugfs_create_file("fw_debug", 0600, dir, dev, &fops_fw_debug);
debugfs_create_file("txs_for_no_skb", 0600, dir, dev, &fops_txs_for_no_skb);
+ debugfs_create_file("rx_group_5_enable", 0600, dir, dev, &fops_rx_group_5_enable);
debugfs_create_file("implicit_txbf", 0600, dir, dev,
&fops_implicit_txbf);
debugfs_create_u32("dfs_hw_pattern", 0400, dir, &dev->hw_pattern);
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/init.c b/drivers/net/wireless/mediatek/mt76/mt7915/init.c
index 6a00c072ee56..e741c4f73d19 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/init.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/init.c
@@ -302,7 +302,8 @@ mt7915_mac_init_band(struct mt7915_dev *dev, u8 band)
mt76_rmw_field(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_MAX_RX_LEN, 1536);
/* disable rx rate report by default due to hw issues */
- mt76_clear(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_RXD_G5_EN);
+ mt76_rmw_field(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_RXD_G5_EN,
+ dev->phy.is_monitor_mode || dev->rx_group_5_enable);
}
static void mt7915_mac_init(struct mt7915_dev *dev)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
index d836c665ddaf..7d5156a9e48d 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
@@ -715,7 +715,8 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
status->flag |= RX_FLAG_8023;
}
- if (rxv && status->flag & RX_FLAG_RADIOTAP_HE) {
+ if (phy->is_monitor_mode &&
+ rxv && status->flag & RX_FLAG_RADIOTAP_HE) {
mt7915_mac_decode_he_radiotap(skb, status, rxv, mode);
if (status->flag & RX_FLAG_RADIOTAP_HE_MU)
mt7915_mac_decode_he_mu_radiotap(skb, status, rxv);
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/main.c b/drivers/net/wireless/mediatek/mt76/mt7915/main.c
index 37c484d32d0b..b3f3b53da843 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/main.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/main.c
@@ -450,13 +450,14 @@ static int mt7915_config(struct ieee80211_hw *hw, u32 changed)
if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
bool enabled = !!(hw->conf.flags & IEEE80211_CONF_MONITOR);
+ phy->is_monitor_mode = enabled;
if (!enabled)
phy->rxfilter |= MT_WF_RFCR_DROP_OTHER_UC;
else
phy->rxfilter &= ~MT_WF_RFCR_DROP_OTHER_UC;
mt76_rmw_field(dev, MT_DMA_DCR0(band), MT_DMA_DCR0_RXD_G5_EN,
- enabled);
+ phy->is_monitor_mode || dev->rx_group_5_enable);
mt76_testmode_reset(phy->mt76, true);
mt76_wr(dev, MT_WF_RFCR(band), phy->rxfilter);
}
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h b/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
index d5e331064682..8086233d6e2b 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
@@ -184,6 +184,7 @@ struct mt7915_phy {
struct thermal_cooling_device *cdev;
u8 throttle_state;
+ u8 is_monitor_mode; /* are we in monitor mode or not ? */
u32 rxfilter;
u64 omac_mask;
@@ -236,6 +237,10 @@ struct mt7915_dev {
* creation by firmware, so may be a performance drag.
*/
bool txs_for_no_skb_enabled;
+ /* Should we enable group-5 rx descriptor logic? This may decrease RX
+ * throughput, but will give per skb rx rate information..
+ */
+ bool rx_group_5_enable;
struct work_struct init_work;
struct work_struct rc_work;
--
2.20.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 05/15] mt76: mt7915: use nss for calculating rx-chains
2021-08-11 21:44 [PATCH 00/15] mt7915 stats and debugging improvements greearb
` (3 preceding siblings ...)
2021-08-11 21:44 ` [PATCH 04/15] mt76: mt7915: support enabling rx group-5 status greearb
@ 2021-08-11 21:44 ` greearb
2021-08-11 21:44 ` [PATCH 06/15] mt76: mt7915: rename amsdu_pack_stats to tx_amsdu_pack_stats greearb
` (9 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: greearb @ 2021-08-11 21:44 UTC (permalink / raw)
To: linux-wireless; +Cc: Ben Greear
From: Ben Greear <greearb@candelatech.com>
When group-5 is enabled, we can find the actuall NSS used.
In that case, update the rx chains info so that the upper
stack can give better idea of actual antenna usage.
Signed-off-by: Ben Greear <greearb@candelatech.com>
---
.../net/wireless/mediatek/mt76/mt7915/mac.c | 32 +++++++++++++------
1 file changed, 22 insertions(+), 10 deletions(-)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
index 7d5156a9e48d..b44ca71e7d06 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
@@ -560,6 +560,7 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
/* RXD Group 3 - P-RXV */
if (rxd1 & MT_RXD1_NORMAL_GROUP_3) {
u32 v0, v1, v2;
+ u8 nss;
rxv = rxd; /* DW16 assuming group 1,2,3,4 */
rxd += 2;
@@ -577,21 +578,12 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
/* TODO: When group-5 is enabled, use nss (and stbc) to
* calculate chains properly for this particular skb.
*/
- status->chains = mphy->antenna_mask;
status->chain_signal[0] = to_rssi(MT_PRXV_RCPI0, v1);
status->chain_signal[1] = to_rssi(MT_PRXV_RCPI1, v1);
status->chain_signal[2] = to_rssi(MT_PRXV_RCPI2, v1);
status->chain_signal[3] = to_rssi(MT_PRXV_RCPI3, v1);
- status->signal = status->chain_signal[0];
- for (i = 1; i < hweight8(mphy->antenna_mask); i++) {
- if (!(status->chains & BIT(i)))
- continue;
-
- /* TODO: Use db sum logic instead of max. */
- status->signal = max(status->signal,
- status->chain_signal[i]);
- }
+ nss = hweight8(mphy->antenna_mask);
/* RXD Group 5 - C-RXV.
* Group 5 Not currently enabled for 7915 except in
@@ -604,6 +596,7 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
u8 gi = FIELD_GET(MT_CRXV_HT_SHORT_GI, v2);
bool cck = false;
+ nss = 1;
rxd += 18;
if ((u8 *)rxd - skb->data >= skb->len)
return -EINVAL;
@@ -623,6 +616,7 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
status->encoding = RX_ENC_HT;
if (i > 31)
return -EINVAL;
+ nss = i / 8 + 1;
break;
case MT_PHY_TYPE_VHT:
status->nss =
@@ -630,6 +624,7 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
status->encoding = RX_ENC_VHT;
if (i > 9)
return -EINVAL;
+ nss = status->nss;
break;
case MT_PHY_TYPE_HE_MU:
status->flag |= RX_FLAG_RADIOTAP_HE_MU;
@@ -639,6 +634,7 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
case MT_PHY_TYPE_HE_TB:
status->nss =
FIELD_GET(MT_PRXV_NSTS, v0) + 1;
+ nss = status->nss;
status->encoding = RX_ENC_HE;
status->flag |= RX_FLAG_RADIOTAP_HE;
i &= GENMASK(3, 0);
@@ -653,6 +649,11 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
}
status->rate_idx = i;
+ if (stbc) {
+ nss *= 2;
+ WARN_ON_ONCE(nss > 4);
+ }
+
switch (FIELD_GET(MT_CRXV_FRAME_MODE, v2)) {
case IEEE80211_STA_RX_BW_20:
break;
@@ -680,6 +681,17 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
if (mode < MT_PHY_TYPE_HE_SU && gi)
status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
}
+
+ status->chains = 1;
+ status->signal = status->chain_signal[0];
+
+ for (i = 1; i < nss; i++) {
+ status->chains |= BIT(i);
+
+ /* TODO: Use db sum logic instead of max. */
+ status->signal = max(status->signal,
+ status->chain_signal[i]);
+ }
}
skb_pull(skb, (u8 *)rxd - skb->data + 2 * remove_pad);
--
2.20.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 06/15] mt76: mt7915: rename amsdu_pack_stats to tx_amsdu_pack_stats
2021-08-11 21:44 [PATCH 00/15] mt7915 stats and debugging improvements greearb
` (4 preceding siblings ...)
2021-08-11 21:44 ` [PATCH 05/15] mt76: mt7915: use nss for calculating rx-chains greearb
@ 2021-08-11 21:44 ` greearb
2021-08-11 21:44 ` [PATCH 07/15] mt76: mt7915: ethtool group-5 rx stats information greearb
` (8 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: greearb @ 2021-08-11 21:44 UTC (permalink / raw)
To: linux-wireless; +Cc: Ben Greear
From: Ben Greear <greearb@candelatech.com>
Make it more clear that this is a tx-stat, and move it to
the tx section of the mib stats struct.
Signed-off-by: Ben Greear <greearb@candelatech.com>
---
drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c | 8 ++++----
drivers/net/wireless/mediatek/mt76/mt7915/mac.c | 4 ++--
drivers/net/wireless/mediatek/mt76/mt7915/main.c | 2 +-
drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h | 3 +--
4 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c b/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c
index 885c60ea2a71..688641ea4bb5 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c
@@ -488,11 +488,11 @@ mt7915_tx_stats_show(struct seq_file *file, void *data)
/* Tx amsdu info */
seq_puts(file, "Tx MSDU statistics:\n");
- for (i = 0, n = 0; i < ARRAY_SIZE(mib->amsdu_pack_stats); i++)
- n += mib->amsdu_pack_stats[i];
+ for (i = 0, n = 0; i < ARRAY_SIZE(mib->tx_amsdu_pack_stats); i++)
+ n += mib->tx_amsdu_pack_stats[i];
- for (i = 0; i < ARRAY_SIZE(mib->amsdu_pack_stats); i++) {
- long si = mib->amsdu_pack_stats[i];
+ for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu_pack_stats); i++) {
+ long si = mib->tx_amsdu_pack_stats[i];
seq_printf(file, "AMSDU pack count of %d MSDU in TXD: %ld ",
i + 1, si);
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
index b44ca71e7d06..f1cff26cbc36 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
@@ -2204,8 +2204,8 @@ mt7915_mac_update_stats(struct mt7915_phy *phy)
}
/* Tx amsdu info (pack-count histogram) */
- for (i = 0; i < ARRAY_SIZE(mib->amsdu_pack_stats); i++)
- mib->amsdu_pack_stats[i] += mt76_rr(dev, MT_PLE_AMSDU_PACK_MSDU_CNT(i));
+ for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu_pack_stats); i++)
+ mib->tx_amsdu_pack_stats[i] += mt76_rr(dev, MT_PLE_AMSDU_PACK_MSDU_CNT(i));
}
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/main.c b/drivers/net/wireless/mediatek/mt76/mt7915/main.c
index b3f3b53da843..427b275f123a 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/main.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/main.c
@@ -1255,7 +1255,7 @@ void mt7915_get_et_stats(struct ieee80211_hw *hw,
/* Tx amsdu info (pack-count histogram) */
for (i = 0; i < 8; i++)
- data[ei++] = mib->amsdu_pack_stats[i];
+ data[ei++] = mib->tx_amsdu_pack_stats[i];
/* rx counters */
data[ei++] = mib->rx_fifo_full_cnt;
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h b/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
index 8086233d6e2b..b446a5c73aa5 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
@@ -147,6 +147,7 @@ struct mib_stats {
u32 tx_rwp_fail_cnt;
u32 tx_rwp_need_cnt;
+ u32 tx_amsdu_pack_stats[8]; /* histogram of how many sub-frames in amsdu */
/* rx stats */
u32 rx_fifo_full_cnt;
@@ -162,8 +163,6 @@ struct mib_stats {
u32 rx_pfdrop_cnt;
u32 rx_vec_queue_overflow_drop_cnt;
u32 rx_ba_cnt;
-
- u32 amsdu_pack_stats[8]; /* histogram of how many sub-frames in amsdu */
};
struct mt7915_hif {
--
2.20.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 07/15] mt76: mt7915: ethtool group-5 rx stats information
2021-08-11 21:44 [PATCH 00/15] mt7915 stats and debugging improvements greearb
` (5 preceding siblings ...)
2021-08-11 21:44 ` [PATCH 06/15] mt76: mt7915: rename amsdu_pack_stats to tx_amsdu_pack_stats greearb
@ 2021-08-11 21:44 ` greearb
2021-08-11 21:44 ` [PATCH 08/15] mt76: mt7915: ethtool counters for driver rx path greearb
` (7 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: greearb @ 2021-08-11 21:44 UTC (permalink / raw)
To: linux-wireless; +Cc: Ben Greear
From: Ben Greear <greearb@candelatech.com>
Add ethtool support for rx-nss, rx-bw, rx-mode stats.
These are only valid when the group-5 rx stats are
enabled.
Signed-off-by: Ben Greear <greearb@candelatech.com>
---
.../net/wireless/mediatek/mt76/mt7915/mac.c | 23 ++++++++++
.../net/wireless/mediatek/mt76/mt7915/main.c | 42 +++++++++++++++++++
.../wireless/mediatek/mt76/mt7915/mt7915.h | 10 +++++
3 files changed, 75 insertions(+)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
index f1cff26cbc36..697dbf62c35f 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
@@ -424,6 +424,7 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
u8 qos_ctl = 0;
__le16 fc = 0;
int i, idx;
+ struct mt7915_sta_stats *mstats = NULL;
memset(status, 0, sizeof(*status));
@@ -451,6 +452,7 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
struct mt7915_sta *msta;
msta = container_of(status->wcid, struct mt7915_sta, wcid);
+ mstats = &msta->stats;
spin_lock_bh(&dev->sta_poll_lock);
if (list_empty(&msta->poll_list))
list_add_tail(&msta->poll_list, &dev->sta_poll_list);
@@ -654,8 +656,19 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
WARN_ON_ONCE(nss > 4);
}
+ if (mstats) {
+ if (nss > 3)
+ mstats->rx_nss[3]++;
+ else
+ mstats->rx_nss[nss - 1]++;
+
+ mstats->rx_mode[mode]++;
+ }
+
switch (FIELD_GET(MT_CRXV_FRAME_MODE, v2)) {
case IEEE80211_STA_RX_BW_20:
+ if (mstats)
+ mstats->rx_bw_20++;
break;
case IEEE80211_STA_RX_BW_40:
if (mode & MT_PHY_TYPE_HE_EXT_SU &&
@@ -663,14 +676,24 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
status->bw = RATE_INFO_BW_HE_RU;
status->he_ru =
NL80211_RATE_INFO_HE_RU_ALLOC_106;
+ if (mstats) {
+ mstats->rx_bw_he_ru++;
+ mstats->rx_ru_106++;
+ }
} else {
status->bw = RATE_INFO_BW_40;
+ if (mstats)
+ mstats->rx_bw_40++;
}
break;
case IEEE80211_STA_RX_BW_80:
status->bw = RATE_INFO_BW_80;
+ if (mstats)
+ mstats->rx_bw_80++;
break;
case IEEE80211_STA_RX_BW_160:
+ if (mstats)
+ mstats->rx_bw_160++;
status->bw = RATE_INFO_BW_160;
break;
default:
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/main.c b/drivers/net/wireless/mediatek/mt76/mt7915/main.c
index 427b275f123a..1ce4260557c7 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/main.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/main.c
@@ -1123,6 +1123,27 @@ static const char mt7915_gstrings_stats[][ETH_GSTRING_LEN] = {
"v_tx_mcs_9",
"v_tx_mcs_10",
"v_tx_mcs_11",
+
+ /* per-vif rx counters */
+ "v_rx_nss1",
+ "v_rx_nss2",
+ "v_rx_nss3",
+ "v_rx_nss4",
+ "v_rx_mode_cck",
+ "v_rx_mode_ofdm",
+ "v_rx_mode_ht",
+ "v_rx_mode_ht_gf",
+ "v_rx_mode_vht",
+ "v_rx_mode_he_su",
+ "v_rx_mode_he_ext_su",
+ "v_rx_mode_he_tb",
+ "v_rx_mode_he_mu",
+ "v_rx_bw_20",
+ "v_rx_bw_40",
+ "v_rx_bw_80",
+ "v_rx_bw_160",
+ "v_rx_bw_he_ru",
+ "v_rx_ru_106",
};
#define MT7915_SSTATS_LEN ARRAY_SIZE(mt7915_gstrings_stats)
@@ -1190,6 +1211,27 @@ static void mt7915_ethtool_worker(void *wi_data, struct ieee80211_sta *sta)
for (q = 0; q < 12; q++)
data[ei++] += mstats->tx_mcs[q];
+ /* rx stats */
+ for (q = 0; q < ARRAY_SIZE(mstats->rx_nss); q++)
+ data[ei++] += mstats->rx_nss[q];
+
+ data[ei++] += mstats->rx_mode[MT_PHY_TYPE_CCK];
+ data[ei++] += mstats->rx_mode[MT_PHY_TYPE_OFDM];
+ data[ei++] += mstats->rx_mode[MT_PHY_TYPE_HT];
+ data[ei++] += mstats->rx_mode[MT_PHY_TYPE_HT_GF];
+ data[ei++] += mstats->rx_mode[MT_PHY_TYPE_VHT];
+ data[ei++] += mstats->rx_mode[MT_PHY_TYPE_HE_SU];
+ data[ei++] += mstats->rx_mode[MT_PHY_TYPE_HE_EXT_SU];
+ data[ei++] += mstats->rx_mode[MT_PHY_TYPE_HE_TB];
+ data[ei++] += mstats->rx_mode[MT_PHY_TYPE_HE_MU];
+
+ data[ei++] += mstats->rx_bw_20;
+ data[ei++] += mstats->rx_bw_40;
+ data[ei++] += mstats->rx_bw_80;
+ data[ei++] += mstats->rx_bw_160;
+ data[ei++] += mstats->rx_bw_he_ru;
+ data[ei++] += mstats->rx_ru_106;
+
wi->worker_stat_count = ei - wi->initial_stat_idx;
}
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h b/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
index b446a5c73aa5..1f0be4fbee35 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
@@ -73,6 +73,16 @@ struct mt7915_sta_stats {
unsigned long tx_bw[4]; /* 20, 40, 80, 160 */
unsigned long tx_nss[4]; /* 1, 2, 3, 4 */
unsigned long tx_mcs[16]; /* mcs idx */
+
+ /* This section requires group-5 in rxd to be enabled. */
+ u32 rx_nss[4]; /* rx-nss histogram */
+ u32 rx_mode[MT_PHY_TYPE_HE_LAST]; /* rx mode histogram */
+ u32 rx_bw_20;
+ u32 rx_bw_40;
+ u32 rx_bw_80;
+ u32 rx_bw_160;
+ u32 rx_bw_he_ru;
+ u32 rx_ru_106;
};
struct mt7915_sta_key_conf {
--
2.20.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 08/15] mt76: mt7915: ethtool counters for driver rx path
2021-08-11 21:44 [PATCH 00/15] mt7915 stats and debugging improvements greearb
` (6 preceding siblings ...)
2021-08-11 21:44 ` [PATCH 07/15] mt76: mt7915: ethtool group-5 rx stats information greearb
@ 2021-08-11 21:44 ` greearb
2021-08-11 21:44 ` [PATCH 09/15] mt76: mt7915: fix rate rix and flags in txs path greearb
` (6 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: greearb @ 2021-08-11 21:44 UTC (permalink / raw)
To: linux-wireless; +Cc: Ben Greear
From: Ben Greear <greearb@candelatech.com>
Add some per-phy counters for rx errors in the driver.
Signed-off-by: Ben Greear <greearb@candelatech.com>
---
.../net/wireless/mediatek/mt76/mt7915/mac.c | 45 ++++++++++++++-----
.../net/wireless/mediatek/mt76/mt7915/main.c | 22 +++++++++
.../wireless/mediatek/mt76/mt7915/mt7915.h | 11 +++++
3 files changed, 68 insertions(+), 10 deletions(-)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
index 697dbf62c35f..138059278ac0 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
@@ -425,9 +425,12 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
__le16 fc = 0;
int i, idx;
struct mt7915_sta_stats *mstats = NULL;
+ struct mib_stats *mib = &phy->mib;
memset(status, 0, sizeof(*status));
+ mib->rx_d_skb++;
+
if (rxd1 & MT_RXD1_NORMAL_BAND_IDX) {
mphy = dev->mt76.phy2;
if (!mphy)
@@ -440,8 +443,10 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
if (!test_bit(MT76_STATE_RUNNING, &mphy->state))
return -EINVAL;
- if (rxd2 & MT_RXD2_NORMAL_AMSDU_ERR)
+ if (rxd2 & MT_RXD2_NORMAL_AMSDU_ERR) {
+ mib->rx_d_rxd2_amsdu_err++;
return -EINVAL;
+ }
unicast = FIELD_GET(MT_RXD3_NORMAL_ADDR_TYPE, rxd3) == MT_RXD3_NORMAL_U2M;
idx = FIELD_GET(MT_RXD1_NORMAL_WLAN_IDX, rxd1);
@@ -466,8 +471,10 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
else
sband = &mphy->sband_2g.sband;
- if (!sband->channels)
+ if (!sband->channels) {
+ mib->rx_d_null_channels++;
return -EINVAL;
+ }
if ((rxd0 & csum_mask) == csum_mask)
skb->ip_summed = CHECKSUM_UNNECESSARY;
@@ -487,8 +494,10 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
remove_pad = FIELD_GET(MT_RXD2_NORMAL_HDR_OFFSET, rxd2);
- if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR)
+ if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR) {
+ mib->rx_d_max_len_err++;
return -EINVAL;
+ }
rxd += 6;
if (rxd1 & MT_RXD1_NORMAL_GROUP_4) {
@@ -500,8 +509,10 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
seq_ctrl = FIELD_GET(MT_RXD8_SEQ_CTRL, v2);
rxd += 4;
- if ((u8 *)rxd - skb->data >= skb->len)
+ if ((u8 *)rxd - skb->data >= skb->len) {
+ mib->rx_d_too_short++;
return -EINVAL;
+ }
}
if (rxd1 & MT_RXD1_NORMAL_GROUP_1) {
@@ -532,8 +543,10 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
}
}
rxd += 4;
- if ((u8 *)rxd - skb->data >= skb->len)
+ if ((u8 *)rxd - skb->data >= skb->len) {
+ mib->rx_d_too_short++;
return -EINVAL;
+ }
}
if (rxd1 & MT_RXD1_NORMAL_GROUP_2) {
@@ -555,8 +568,10 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
}
rxd += 2;
- if ((u8 *)rxd - skb->data >= skb->len)
+ if ((u8 *)rxd - skb->data >= skb->len) {
+ mib->rx_d_too_short++;
return -EINVAL;
+ }
}
/* RXD Group 3 - P-RXV */
@@ -566,8 +581,10 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
rxv = rxd; /* DW16 assuming group 1,2,3,4 */
rxd += 2;
- if ((u8 *)rxd - skb->data >= skb->len)
+ if ((u8 *)rxd - skb->data >= skb->len) {
+ mib->rx_d_too_short++;
return -EINVAL;
+ }
v0 = le32_to_cpu(rxv[0]); /* DW16, P-VEC1 31:0 */
/* DW17, RX_RCPI copied over P-VEC 64:32 Per RX Format doc. */
@@ -600,8 +617,10 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
nss = 1;
rxd += 18;
- if ((u8 *)rxd - skb->data >= skb->len)
+ if ((u8 *)rxd - skb->data >= skb->len) {
+ mib->rx_d_too_short++;
return -EINVAL;
+ }
idx = i = FIELD_GET(MT_PRXV_TX_RATE, v0);
mode = FIELD_GET(MT_CRXV_TX_MODE, v2);
@@ -616,16 +635,20 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
case MT_PHY_TYPE_HT_GF:
case MT_PHY_TYPE_HT:
status->encoding = RX_ENC_HT;
- if (i > 31)
+ if (i > 31) {
+ mib->rx_d_bad_ht_rix++;
return -EINVAL;
+ }
nss = i / 8 + 1;
break;
case MT_PHY_TYPE_VHT:
status->nss =
FIELD_GET(MT_PRXV_NSTS, v0) + 1;
status->encoding = RX_ENC_VHT;
- if (i > 9)
+ if (i > 9) {
+ mib->rx_d_bad_vht_rix++;
return -EINVAL;
+ }
nss = status->nss;
break;
case MT_PHY_TYPE_HE_MU:
@@ -647,6 +670,7 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
status->he_dcm = !!(idx & MT_PRXV_TX_DCM);
break;
default:
+ mib->rx_d_bad_mode++;
return -EINVAL;
}
status->rate_idx = i;
@@ -697,6 +721,7 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
status->bw = RATE_INFO_BW_160;
break;
default:
+ mib->rx_d_bad_bw++;
return -EINVAL;
}
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/main.c b/drivers/net/wireless/mediatek/mt76/mt7915/main.c
index 1ce4260557c7..22ceb46be4bf 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/main.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/main.c
@@ -1093,6 +1093,17 @@ static const char mt7915_gstrings_stats[][ETH_GSTRING_LEN] = {
"rx_vec_queue_overflow_drop_cnt",
"rx_ba_cnt",
+ /* driver rx counters */
+ "d_rx_skb",
+ "d_rx_rxd2_amsdu_err",
+ "d_rx_null_channels",
+ "d_rx_max_len_err",
+ "d_rx_too_short",
+ "d_rx_bad_ht_rix",
+ "d_rx_bad_vht_rix",
+ "d_rx_bad_mode",
+ "d_rx_bad_bw",
+
/* per vif counters */
"v_tx_mpdu_attempts", /* counting any retries */
"v_tx_mpdu_fail", /* frames that failed even after retry */
@@ -1314,6 +1325,17 @@ void mt7915_get_et_stats(struct ieee80211_hw *hw,
data[ei++] = mib->rx_vec_queue_overflow_drop_cnt;
data[ei++] = mib->rx_ba_cnt;
+ /* rx stats from driver */
+ data[ei++] = mib->rx_d_skb;
+ data[ei++] = mib->rx_d_rxd2_amsdu_err;
+ data[ei++] = mib->rx_d_null_channels;
+ data[ei++] = mib->rx_d_max_len_err;
+ data[ei++] = mib->rx_d_too_short;
+ data[ei++] = mib->rx_d_bad_ht_rix;
+ data[ei++] = mib->rx_d_bad_vht_rix;
+ data[ei++] = mib->rx_d_bad_mode;
+ data[ei++] = mib->rx_d_bad_bw;
+
/* Add values for all stations owned by this vif */
wi.data = data;
wi.mvif = mvif;
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h b/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
index 1f0be4fbee35..2d7c84946e40 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
@@ -173,6 +173,17 @@ struct mib_stats {
u32 rx_pfdrop_cnt;
u32 rx_vec_queue_overflow_drop_cnt;
u32 rx_ba_cnt;
+
+ /* rx stats from the driver */
+ u32 rx_d_skb; /* total skb received in rx path */
+ u32 rx_d_rxd2_amsdu_err;
+ u32 rx_d_null_channels;
+ u32 rx_d_max_len_err;
+ u32 rx_d_too_short;
+ u32 rx_d_bad_ht_rix;
+ u32 rx_d_bad_vht_rix;
+ u32 rx_d_bad_mode;
+ u32 rx_d_bad_bw;
};
struct mt7915_hif {
--
2.20.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 09/15] mt76: mt7915: fix rate rix and flags in txs path
2021-08-11 21:44 [PATCH 00/15] mt7915 stats and debugging improvements greearb
` (7 preceding siblings ...)
2021-08-11 21:44 ` [PATCH 08/15] mt76: mt7915: ethtool counters for driver rx path greearb
@ 2021-08-11 21:44 ` greearb
2021-08-11 21:44 ` [PATCH 10/15] mt76: mt7915: add ethtool tx/rx pkts/bytes greearb
` (5 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: greearb @ 2021-08-11 21:44 UTC (permalink / raw)
To: linux-wireless; +Cc: Ben Greear
From: Ben Greear <greearb@candelatech.com>
Do not initialize rix to -1, build the rix and set flags
based on the mcs, nss, and mode.
Signed-off-by: Ben Greear <greearb@candelatech.com>
---
drivers/net/wireless/mediatek/mt76/mt7915/mac.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
index 138059278ac0..7ca06b8c9671 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
@@ -1541,8 +1541,6 @@ mt7915_mac_parse_txs(struct mt7915_dev *dev, struct mt76_wcid *wcid,
info->status.ampdu_ack_len = !!(info->flags &
IEEE80211_TX_STAT_ACK);
- info->status.rates[0].idx = -1;
-
txrate = FIELD_GET(MT_TXS0_TX_RATE, txs);
rate->mcs = FIELD_GET(MT_TX_RATE_IDX, txrate);
@@ -1575,6 +1573,7 @@ mt7915_mac_parse_txs(struct mt7915_dev *dev, struct mt76_wcid *wcid,
rate->mcs = mt76_get_rate(mphy->dev, sband, rate->mcs, cck);
rate->legacy = sband->bitrates[rate->mcs].bitrate;
+ info->status.rates[0].idx = rate->mcs;
break;
case MT_PHY_TYPE_HT:
case MT_PHY_TYPE_HT_GF:
@@ -1585,6 +1584,8 @@ mt7915_mac_parse_txs(struct mt7915_dev *dev, struct mt76_wcid *wcid,
rate->flags = RATE_INFO_FLAGS_MCS;
if (wcid->rate_short_gi)
rate->flags |= RATE_INFO_FLAGS_SHORT_GI;
+ info->status.rates[0].idx = rate->mcs + rate->nss * 8;
+ info->status.rates[0].flags |= IEEE80211_TX_RC_MCS;
break;
case MT_PHY_TYPE_VHT:
if (rate->mcs > 9)
@@ -1593,6 +1594,8 @@ mt7915_mac_parse_txs(struct mt7915_dev *dev, struct mt76_wcid *wcid,
rate->flags = RATE_INFO_FLAGS_VHT_MCS;
if (wcid->rate_short_gi)
rate->flags |= RATE_INFO_FLAGS_SHORT_GI;
+ info->status.rates[0].idx = (rate->nss << 4) | rate->mcs;
+ info->status.rates[0].flags |= IEEE80211_TX_RC_VHT_MCS;
break;
case MT_PHY_TYPE_HE_SU:
case MT_PHY_TYPE_HE_EXT_SU:
@@ -1604,6 +1607,7 @@ mt7915_mac_parse_txs(struct mt7915_dev *dev, struct mt76_wcid *wcid,
rate->he_gi = wcid->rate_he_gi;
rate->he_dcm = FIELD_GET(MT_TX_RATE_DCM, txrate);
rate->flags = RATE_INFO_FLAGS_HE_MCS;
+ info->status.rates[0].idx = (rate->nss << 4) | rate->mcs;
break;
default:
WARN_ON_ONCE(true);
--
2.20.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 10/15] mt76: mt7915: add ethtool tx/rx pkts/bytes
2021-08-11 21:44 [PATCH 00/15] mt7915 stats and debugging improvements greearb
` (8 preceding siblings ...)
2021-08-11 21:44 ` [PATCH 09/15] mt76: mt7915: fix rate rix and flags in txs path greearb
@ 2021-08-11 21:44 ` greearb
2021-08-11 21:44 ` [PATCH 11/15] mt76: mt7915: debugfs display for pse non-empty queues greearb
` (4 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: greearb @ 2021-08-11 21:44 UTC (permalink / raw)
To: linux-wireless; +Cc: Ben Greear
From: Ben Greear <greearb@candelatech.com>
These stats are provided with same name by ath10k
and some intel wired NIC drivers. Add them to mt7915
as well to allow user-space code to more easily get some
basic stats out of the radio.
Signed-off-by: Ben Greear <greearb@candelatech.com>
---
drivers/net/wireless/mediatek/mt76/mt7915/mac.c | 7 +++++++
drivers/net/wireless/mediatek/mt76/mt7915/main.c | 11 +++++++++++
drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h | 7 +++++++
3 files changed, 25 insertions(+)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
index 7ca06b8c9671..9883d1e55f5b 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
@@ -782,6 +782,9 @@ mt7915_mac_fill_rx(struct mt7915_dev *dev, struct sk_buff *skb)
mt7915_mac_decode_he_mu_radiotap(skb, status, rxv);
}
+ mib->rx_pkts_nic++;
+ mib->rx_bytes_nic += skb->len;
+
if (!status->wcid || !ieee80211_is_data_qos(fc))
return 0;
@@ -1341,6 +1344,8 @@ mt7915_txwi_free(struct mt7915_dev *dev, struct mt76_txwi_cache *t,
u16 wcid_idx;
struct ieee80211_tx_info *info;
struct ieee80211_tx_rate *rate;
+ struct mt7915_phy *phy = &dev->phy;
+ struct mib_stats *mib = &phy->mib;
mt7915_txp_skb_unmap(mdev, t);
if (!t->skb)
@@ -1422,6 +1427,8 @@ mt7915_txwi_free(struct mt7915_dev *dev, struct mt76_txwi_cache *t,
/* Apply the values that this txfree path reports */
rate->count = tx_cnt;
if (tx_status == 0) {
+ mib->tx_pkts_nic++;
+ mib->tx_bytes_nic += t->skb->len;
info->flags |= IEEE80211_TX_STAT_ACK;
info->status.ampdu_ack_len = 1;
} else {
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/main.c b/drivers/net/wireless/mediatek/mt76/mt7915/main.c
index 22ceb46be4bf..4f609a5d38a4 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/main.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/main.c
@@ -1030,6 +1030,10 @@ static void mt7915_sta_set_decap_offload(struct ieee80211_hw *hw,
}
static const char mt7915_gstrings_stats[][ETH_GSTRING_LEN] = {
+ "tx_pkts_nic", /* from driver, phy tx-ok skb */
+ "tx_bytes_nic", /* from driver, phy tx-ok bytes */
+ "rx_pkts_nic", /* from driver, phy rx OK skb */
+ "rx_bytes_nic", /* from driver, phy rx OK bytes */
"tx_ampdu_cnt",
"tx_stop_q_empty_cnt",
"tx_mpdu_attempts",
@@ -1265,6 +1269,13 @@ void mt7915_get_et_stats(struct ieee80211_hw *hw,
if (!phy)
return;
+ /* driver phy-wide stats */
+ data[ei++] = mib->tx_pkts_nic;
+ data[ei++] = mib->tx_bytes_nic;
+ data[ei++] = mib->rx_pkts_nic;
+ data[ei++] = mib->rx_bytes_nic;
+
+ /* MIB stats from FW/HW */
data[ei++] = mib->tx_ampdu_cnt;
data[ei++] = mib->tx_stop_q_empty_cnt;
data[ei++] = mib->tx_mpdu_attempts_cnt;
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h b/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
index 2d7c84946e40..1a0d7d62c582 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
@@ -125,6 +125,13 @@ struct mt7915_vif {
/* per-phy stats. */
struct mib_stats {
+ /* phy wide driver stats */
+ u32 tx_pkts_nic; /* tx OK skb */
+ u32 tx_bytes_nic; /* tx OK bytes */
+ u32 rx_pkts_nic; /* rx OK skb */
+ u32 rx_bytes_nic; /* rx OK bytes */
+
+ /* MIB counters from FW/HW */
u32 ack_fail_cnt;
u32 fcs_err_cnt;
u32 rts_cnt;
--
2.20.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 11/15] mt76: mt7915: debugfs display for pse non-empty queues
2021-08-11 21:44 [PATCH 00/15] mt7915 stats and debugging improvements greearb
` (9 preceding siblings ...)
2021-08-11 21:44 ` [PATCH 10/15] mt76: mt7915: add ethtool tx/rx pkts/bytes greearb
@ 2021-08-11 21:44 ` greearb
2021-08-11 21:44 ` [PATCH 12/15] mt76: mt7915: add more pse queue data to debugfs greearb
` (3 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: greearb @ 2021-08-11 21:44 UTC (permalink / raw)
To: linux-wireless; +Cc: Ben Greear
From: Ben Greear <greearb@candelatech.com>
This may give user some idea of how the buffer utilization is being used
in the firmware/hardware.
Signed-off-by: Ben Greear <greearb@candelatech.com>
---
.../wireless/mediatek/mt76/mt7915/debugfs.c | 141 ++++++++++++
.../net/wireless/mediatek/mt76/mt7915/regs.h | 201 ++++++++++++++++++
2 files changed, 342 insertions(+)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c b/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c
index 688641ea4bb5..5c6a75f45f8f 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c
@@ -507,6 +507,146 @@ mt7915_tx_stats_show(struct seq_file *file, void *data)
DEFINE_SHOW_ATTRIBUTE(mt7915_tx_stats);
+struct mt7915_empty_q_info {
+ const char *qname;
+ u32 port_id;
+ u32 q_id;
+};
+
+static struct mt7915_empty_q_info pse_queue_empty_info[] = {
+ {"CPU Q0", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_0},
+ {"CPU Q1", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_1},
+ {"CPU Q2", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_2},
+ {"CPU Q3", ENUM_UMAC_CPU_PORT_1, ENUM_UMAC_CTX_Q_3},
+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 4~7 not defined */
+ {"HIF Q0", ENUM_UMAC_HIF_PORT_0, 0}, /* Q8 */
+ {"HIF Q1", ENUM_UMAC_HIF_PORT_0, 1},
+ {"HIF Q2", ENUM_UMAC_HIF_PORT_0, 2},
+ {"HIF Q3", ENUM_UMAC_HIF_PORT_0, 3},
+ {"HIF Q4", ENUM_UMAC_HIF_PORT_0, 4},
+ {"HIF Q5", ENUM_UMAC_HIF_PORT_0, 5},
+ {NULL, 0, 0}, {NULL, 0, 0}, /* 14~15 not defined */
+ {"LMAC Q", ENUM_UMAC_LMAC_PORT_2, 0},
+ {"MDP TX Q", ENUM_UMAC_LMAC_PORT_2, 1},
+ {"MDP RX Q", ENUM_UMAC_LMAC_PORT_2, 2},
+ {"SEC TX Q", ENUM_UMAC_LMAC_PORT_2, 3},
+ {"SEC RX Q", ENUM_UMAC_LMAC_PORT_2, 4},
+ {"SFD_PARK Q", ENUM_UMAC_LMAC_PORT_2, 5},
+ {"MDP_TXIOC Q", ENUM_UMAC_LMAC_PORT_2, 6},
+ {"MDP_RXIOC Q", ENUM_UMAC_LMAC_PORT_2, 7},
+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0},
+ {NULL, 0, 0}, {NULL, 0, 0}, {NULL, 0, 0}, /* 24~30 not defined */
+ {"RLS Q", ENUM_PLE_CTRL_PSE_PORT_3, ENUM_UMAC_PLE_CTRL_P3_Q_0X1F}
+};
+
+static void
+mt7915_pse_q_nonempty_stat_read_phy(struct mt7915_phy *phy,
+ struct seq_file *file)
+{
+ struct mt7915_dev *dev = file->private;
+ u32 pse_stat;
+ int i;
+
+ pse_stat = mt76_rr(dev, WF_PSE_TOP_QUEUE_EMPTY_ADDR);
+
+ /* Queue Empty Status */
+ seq_puts(file, "PSE Queue Empty Status:\n");
+ seq_printf(file, "\tQUEUE_EMPTY: 0x%08x\n", pse_stat);
+ seq_printf(file, "\t\tCPU Q0/1/2/3 empty=%d/%d/%d/%d\n",
+ ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_CPU_Q0_EMPTY_MASK)
+ >> WF_PSE_TOP_QUEUE_EMPTY_CPU_Q0_EMPTY_SHFT),
+ ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_CPU_Q1_EMPTY_MASK)
+ >> WF_PSE_TOP_QUEUE_EMPTY_CPU_Q1_EMPTY_SHFT),
+ ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_CPU_Q2_EMPTY_MASK)
+ >> WF_PSE_TOP_QUEUE_EMPTY_CPU_Q2_EMPTY_SHFT),
+ ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_CPU_Q3_EMPTY_MASK)
+ >> WF_PSE_TOP_QUEUE_EMPTY_CPU_Q3_EMPTY_SHFT));
+ seq_printf(file, "\t\tHIF Q0/1/2/3/4/5 empty=%d/%d/%d/%d/%d/%d\n",
+ ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_HIF_0_EMPTY_MASK)
+ >> WF_PSE_TOP_QUEUE_EMPTY_HIF_0_EMPTY_SHFT),
+ ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_HIF_1_EMPTY_MASK)
+ >> WF_PSE_TOP_QUEUE_EMPTY_HIF_1_EMPTY_SHFT),
+ ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_HIF_2_EMPTY_MASK)
+ >> WF_PSE_TOP_QUEUE_EMPTY_HIF_2_EMPTY_SHFT),
+ ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_HIF_3_EMPTY_MASK)
+ >> WF_PSE_TOP_QUEUE_EMPTY_HIF_3_EMPTY_SHFT),
+ ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_HIF_4_EMPTY_MASK)
+ >> WF_PSE_TOP_QUEUE_EMPTY_HIF_4_EMPTY_SHFT),
+ ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_HIF_5_EMPTY_MASK)
+ >> WF_PSE_TOP_QUEUE_EMPTY_HIF_5_EMPTY_SHFT));
+ seq_printf(file, "\t\tLMAC TX Q empty=%d\n",
+ ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_MASK)
+ >> WF_PSE_TOP_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_SHFT));
+ seq_printf(file, "\t\tMDP TX Q/RX Q empty=%d/%d\n",
+ ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_MASK)
+ >> WF_PSE_TOP_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_SHFT),
+ ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_MASK)
+ >> WF_PSE_TOP_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_SHFT));
+ seq_printf(file, "\t\tSEC TX Q/RX Q empty=%d/%d\n",
+ ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_MASK)
+ >> WF_PSE_TOP_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_SHFT),
+ ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_MASK)
+ >> WF_PSE_TOP_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_SHFT));
+ seq_printf(file, "\t\tSFD PARK Q empty=%d\n",
+ ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_MASK)
+ >> WF_PSE_TOP_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_SHFT));
+ seq_printf(file, "\t\tMDP TXIOC Q/RXIOC Q empty=%d/%d\n",
+ ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_MASK)
+ >> WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_SHFT),
+ ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_MASK)
+ >> WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_SHFT));
+ seq_printf(file, "\t\tRLS Q empty=%d\n",
+ ((pse_stat & WF_PSE_TOP_QUEUE_EMPTY_RLS_Q_EMTPY_MASK)
+ >> WF_PSE_TOP_QUEUE_EMPTY_RLS_Q_EMTPY_SHFT));
+ seq_printf(file, ("Non-Empty Q info:\n"));
+
+ for (i = 0; i < 31; i++) {
+ if (((pse_stat & (0x1 << i)) >> i) == 0) {
+ u32 hfid, tfid, pktcnt, fl_que_ctrl[3] = {0};
+
+ if (pse_queue_empty_info[i].qname) {
+ seq_printf(file, "\t%s: ", pse_queue_empty_info[i].qname);
+ fl_que_ctrl[0] |= WF_PSE_TOP_FL_QUE_CTRL_0_EXECUTE_MASK;
+ fl_que_ctrl[0] |= (pse_queue_empty_info[i].port_id
+ << WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_PID_SHFT);
+ fl_que_ctrl[0] |= (pse_queue_empty_info[i].q_id
+ << WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_SHFT);
+ } else {
+ continue;
+ }
+
+ /* Executes frame link and queue structure buffer read command */
+ fl_que_ctrl[0] |= (0x1 << 31);
+ mt76_wr(dev, WF_PSE_TOP_FL_QUE_CTRL_0_ADDR, fl_que_ctrl[0]);
+
+ fl_que_ctrl[1] = mt76_rr(dev, WF_PSE_TOP_FL_QUE_CTRL_2_ADDR);
+ fl_que_ctrl[2] = mt76_rr(dev, WF_PSE_TOP_FL_QUE_CTRL_3_ADDR);
+ hfid = (fl_que_ctrl[1] & WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK)
+ >> WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_SHFT;
+ tfid = (fl_que_ctrl[1] & WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK)
+ >> WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_SHFT;
+ pktcnt = (fl_que_ctrl[2] & WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK)
+ >> WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_SHFT;
+ seq_printf(file, "tail/head fid = 0x%03x/0x%03x, pkt cnt = 0x%03x\n",
+ tfid, hfid, pktcnt);
+ }
+ }
+}
+
+static int
+mt7915_rx_pse_stats_show(struct seq_file *file, void *data)
+{
+ struct mt7915_dev *dev = file->private;
+
+ seq_puts(file, "RX PSE Stats\n");
+
+ mt7915_pse_q_nonempty_stat_read_phy(&dev->phy, file);
+
+ return 0;
+}
+
+DEFINE_SHOW_ATTRIBUTE(mt7915_rx_pse_stats);
+
static int
mt7915_queues_acq(struct seq_file *s, void *data)
{
@@ -622,6 +762,7 @@ int mt7915_init_debugfs(struct mt7915_dev *dev)
debugfs_create_devm_seqfile(dev->mt76.dev, "acq", dir,
mt7915_queues_acq);
debugfs_create_file("tx_stats", 0400, dir, dev, &mt7915_tx_stats_fops);
+ debugfs_create_file("rx_pse_stats", 0400, dir, dev, &mt7915_rx_pse_stats_fops);
debugfs_create_file("fw_debug", 0600, dir, dev, &fops_fw_debug);
debugfs_create_file("txs_for_no_skb", 0600, dir, dev, &fops_txs_for_no_skb);
debugfs_create_file("rx_group_5_enable", 0600, dir, dev, &fops_rx_group_5_enable);
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/regs.h b/drivers/net/wireless/mediatek/mt76/mt7915/regs.h
index ac4d233b8cf2..1e3ce90ff3dd 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/regs.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/regs.h
@@ -566,4 +566,205 @@
#define MT_WF_PHY_RXTD12_IRPI_SW_CLR_ONLY BIT(18)
#define MT_WF_PHY_RXTD12_IRPI_SW_CLR BIT(29)
+/* PSE queue related registers and enums */
+
+/* PLE info */
+enum ENUM_UMAC_PORT {
+ ENUM_UMAC_HIF_PORT_0 = 0,
+ ENUM_UMAC_CPU_PORT_1 = 1,
+ ENUM_UMAC_LMAC_PORT_2 = 2,
+ ENUM_PLE_CTRL_PSE_PORT_3 = 3,
+ ENUM_UMAC_PSE_PLE_PORT_TOTAL_NUM = 4
+};
+
+/* N9 MCU QUEUE LIST */
+enum ENUM_UMAC_CPU_P_QUEUE {
+ ENUM_UMAC_CTX_Q_0 = 0,
+ ENUM_UMAC_CTX_Q_1 = 1,
+ ENUM_UMAC_CTX_Q_2 = 2,
+ ENUM_UMAC_CTX_Q_3 = 3,
+ ENUM_UMAC_CRX = 0,
+ ENUM_UMAC_CIF_QUEUE_TOTAL_NUM = 4
+};
+
+/* LMAC PLE TX QUEUE LIST */
+enum ENUM_UMAC_LMAC_PLE_TX_P_QUEUE {
+ ENUM_UMAC_LMAC_PLE_TX_Q_00 = 0x00,
+ ENUM_UMAC_LMAC_PLE_TX_Q_01 = 0x01,
+ ENUM_UMAC_LMAC_PLE_TX_Q_02 = 0x02,
+ ENUM_UMAC_LMAC_PLE_TX_Q_03 = 0x03,
+
+ ENUM_UMAC_LMAC_PLE_TX_Q_10 = 0x04,
+ ENUM_UMAC_LMAC_PLE_TX_Q_11 = 0x05,
+ ENUM_UMAC_LMAC_PLE_TX_Q_12 = 0x06,
+ ENUM_UMAC_LMAC_PLE_TX_Q_13 = 0x07,
+
+ ENUM_UMAC_LMAC_PLE_TX_Q_20 = 0x08,
+ ENUM_UMAC_LMAC_PLE_TX_Q_21 = 0x09,
+ ENUM_UMAC_LMAC_PLE_TX_Q_22 = 0x0a,
+ ENUM_UMAC_LMAC_PLE_TX_Q_23 = 0x0b,
+
+ ENUM_UMAC_LMAC_PLE_TX_Q_30 = 0x0c,
+ ENUM_UMAC_LMAC_PLE_TX_Q_31 = 0x0d,
+ ENUM_UMAC_LMAC_PLE_TX_Q_32 = 0x0e,
+ ENUM_UMAC_LMAC_PLE_TX_Q_33 = 0x0f,
+
+ ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_0 = 0x10,
+ ENUM_UMAC_LMAC_PLE_TX_Q_BMC_0 = 0x11,
+ ENUM_UMAC_LMAC_PLE_TX_Q_BNC_0 = 0x12,
+ ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_0 = 0x13,
+
+ ENUM_UMAC_LMAC_PLE_TX_Q_ALTX_1 = 0x14,
+ ENUM_UMAC_LMAC_PLE_TX_Q_BMC_1 = 0x15,
+ ENUM_UMAC_LMAC_PLE_TX_Q_BNC_1 = 0x16,
+ ENUM_UMAC_LMAC_PLE_TX_Q_PSMP_1 = 0x17,
+ ENUM_UMAC_LMAC_PLE_TX_Q_NAF = 0x18,
+ ENUM_UMAC_LMAC_PLE_TX_Q_NBCN = 0x19,
+ /* DE suggests not to use 0x1f, it's only for hw free queue */
+ ENUM_UMAC_LMAC_PLE_TX_Q_RELEASE = 0x1f,
+ ENUM_UMAC_LMAC_QUEUE_TOTAL_NUM = 24,
+};
+
+/* LMAC PLE For PSE Control P3 */
+enum _ENUM_UMAC_PLE_CTRL_P3_QUEUE {
+ ENUM_UMAC_PLE_CTRL_P3_Q_0X1E = 0x1e,
+ ENUM_UMAC_PLE_CTRL_P3_Q_0X1F = 0x1f,
+ ENUM_UMAC_PLE_CTRL_P3_TOTAL_NUM = 2
+};
+
+#define WF_PSE_TOP_BASE 0x820C8000
+
+#define WF_PSE_TOP_QUEUE_EMPTY_ADDR (WF_PSE_TOP_BASE + 0xB0) /* 80B0 */
+#define WF_PSE_TOP_QUEUE_EMPTY_MASK_ADDR (WF_PSE_TOP_BASE + 0xB4) /* 80B4 */
+
+#define WF_PSE_TOP_FL_QUE_CTRL_0_ADDR (WF_PSE_TOP_BASE + 0x1B0) /* 81B0 */
+#define WF_PSE_TOP_FL_QUE_CTRL_1_ADDR (WF_PSE_TOP_BASE + 0x1B4) /* 81B4 */
+#define WF_PSE_TOP_FL_QUE_CTRL_2_ADDR (WF_PSE_TOP_BASE + 0x1B8) /* 81B8 */
+#define WF_PSE_TOP_FL_QUE_CTRL_3_ADDR (WF_PSE_TOP_BASE + 0x1BC) /* 81BC */
+
+#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_6_EMPTY_MASK_ADDR WF_PSE_TOP_QUEUE_EMPTY_MASK_ADDR
+#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_6_EMPTY_MASK_MASK 0x00004000 /* HIF_6_EMPTY_MASK[14] */
+#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_6_EMPTY_MASK_SHFT 14
+#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_5_EMPTY_MASK_ADDR WF_PSE_TOP_QUEUE_EMPTY_MASK_ADDR
+#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_5_EMPTY_MASK_MASK 0x00002000 /* HIF_5_EMPTY_MASK[13] */
+#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_5_EMPTY_MASK_SHFT 13
+#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_4_EMPTY_MASK_ADDR WF_PSE_TOP_QUEUE_EMPTY_MASK_ADDR
+#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_4_EMPTY_MASK_MASK 0x00001000 /* HIF_4_EMPTY_MASK[12] */
+#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_4_EMPTY_MASK_SHFT 12
+#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_3_EMPTY_MASK_ADDR WF_PSE_TOP_QUEUE_EMPTY_MASK_ADDR
+#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_3_EMPTY_MASK_MASK 0x00000800 /* HIF_3_EMPTY_MASK[11] */
+#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_3_EMPTY_MASK_SHFT 11
+#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_2_EMPTY_MASK_ADDR WF_PSE_TOP_QUEUE_EMPTY_MASK_ADDR
+#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_2_EMPTY_MASK_MASK 0x00000400 /* HIF_2_EMPTY_MASK[10] */
+#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_2_EMPTY_MASK_SHFT 10
+#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_1_EMPTY_MASK_ADDR WF_PSE_TOP_QUEUE_EMPTY_MASK_ADDR
+#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_1_EMPTY_MASK_MASK 0x00000200 /* HIF_1_EMPTY_MASK[9] */
+#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_1_EMPTY_MASK_SHFT 9
+#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_0_EMPTY_MASK_ADDR WF_PSE_TOP_QUEUE_EMPTY_MASK_ADDR
+#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_0_EMPTY_MASK_MASK 0x00000100 /* HIF_0_EMPTY_MASK[8] */
+#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_0_EMPTY_MASK_SHFT 8
+
+#define WF_PSE_TOP_QUEUE_EMPTY_RLS_Q_EMTPY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
+#define WF_PSE_TOP_QUEUE_EMPTY_RLS_Q_EMTPY_MASK 0x80000000 /* RLS_Q_EMTPY[31] */
+#define WF_PSE_TOP_QUEUE_EMPTY_RLS_Q_EMTPY_SHFT 31
+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC1_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC1_QUEUE_EMPTY_MASK 0x08000000 /* MDP_RXIOC1_QE[27] */
+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC1_QUEUE_EMPTY_SHFT 27
+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC1_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC1_QUEUE_EMPTY_MASK 0x04000000 /* MDP_TXIOC1_QE[26] */
+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC1_QUEUE_EMPTY_SHFT 26
+#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX1_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
+#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX1_QUEUE_EMPTY_MASK 0x02000000 /* SEC_TX1_QE[25] */
+#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX1_QUEUE_EMPTY_SHFT 25
+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX1_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX1_QUEUE_EMPTY_MASK 0x01000000 /* MDP_TX1_QE[24] */
+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX1_QUEUE_EMPTY_SHFT 24
+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_MASK 0x00800000 /* MDP_RXIOC_QE[23] */
+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RXIOC_QUEUE_EMPTY_SHFT 23
+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_MASK 0x00400000 /* MDP_TXIOC_QE[22] */
+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TXIOC_QUEUE_EMPTY_SHFT 22
+#define WF_PSE_TOP_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
+#define WF_PSE_TOP_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_MASK 0x00200000 /* SFD_PARK_QE[21] */
+#define WF_PSE_TOP_QUEUE_EMPTY_SFD_PARK_QUEUE_EMPTY_SHFT 21
+#define WF_PSE_TOP_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
+#define WF_PSE_TOP_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_MASK 0x00100000 /* SEC_RX_QE[20] */
+#define WF_PSE_TOP_QUEUE_EMPTY_SEC_RX_QUEUE_EMPTY_SHFT 20
+#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
+#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_MASK 0x00080000 /* SEC_TX_QE[19] */
+#define WF_PSE_TOP_QUEUE_EMPTY_SEC_TX_QUEUE_EMPTY_SHFT 19
+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_MASK 0x00040000 /* MDP_RX_QE[18] */
+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_RX_QUEUE_EMPTY_SHFT 18
+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_MASK 0x00020000 /* MDP_TX_QE[17] */
+#define WF_PSE_TOP_QUEUE_EMPTY_MDP_TX_QUEUE_EMPTY_SHFT 17
+#define WF_PSE_TOP_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
+#define WF_PSE_TOP_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_MASK 0x00010000 /* LMAC_TX_QE[16] */
+#define WF_PSE_TOP_QUEUE_EMPTY_LMAC_TX_QUEUE_EMPTY_SHFT 16
+#define WF_PSE_TOP_QUEUE_EMPTY_HIF_6_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
+#define WF_PSE_TOP_QUEUE_EMPTY_HIF_6_EMPTY_MASK 0x00004000 /* HIF_6_EMPTY[14] */
+#define WF_PSE_TOP_QUEUE_EMPTY_HIF_6_EMPTY_SHFT 14
+#define WF_PSE_TOP_QUEUE_EMPTY_HIF_5_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
+#define WF_PSE_TOP_QUEUE_EMPTY_HIF_5_EMPTY_MASK 0x00002000 /* HIF_5_EMPTY[13] */
+#define WF_PSE_TOP_QUEUE_EMPTY_HIF_5_EMPTY_SHFT 13
+#define WF_PSE_TOP_QUEUE_EMPTY_HIF_4_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
+#define WF_PSE_TOP_QUEUE_EMPTY_HIF_4_EMPTY_MASK 0x00001000 /* HIF_4_EMPTY[12] */
+#define WF_PSE_TOP_QUEUE_EMPTY_HIF_4_EMPTY_SHFT 12
+#define WF_PSE_TOP_QUEUE_EMPTY_HIF_3_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
+#define WF_PSE_TOP_QUEUE_EMPTY_HIF_3_EMPTY_MASK 0x00000800 /* HIF_3_EMPTY[11] */
+#define WF_PSE_TOP_QUEUE_EMPTY_HIF_3_EMPTY_SHFT 11
+#define WF_PSE_TOP_QUEUE_EMPTY_HIF_2_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
+#define WF_PSE_TOP_QUEUE_EMPTY_HIF_2_EMPTY_MASK 0x00000400 /* HIF_2_EMPTY[10] */
+#define WF_PSE_TOP_QUEUE_EMPTY_HIF_2_EMPTY_SHFT 10
+#define WF_PSE_TOP_QUEUE_EMPTY_HIF_1_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
+#define WF_PSE_TOP_QUEUE_EMPTY_HIF_1_EMPTY_MASK 0x00000200 /* HIF_1_EMPTY[9] */
+#define WF_PSE_TOP_QUEUE_EMPTY_HIF_1_EMPTY_SHFT 9
+#define WF_PSE_TOP_QUEUE_EMPTY_HIF_0_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
+#define WF_PSE_TOP_QUEUE_EMPTY_HIF_0_EMPTY_MASK 0x00000100 /* HIF_0_EMPTY[8] */
+#define WF_PSE_TOP_QUEUE_EMPTY_HIF_0_EMPTY_SHFT 8
+#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q3_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
+#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q3_EMPTY_MASK 0x00000008 /* CPU_Q3_EMPTY[3] */
+#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q3_EMPTY_SHFT 3
+#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q2_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
+#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q2_EMPTY_MASK 0x00000004 /* CPU_Q2_EMPTY[2] */
+#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q2_EMPTY_SHFT 2
+#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q1_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
+#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q1_EMPTY_MASK 0x00000002 /* CPU_Q1_EMPTY[1] */
+#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q1_EMPTY_SHFT 1
+#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q0_EMPTY_ADDR WF_PSE_TOP_QUEUE_EMPTY_ADDR
+#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q0_EMPTY_MASK 0x00000001 /* CPU_Q0_EMPTY[0] */
+#define WF_PSE_TOP_QUEUE_EMPTY_CPU_Q0_EMPTY_SHFT 0
+
+#define WF_PSE_TOP_FL_QUE_CTRL_0_EXECUTE_ADDR WF_PSE_TOP_FL_QUE_CTRL_0_ADDR
+#define WF_PSE_TOP_FL_QUE_CTRL_0_EXECUTE_MASK 0x80000000 /* EXECUTE[31] */
+#define WF_PSE_TOP_FL_QUE_CTRL_0_EXECUTE_SHFT 31
+#define WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_ADDR WF_PSE_TOP_FL_QUE_CTRL_0_ADDR
+#define WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_MASK 0x7F000000 /* Q_BUF_QID[30..24] */
+#define WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_QID_SHFT 24
+#define WF_PSE_TOP_FL_QUE_CTRL_0_FL_BUFFER_ADDR_ADDR WF_PSE_TOP_FL_QUE_CTRL_0_ADDR
+#define WF_PSE_TOP_FL_QUE_CTRL_0_FL_BUFFER_ADDR_MASK 0x00FFF000 /* FL_BUFFER_ADDR[23..12] */
+#define WF_PSE_TOP_FL_QUE_CTRL_0_FL_BUFFER_ADDR_SHFT 12
+#define WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_PID_ADDR WF_PSE_TOP_FL_QUE_CTRL_0_ADDR
+#define WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_PID_MASK 0x00000C00 /* Q_BUF_PID[11..10] */
+#define WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_PID_SHFT 10
+#define WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_WLANID_ADDR WF_PSE_TOP_FL_QUE_CTRL_0_ADDR
+#define WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_WLANID_MASK 0x000003FF /* Q_BUF_WLANID[9..0] */
+#define WF_PSE_TOP_FL_QUE_CTRL_0_Q_BUF_WLANID_SHFT 0
+
+#define WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_ADDR WF_PSE_TOP_FL_QUE_CTRL_2_ADDR
+#define WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_MASK 0x0FFF0000 /* QUEUE_TAIL_FID[27..16] */
+#define WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_TAIL_FID_SHFT 16
+#define WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_ADDR WF_PSE_TOP_FL_QUE_CTRL_2_ADDR
+#define WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_MASK 0x00000FFF /* QUEUE_HEAD_FID[11..0] */
+#define WF_PSE_TOP_FL_QUE_CTRL_2_QUEUE_HEAD_FID_SHFT 0
+
+#define WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PAGE_NUM_ADDR WF_PSE_TOP_FL_QUE_CTRL_3_ADDR
+#define WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PAGE_NUM_MASK 0x00FFF000 /* QUEUE_PAGE_NUM[23..12] */
+#define WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PAGE_NUM_SHFT 12
+#define WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_ADDR WF_PSE_TOP_FL_QUE_CTRL_3_ADDR
+#define WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_MASK 0x00000FFF /* QUEUE_PKT_NUM[11..0] */
+#define WF_PSE_TOP_FL_QUE_CTRL_3_QUEUE_PKT_NUM_SHFT 0
+
#endif
--
2.20.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 12/15] mt76: mt7915: add more pse queue data to debugfs
2021-08-11 21:44 [PATCH 00/15] mt7915 stats and debugging improvements greearb
` (10 preceding siblings ...)
2021-08-11 21:44 ` [PATCH 11/15] mt76: mt7915: debugfs display for pse non-empty queues greearb
@ 2021-08-11 21:44 ` greearb
2021-08-11 21:44 ` [PATCH 13/15] mt76: mt7915: add rx-ppdu-size-out-of-range ethtool counter greearb
` (2 subsequent siblings)
14 siblings, 0 replies; 16+ messages in thread
From: greearb @ 2021-08-11 21:44 UTC (permalink / raw)
To: linux-wireless; +Cc: Ben Greear
From: Ben Greear <greearb@candelatech.com>
This may provide some clues in case rx packet drops are suspected.
Signed-off-by: Ben Greear <greearb@candelatech.com>
---
.../wireless/mediatek/mt76/mt7915/debugfs.c | 111 ++++++++
.../net/wireless/mediatek/mt76/mt7915/regs.h | 246 +++++++++++++++++-
2 files changed, 356 insertions(+), 1 deletion(-)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c b/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c
index 5c6a75f45f8f..9786fb9d7f73 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c
@@ -546,9 +546,120 @@ mt7915_pse_q_nonempty_stat_read_phy(struct mt7915_phy *phy,
struct mt7915_dev *dev = file->private;
u32 pse_stat;
int i;
+ u32 pg_flow_ctrl[22] = {0};
+ u32 fpg_cnt, ffa_cnt, fpg_head, fpg_tail;
+ u32 max_q, min_q, rsv_pg, used_pg;
+ u32 pse_buf_ctrl, pg_sz, pg_num;
+
pse_stat = mt76_rr(dev, WF_PSE_TOP_QUEUE_EMPTY_ADDR);
+ pse_buf_ctrl = mt76_rr(dev, WF_PSE_TOP_PBUF_CTRL_ADDR);
+ pg_flow_ctrl[0] = mt76_rr(dev, WF_PSE_TOP_FREEPG_CNT_ADDR);
+ pg_flow_ctrl[1] = mt76_rr(dev, WF_PSE_TOP_FREEPG_HEAD_TAIL_ADDR);
+ pg_flow_ctrl[2] = mt76_rr(dev, WF_PSE_TOP_PG_HIF0_GROUP_ADDR);
+ pg_flow_ctrl[3] = mt76_rr(dev, WF_PSE_TOP_HIF0_PG_INFO_ADDR);
+ pg_flow_ctrl[4] = mt76_rr(dev, WF_PSE_TOP_PG_HIF1_GROUP_ADDR);
+ pg_flow_ctrl[5] = mt76_rr(dev, WF_PSE_TOP_HIF1_PG_INFO_ADDR);
+ pg_flow_ctrl[6] = mt76_rr(dev, WF_PSE_TOP_PG_CPU_GROUP_ADDR);
+ pg_flow_ctrl[7] = mt76_rr(dev, WF_PSE_TOP_CPU_PG_INFO_ADDR);
+ pg_flow_ctrl[8] = mt76_rr(dev, WF_PSE_TOP_PG_LMAC0_GROUP_ADDR);
+ pg_flow_ctrl[9] = mt76_rr(dev, WF_PSE_TOP_LMAC0_PG_INFO_ADDR);
+ pg_flow_ctrl[10] = mt76_rr(dev, WF_PSE_TOP_PG_LMAC1_GROUP_ADDR);
+ pg_flow_ctrl[11] = mt76_rr(dev, WF_PSE_TOP_LMAC1_PG_INFO_ADDR);
+ pg_flow_ctrl[12] = mt76_rr(dev, WF_PSE_TOP_PG_LMAC2_GROUP_ADDR);
+ pg_flow_ctrl[13] = mt76_rr(dev, WF_PSE_TOP_LMAC2_PG_INFO_ADDR);
+ pg_flow_ctrl[14] = mt76_rr(dev, WF_PSE_TOP_PG_PLE_GROUP_ADDR);
+ pg_flow_ctrl[15] = mt76_rr(dev, WF_PSE_TOP_PLE_PG_INFO_ADDR);
+ pg_flow_ctrl[16] = mt76_rr(dev, WF_PSE_TOP_PG_LMAC3_GROUP_ADDR);
+ pg_flow_ctrl[17] = mt76_rr(dev, WF_PSE_TOP_LMAC3_PG_INFO_ADDR);
+ pg_flow_ctrl[18] = mt76_rr(dev, WF_PSE_TOP_PG_MDP_GROUP_ADDR);
+ pg_flow_ctrl[19] = mt76_rr(dev, WF_PSE_TOP_MDP_PG_INFO_ADDR);
+ pg_flow_ctrl[20] = mt76_rr(dev, WF_PSE_TOP_PG_PLE1_GROUP_ADDR);
+ pg_flow_ctrl[21] = mt76_rr(dev, WF_PSE_TOP_PLE1_PG_INFO_ADDR);
+
+ seq_puts(file, "PSE Configuration Info:\n");
+ seq_printf(file, "\tPacket Buffer Control: 0x%08x\n", pse_buf_ctrl);
+
+ pg_sz = (pse_buf_ctrl & WF_PSE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_MASK)
+ >> WF_PSE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_SHFT;
+ seq_printf(file, "\t\tPage Size: %d(%d bytes per page)\n",
+ pg_sz, (pg_sz == 1 ? 256 : 128));
+ seq_printf(file, "\t\tPage Offset: %d(in unit of 64KB)\n",
+ (pse_buf_ctrl & WF_PSE_TOP_PBUF_CTRL_PBUF_OFFSET_MASK)
+ >> WF_PSE_TOP_PBUF_CTRL_PBUF_OFFSET_SHFT);
+ pg_num = (pse_buf_ctrl & WF_PSE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_MASK)
+ >> WF_PSE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_SHFT;
+ seq_printf(file, "\t\tTotal page numbers: %d pages\n", pg_num);
+
+ /* Page Flow Control */
+ seq_puts(file, "PSE Page Flow Control:\n");
+ seq_printf(file, "\tFree page counter: 0x%08x\n", pg_flow_ctrl[0]);
+ fpg_cnt = (pg_flow_ctrl[0] & WF_PSE_TOP_FREEPG_CNT_FREEPG_CNT_MASK)
+ >> WF_PSE_TOP_FREEPG_CNT_FREEPG_CNT_SHFT;
+ seq_printf(file, "\t\tThe toal page number of free: 0x%03x\n", fpg_cnt);
+ ffa_cnt = (pg_flow_ctrl[0] & WF_PSE_TOP_FREEPG_CNT_FFA_CNT_MASK)
+ >> WF_PSE_TOP_FREEPG_CNT_FFA_CNT_SHFT;
+ seq_printf(file, "\t\tThe free page numbers of free for all: 0x%03x\n",
+ ffa_cnt);
+ seq_printf(file, "\tFree page head and tail: 0x%08x\n", pg_flow_ctrl[1]);
+ fpg_head = (pg_flow_ctrl[1] & WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK)
+ >> WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_SHFT;
+ fpg_tail = (pg_flow_ctrl[1] & WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK)
+ >> WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_SHFT;
+ seq_printf(file, "\t\tThe tail/head page of free page list: 0x%03x/0x%03x\n",
+ fpg_tail, fpg_head);
+
+#define MT7915_MMQ(idx, type, text) \
+ do { \
+ int i2 = (idx); \
+ \
+ min_q = (pg_flow_ctrl[i2] & type##_MIN_QUOTA_MASK) \
+ >> type##_MIN_QUOTA_SHFT; \
+ max_q = (pg_flow_ctrl[i2] & type##_MAX_QUOTA_MASK) \
+ >> type##_MAX_QUOTA_SHFT; \
+ seq_printf(file, "\t\t%s: %d/%d\n", \
+ text, max_q, min_q); \
+ } while (false)
+
+#define MT7915_RSQ(idx, type, text) \
+ do { \
+ int i3 = (idx); \
+ \
+ rsv_pg = (pg_flow_ctrl[i3] & type##_RSV_CNT_MASK) \
+ >> type##_RSV_CNT_SHFT; \
+ used_pg = (pg_flow_ctrl[i3] & type##_SRC_CNT_MASK) \
+ >> type##_SRC_CNT_SHFT; \
+ seq_printf(file, "\t\t%s: %d/%d\n", \
+ text, used_pg, rsv_pg); \
+ } while (false)
+
+#define MT7915_MMQ_RSQ(idx, type) \
+ do { \
+ int i4 = (idx); \
+ \
+ seq_printf(file, "\tReserved page counter of " \
+ #type " group: 0x%08x\n", \
+ pg_flow_ctrl[i4]); \
+ seq_printf(file, "\t" #type " group page status: 0x%08x\n", \
+ pg_flow_ctrl[i4 + 1]); \
+ MT7915_MMQ(i4, WF_PSE_TOP_PG_##type##_GROUP_##type, \
+ "The max/min quota pages of " #type " group"); \
+ MT7915_RSQ(i4 + 1, WF_PSE_TOP_##type##_PG_INFO_##type, \
+ "The used/reserved pages of " #type " group"); \
+ } while (false)
+
+ MT7915_MMQ_RSQ(2, HIF0);
+ MT7915_MMQ_RSQ(4, HIF1);
+ MT7915_MMQ_RSQ(6, CPU);
+ MT7915_MMQ_RSQ(8, LMAC0);
+ MT7915_MMQ_RSQ(10, LMAC1);
+ MT7915_MMQ_RSQ(12, LMAC2);
+ MT7915_MMQ_RSQ(16, LMAC3);
+ MT7915_MMQ_RSQ(14, PLE);
+ MT7915_MMQ_RSQ(20, PLE1);
+ MT7915_MMQ_RSQ(18, MDP);
+
/* Queue Empty Status */
seq_puts(file, "PSE Queue Empty Status:\n");
seq_printf(file, "\tQUEUE_EMPTY: 0x%08x\n", pse_stat);
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/regs.h b/drivers/net/wireless/mediatek/mt76/mt7915/regs.h
index 1e3ce90ff3dd..0bd911075aa9 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/regs.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/regs.h
@@ -634,13 +634,257 @@ enum _ENUM_UMAC_PLE_CTRL_P3_QUEUE {
#define WF_PSE_TOP_BASE 0x820C8000
+#define WF_PSE_TOP_GC_ADDR (WF_PSE_TOP_BASE + 0x00) /* 8000 */
+#define WF_PSE_TOP_PBUF_CTRL_ADDR (WF_PSE_TOP_BASE + 0x14) /* 8014 */
+#define WF_PSE_TOP_INT_N9_EN_MASK_ADDR (WF_PSE_TOP_BASE + 0x20) /* 8020 */
+#define WF_PSE_TOP_INT_N9_STS_ADDR (WF_PSE_TOP_BASE + 0x24) /* 8024 */
+#define WF_PSE_TOP_INT_N9_ERR_STS_ADDR (WF_PSE_TOP_BASE + 0x28) /* 8028 */
+#define WF_PSE_TOP_INT_N9_ERR_MASK_ADDR (WF_PSE_TOP_BASE + 0x2C) /* 802C */
+#define WF_PSE_TOP_INT_N9_ERR1_STS_ADDR (WF_PSE_TOP_BASE + 0x30) /* 8030 */
+#define WF_PSE_TOP_INT_N9_ERR1_MASK_ADDR (WF_PSE_TOP_BASE + 0x34) /* 8034 */
+#define WF_PSE_TOP_C_GET_FID_0_ADDR (WF_PSE_TOP_BASE + 0x40) /* 8040 */
+#define WF_PSE_TOP_C_GET_FID_1_ADDR (WF_PSE_TOP_BASE + 0x44) /* 8044 */
+#define WF_PSE_TOP_C_EN_QUEUE_0_ADDR (WF_PSE_TOP_BASE + 0x60) /* 8060 */
+#define WF_PSE_TOP_C_EN_QUEUE_1_ADDR (WF_PSE_TOP_BASE + 0x64) /* 8064 */
+#define WF_PSE_TOP_C_EN_QUEUE_2_ADDR (WF_PSE_TOP_BASE + 0x68) /* 8068 */
+#define WF_PSE_TOP_C_DE_QUEUE_0_ADDR (WF_PSE_TOP_BASE + 0x80) /* 8080 */
+#define WF_PSE_TOP_C_DE_QUEUE_1_ADDR (WF_PSE_TOP_BASE + 0x84) /* 8084 */
+#define WF_PSE_TOP_C_DE_QUEUE_2_ADDR (WF_PSE_TOP_BASE + 0x88) /* 8088 */
+#define WF_PSE_TOP_C_DE_QUEUE_3_ADDR (WF_PSE_TOP_BASE + 0x8c) /* 808C */
+#define WF_PSE_TOP_C_DE_QUEUE_4_ADDR (WF_PSE_TOP_BASE + 0x90) /* 8090 */
+#define WF_PSE_TOP_ALLOCATE_0_ADDR (WF_PSE_TOP_BASE + 0xA0) /* 80A0 */
+#define WF_PSE_TOP_ALLOCATE_1_ADDR (WF_PSE_TOP_BASE + 0xA4) /* 80A4 */
#define WF_PSE_TOP_QUEUE_EMPTY_ADDR (WF_PSE_TOP_BASE + 0xB0) /* 80B0 */
#define WF_PSE_TOP_QUEUE_EMPTY_MASK_ADDR (WF_PSE_TOP_BASE + 0xB4) /* 80B4 */
-
+#define WF_PSE_TOP_FREEPG_START_END_ADDR (WF_PSE_TOP_BASE + 0xC0) /* 80C0 */
+#define WF_PSE_TOP_PSE_MODULE_CKG_DIS_ADDR (WF_PSE_TOP_BASE + 0xc4) /* 80C4 */
+#define WF_PSE_TOP_TO_N9_INT_ADDR (WF_PSE_TOP_BASE + 0xf0) /* 80F0 */
+#define WF_PSE_TOP_FREEPG_CNT_ADDR (WF_PSE_TOP_BASE + 0x100) /* 8100 */
+#define WF_PSE_TOP_FREEPG_HEAD_TAIL_ADDR (WF_PSE_TOP_BASE + 0x104) /* 8104 */
+#define WF_PSE_TOP_GROUP_REFILL_CTRL_ADDR (WF_PSE_TOP_BASE + 0x108) /* 8108 */
+#define WF_PSE_TOP_PG_HIF0_GROUP_ADDR (WF_PSE_TOP_BASE + 0x110) /* 8110 */
+#define WF_PSE_TOP_HIF0_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x114) /* 8114 */
+#define WF_PSE_TOP_PG_HIF1_GROUP_ADDR (WF_PSE_TOP_BASE + 0x118) /* 8118 */
+#define WF_PSE_TOP_HIF1_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x11C) /* 811C */
+#define WF_PSE_TOP_PG_CPU_GROUP_ADDR (WF_PSE_TOP_BASE + 0x150) /* 8150 */
+#define WF_PSE_TOP_CPU_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x154) /* 8154 */
+#define WF_PSE_TOP_PG_PLE_GROUP_ADDR (WF_PSE_TOP_BASE + 0x160) /* 8160 */
+#define WF_PSE_TOP_PLE_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x164) /* 8164 */
+#define WF_PSE_TOP_PG_PLE1_GROUP_ADDR (WF_PSE_TOP_BASE + 0x168) /* 8168 */
+#define WF_PSE_TOP_PLE1_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x16C) /* 816C */
+#define WF_PSE_TOP_PG_LMAC0_GROUP_ADDR (WF_PSE_TOP_BASE + 0x170) /* 8170 */
+#define WF_PSE_TOP_LMAC0_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x174) /* 8174 */
+#define WF_PSE_TOP_PG_LMAC1_GROUP_ADDR (WF_PSE_TOP_BASE + 0x178) /* 8178 */
+#define WF_PSE_TOP_LMAC1_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x17C) /* 817C */
+#define WF_PSE_TOP_PG_LMAC2_GROUP_ADDR (WF_PSE_TOP_BASE + 0x180) /* 8180 */
+#define WF_PSE_TOP_LMAC2_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x184) /* 8184 */
+#define WF_PSE_TOP_PG_LMAC3_GROUP_ADDR (WF_PSE_TOP_BASE + 0x188) /* 8188 */
+#define WF_PSE_TOP_LMAC3_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x18C) /* 818C */
+#define WF_PSE_TOP_PG_MDP_GROUP_ADDR (WF_PSE_TOP_BASE + 0x198) /* 8198 */
+#define WF_PSE_TOP_MDP_PG_INFO_ADDR (WF_PSE_TOP_BASE + 0x19C) /* 819C */
+#define WF_PSE_TOP_RL_BUF_CTRL_0_ADDR (WF_PSE_TOP_BASE + 0x1A0) /* 81A0 */
+#define WF_PSE_TOP_RL_BUF_CTRL_1_ADDR (WF_PSE_TOP_BASE + 0x1A4) /* 81A4 */
#define WF_PSE_TOP_FL_QUE_CTRL_0_ADDR (WF_PSE_TOP_BASE + 0x1B0) /* 81B0 */
#define WF_PSE_TOP_FL_QUE_CTRL_1_ADDR (WF_PSE_TOP_BASE + 0x1B4) /* 81B4 */
#define WF_PSE_TOP_FL_QUE_CTRL_2_ADDR (WF_PSE_TOP_BASE + 0x1B8) /* 81B8 */
#define WF_PSE_TOP_FL_QUE_CTRL_3_ADDR (WF_PSE_TOP_BASE + 0x1BC) /* 81BC */
+#define WF_PSE_TOP_PL_QUE_CTRL_0_ADDR (WF_PSE_TOP_BASE + 0x1C0) /* 81C0 */
+#define WF_PSE_TOP_PSE_LP_CTRL_ADDR (WF_PSE_TOP_BASE + 0x1D0) /* 81D0 */
+#define WF_PSE_TOP_PSE_WFDMA_BUF_CTRL_ADDR (WF_PSE_TOP_BASE + 0x1E0) /* 81E0 */
+#define WF_PSE_TOP_PSE_CT_PRI_CTRL_ADDR (WF_PSE_TOP_BASE + 0x1EC) /* 81EC */
+#define WF_PSE_TOP_PLE_ENQ_PKT_NUM_ADDR (WF_PSE_TOP_BASE + 0x1F0) /* 81F0 */
+#define WF_PSE_TOP_CPU_ENQ_PKT_NUM_ADDR (WF_PSE_TOP_BASE + 0x1F4) /* 81F4 */
+#define WF_PSE_TOP_LMAC_ENQ_PKT_NUM_ADDR (WF_PSE_TOP_BASE + 0x1F8) /* 81F8 */
+#define WF_PSE_TOP_HIF_ENQ_PKT_NUM_ADDR (WF_PSE_TOP_BASE + 0x1FC) /* 81FC */
+#define WF_PSE_TOP_MDP_ENQ_PKT_NUM_ADDR (WF_PSE_TOP_BASE + 0x200) /* 8200 */
+#define WF_PSE_TOP_TIMEOUT_CTRL_ADDR (WF_PSE_TOP_BASE + 0x244) /* 8244 */
+#define WF_PSE_TOP_FSM_IDLE_WD_CTRL_ADDR (WF_PSE_TOP_BASE + 0x24C) /* 824C */
+#define WF_PSE_TOP_FSM_IDLE_WD_EN_ADDR (WF_PSE_TOP_BASE + 0x250) /* 8250 */
+#define WF_PSE_TOP_PSE_INTER_ERR_FLAG_ADDR (WF_PSE_TOP_BASE + 0x280) /* 8280 */
+#define WF_PSE_TOP_PSE_SER_CTRL_ADDR (WF_PSE_TOP_BASE + 0x2a0) /* 82A0 */
+#define WF_PSE_TOP_PSE_MBIST_RP_FUSE_ADDR (WF_PSE_TOP_BASE + 0x2b0) /* 82B0 */
+#define WF_PSE_TOP_PSE_MBIST_BSEL_ADDR (WF_PSE_TOP_BASE + 0x2b4) /* 82B4 */
+#define WF_PSE_TOP_SRAM_MBIST_BACKGROUND_ADDR (WF_PSE_TOP_BASE + 0x2d0) /* 82D0 */
+#define WF_PSE_TOP_PSE_MISC_FUNC_CTRL_ADDR (WF_PSE_TOP_BASE + 0x2d4) /* 82D4 */
+#define WF_PSE_TOP_SRAM_MBIST_DONE_ADDR (WF_PSE_TOP_BASE + 0x2d8) /* 82D8 */
+#define WF_PSE_TOP_SRAM_MBIST_FAIL_ADDR (WF_PSE_TOP_BASE + 0x2dc) /* 82DC */
+#define WF_PSE_TOP_SRAM_MBIST_CTRL_ADDR (WF_PSE_TOP_BASE + 0x2e0) /* 82E0 */
+#define WF_PSE_TOP_SRAM_MBIST_DELSEL_ADDR (WF_PSE_TOP_BASE + 0x2e4) /* 82E4 */
+#define WF_PSE_TOP_SRAM_AWT_HDEN_CTRL_ADDR (WF_PSE_TOP_BASE + 0x2e8) /* 82E8 */
+#define WF_PSE_TOP_PSE_SEEK_CR_00_ADDR (WF_PSE_TOP_BASE + 0x3d0) /* 83D0 */
+#define WF_PSE_TOP_PSE_SEEK_CR_01_ADDR (WF_PSE_TOP_BASE + 0x3d4) /* 83D4 */
+#define WF_PSE_TOP_PSE_SEEK_CR_02_ADDR (WF_PSE_TOP_BASE + 0x3d8) /* 83D8 */
+#define WF_PSE_TOP_PSE_SEEK_CR_03_ADDR (WF_PSE_TOP_BASE + 0x3dc) /* 83DC */
+#define WF_PSE_TOP_PSE_SEEK_CR_04_ADDR (WF_PSE_TOP_BASE + 0x3e0) /* 83E0 */
+#define WF_PSE_TOP_PSE_SEEK_CR_05_ADDR (WF_PSE_TOP_BASE + 0x3e4) /* 83E4 */
+#define WF_PSE_TOP_PSE_SEEK_CR_06_ADDR (WF_PSE_TOP_BASE + 0x3e8) /* 83E8 */
+#define WF_PSE_TOP_PSE_SEEK_CR_07_ADDR (WF_PSE_TOP_BASE + 0x3ec) /* 83EC */
+#define WF_PSE_TOP_PSE_SEEK_CR_08_ADDR (WF_PSE_TOP_BASE + 0x3f0) /* 83F0 */
+#define WF_PSE_TOP_PSE_SEEK_CR_09_ADDR (WF_PSE_TOP_BASE + 0x3f4) /* 83F4 */
+
+#define WF_PSE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_ADDR WF_PSE_TOP_PBUF_CTRL_ADDR
+#define WF_PSE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_MASK 0x80000000 /* PAGE_SIZE_CFG[31] */
+#define WF_PSE_TOP_PBUF_CTRL_PAGE_SIZE_CFG_SHFT 31
+#define WF_PSE_TOP_PBUF_CTRL_PBUF_OFFSET_ADDR WF_PSE_TOP_PBUF_CTRL_ADDR
+#define WF_PSE_TOP_PBUF_CTRL_PBUF_OFFSET_MASK 0x03FE0000 /* PBUF_OFFSET[25..17] */
+#define WF_PSE_TOP_PBUF_CTRL_PBUF_OFFSET_SHFT 17
+#define WF_PSE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_ADDR WF_PSE_TOP_PBUF_CTRL_ADDR
+#define WF_PSE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_MASK 0x00000FFF /* TOTAL_PAGE_NUM[11..0] */
+#define WF_PSE_TOP_PBUF_CTRL_TOTAL_PAGE_NUM_SHFT 0
+
+#define WF_PSE_TOP_FREEPG_CNT_FFA_CNT_ADDR WF_PSE_TOP_FREEPG_CNT_ADDR
+#define WF_PSE_TOP_FREEPG_CNT_FFA_CNT_MASK 0x0FFF0000 /* FFA_CNT[27..16] */
+#define WF_PSE_TOP_FREEPG_CNT_FFA_CNT_SHFT 16
+#define WF_PSE_TOP_FREEPG_CNT_FREEPG_CNT_ADDR WF_PSE_TOP_FREEPG_CNT_ADDR
+#define WF_PSE_TOP_FREEPG_CNT_FREEPG_CNT_MASK 0x00000FFF /* FREEPG_CNT[11..0] */
+#define WF_PSE_TOP_FREEPG_CNT_FREEPG_CNT_SHFT 0
+
+#define WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_ADDR WF_PSE_TOP_FREEPG_HEAD_TAIL_ADDR
+#define WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_MASK 0x0FFF0000 /* FREEPG_TAIL[27..16] */
+#define WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_TAIL_SHFT 16
+#define WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_ADDR WF_PSE_TOP_FREEPG_HEAD_TAIL_ADDR
+#define WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_MASK 0x00000FFF /* FREEPG_HEAD[11..0] */
+#define WF_PSE_TOP_FREEPG_HEAD_TAIL_FREEPG_HEAD_SHFT 0
+
+#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MAX_QUOTA_ADDR WF_PSE_TOP_PG_HIF0_GROUP_ADDR
+#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MAX_QUOTA_MASK 0x0FFF0000 /* HIF0_MAX_QUOTA[27..16] */
+#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MAX_QUOTA_SHFT 16
+#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MIN_QUOTA_ADDR WF_PSE_TOP_PG_HIF0_GROUP_ADDR
+#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MIN_QUOTA_MASK 0x00000FFF /* HIF0_MIN_QUOTA[11..0] */
+#define WF_PSE_TOP_PG_HIF0_GROUP_HIF0_MIN_QUOTA_SHFT 0
+
+#define WF_PSE_TOP_HIF0_PG_INFO_HIF0_SRC_CNT_ADDR WF_PSE_TOP_HIF0_PG_INFO_ADDR
+#define WF_PSE_TOP_HIF0_PG_INFO_HIF0_SRC_CNT_MASK 0x0FFF0000 /* HIF0_SRC_CNT[27..16] */
+#define WF_PSE_TOP_HIF0_PG_INFO_HIF0_SRC_CNT_SHFT 16
+#define WF_PSE_TOP_HIF0_PG_INFO_HIF0_RSV_CNT_ADDR WF_PSE_TOP_HIF0_PG_INFO_ADDR
+#define WF_PSE_TOP_HIF0_PG_INFO_HIF0_RSV_CNT_MASK 0x00000FFF /* HIF0_RSV_CNT[11..0] */
+#define WF_PSE_TOP_HIF0_PG_INFO_HIF0_RSV_CNT_SHFT 0
+
+#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MAX_QUOTA_ADDR WF_PSE_TOP_PG_HIF1_GROUP_ADDR
+#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MAX_QUOTA_MASK 0x0FFF0000 /* HIF1_MAX_QUOTA[27..16] */
+#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MAX_QUOTA_SHFT 16
+#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MIN_QUOTA_ADDR WF_PSE_TOP_PG_HIF1_GROUP_ADDR
+#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MIN_QUOTA_MASK 0x00000FFF /* HIF1_MIN_QUOTA[11..0] */
+#define WF_PSE_TOP_PG_HIF1_GROUP_HIF1_MIN_QUOTA_SHFT 0
+
+#define WF_PSE_TOP_HIF1_PG_INFO_HIF1_SRC_CNT_ADDR WF_PSE_TOP_HIF1_PG_INFO_ADDR
+#define WF_PSE_TOP_HIF1_PG_INFO_HIF1_SRC_CNT_MASK 0x0FFF0000 /* HIF1_SRC_CNT[27..16] */
+#define WF_PSE_TOP_HIF1_PG_INFO_HIF1_SRC_CNT_SHFT 16
+#define WF_PSE_TOP_HIF1_PG_INFO_HIF1_RSV_CNT_ADDR WF_PSE_TOP_HIF1_PG_INFO_ADDR
+#define WF_PSE_TOP_HIF1_PG_INFO_HIF1_RSV_CNT_MASK 0x00000FFF /* HIF1_RSV_CNT[11..0] */
+#define WF_PSE_TOP_HIF1_PG_INFO_HIF1_RSV_CNT_SHFT 0
+
+#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_ADDR WF_PSE_TOP_PG_CPU_GROUP_ADDR
+#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_MASK 0x0FFF0000 /* CPU_MAX_QUOTA[27..16] */
+#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MAX_QUOTA_SHFT 16
+#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_ADDR WF_PSE_TOP_PG_CPU_GROUP_ADDR
+#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_MASK 0x00000FFF /* CPU_MIN_QUOTA[11..0] */
+#define WF_PSE_TOP_PG_CPU_GROUP_CPU_MIN_QUOTA_SHFT 0
+
+#define WF_PSE_TOP_CPU_PG_INFO_CPU_SRC_CNT_ADDR WF_PSE_TOP_CPU_PG_INFO_ADDR
+#define WF_PSE_TOP_CPU_PG_INFO_CPU_SRC_CNT_MASK 0x0FFF0000 /* CPU_SRC_CNT[27..16] */
+#define WF_PSE_TOP_CPU_PG_INFO_CPU_SRC_CNT_SHFT 16
+#define WF_PSE_TOP_CPU_PG_INFO_CPU_RSV_CNT_ADDR WF_PSE_TOP_CPU_PG_INFO_ADDR
+#define WF_PSE_TOP_CPU_PG_INFO_CPU_RSV_CNT_MASK 0x00000FFF /* CPU_RSV_CNT[11..0] */
+#define WF_PSE_TOP_CPU_PG_INFO_CPU_RSV_CNT_SHFT 0
+
+#define WF_PSE_TOP_PG_PLE_GROUP_PLE_MAX_QUOTA_ADDR WF_PSE_TOP_PG_PLE_GROUP_ADDR
+#define WF_PSE_TOP_PG_PLE_GROUP_PLE_MAX_QUOTA_MASK 0x0FFF0000 /* PLE_MAX_QUOTA[27..16] */
+#define WF_PSE_TOP_PG_PLE_GROUP_PLE_MAX_QUOTA_SHFT 16
+#define WF_PSE_TOP_PG_PLE_GROUP_PLE_MIN_QUOTA_ADDR WF_PSE_TOP_PG_PLE_GROUP_ADDR
+#define WF_PSE_TOP_PG_PLE_GROUP_PLE_MIN_QUOTA_MASK 0x00000FFF /* PLE_MIN_QUOTA[11..0] */
+#define WF_PSE_TOP_PG_PLE_GROUP_PLE_MIN_QUOTA_SHFT 0
+
+#define WF_PSE_TOP_PLE_PG_INFO_PLE_SRC_CNT_ADDR WF_PSE_TOP_PLE_PG_INFO_ADDR
+#define WF_PSE_TOP_PLE_PG_INFO_PLE_SRC_CNT_MASK 0x0FFF0000 /* PLE_SRC_CNT[27..16] */
+#define WF_PSE_TOP_PLE_PG_INFO_PLE_SRC_CNT_SHFT 16
+#define WF_PSE_TOP_PLE_PG_INFO_PLE_RSV_CNT_ADDR WF_PSE_TOP_PLE_PG_INFO_ADDR
+#define WF_PSE_TOP_PLE_PG_INFO_PLE_RSV_CNT_MASK 0x00000FFF /* PLE_RSV_CNT[11..0] */
+#define WF_PSE_TOP_PLE_PG_INFO_PLE_RSV_CNT_SHFT 0
+
+#define WF_PSE_TOP_PG_PLE1_GROUP_PLE1_MAX_QUOTA_ADDR WF_PSE_TOP_PG_PLE1_GROUP_ADDR
+#define WF_PSE_TOP_PG_PLE1_GROUP_PLE1_MAX_QUOTA_MASK 0x0FFF0000 /* PLE_MAX_QUOTA[27..16] */
+#define WF_PSE_TOP_PG_PLE1_GROUP_PLE1_MAX_QUOTA_SHFT 16
+#define WF_PSE_TOP_PG_PLE1_GROUP_PLE1_MIN_QUOTA_ADDR WF_PSE_TOP_PG_PLE1_GROUP_ADDR
+#define WF_PSE_TOP_PG_PLE1_GROUP_PLE1_MIN_QUOTA_MASK 0x00000FFF /* PLE_MIN_QUOTA[11..0] */
+#define WF_PSE_TOP_PG_PLE1_GROUP_PLE1_MIN_QUOTA_SHFT 0
+
+#define WF_PSE_TOP_PLE1_PG_INFO_PLE1_SRC_CNT_ADDR WF_PSE_TOP_PLE1_PG_INFO_ADDR
+#define WF_PSE_TOP_PLE1_PG_INFO_PLE1_SRC_CNT_MASK 0x0FFF0000 /* PLE_SRC_CNT[27..16] */
+#define WF_PSE_TOP_PLE1_PG_INFO_PLE1_SRC_CNT_SHFT 16
+#define WF_PSE_TOP_PLE1_PG_INFO_PLE1_RSV_CNT_ADDR WF_PSE_TOP_PLE1_PG_INFO_ADDR
+#define WF_PSE_TOP_PLE1_PG_INFO_PLE1_RSV_CNT_MASK 0x00000FFF /* PLE_RSV_CNT[11..0] */
+#define WF_PSE_TOP_PLE1_PG_INFO_PLE1_RSV_CNT_SHFT 0
+
+#define WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_ADDR WF_PSE_TOP_PG_LMAC0_GROUP_ADDR
+#define WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_MASK 0x0FFF0000 /* LMAC0_MAX_QUOTA[27..16] */
+#define WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MAX_QUOTA_SHFT 16
+#define WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_ADDR WF_PSE_TOP_PG_LMAC0_GROUP_ADDR
+#define WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_MASK 0x00000FFF /* LMAC0_MIN_QUOTA[11..0] */
+#define WF_PSE_TOP_PG_LMAC0_GROUP_LMAC0_MIN_QUOTA_SHFT 0
+
+#define WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_SRC_CNT_ADDR WF_PSE_TOP_LMAC0_PG_INFO_ADDR
+#define WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_SRC_CNT_MASK 0x0FFF0000 /* LMAC0_SRC_CNT[27..16] */
+#define WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_SRC_CNT_SHFT 16
+#define WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_RSV_CNT_ADDR WF_PSE_TOP_LMAC0_PG_INFO_ADDR
+#define WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_RSV_CNT_MASK 0x00000FFF /* LMAC0_RSV_CNT[11..0] */
+#define WF_PSE_TOP_LMAC0_PG_INFO_LMAC0_RSV_CNT_SHFT 0
+
+#define WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_ADDR WF_PSE_TOP_PG_LMAC1_GROUP_ADDR
+#define WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_MASK 0x0FFF0000 /* LMAC1_MAX_QUOTA[27..16] */
+#define WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MAX_QUOTA_SHFT 16
+#define WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_ADDR WF_PSE_TOP_PG_LMAC1_GROUP_ADDR
+#define WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_MASK 0x00000FFF /* LMAC1_MIN_QUOTA[11..0] */
+#define WF_PSE_TOP_PG_LMAC1_GROUP_LMAC1_MIN_QUOTA_SHFT 0
+
+#define WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_SRC_CNT_ADDR WF_PSE_TOP_LMAC1_PG_INFO_ADDR
+#define WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_SRC_CNT_MASK 0x0FFF0000 /* LMAC1_SRC_CNT[27..16] */
+#define WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_SRC_CNT_SHFT 16
+#define WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_RSV_CNT_ADDR WF_PSE_TOP_LMAC1_PG_INFO_ADDR
+#define WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_RSV_CNT_MASK 0x00000FFF /* LMAC1_RSV_CNT[11..0] */
+#define WF_PSE_TOP_LMAC1_PG_INFO_LMAC1_RSV_CNT_SHFT 0
+
+#define WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_ADDR WF_PSE_TOP_PG_LMAC2_GROUP_ADDR
+#define WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_MASK 0x0FFF0000 /* LMAC2_MAX_QUOTA[27..16] */
+#define WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MAX_QUOTA_SHFT 16
+#define WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_ADDR WF_PSE_TOP_PG_LMAC2_GROUP_ADDR
+#define WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_MASK 0x00000FFF /* LMAC2_MIN_QUOTA[11..0] */
+#define WF_PSE_TOP_PG_LMAC2_GROUP_LMAC2_MIN_QUOTA_SHFT 0
+
+#define WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_SRC_CNT_ADDR WF_PSE_TOP_LMAC2_PG_INFO_ADDR
+#define WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_SRC_CNT_MASK 0x0FFF0000 /* LMAC2_SRC_CNT[27..16] */
+#define WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_SRC_CNT_SHFT 16
+#define WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_RSV_CNT_ADDR WF_PSE_TOP_LMAC2_PG_INFO_ADDR
+#define WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_RSV_CNT_MASK 0x00000FFF /* LMAC2_RSV_CNT[11..0] */
+#define WF_PSE_TOP_LMAC2_PG_INFO_LMAC2_RSV_CNT_SHFT 0
+
+#define WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_ADDR WF_PSE_TOP_PG_LMAC3_GROUP_ADDR
+#define WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_MASK 0x0FFF0000 /* LMAC3_MAX_QUOTA[27..16] */
+#define WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MAX_QUOTA_SHFT 16
+#define WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_ADDR WF_PSE_TOP_PG_LMAC3_GROUP_ADDR
+#define WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_MASK 0x00000FFF /* LMAC3_MIN_QUOTA[11..0] */
+#define WF_PSE_TOP_PG_LMAC3_GROUP_LMAC3_MIN_QUOTA_SHFT 0
+
+#define WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_SRC_CNT_ADDR WF_PSE_TOP_LMAC3_PG_INFO_ADDR
+#define WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_SRC_CNT_MASK 0x0FFF0000 /* LMAC3_SRC_CNT[27..16] */
+#define WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_SRC_CNT_SHFT 16
+#define WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_RSV_CNT_ADDR WF_PSE_TOP_LMAC3_PG_INFO_ADDR
+#define WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_RSV_CNT_MASK 0x00000FFF /* LMAC3_RSV_CNT[11..0] */
+#define WF_PSE_TOP_LMAC3_PG_INFO_LMAC3_RSV_CNT_SHFT 0
+
+#define WF_PSE_TOP_PG_MDP_GROUP_MDP_MAX_QUOTA_ADDR WF_PSE_TOP_PG_MDP_GROUP_ADDR
+#define WF_PSE_TOP_PG_MDP_GROUP_MDP_MAX_QUOTA_MASK 0x0FFF0000 /* MDP_MAX_QUOTA[27..16] */
+#define WF_PSE_TOP_PG_MDP_GROUP_MDP_MAX_QUOTA_SHFT 16
+#define WF_PSE_TOP_PG_MDP_GROUP_MDP_MIN_QUOTA_ADDR WF_PSE_TOP_PG_MDP_GROUP_ADDR
+#define WF_PSE_TOP_PG_MDP_GROUP_MDP_MIN_QUOTA_MASK 0x00000FFF /* MDP_MIN_QUOTA[11..0] */
+#define WF_PSE_TOP_PG_MDP_GROUP_MDP_MIN_QUOTA_SHFT 0
+
+#define WF_PSE_TOP_MDP_PG_INFO_MDP_SRC_CNT_ADDR WF_PSE_TOP_MDP_PG_INFO_ADDR
+#define WF_PSE_TOP_MDP_PG_INFO_MDP_SRC_CNT_MASK 0x0FFF0000 /* MDP_SRC_CNT[27..16] */
+#define WF_PSE_TOP_MDP_PG_INFO_MDP_SRC_CNT_SHFT 16
+#define WF_PSE_TOP_MDP_PG_INFO_MDP_RSV_CNT_ADDR WF_PSE_TOP_MDP_PG_INFO_ADDR
+#define WF_PSE_TOP_MDP_PG_INFO_MDP_RSV_CNT_MASK 0x00000FFF /* MDP_RSV_CNT[11..0] */
+#define WF_PSE_TOP_MDP_PG_INFO_MDP_RSV_CNT_SHFT 0
#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_6_EMPTY_MASK_ADDR WF_PSE_TOP_QUEUE_EMPTY_MASK_ADDR
#define WF_PSE_TOP_QUEUE_EMPTY_MASK_HIF_6_EMPTY_MASK_MASK 0x00004000 /* HIF_6_EMPTY_MASK[14] */
--
2.20.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 13/15] mt76: mt7915: add rx-ppdu-size-out-of-range ethtool counter
2021-08-11 21:44 [PATCH 00/15] mt7915 stats and debugging improvements greearb
` (11 preceding siblings ...)
2021-08-11 21:44 ` [PATCH 12/15] mt76: mt7915: add more pse queue data to debugfs greearb
@ 2021-08-11 21:44 ` greearb
2021-08-11 21:44 ` [PATCH 14/15] mt76: mt7915: ethtool and mib rx stats greearb
2021-08-11 21:44 ` [PATCH 15/15] mt76: mt7915: poll mib counters every 200ms greearb
14 siblings, 0 replies; 16+ messages in thread
From: greearb @ 2021-08-11 21:44 UTC (permalink / raw)
To: linux-wireless; +Cc: Ben Greear
From: Ben Greear <greearb@candelatech.com>
Support this additional MIB counter, it shares register with
the rx-fifo-overflow counter.
Signed-off-by: Ben Greear <greearb@candelatech.com>
---
drivers/net/wireless/mediatek/mt76/mt7915/mac.c | 1 +
drivers/net/wireless/mediatek/mt76/mt7915/main.c | 4 +++-
drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h | 1 +
drivers/net/wireless/mediatek/mt76/mt7915/regs.h | 1 +
4 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
index 9883d1e55f5b..44c76f7480f5 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
@@ -2146,6 +2146,7 @@ mt7915_mac_update_stats(struct mt7915_phy *phy)
cnt = mt76_rr(dev, MT_MIB_SDR4(ext_phy));
mib->rx_fifo_full_cnt += FIELD_GET(MT_MIB_SDR4_RX_FIFO_FULL_MASK, cnt);
+ mib->rx_oor_cnt += FIELD_GET(MT_MIB_SDR4_RX_OOR_MASK, cnt);
cnt = mt76_rr(dev, MT_MIB_SDR5(ext_phy));
mib->rx_mpdu_cnt += cnt;
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/main.c b/drivers/net/wireless/mediatek/mt76/mt7915/main.c
index 4f609a5d38a4..fa9e3fd9bb4b 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/main.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/main.c
@@ -1084,6 +1084,7 @@ static const char mt7915_gstrings_stats[][ETH_GSTRING_LEN] = {
/* rx counters */
"rx_fifo_full_cnt",
+ "rx_oor_cnt", /* rx ppdu length is bad */
"rx_mpdu_cnt",
"channel_idle_cnt",
"rx_vector_mismatch_cnt",
@@ -1322,7 +1323,8 @@ void mt7915_get_et_stats(struct ieee80211_hw *hw,
data[ei++] = mib->tx_amsdu_pack_stats[i];
/* rx counters */
- data[ei++] = mib->rx_fifo_full_cnt;
+ data[ei++] = mib->rx_fifo_full_cnt; /* group-5 might exacerbate this */
+ data[ei++] = mib->rx_oor_cnt;
data[ei++] = mib->rx_mpdu_cnt;
data[ei++] = mib->channel_idle_cnt;
data[ei++] = mib->rx_vector_mismatch_cnt;
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h b/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
index 1a0d7d62c582..4515d42e5f74 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
@@ -168,6 +168,7 @@ struct mib_stats {
/* rx stats */
u32 rx_fifo_full_cnt;
+ u32 rx_oor_cnt;
u32 channel_idle_cnt;
u32 rx_vector_mismatch_cnt;
u32 rx_delimiter_fail_cnt;
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/regs.h b/drivers/net/wireless/mediatek/mt76/mt7915/regs.h
index 0bd911075aa9..6898cbe34470 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/regs.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/regs.h
@@ -149,6 +149,7 @@
#define MT_MIB_SDR4(_band) MT_WF_MIB(_band, 0x018)
#define MT_MIB_SDR4_RX_FIFO_FULL_MASK GENMASK(15, 0)
+#define MT_MIB_SDR4_RX_OOR_MASK GENMASK(23, 16)
/* rx mpdu counter, full 32 bits */
#define MT_MIB_SDR5(_band) MT_WF_MIB(_band, 0x01c)
--
2.20.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 14/15] mt76: mt7915: ethtool and mib rx stats
2021-08-11 21:44 [PATCH 00/15] mt7915 stats and debugging improvements greearb
` (12 preceding siblings ...)
2021-08-11 21:44 ` [PATCH 13/15] mt76: mt7915: add rx-ppdu-size-out-of-range ethtool counter greearb
@ 2021-08-11 21:44 ` greearb
2021-08-11 21:44 ` [PATCH 15/15] mt76: mt7915: poll mib counters every 200ms greearb
14 siblings, 0 replies; 16+ messages in thread
From: greearb @ 2021-08-11 21:44 UTC (permalink / raw)
To: linux-wireless; +Cc: Ben Greear
From: Ben Greear <greearb@candelatech.com>
Add some new stats read from MIB registers, including
rx-mu-vht histogram data.
Signed-off-by: Ben Greear <greearb@candelatech.com>
---
.../net/wireless/mediatek/mt76/mt7915/mac.c | 45 ++++++++++-
.../net/wireless/mediatek/mt76/mt7915/main.c | 77 ++++++++++++++++++-
.../wireless/mediatek/mt76/mt7915/mt7915.h | 12 +++
.../net/wireless/mediatek/mt76/mt7915/regs.h | 47 +++++++++++
4 files changed, 179 insertions(+), 2 deletions(-)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
index 44c76f7480f5..ba1c71bee149 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
@@ -2139,7 +2139,7 @@ mt7915_mac_update_stats(struct mt7915_phy *phy)
struct mt7915_dev *dev = phy->dev;
struct mib_stats *mib = &phy->mib;
bool ext_phy = phy != &dev->phy;
- int i, aggr0, aggr1, cnt;
+ int i, q, aggr0, aggr1, cnt;
mib->fcs_err_cnt += mt76_get_field(dev, MT_MIB_SDR3(ext_phy),
MT_MIB_SDR3_FCS_ERR_MASK);
@@ -2212,6 +2212,26 @@ mt7915_mac_update_stats(struct mt7915_phy *phy)
cnt = mt76_rr(dev, MT_MIB_SDR34(ext_phy));
mib->tx_bf_cnt += FIELD_GET(MT_MIB_MU_BF_TX_CNT, cnt);
+ cnt = mt76_rr(dev, MT_MIB_SDR38(ext_phy));
+ mib->tx_mgt_frame_cnt += FIELD_GET(MT_MIB_CTRL_TX_CNT, cnt);
+
+ cnt = mt76_rr(dev, MT_MIB_SDR39(ext_phy));
+ mib->tx_mgt_frame_retry_cnt += FIELD_GET(MT_MIB_MGT_RETRY_CNT, cnt);
+
+ cnt = mt76_rr(dev, MT_MIB_SDR40(ext_phy));
+ mib->tx_data_frame_retry_cnt += FIELD_GET(MT_MIB_DATA_RETRY_CNT, cnt);
+
+ cnt = mt76_rr(dev, MT_MIB_SDR42(ext_phy));
+ mib->rx_partial_beacon_cnt += FIELD_GET(MT_MIB_RX_PARTIAL_BEACON_BSSID0, cnt);
+ mib->rx_partial_beacon_cnt += FIELD_GET(MT_MIB_RX_PARTIAL_BEACON_BSSID1, cnt);
+
+ cnt = mt76_rr(dev, MT_MIB_SDR43(ext_phy));
+ mib->rx_partial_beacon_cnt += FIELD_GET(MT_MIB_RX_PARTIAL_BEACON_BSSID2, cnt);
+ mib->rx_partial_beacon_cnt += FIELD_GET(MT_MIB_RX_PARTIAL_BEACON_BSSID3, cnt);
+
+ cnt = mt76_rr(dev, MT_MIB_SDR46(ext_phy));
+ mib->rx_oppo_ps_rx_dis_drop_cnt += FIELD_GET(MT_MIB_OPPO_PS_RX_DIS_DROP_COUNT, cnt);
+
cnt = mt76_rr(dev, MT_MIB_DR8(ext_phy));
mib->tx_mu_mpdu_cnt += cnt;
@@ -2267,6 +2287,29 @@ mt7915_mac_update_stats(struct mt7915_phy *phy)
for (i = 0; i < ARRAY_SIZE(mib->tx_amsdu_pack_stats); i++)
mib->tx_amsdu_pack_stats[i] += mt76_rr(dev, MT_PLE_AMSDU_PACK_MSDU_CNT(i));
+ cnt = mt76_rr(dev, MT_MIB_M0DROPSR00(ext_phy));
+ mib->tx_drop_rts_retry_fail_cnt += FIELD_GET(MT_MIB_RTS_RETRY_FAIL_DROP_MASK, cnt);
+ mib->tx_drop_mpdu_retry_fail_cnt += FIELD_GET(MT_MIB_RTS_RETRY_FAIL_DROP_MASK, cnt);
+
+ cnt = mt76_rr(dev, MT_MIB_M0DROPSR01(ext_phy));
+ mib->tx_drop_lto_limit_fail_cnt += FIELD_GET(MT_MIB_LTO_FAIL_DROP_MASK, cnt);
+
+ cnt = mt76_rr(dev, MT_MIB_SDR50(ext_phy));
+ mib->tx_dbnss_cnt += FIELD_GET(MT_MIB_DBNSS_CNT_DROP_MASK, cnt);
+
+ cnt = mt76_rr(dev, MT_MIB_SDR51(ext_phy));
+ mib->rx_fcs_ok_cnt += FIELD_GET(MT_MIB_RX_FCS_OK_MASK, cnt);
+
+ for (i = 0; i < 2; i++) {
+ for (q = 0; q < 10; q++) {
+ cnt = mt76_rr(dev, MT_MIB_VHT_RX_FCS_HISTOGRAM(ext_phy, i, q));
+ mib->rx_mu_fcs_ok_hist[i][q] +=
+ FIELD_GET(MT_MIB_VHT_RX_FCS_HIST_OK_MASK, cnt);
+ mib->rx_mu_fcs_err_hist[i][q] +=
+ FIELD_GET(MT_MIB_VHT_RX_FCS_HIST_ERR_MASK, cnt);
+ }
+ }
+
}
void mt7915_mac_sta_rc_work(struct work_struct *work)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/main.c b/drivers/net/wireless/mediatek/mt76/mt7915/main.c
index fa9e3fd9bb4b..0c49b86c5058 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/main.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/main.c
@@ -1081,6 +1081,13 @@ static const char mt7915_gstrings_stats[][ETH_GSTRING_LEN] = {
"tx_msdu_pack_6",
"tx_msdu_pack_7",
"tx_msdu_pack_8",
+ "tx_mgt_frame", /* SDR38, management frame tx counter */
+ "tx_mgt_frame_retry", /* SDR39, management frame retried counter */
+ "tx_data_frame_retry", /* SDR40, data frame retried counter */
+ "tx_drop_rts_retry_fail", /* TX Drop, RTS retries exhausted */
+ "tx_drop_mpdu_retry_fail", /* TX Drop, MPDU retries exhausted */
+ "tx_drop_lto_limit_fail", /* TX drop, Life Time Out limit reached. */
+ "tx_dbnss", /* pkts TX using double number of spatial streams */
/* rx counters */
"rx_fifo_full_cnt",
@@ -1097,6 +1104,54 @@ static const char mt7915_gstrings_stats[][ETH_GSTRING_LEN] = {
"rx_pfdrop_cnt",
"rx_vec_queue_overflow_drop_cnt",
"rx_ba_cnt",
+ "rx_partial_beacon",
+ "rx_oppo_ps_rx_dis_drop",
+ "rx_fcs_ok",
+
+ /* rx MU VHT histogram */
+ "rx_mu_fcs_ok_nss1_mcs0",
+ "rx_mu_fcs_ok_nss1_mcs1",
+ "rx_mu_fcs_ok_nss1_mcs2",
+ "rx_mu_fcs_ok_nss1_mcs3",
+ "rx_mu_fcs_ok_nss1_mcs4",
+ "rx_mu_fcs_ok_nss1_mcs5",
+ "rx_mu_fcs_ok_nss1_mcs6",
+ "rx_mu_fcs_ok_nss1_mcs7",
+ "rx_mu_fcs_ok_nss1_mcs8",
+ "rx_mu_fcs_ok_nss1_mcs9",
+
+ "rx_mu_fcs_ok_nss2_mcs0",
+ "rx_mu_fcs_ok_nss2_mcs1",
+ "rx_mu_fcs_ok_nss2_mcs2",
+ "rx_mu_fcs_ok_nss2_mcs3",
+ "rx_mu_fcs_ok_nss2_mcs4",
+ "rx_mu_fcs_ok_nss2_mcs5",
+ "rx_mu_fcs_ok_nss2_mcs6",
+ "rx_mu_fcs_ok_nss2_mcs7",
+ "rx_mu_fcs_ok_nss2_mcs8",
+ "rx_mu_fcs_ok_nss2_mcs9",
+
+ "rx_mu_fcs_err_nss1_mcs0",
+ "rx_mu_fcs_err_nss1_mcs1",
+ "rx_mu_fcs_err_nss1_mcs2",
+ "rx_mu_fcs_err_nss1_mcs3",
+ "rx_mu_fcs_err_nss1_mcs4",
+ "rx_mu_fcs_err_nss1_mcs5",
+ "rx_mu_fcs_err_nss1_mcs6",
+ "rx_mu_fcs_err_nss1_mcs7",
+ "rx_mu_fcs_err_nss1_mcs8",
+ "rx_mu_fcs_err_nss1_mcs9",
+
+ "rx_mu_fcs_err_nss2_mcs0",
+ "rx_mu_fcs_err_nss2_mcs1",
+ "rx_mu_fcs_err_nss2_mcs2",
+ "rx_mu_fcs_err_nss2_mcs3",
+ "rx_mu_fcs_err_nss2_mcs4",
+ "rx_mu_fcs_err_nss2_mcs5",
+ "rx_mu_fcs_err_nss2_mcs6",
+ "rx_mu_fcs_err_nss2_mcs7",
+ "rx_mu_fcs_err_nss2_mcs8",
+ "rx_mu_fcs_err_nss2_mcs9",
/* driver rx counters */
"d_rx_skb",
@@ -1264,7 +1319,7 @@ void mt7915_get_et_stats(struct ieee80211_hw *hw,
/* See mt7915_ampdu_stat_read_phy, etc */
bool ext_phy = phy != &dev->phy;
- int i, n;
+ int i, n, q;
int ei = 0;
if (!phy)
@@ -1322,6 +1377,14 @@ void mt7915_get_et_stats(struct ieee80211_hw *hw,
for (i = 0; i < 8; i++)
data[ei++] = mib->tx_amsdu_pack_stats[i];
+ data[ei++] = mib->tx_mgt_frame_cnt;
+ data[ei++] = mib->tx_mgt_frame_retry_cnt;
+ data[ei++] = mib->tx_data_frame_retry_cnt;
+ data[ei++] = mib->tx_drop_rts_retry_fail_cnt;
+ data[ei++] = mib->tx_drop_mpdu_retry_fail_cnt;
+ data[ei++] = mib->tx_drop_lto_limit_fail_cnt;
+ data[ei++] = mib->tx_dbnss_cnt;
+
/* rx counters */
data[ei++] = mib->rx_fifo_full_cnt; /* group-5 might exacerbate this */
data[ei++] = mib->rx_oor_cnt;
@@ -1337,6 +1400,18 @@ void mt7915_get_et_stats(struct ieee80211_hw *hw,
data[ei++] = mib->rx_pfdrop_cnt;
data[ei++] = mib->rx_vec_queue_overflow_drop_cnt;
data[ei++] = mib->rx_ba_cnt;
+ data[ei++] = mib->rx_partial_beacon_cnt;
+ data[ei++] = mib->rx_oppo_ps_rx_dis_drop_cnt;
+ data[ei++] = mib->rx_fcs_ok_cnt;
+
+ for (i = 0; i < 2; i++) { /* for each nss */
+ for (q = 0; q < 10; q++) /* for each mcs */
+ data[ei++] = mib->rx_mu_fcs_ok_hist[i][q];
+ }
+ for (i = 0; i < 2; i++) { /* for each nss */
+ for (q = 0; q < 10; q++) /* for each mcs */
+ data[ei++] = mib->rx_mu_fcs_err_hist[i][q];
+ }
/* rx stats from driver */
data[ei++] = mib->rx_d_skb;
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h b/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
index 4515d42e5f74..34c8e7a3b317 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mt7915.h
@@ -165,6 +165,13 @@ struct mib_stats {
u32 tx_rwp_fail_cnt;
u32 tx_rwp_need_cnt;
u32 tx_amsdu_pack_stats[8]; /* histogram of how many sub-frames in amsdu */
+ u32 tx_mgt_frame_cnt;
+ u32 tx_mgt_frame_retry_cnt;
+ u32 tx_data_frame_retry_cnt;
+ u32 tx_drop_rts_retry_fail_cnt;
+ u32 tx_drop_mpdu_retry_fail_cnt;
+ u32 tx_drop_lto_limit_fail_cnt;
+ u32 tx_dbnss_cnt;
/* rx stats */
u32 rx_fifo_full_cnt;
@@ -181,6 +188,11 @@ struct mib_stats {
u32 rx_pfdrop_cnt;
u32 rx_vec_queue_overflow_drop_cnt;
u32 rx_ba_cnt;
+ u32 rx_partial_beacon_cnt;
+ u32 rx_oppo_ps_rx_dis_drop_cnt;
+ u32 rx_fcs_ok_cnt;
+ u32 rx_mu_fcs_ok_hist[2][10]; /* nss, mcs */
+ u32 rx_mu_fcs_err_hist[2][10]; /* nss, mcs */
/* rx stats from the driver */
u32 rx_d_skb; /* total skb received in rx path */
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/regs.h b/drivers/net/wireless/mediatek/mt76/mt7915/regs.h
index 6898cbe34470..8c559c78860b 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/regs.h
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/regs.h
@@ -247,6 +247,29 @@
/* 36, 37 both DNR */
+#define MT_MIB_SDR38(_band) MT_WF_MIB(_band, 0x0d0)
+#define MT_MIB_CTRL_TX_CNT GENMASK(23, 0)
+
+#define MT_MIB_SDR39(_band) MT_WF_MIB(_band, 0x0d4)
+#define MT_MIB_MGT_RETRY_CNT GENMASK(23, 0)
+
+#define MT_MIB_SDR40(_band) MT_WF_MIB(_band, 0x0d8)
+#define MT_MIB_DATA_RETRY_CNT GENMASK(23, 0)
+
+#define MT_MIB_SDR42(_band) MT_WF_MIB(_band, 0x0e0)
+#define MT_MIB_RX_PARTIAL_BEACON_BSSID0 GENMASK(15, 0)
+#define MT_MIB_RX_PARTIAL_BEACON_BSSID1 GENMASK(31, 16)
+
+#define MT_MIB_SDR43(_band) MT_WF_MIB(_band, 0x0e4)
+#define MT_MIB_RX_PARTIAL_BEACON_BSSID2 GENMASK(15, 0)
+#define MT_MIB_RX_PARTIAL_BEACON_BSSID3 GENMASK(31, 16)
+
+/* This counter shall increment when PPDUs dropped by the oppo_ps_rx_dis
+ * mechanism
+ */
+#define MT_MIB_SDR46(_band) MT_WF_MIB(_band, 0x0f0)
+#define MT_MIB_OPPO_PS_RX_DIS_DROP_COUNT GENMASK(15, 0)
+
#define MT_MIB_DR8(_band) MT_WF_MIB(_band, 0x0c0)
#define MT_MIB_DR9(_band) MT_WF_MIB(_band, 0x0c4)
#define MT_MIB_DR11(_band) MT_WF_MIB(_band, 0x0cc)
@@ -264,6 +287,30 @@
#define MT_MIB_ARNG(_band, n) MT_WF_MIB(_band, 0x4b8 + ((n) << 2))
#define MT_MIB_ARNCR_RANGE(val, n) (((val) >> ((n) << 3)) & GENMASK(7, 0))
+/* drop due to retries being exhausted */
+#define MT_MIB_M0DROPSR00(_band) MT_WF_MIB(_band, 0x190)
+#define MT_MIB_RTS_RETRY_FAIL_DROP_MASK GENMASK(15, 0)
+#define MT_MIB_MPDU_RETRY_FAIL_DROP_MASK GENMASK(31, 16)
+
+/* life time out limit */
+#define MT_MIB_M0DROPSR01(_band) MT_WF_MIB(_band, 0x194)
+#define MT_MIB_LTO_FAIL_DROP_MASK GENMASK(15, 0)
+
+/* increment when using double number of spatial streams */
+#define MT_MIB_SDR50(_band) MT_WF_MIB(_band, 0x1dc)
+#define MT_MIB_DBNSS_CNT_DROP_MASK GENMASK(15, 0)
+
+/* NOTE: Would need to poll this quickly since it is 16-bit */
+#define MT_MIB_SDR51(_band) MT_WF_MIB(_band, 0x1e0)
+#define MT_MIB_RX_FCS_OK_MASK GENMASK(15, 0)
+
+/* VHT MU rx fcs ok, fcs fail. NSS: 0,1 MCS: 0..9 */
+#define MT_MIB_VHT_RX_FCS_HISTOGRAM_BASE_M0NSS1MCS0(_band) MT_WF_MIB(_band, 0x400)
+#define MT_MIB_VHT_RX_FCS_HIST_OK_MASK GENMASK(15, 0)
+#define MT_MIB_VHT_RX_FCS_HIST_ERR_MASK GENMASK(31, 16)
+#define MT_MIB_VHT_RX_FCS_HISTOGRAM(_band, nss, mcs) \
+ (MT_MIB_VHT_RX_FCS_HISTOGRAM_BASE_M0NSS1MCS0(_band) + (nss) * 4 + (mcs))
+
#define MT_WTBLON_TOP_BASE 0x34000
#define MT_WTBLON_TOP(ofs) (MT_WTBLON_TOP_BASE + (ofs))
#define MT_WTBLON_TOP_WDUCR MT_WTBLON_TOP(0x0)
--
2.20.1
^ permalink raw reply related [flat|nested] 16+ messages in thread* [PATCH 15/15] mt76: mt7915: poll mib counters every 200ms
2021-08-11 21:44 [PATCH 00/15] mt7915 stats and debugging improvements greearb
` (13 preceding siblings ...)
2021-08-11 21:44 ` [PATCH 14/15] mt76: mt7915: ethtool and mib rx stats greearb
@ 2021-08-11 21:44 ` greearb
14 siblings, 0 replies; 16+ messages in thread
From: greearb @ 2021-08-11 21:44 UTC (permalink / raw)
To: linux-wireless; +Cc: Ben Greear
From: Ben Greear <greearb@candelatech.com>
Instead of every 500ms, this will do better job of catching wraps
of 16-bit pkt counters.
Signed-off-by: Ben Greear <greearb@candelatech.com>
---
drivers/net/wireless/mediatek/mt76/mt7915/mac.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
index ba1c71bee149..77d7477f8667 100644
--- a/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
+++ b/drivers/net/wireless/mediatek/mt76/mt7915/mac.c
@@ -2362,7 +2362,11 @@ void mt7915_mac_work(struct work_struct *work)
mutex_lock(&mphy->dev->mutex);
mt76_update_survey(mphy);
- if (++mphy->mac_work_count == 5) {
+
+ /* this method is called about every 100ms. Some pkt counters are 16-bit,
+ * so poll every 200ms to keep overflows at a minimum.
+ */
+ if (++mphy->mac_work_count == 2) {
mphy->mac_work_count = 0;
mt7915_mac_update_stats(phy);
--
2.20.1
^ permalink raw reply related [flat|nested] 16+ messages in thread