* [PATCH 0/9] ath9k: add support for QCN550x
@ 2022-04-18 7:13 Wenli Looi
2022-04-18 7:13 ` [PATCH 1/9] ath9k: add QCN550x device IDs Wenli Looi
` (9 more replies)
0 siblings, 10 replies; 15+ messages in thread
From: Wenli Looi @ 2022-04-18 7:13 UTC (permalink / raw)
To: Toke Høiland-Jørgensen
Cc: Kalle Valo, linux-wireless, ath9k-devel, Wenli Looi
This patchset adds support for QCN550x. It is an attempt to write a
cleaner version of the following patch:
https://github.com/openwrt/openwrt/pull/9389
I'm definitely open to ideas on how to better implement this change.
Notes:
- While QCN5502 is a 4-stream device, ath9k only supports 3 streams, and
that is unchanged.
- The QCN550x EEPROM format is different from other AR9003 devices due
to the 4th stream. An abstraction layer has been added over the EEPROM
to support both formats.
- The QCN550x initvals here are a hacked version of the QCA956x
initvals, and have only been partially tested.
- This change has been tested on the following devices, which appear to
work as an access point:
- QCN5502: Netgear EX6400v2
- QCA9558: Netgear EX7300v1
Relevant links:
- QCN550x SoC support, which appears to be identical to QCA956x:
https://github.com/torvalds/linux/commit/a0b8cd5c223042efe764864b8dd9396ee127c763
- QSDK patch for QCN550x:
https://source.codeaurora.org/quic/qsdk/oss/system/openwrt/tree/target/linux/ar71xx/patches-3.3/9991-MIPS-ath79-add-SoC-detection-code-for-QCN550X.patch?h=aa/banana
Wenli Looi (9):
ath9k: add QCN550x device IDs
ath9k: basic support for QCN550x
ath9k: add QCN550x initvals
ath9k: implement QCN550x rx
ath9k: implement QCN550x tx
ath9k: group some ar9300 eeprom functions at the top
ath9k: add abstractions over ar9300 eeprom
ath9k: rename ar9300_eeprom to ar9300_eeprom_v1
ath9k: add ar9300_eeprom_v2
drivers/net/wireless/ath/ath9k/ahb.c | 4 +
drivers/net/wireless/ath/ath9k/ani.c | 2 +-
.../net/wireless/ath/ath9k/ar550x_initvals.h | 1296 +++++++++++++++++
drivers/net/wireless/ath/ath9k/ar9003_calib.c | 4 +-
.../net/wireless/ath/ath9k/ar9003_eeprom.c | 949 ++++++++----
.../net/wireless/ath/ath9k/ar9003_eeprom.h | 144 +-
drivers/net/wireless/ath/ath9k/ar9003_hw.c | 59 +
drivers/net/wireless/ath/ath9k/ar9003_mac.c | 79 +-
drivers/net/wireless/ath/ath9k/ar9003_mac.h | 10 +
drivers/net/wireless/ath/ath9k/ar9003_paprd.c | 4 +-
drivers/net/wireless/ath/ath9k/ar9003_phy.c | 35 +-
drivers/net/wireless/ath/ath9k/ar9003_phy.h | 83 +-
drivers/net/wireless/ath/ath9k/hw.c | 38 +-
drivers/net/wireless/ath/ath9k/hw.h | 4 +-
drivers/net/wireless/ath/ath9k/mac.c | 2 +-
drivers/net/wireless/ath/ath9k/mac.h | 12 +
drivers/net/wireless/ath/ath9k/recv.c | 2 +-
drivers/net/wireless/ath/ath9k/reg.h | 11 +-
drivers/net/wireless/ath/ath9k/reg_aic.h | 6 +-
19 files changed, 2330 insertions(+), 414 deletions(-)
create mode 100644 drivers/net/wireless/ath/ath9k/ar550x_initvals.h
--
2.25.1
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH 1/9] ath9k: add QCN550x device IDs 2022-04-18 7:13 [PATCH 0/9] ath9k: add support for QCN550x Wenli Looi @ 2022-04-18 7:13 ` Wenli Looi 2022-04-20 12:00 ` Kalle Valo 2022-04-18 7:13 ` [PATCH 2/9] ath9k: basic support for QCN550x Wenli Looi ` (8 subsequent siblings) 9 siblings, 1 reply; 15+ messages in thread From: Wenli Looi @ 2022-04-18 7:13 UTC (permalink / raw) To: Toke Høiland-Jørgensen Cc: Kalle Valo, linux-wireless, ath9k-devel, Wenli Looi Signed-off-by: Wenli Looi <wlooi@ucalgary.ca> --- drivers/net/wireless/ath/ath9k/ahb.c | 4 ++++ drivers/net/wireless/ath/ath9k/hw.c | 6 ++++++ drivers/net/wireless/ath/ath9k/hw.h | 1 + drivers/net/wireless/ath/ath9k/reg.h | 5 ++++- 4 files changed, 15 insertions(+), 1 deletion(-) diff --git a/drivers/net/wireless/ath/ath9k/ahb.c b/drivers/net/wireless/ath/ath9k/ahb.c index 9cd12b20b..1835b4469 100644 --- a/drivers/net/wireless/ath/ath9k/ahb.c +++ b/drivers/net/wireless/ath/ath9k/ahb.c @@ -47,6 +47,10 @@ static const struct platform_device_id ath9k_platform_id_table[] = { .name = "qca956x_wmac", .driver_data = AR9300_DEVID_QCA956X, }, + { + .name = "qcn550x_wmac", + .driver_data = AR9300_DEVID_QCN550X, + }, {}, }; diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c index 172081ffe..047512ce1 100644 --- a/drivers/net/wireless/ath/ath9k/hw.c +++ b/drivers/net/wireless/ath/ath9k/hw.c @@ -282,6 +282,9 @@ static bool ath9k_hw_read_revisions(struct ath_hw *ah) case AR9300_DEVID_QCA956X: ah->hw_version.macVersion = AR_SREV_VERSION_9561; return true; + case AR9300_DEVID_QCN550X: + ah->hw_version.macVersion = AR_SREV_VERSION_5502; + return true; } srev = REG_READ(ah, AR_SREV); @@ -592,6 +595,7 @@ static int __ath9k_hw_init(struct ath_hw *ah) case AR_SREV_VERSION_9565: case AR_SREV_VERSION_9531: case AR_SREV_VERSION_9561: + case AR_SREV_VERSION_5502: break; default: ath_err(common, @@ -688,6 +692,7 @@ int ath9k_hw_init(struct ath_hw *ah) case AR9300_DEVID_AR9565: case AR9300_DEVID_AR953X: case AR9300_DEVID_QCA956X: + case AR9300_DEVID_QCN550X: break; default: if (common->bus_ops->ath_bus_type == ATH_USB) @@ -3315,6 +3320,7 @@ static struct { { AR_SREV_VERSION_9565, "9565" }, { AR_SREV_VERSION_9531, "9531" }, { AR_SREV_VERSION_9561, "9561" }, + { AR_SREV_VERSION_5502, "5502" }, }; /* For devices with external radios */ diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h index 096a206f4..759a5991a 100644 --- a/drivers/net/wireless/ath/ath9k/hw.h +++ b/drivers/net/wireless/ath/ath9k/hw.h @@ -56,6 +56,7 @@ #define AR9300_DEVID_AR9565 0x0036 #define AR9300_DEVID_AR953X 0x003d #define AR9300_DEVID_QCA956X 0x003f +#define AR9300_DEVID_QCN550X 0x0040 #define AR5416_AR9100_DEVID 0x000b diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h index 8983ea6fc..5a07cf7d8 100644 --- a/drivers/net/wireless/ath/ath9k/reg.h +++ b/drivers/net/wireless/ath/ath9k/reg.h @@ -825,6 +825,7 @@ #define AR_SREV_REVISION_9531_11 1 #define AR_SREV_REVISION_9531_20 2 #define AR_SREV_VERSION_9561 0x600 +#define AR_SREV_VERSION_5502 0x700 #define AR_SREV_5416(_ah) \ (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \ @@ -992,10 +993,12 @@ #define AR_SREV_9561(_ah) \ (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9561)) +#define AR_SREV_5502(_ah) \ + (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5502)) #define AR_SREV_SOC(_ah) \ (AR_SREV_9340(_ah) || AR_SREV_9531(_ah) || AR_SREV_9550(_ah) || \ - AR_SREV_9561(_ah)) + AR_SREV_9561(_ah) || AR_SREV_5502(_ah)) /* NOTE: When adding chips newer than Peacock, add chip check here */ #define AR_SREV_9580_10_OR_LATER(_ah) \ -- 2.25.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 1/9] ath9k: add QCN550x device IDs 2022-04-18 7:13 ` [PATCH 1/9] ath9k: add QCN550x device IDs Wenli Looi @ 2022-04-20 12:00 ` Kalle Valo 0 siblings, 0 replies; 15+ messages in thread From: Kalle Valo @ 2022-04-20 12:00 UTC (permalink / raw) To: Wenli Looi; +Cc: Toke Høiland-Jørgensen, linux-wireless, ath9k-devel Wenli Looi <wlooi@ucalgary.ca> writes: > Signed-off-by: Wenli Looi <wlooi@ucalgary.ca> No empty commit logs, please. -- https://patchwork.kernel.org/project/linux-wireless/list/ https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 2/9] ath9k: basic support for QCN550x 2022-04-18 7:13 [PATCH 0/9] ath9k: add support for QCN550x Wenli Looi 2022-04-18 7:13 ` [PATCH 1/9] ath9k: add QCN550x device IDs Wenli Looi @ 2022-04-18 7:13 ` Wenli Looi 2022-04-20 12:01 ` Kalle Valo 2022-04-18 7:13 ` [PATCH 3/9] ath9k: add QCN550x initvals Wenli Looi ` (7 subsequent siblings) 9 siblings, 1 reply; 15+ messages in thread From: Wenli Looi @ 2022-04-18 7:13 UTC (permalink / raw) To: Toke Høiland-Jørgensen Cc: Kalle Valo, linux-wireless, ath9k-devel, Wenli Looi QCN550x is very similar to QCA956x. Note that AR_CH0_XTAL is intentionally unchanged. Certain arrays are no longer static because they are no longer constant. --- drivers/net/wireless/ath/ath9k/ani.c | 2 +- drivers/net/wireless/ath/ath9k/ar9003_calib.c | 4 +- .../net/wireless/ath/ath9k/ar9003_eeprom.c | 17 ++-- drivers/net/wireless/ath/ath9k/ar9003_paprd.c | 4 +- drivers/net/wireless/ath/ath9k/ar9003_phy.c | 35 ++++---- drivers/net/wireless/ath/ath9k/ar9003_phy.h | 83 ++++++++++++------- drivers/net/wireless/ath/ath9k/hw.c | 28 ++++--- drivers/net/wireless/ath/ath9k/mac.c | 2 +- drivers/net/wireless/ath/ath9k/recv.c | 2 +- drivers/net/wireless/ath/ath9k/reg.h | 4 +- drivers/net/wireless/ath/ath9k/reg_aic.h | 6 +- 11 files changed, 112 insertions(+), 75 deletions(-) diff --git a/drivers/net/wireless/ath/ath9k/ani.c b/drivers/net/wireless/ath/ath9k/ani.c index 41d192709..281103865 100644 --- a/drivers/net/wireless/ath/ath9k/ani.c +++ b/drivers/net/wireless/ath/ath9k/ani.c @@ -261,7 +261,7 @@ static void ath9k_hw_set_cck_nil(struct ath_hw *ah, u_int8_t immunityLevel, /* Skip MRC CCK for pre AR9003 families */ if (!AR_SREV_9300_20_OR_LATER(ah) || AR_SREV_9485(ah) || - AR_SREV_9565(ah) || AR_SREV_9561(ah)) + AR_SREV_9565(ah) || AR_SREV_9561(ah) || AR_SREV_5502(ah)) return; if (aniState->mrcCCK != entry_cck->mrc_cck_on) diff --git a/drivers/net/wireless/ath/ath9k/ar9003_calib.c b/drivers/net/wireless/ath/ath9k/ar9003_calib.c index 6ca089f15..e2cf4b733 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_calib.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c @@ -201,7 +201,7 @@ static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) u32 qCoffDenom, iCoffDenom; int32_t qCoff, iCoff; int iqCorrNeg, i; - static const u_int32_t offset_array[3] = { + const u_int32_t offset_array[3] = { AR_PHY_RX_IQCAL_CORR_B0, AR_PHY_RX_IQCAL_CORR_B1, AR_PHY_RX_IQCAL_CORR_B2, @@ -1202,7 +1202,7 @@ static void ar9003_hw_manual_peak_cal(struct ath_hw *ah, u8 chain, bool is_2g) if (AR_SREV_9550(ah) || AR_SREV_9531(ah)) peak_detect_threshold = 8; - else if (AR_SREV_9561(ah)) + else if (AR_SREV_9561(ah) || AR_SREV_5502(ah)) peak_detect_threshold = 11; /* diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c index 16bfcd0a1..49be3a315 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c @@ -3608,6 +3608,8 @@ static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz) if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah)) REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias); + else if (AR_SREV_5502(ah)) + REG_RMW_FIELD(ah, AR_CH0_TOP3, AR_CH0_TOP3_XPABIASLVL, bias); else if (AR_SREV_9462(ah) || AR_SREV_9550(ah) || AR_SREV_9565(ah)) REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias); else { @@ -3648,7 +3650,7 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz) struct ath9k_hw_capabilities *pCap = &ah->caps; int chain; u32 regval, value, gpio; - static const u32 switch_chain_reg[AR9300_MAX_CHAINS] = { + const u32 switch_chain_reg[AR9300_MAX_CHAINS] = { AR_PHY_SWITCH_CHAIN_0, AR_PHY_SWITCH_CHAIN_1, AR_PHY_SWITCH_CHAIN_2, @@ -3669,7 +3671,8 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz) if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) { REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, AR_SWITCH_TABLE_COM_AR9462_ALL, value); - } else if (AR_SREV_9550(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah)) { + } else if (AR_SREV_9550(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah) || + AR_SREV_5502(ah)) { REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, AR_SWITCH_TABLE_COM_AR9550_ALL, value); } else @@ -4000,11 +4003,11 @@ void ar9003_hw_internal_regulator_apply(struct ath_hw *ah) if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set)) return; } else if (AR_SREV_9462(ah) || AR_SREV_9565(ah) || - AR_SREV_9561(ah)) { + AR_SREV_9561(ah) || AR_SREV_5502(ah)) { reg_val = le32_to_cpu(pBase->swreg); REG_WRITE(ah, AR_PHY_PMU1, reg_val); - if (AR_SREV_9561(ah)) + if (AR_SREV_9561(ah) || AR_SREV_5502(ah)) REG_WRITE(ah, AR_PHY_PMU2, 0x10200000); } else { /* Internal regulator is ON. Write swreg register. */ @@ -4109,7 +4112,8 @@ static void ar9003_hw_xpa_timing_control_apply(struct ath_hw *ah, bool is2ghz) !AR_SREV_9340(ah) && !AR_SREV_9580(ah) && !AR_SREV_9531(ah) && - !AR_SREV_9561(ah)) + !AR_SREV_9561(ah) && + !AR_SREV_5502(ah)) return; xpa_ctl = ar9003_modal_header(ah, is2ghz)->txFrameToXpaOn; @@ -4889,7 +4893,8 @@ static void ar9003_hw_power_control_override(struct ath_hw *ah, } tempslope: - if (AR_SREV_9550(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah)) { + if (AR_SREV_9550(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah) || + AR_SREV_5502(ah)) { u8 txmask = (eep->baseEepHeader.txrxMask & 0xf0) >> 4; /* diff --git a/drivers/net/wireless/ath/ath9k/ar9003_paprd.c b/drivers/net/wireless/ath/ath9k/ar9003_paprd.c index b2d53b6c0..ff45abd14 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_paprd.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_paprd.c @@ -138,12 +138,12 @@ static int ar9003_get_training_power_5g(struct ath_hw *ah) static int ar9003_paprd_setup_single_table(struct ath_hw *ah) { struct ath_common *common = ath9k_hw_common(ah); - static const u32 ctrl0[3] = { + const u32 ctrl0[3] = { AR_PHY_PAPRD_CTRL0_B0, AR_PHY_PAPRD_CTRL0_B1, AR_PHY_PAPRD_CTRL0_B2 }; - static const u32 ctrl1[3] = { + const u32 ctrl1[3] = { AR_PHY_PAPRD_CTRL1_B0, AR_PHY_PAPRD_CTRL1_B1, AR_PHY_PAPRD_CTRL1_B2 diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c index dc0e5ea25..7cbe30bc4 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c @@ -157,9 +157,9 @@ static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) freq = centers.synth_center; if (freq < 4800) { /* 2 GHz, fractional mode */ - if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || - AR_SREV_9531(ah) || AR_SREV_9550(ah) || - AR_SREV_9561(ah) || AR_SREV_9565(ah)) { + if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9531(ah) || + AR_SREV_9550(ah) || AR_SREV_9561(ah) || AR_SREV_5502(ah) || + AR_SREV_9565(ah)) { if (ah->is_clk_25mhz) div = 75; else @@ -182,8 +182,8 @@ static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) /* Set to 2G mode */ bMode = 1; } else { - if ((AR_SREV_9340(ah) || AR_SREV_9550(ah) || - AR_SREV_9531(ah) || AR_SREV_9561(ah)) && + if ((AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || + AR_SREV_9561(ah) || AR_SREV_5502(ah)) && ah->is_clk_25mhz) { channelSel = freq / 75; chan_frac = ((freq % 75) * 0x20000) / 75; @@ -250,7 +250,7 @@ static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah, */ if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || - AR_SREV_9550(ah) || AR_SREV_9561(ah)) { + AR_SREV_9550(ah) || AR_SREV_9561(ah) || AR_SREV_5502(ah)) { if (spur_fbin_ptr[0] == 0) /* No spur */ return; max_spur_cnts = 5; @@ -277,7 +277,7 @@ static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah, negative = 0; if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) || - AR_SREV_9550(ah) || AR_SREV_9561(ah)) + AR_SREV_9550(ah) || AR_SREV_9561(ah) || AR_SREV_5502(ah)) cur_bb_spur = ath9k_hw_fbin2freq(spur_fbin_ptr[i], IS_CHAN_2GHZ(chan)); else @@ -619,7 +619,7 @@ static void ar9003_hw_set_channel_regs(struct ath_hw *ah, /* Enable 11n HT, 20 MHz */ phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SHORT_GI_40 | enableDacFifo; - if (!AR_SREV_9561(ah)) + if (!(AR_SREV_9561(ah) || AR_SREV_5502(ah))) phymode |= AR_PHY_GC_SINGLE_HT_LTF1; /* Configure baseband for dynamic 20/40 operation */ @@ -724,7 +724,7 @@ static void ar9003_hw_override_ini(struct ath_hw *ah) ah->enabled_cals &= ~TX_CL_CAL; if (AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9550(ah) || - AR_SREV_9561(ah)) { + AR_SREV_9561(ah) || AR_SREV_5502(ah)) { if (ah->is_clk_25mhz) { REG_WRITE(ah, AR_RTC_DERIVED_CLK, 0x17c << 1); REG_WRITE(ah, AR_SLP32_MODE, 0x0010f3d7); @@ -905,23 +905,25 @@ static int ar9003_hw_process_ini(struct ath_hw *ah, } } - if (AR_SREV_9550(ah) || AR_SREV_9561(ah)) + if (AR_SREV_9550(ah) || AR_SREV_9561(ah) || AR_SREV_5502(ah)) REG_WRITE_ARRAY(&ah->ini_modes_rx_gain_bounds, modesIndex, regWrites); - if (AR_SREV_9561(ah) && (ar9003_hw_get_rx_gain_idx(ah) == 0)) + if ((AR_SREV_9561(ah) || AR_SREV_5502(ah)) && + (ar9003_hw_get_rx_gain_idx(ah) == 0)) REG_WRITE_ARRAY(&ah->ini_modes_rxgain_xlna, modesIndex, regWrites); /* * TXGAIN initvals. */ - if (AR_SREV_9550(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah)) { + if (AR_SREV_9550(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah) || + AR_SREV_5502(ah)) { int modes_txgain_index = 1; if (AR_SREV_9550(ah)) modes_txgain_index = ar9550_hw_get_modes_txgain_index(ah, chan); - if (AR_SREV_9561(ah)) + if (AR_SREV_9561(ah) || AR_SREV_5502(ah)) modes_txgain_index = ar9561_hw_get_modes_txgain_index(ah, chan); @@ -1922,7 +1924,7 @@ void ar9003_hw_attach_phy_ops(struct ath_hw *ah) { struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); struct ath_hw_ops *ops = ath9k_hw_ops(ah); - static const u32 ar9300_cca_regs[6] = { + const u32 ar9300_cca_regs[6] = { AR_PHY_CCA_0, AR_PHY_CCA_1, AR_PHY_CCA_2, @@ -1935,7 +1937,7 @@ void ar9003_hw_attach_phy_ops(struct ath_hw *ah) priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate; if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || - AR_SREV_9561(ah)) + AR_SREV_9561(ah) || AR_SREV_5502(ah)) priv_ops->compute_pll_control = ar9003_hw_compute_pll_control_soc; else priv_ops->compute_pll_control = ar9003_hw_compute_pll_control; @@ -2021,7 +2023,8 @@ bool ar9003_hw_bb_watchdog_check(struct ath_hw *ah) case 0x04000b09: return true; case 0x04000409: - if (AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah)) + if (AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah) || + AR_SREV_5502(ah)) return false; else return true; diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.h b/drivers/net/wireless/ath/ath9k/ar9003_phy.h index a171dbb29..4e258d70e 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_phy.h +++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.h @@ -20,7 +20,7 @@ /* * Channel Register Map */ -#define AR_CHAN_BASE 0x9800 +#define AR_CHAN_BASE (AR_SREV_5502(ah) ? 0x29800 : 0x9800) #define AR_PHY_TIMING1 (AR_CHAN_BASE + 0x0) #define AR_PHY_TIMING2 (AR_CHAN_BASE + 0x4) @@ -214,7 +214,7 @@ /* * MRC Register Map */ -#define AR_MRC_BASE 0x9c00 +#define AR_MRC_BASE (AR_SREV_5502(ah) ? 0x29c00 : 0x9c00) #define AR_PHY_TIMING_3A (AR_MRC_BASE + 0x0) #define AR_PHY_LDPC_CNTL1 (AR_MRC_BASE + 0x4) @@ -255,12 +255,12 @@ /* * BBB Register Map */ -#define AR_BBB_BASE 0x9d00 +#define AR_BBB_BASE (AR_SREV_5502(ah) ? 0x29d00 : 0x9d00) /* * AGC Register Map */ -#define AR_AGC_BASE 0x9e00 +#define AR_AGC_BASE (AR_SREV_5502(ah) ? 0x29e00 : 0x9e00) #define AR_PHY_SETTLING (AR_AGC_BASE + 0x0) #define AR_PHY_FORCEMAX_GAINS_0 (AR_AGC_BASE + 0x4) @@ -448,14 +448,16 @@ /* * SM Register Map */ -#define AR_SM_BASE 0xa200 +#define AR_SM_BASE (AR_SREV_5502(ah) ? 0x2a200 : 0xa200) #define AR_PHY_D2_CHIP_ID (AR_SM_BASE + 0x0) #define AR_PHY_GEN_CTRL (AR_SM_BASE + 0x4) #define AR_PHY_MODE (AR_SM_BASE + 0x8) #define AR_PHY_ACTIVE (AR_SM_BASE + 0xc) -#define AR_PHY_SPUR_MASK_A (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x18 : 0x20)) -#define AR_PHY_SPUR_MASK_B (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x1c : 0x24)) +#define AR_PHY_SPUR_MASK_A \ + (AR_SM_BASE + ((AR_SREV_9561(ah) || AR_SREV_5502(ah)) ? 0x18 : 0x20)) +#define AR_PHY_SPUR_MASK_B \ + (AR_SM_BASE + ((AR_SREV_9561(ah) || AR_SREV_5502(ah)) ? 0x1c : 0x24)) #define AR_PHY_SPECTRAL_SCAN (AR_SM_BASE + 0x28) #define AR_PHY_RADAR_BW_FILTER (AR_SM_BASE + 0x2c) #define AR_PHY_SEARCH_START_DELAY (AR_SM_BASE + 0x30) @@ -498,7 +500,8 @@ #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A 0x3FF #define AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A_S 0 -#define AR_PHY_TEST (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x15c : 0x160)) +#define AR_PHY_TEST \ + (AR_SM_BASE + ((AR_SREV_9561(ah) || AR_SREV_5502(ah)) ? 0x15c : 0x160)) #define AR_PHY_TEST_BBB_OBS_SEL 0x780000 #define AR_PHY_TEST_BBB_OBS_SEL_S 19 @@ -509,7 +512,8 @@ #define AR_PHY_TEST_CHAIN_SEL 0xC0000000 #define AR_PHY_TEST_CHAIN_SEL_S 30 -#define AR_PHY_TEST_CTL_STATUS (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x160 : 0x164)) +#define AR_PHY_TEST_CTL_STATUS \ + (AR_SM_BASE + ((AR_SREV_9561(ah) || AR_SREV_5502(ah)) ? 0x160 : 0x164)) #define AR_PHY_TEST_CTL_TSTDAC_EN 0x1 #define AR_PHY_TEST_CTL_TSTDAC_EN_S 0 #define AR_PHY_TEST_CTL_TX_OBS_SEL 0x1C @@ -523,23 +527,32 @@ #define AR_PHY_TEST_CTL_DEBUGPORT_SEL 0xe0000000 #define AR_PHY_TEST_CTL_DEBUGPORT_SEL_S 29 +#define AR_PHY_TSTDAC \ + (AR_SM_BASE + ((AR_SREV_9561(ah) || AR_SREV_5502(ah)) ? 0x164 : 0x168)) -#define AR_PHY_TSTDAC (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x164 : 0x168)) +#define AR_PHY_CHAN_STATUS \ + (AR_SM_BASE + ((AR_SREV_9561(ah) || AR_SREV_5502(ah)) ? 0x168 : 0x16c)) -#define AR_PHY_CHAN_STATUS (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x168 : 0x16c)) - -#define AR_PHY_CHAN_INFO_MEMORY (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x16c : 0x170)) +#define AR_PHY_CHAN_INFO_MEMORY \ + (AR_SM_BASE + ((AR_SREV_9561(ah) || AR_SREV_5502(ah)) ? 0x16c : 0x170)) #define AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ 0x00000008 #define AR_PHY_CHAN_INFO_MEMORY_CHANINFOMEM_S2_READ_S 3 -#define AR_PHY_CHNINFO_NOISEPWR (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x170 : 0x174)) -#define AR_PHY_CHNINFO_GAINDIFF (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x174 : 0x178)) -#define AR_PHY_CHNINFO_FINETIM (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x178 : 0x17c)) -#define AR_PHY_CHAN_INFO_GAIN_0 (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x17c : 0x180)) -#define AR_PHY_SCRAMBLER_SEED (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x184 : 0x190)) -#define AR_PHY_CCK_TX_CTRL (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x188 : 0x194)) - -#define AR_PHY_HEAVYCLIP_CTL (AR_SM_BASE + (AR_SREV_9561(ah) ? 0x198 : 0x1a4)) +#define AR_PHY_CHNINFO_NOISEPWR \ + (AR_SM_BASE + ((AR_SREV_9561(ah) || AR_SREV_5502(ah)) ? 0x170 : 0x174)) +#define AR_PHY_CHNINFO_GAINDIFF \ + (AR_SM_BASE + ((AR_SREV_9561(ah) || AR_SREV_5502(ah)) ? 0x174 : 0x178)) +#define AR_PHY_CHNINFO_FINETIM \ + (AR_SM_BASE + ((AR_SREV_9561(ah) || AR_SREV_5502(ah)) ? 0x178 : 0x17c)) +#define AR_PHY_CHAN_INFO_GAIN_0 \ + (AR_SM_BASE + ((AR_SREV_9561(ah) || AR_SREV_5502(ah)) ? 0x17c : 0x180)) +#define AR_PHY_SCRAMBLER_SEED \ + (AR_SM_BASE + ((AR_SREV_9561(ah) || AR_SREV_5502(ah)) ? 0x184 : 0x190)) +#define AR_PHY_CCK_TX_CTRL \ + (AR_SM_BASE + ((AR_SREV_9561(ah) || AR_SREV_5502(ah)) ? 0x188 : 0x194)) + +#define AR_PHY_HEAVYCLIP_CTL \ + (AR_SM_BASE + ((AR_SREV_9561(ah) || AR_SREV_5502(ah)) ? 0x198 : 0x1a4)) #define AR_PHY_HEAVYCLIP_20 (AR_SM_BASE + 0x1a8) #define AR_PHY_HEAVYCLIP_40 (AR_SM_BASE + 0x1ac) #define AR_PHY_HEAVYCLIP_1 (AR_SM_BASE + 0x19c) @@ -722,6 +735,10 @@ #define AR_CH0_TOP2_XPABIASLVL (AR_SREV_9561(ah) ? 0x1e00 : 0xf000) #define AR_CH0_TOP2_XPABIASLVL_S 12 +#define AR_CH0_TOP3 0x16288 +#define AR_CH0_TOP3_XPABIASLVL 0xf0000 +#define AR_CH0_TOP3_XPABIASLVL_S 16 + #define AR_CH0_XTAL (AR_SREV_9300(ah) ? 0x16294 : \ ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x16298 : \ (AR_SREV_9561(ah) ? 0x162c0 : 0x16290))) @@ -730,13 +747,17 @@ #define AR_CH0_XTAL_CAPOUTDAC 0x00fe0000 #define AR_CH0_XTAL_CAPOUTDAC_S 17 -#define AR_PHY_PMU1 ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x16340 : \ - (AR_SREV_9561(ah) ? 0x16cc0 : 0x16c40)) +#define AR_PHY_PMU1 \ + ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? \ + 0x16340 : \ + ((AR_SREV_9561(ah) || AR_SREV_5502(ah)) ? 0x16cc0 : 0x16c40)) #define AR_PHY_PMU1_PWD 0x1 #define AR_PHY_PMU1_PWD_S 0 -#define AR_PHY_PMU2 ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x16344 : \ - (AR_SREV_9561(ah) ? 0x16cc4 : 0x16c44)) +#define AR_PHY_PMU2 \ + ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? \ + 0x16344 : \ + ((AR_SREV_9561(ah) || AR_SREV_5502(ah)) ? 0x16cc4 : 0x16c44)) #define AR_PHY_PMU2_PGM 0x00200000 #define AR_PHY_PMU2_PGM_S 21 @@ -925,7 +946,7 @@ /* * Channel 1 Register Map */ -#define AR_CHAN1_BASE 0xa800 +#define AR_CHAN1_BASE (AR_SREV_5502(ah) ? 0x2a800 : 0xa800) #define AR_PHY_EXT_CCA_1 (AR_CHAN1_BASE + 0x30) #define AR_PHY_TX_PHASE_RAMP_1 (AR_CHAN1_BASE + 0xd0) @@ -944,7 +965,7 @@ /* * AGC 1 Register Map */ -#define AR_AGC1_BASE 0xae00 +#define AR_AGC1_BASE (AR_SREV_5502(ah) ? 0x2ae00 : 0xae00) #define AR_PHY_FORCEMAX_GAINS_1 (AR_AGC1_BASE + 0x4) #define AR_PHY_EXT_ATTEN_CTL_1 (AR_AGC1_BASE + 0x18) @@ -963,7 +984,7 @@ /* * SM 1 Register Map */ -#define AR_SM1_BASE 0xb200 +#define AR_SM1_BASE (AR_SREV_5502(ah) ? 0x2b200 : 0xb200) #define AR_PHY_SWITCH_CHAIN_1 (AR_SM1_BASE + 0x84) #define AR_PHY_FCAL_2_1 (AR_SM1_BASE + 0xd0) @@ -989,7 +1010,7 @@ /* * Channel 2 Register Map */ -#define AR_CHAN2_BASE 0xb800 +#define AR_CHAN2_BASE (AR_SREV_5502(ah) ? 0x2b800 : 0xb800) #define AR_PHY_EXT_CCA_2 (AR_CHAN2_BASE + 0x30) #define AR_PHY_TX_PHASE_RAMP_2 (AR_CHAN2_BASE + 0xd0) @@ -1007,7 +1028,7 @@ /* * AGC 2 Register Map */ -#define AR_AGC2_BASE 0xbe00 +#define AR_AGC2_BASE (AR_SREV_5502(ah) ? 0x2be00 : 0xbe00) #define AR_PHY_FORCEMAX_GAINS_2 (AR_AGC2_BASE + 0x4) #define AR_PHY_EXT_ATTEN_CTL_2 (AR_AGC2_BASE + 0x18) @@ -1024,7 +1045,7 @@ /* * SM 2 Register Map */ -#define AR_SM2_BASE 0xc200 +#define AR_SM2_BASE (AR_SREV_5502(ah) ? 0x2c200 : 0xc200) #define AR_PHY_SWITCH_CHAIN_2 (AR_SM2_BASE + 0x84) #define AR_PHY_FCAL_2_2 (AR_SM2_BASE + 0xd0) diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c index 047512ce1..c32b201a3 100644 --- a/drivers/net/wireless/ath/ath9k/hw.c +++ b/drivers/net/wireless/ath/ath9k/hw.c @@ -834,7 +834,7 @@ static void ath9k_hw_init_pll(struct ath_hw *ah, REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3, AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1); } else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || - AR_SREV_9561(ah)) { + AR_SREV_9561(ah) || AR_SREV_5502(ah)) { u32 regval, pll2_divint, pll2_divfrac, refdiv; REG_WRITE(ah, AR_RTC_PLL_CONTROL, @@ -845,7 +845,8 @@ static void ath9k_hw_init_pll(struct ath_hw *ah, udelay(100); if (ah->is_clk_25mhz) { - if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) { + if (AR_SREV_9531(ah) || AR_SREV_9561(ah) || + AR_SREV_5502(ah)) { pll2_divint = 0x1c; pll2_divfrac = 0xa3d2; refdiv = 1; @@ -861,15 +862,16 @@ static void ath9k_hw_init_pll(struct ath_hw *ah, refdiv = 5; } else { pll2_divint = 0x11; - pll2_divfrac = (AR_SREV_9531(ah) || - AR_SREV_9561(ah)) ? + pll2_divfrac = + (AR_SREV_9531(ah) || AR_SREV_9561(ah) || + AR_SREV_5502(ah)) ? 0x26665 : 0x26666; refdiv = 1; } } regval = REG_READ(ah, AR_PHY_PLL_MODE); - if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) + if (AR_SREV_9531(ah) || AR_SREV_9561(ah) || AR_SREV_5502(ah)) regval |= (0x1 << 22); else regval |= (0x1 << 16); @@ -887,7 +889,8 @@ static void ath9k_hw_init_pll(struct ath_hw *ah, (0x1 << 13) | (0x4 << 26) | (0x18 << 19); - else if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) { + else if (AR_SREV_9531(ah) || AR_SREV_9561(ah) || + AR_SREV_5502(ah)) { regval = (regval & 0x01c00fff) | (0x1 << 31) | (0x2 << 29) | @@ -904,7 +907,7 @@ static void ath9k_hw_init_pll(struct ath_hw *ah, (0x60 << 19); REG_WRITE(ah, AR_PHY_PLL_MODE, regval); - if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) + if (AR_SREV_9531(ah) || AR_SREV_9561(ah) || AR_SREV_5502(ah)) REG_WRITE(ah, AR_PHY_PLL_MODE, REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff); else @@ -945,7 +948,7 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah, u32 msi_cfg = 0; if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || - AR_SREV_9561(ah)) + AR_SREV_9561(ah) || AR_SREV_5502(ah)) sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; if (AR_SREV_9300_20_OR_LATER(ah)) { @@ -1777,7 +1780,7 @@ static void ath9k_hw_init_desc(struct ath_hw *ah) #ifdef __BIG_ENDIAN else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || - AR_SREV_9561(ah)) + AR_SREV_9561(ah) || AR_SREV_5502(ah)) REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0); else REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD); @@ -2474,6 +2477,9 @@ static void ath9k_gpio_cap_init(struct ath_hw *ah) } else if (AR_SREV_9561(ah)) { pCap->num_gpio_pins = AR9561_NUM_GPIO; pCap->gpio_mask = AR9561_GPIO_MASK; + } else if (AR_SREV_5502(ah)) { + pCap->num_gpio_pins = AR5502_NUM_GPIO; + pCap->gpio_mask = AR5502_GPIO_MASK; } else if (AR_SREV_9565(ah)) { pCap->num_gpio_pins = AR9565_NUM_GPIO; pCap->gpio_mask = AR9565_GPIO_MASK; @@ -2610,7 +2616,7 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah) if (AR_SREV_9300_20_OR_LATER(ah)) { pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK; if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) && - !AR_SREV_9561(ah) && !AR_SREV_9565(ah)) + !AR_SREV_9561(ah) && !AR_SREV_5502(ah) && !AR_SREV_9565(ah)) pCap->hw_caps |= ATH9K_HW_CAP_LDPC; pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; @@ -2627,7 +2633,7 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah) if (AR_SREV_9300_20_OR_LATER(ah)) pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED; - if (AR_SREV_9561(ah)) + if (AR_SREV_9561(ah) || AR_SREV_5502(ah)) ah->ent_mode = 0x3BDA000; else if (AR_SREV_9300_20_OR_LATER(ah)) ah->ent_mode = REG_READ(ah, AR_ENT_OTP); diff --git a/drivers/net/wireless/ath/ath9k/mac.c b/drivers/net/wireless/ath/ath9k/mac.c index 58d02c19b..08f91f558 100644 --- a/drivers/net/wireless/ath/ath9k/mac.c +++ b/drivers/net/wireless/ath/ath9k/mac.c @@ -813,7 +813,7 @@ static void __ath9k_hw_enable_interrupts(struct ath_hw *ah) u32 async_mask; if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) || - AR_SREV_9561(ah)) + AR_SREV_9561(ah) || AR_SREV_5502(ah)) sync_default &= ~AR_INTR_SYNC_HOST1_FATAL; async_mask = AR_INTR_MAC_IRQ; diff --git a/drivers/net/wireless/ath/ath9k/recv.c b/drivers/net/wireless/ath/ath9k/recv.c index 0c0624a3b..3299aef65 100644 --- a/drivers/net/wireless/ath/ath9k/recv.c +++ b/drivers/net/wireless/ath/ath9k/recv.c @@ -422,7 +422,7 @@ u32 ath_calcrxfilter(struct ath_softc *sc) } if (AR_SREV_9550(sc->sc_ah) || AR_SREV_9531(sc->sc_ah) || - AR_SREV_9561(sc->sc_ah)) + AR_SREV_9561(sc->sc_ah) || AR_SREV_5502(sc->sc_ah)) rfilt |= ATH9K_RX_FILTER_4ADDRESS; if (AR_SREV_9462(sc->sc_ah) || AR_SREV_9565(sc->sc_ah)) diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h index 5a07cf7d8..d465167ac 100644 --- a/drivers/net/wireless/ath/ath9k/reg.h +++ b/drivers/net/wireless/ath/ath9k/reg.h @@ -1138,6 +1138,7 @@ enum { #define AR9531_NUM_GPIO 18 #define AR9550_NUM_GPIO 24 #define AR9561_NUM_GPIO 23 +#define AR5502_NUM_GPIO 20 #define AR9565_NUM_GPIO 14 #define AR9580_NUM_GPIO 16 #define AR7010_NUM_GPIO 16 @@ -1155,6 +1156,7 @@ enum { #define AR9531_GPIO_MASK 0x0000000F #define AR9550_GPIO_MASK 0x0000000F #define AR9561_GPIO_MASK 0x0000000F +#define AR5502_GPIO_MASK 0x0000000F #define AR9565_GPIO_MASK 0x00003FFF #define AR9580_GPIO_MASK 0x0000F4FF #define AR7010_GPIO_MASK 0x0000FFFF @@ -2114,7 +2116,7 @@ enum { * pcu_txsm. */ -#define AR9300_SM_BASE 0xa200 +#define AR9300_SM_BASE (AR_SREV_5502(ah) ? 0x2a200 : 0xa200) #define AR9002_PHY_AGC_CONTROL 0x9860 #define AR9003_PHY_AGC_CONTROL AR9300_SM_BASE + 0xc4 #define AR_PHY_AGC_CONTROL (AR_SREV_9300_20_OR_LATER(ah) ? AR9003_PHY_AGC_CONTROL : AR9002_PHY_AGC_CONTROL) diff --git a/drivers/net/wireless/ath/ath9k/reg_aic.h b/drivers/net/wireless/ath/ath9k/reg_aic.h index 955147ab4..abd0370e0 100644 --- a/drivers/net/wireless/ath/ath9k/reg_aic.h +++ b/drivers/net/wireless/ath/ath9k/reg_aic.h @@ -17,9 +17,9 @@ #ifndef REG_AIC_H #define REG_AIC_H -#define AR_SM_BASE 0xa200 -#define AR_SM1_BASE 0xb200 -#define AR_AGC_BASE 0x9e00 +#define AR_SM_BASE (AR_SREV_5502(ah) ? 0x2a200 : 0xa200) +#define AR_SM1_BASE (AR_SREV_5502(ah) ? 0x2b200 : 0xb200) +#define AR_AGC_BASE (AR_SREV_5502(ah) ? 0x29e00 : 0x9e00) #define AR_PHY_AIC_CTRL_0_B0 (AR_SM_BASE + 0x4b0) #define AR_PHY_AIC_CTRL_1_B0 (AR_SM_BASE + 0x4b4) -- 2.25.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 2/9] ath9k: basic support for QCN550x 2022-04-18 7:13 ` [PATCH 2/9] ath9k: basic support for QCN550x Wenli Looi @ 2022-04-20 12:01 ` Kalle Valo 0 siblings, 0 replies; 15+ messages in thread From: Kalle Valo @ 2022-04-20 12:01 UTC (permalink / raw) To: Wenli Looi; +Cc: Toke Høiland-Jørgensen, linux-wireless, ath9k-devel Wenli Looi <wlooi@ucalgary.ca> writes: > QCN550x is very similar to QCA956x. Note that AR_CH0_XTAL is > intentionally unchanged. Certain arrays are no longer static because > they are no longer constant. s-o-b missing in patches 2-5. -- https://patchwork.kernel.org/project/linux-wireless/list/ https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 3/9] ath9k: add QCN550x initvals 2022-04-18 7:13 [PATCH 0/9] ath9k: add support for QCN550x Wenli Looi 2022-04-18 7:13 ` [PATCH 1/9] ath9k: add QCN550x device IDs Wenli Looi 2022-04-18 7:13 ` [PATCH 2/9] ath9k: basic support for QCN550x Wenli Looi @ 2022-04-18 7:13 ` Wenli Looi 2022-04-18 7:13 ` [PATCH 4/9] ath9k: implement QCN550x rx Wenli Looi ` (6 subsequent siblings) 9 siblings, 0 replies; 15+ messages in thread From: Wenli Looi @ 2022-04-18 7:13 UTC (permalink / raw) To: Toke Høiland-Jørgensen Cc: Kalle Valo, linux-wireless, ath9k-devel, Wenli Looi These initvals are identical to the QCA956x initvals in ath9k except for the following register shifts and a single modified value: if (reg >= 0x9800 && reg < 0x10000) reg += 0x20000; else if (reg >= 0x162c0 && reg < 0x162cc) reg -= 0x30; if (reg == 0x16284) val &= ~0x180000; Of the TX gain tables, only qcn550x_1p0_modes_no_xpa_tx_gain_table has been tested. --- .../net/wireless/ath/ath9k/ar550x_initvals.h | 1296 +++++++++++++++++ drivers/net/wireless/ath/ath9k/ar9003_hw.c | 59 + 2 files changed, 1355 insertions(+) create mode 100644 drivers/net/wireless/ath/ath9k/ar550x_initvals.h diff --git a/drivers/net/wireless/ath/ath9k/ar550x_initvals.h b/drivers/net/wireless/ath/ath9k/ar550x_initvals.h new file mode 100644 index 000000000..4ea6045fc --- /dev/null +++ b/drivers/net/wireless/ath/ath9k/ar550x_initvals.h @@ -0,0 +1,1296 @@ +#ifndef INITVALS_550X_H +#define INITVALS_550X_H + +#define qcn550x_1p0_mac_core ar955x_1p0_mac_core + +#define qcn550x_1p0_mac_postamble ar9331_1p1_mac_postamble + +#define qcn550x_1p0_soc_preamble ar955x_1p0_soc_preamble + +#define qcn550x_1p0_soc_postamble ar9300_2p2_soc_postamble + +static const u32 qcn550x_1p0_common_wo_xlna_rx_gain_table[][2] = { + /* Addr allmodes */ + {0x0002a000, 0x00010000}, + {0x0002a004, 0x00030002}, + {0x0002a008, 0x00050004}, + {0x0002a00c, 0x00810080}, + {0x0002a010, 0x00830082}, + {0x0002a014, 0x01810180}, + {0x0002a018, 0x01830182}, + {0x0002a01c, 0x01850184}, + {0x0002a020, 0x01890188}, + {0x0002a024, 0x018b018a}, + {0x0002a028, 0x018d018c}, + {0x0002a02c, 0x03820190}, + {0x0002a030, 0x03840383}, + {0x0002a034, 0x03880385}, + {0x0002a038, 0x038a0389}, + {0x0002a03c, 0x038c038b}, + {0x0002a040, 0x0390038d}, + {0x0002a044, 0x03920391}, + {0x0002a048, 0x03940393}, + {0x0002a04c, 0x03960395}, + {0x0002a050, 0x00000000}, + {0x0002a054, 0x00000000}, + {0x0002a058, 0x00000000}, + {0x0002a05c, 0x00000000}, + {0x0002a060, 0x00000000}, + {0x0002a064, 0x00000000}, + {0x0002a068, 0x00000000}, + {0x0002a06c, 0x00000000}, + {0x0002a070, 0x00000000}, + {0x0002a074, 0x00000000}, + {0x0002a078, 0x00000000}, + {0x0002a07c, 0x00000000}, + {0x0002a080, 0x29292929}, + {0x0002a084, 0x29292929}, + {0x0002a088, 0x29292929}, + {0x0002a08c, 0x29292929}, + {0x0002a090, 0x22292929}, + {0x0002a094, 0x1d1d2222}, + {0x0002a098, 0x0c111117}, + {0x0002a09c, 0x00030303}, + {0x0002a0a0, 0x00000000}, + {0x0002a0a4, 0x00000000}, + {0x0002a0a8, 0x00000000}, + {0x0002a0ac, 0x00000000}, + {0x0002a0b0, 0x00000000}, + {0x0002a0b4, 0x00000000}, + {0x0002a0b8, 0x00000000}, + {0x0002a0bc, 0x00000000}, + {0x0002a0c0, 0x001f0000}, + {0x0002a0c4, 0x01000101}, + {0x0002a0c8, 0x011e011f}, + {0x0002a0cc, 0x011c011d}, + {0x0002a0d0, 0x02030204}, + {0x0002a0d4, 0x02010202}, + {0x0002a0d8, 0x021f0200}, + {0x0002a0dc, 0x0302021e}, + {0x0002a0e0, 0x03000301}, + {0x0002a0e4, 0x031e031f}, + {0x0002a0e8, 0x0402031d}, + {0x0002a0ec, 0x04000401}, + {0x0002a0f0, 0x041e041f}, + {0x0002a0f4, 0x0502041d}, + {0x0002a0f8, 0x05000501}, + {0x0002a0fc, 0x051e051f}, + {0x0002a100, 0x06010602}, + {0x0002a104, 0x061f0600}, + {0x0002a108, 0x061d061e}, + {0x0002a10c, 0x07020703}, + {0x0002a110, 0x07000701}, + {0x0002a114, 0x00000000}, + {0x0002a118, 0x00000000}, + {0x0002a11c, 0x00000000}, + {0x0002a120, 0x00000000}, + {0x0002a124, 0x00000000}, + {0x0002a128, 0x00000000}, + {0x0002a12c, 0x00000000}, + {0x0002a130, 0x00000000}, + {0x0002a134, 0x00000000}, + {0x0002a138, 0x00000000}, + {0x0002a13c, 0x00000000}, + {0x0002a140, 0x001f0000}, + {0x0002a144, 0x01000101}, + {0x0002a148, 0x011e011f}, + {0x0002a14c, 0x011c011d}, + {0x0002a150, 0x02030204}, + {0x0002a154, 0x02010202}, + {0x0002a158, 0x021f0200}, + {0x0002a15c, 0x0302021e}, + {0x0002a160, 0x03000301}, + {0x0002a164, 0x031e031f}, + {0x0002a168, 0x0402031d}, + {0x0002a16c, 0x04000401}, + {0x0002a170, 0x041e041f}, + {0x0002a174, 0x0502041d}, + {0x0002a178, 0x05000501}, + {0x0002a17c, 0x051e051f}, + {0x0002a180, 0x06010602}, + {0x0002a184, 0x061f0600}, + {0x0002a188, 0x061d061e}, + {0x0002a18c, 0x07020703}, + {0x0002a190, 0x07000701}, + {0x0002a194, 0x00000000}, + {0x0002a198, 0x00000000}, + {0x0002a19c, 0x00000000}, + {0x0002a1a0, 0x00000000}, + {0x0002a1a4, 0x00000000}, + {0x0002a1a8, 0x00000000}, + {0x0002a1ac, 0x00000000}, + {0x0002a1b0, 0x00000000}, + {0x0002a1b4, 0x00000000}, + {0x0002a1b8, 0x00000000}, + {0x0002a1bc, 0x00000000}, + {0x0002a1c0, 0x00000000}, + {0x0002a1c4, 0x00000000}, + {0x0002a1c8, 0x00000000}, + {0x0002a1cc, 0x00000000}, + {0x0002a1d0, 0x00000000}, + {0x0002a1d4, 0x00000000}, + {0x0002a1d8, 0x00000000}, + {0x0002a1dc, 0x00000000}, + {0x0002a1e0, 0x00000000}, + {0x0002a1e4, 0x00000000}, + {0x0002a1e8, 0x00000000}, + {0x0002a1ec, 0x00000000}, + {0x0002a1f0, 0x00000396}, + {0x0002a1f4, 0x00000396}, + {0x0002a1f8, 0x00000396}, + {0x0002a1fc, 0x00000196}, + {0x0002b000, 0x00010000}, + {0x0002b004, 0x00030002}, + {0x0002b008, 0x00050004}, + {0x0002b00c, 0x00810080}, + {0x0002b010, 0x00830082}, + {0x0002b014, 0x01810180}, + {0x0002b018, 0x01830182}, + {0x0002b01c, 0x01850184}, + {0x0002b020, 0x02810280}, + {0x0002b024, 0x02830282}, + {0x0002b028, 0x02850284}, + {0x0002b02c, 0x02890288}, + {0x0002b030, 0x028b028a}, + {0x0002b034, 0x0388028c}, + {0x0002b038, 0x038a0389}, + {0x0002b03c, 0x038c038b}, + {0x0002b040, 0x0390038d}, + {0x0002b044, 0x03920391}, + {0x0002b048, 0x03940393}, + {0x0002b04c, 0x03960395}, + {0x0002b050, 0x00000000}, + {0x0002b054, 0x00000000}, + {0x0002b058, 0x00000000}, + {0x0002b05c, 0x00000000}, + {0x0002b060, 0x00000000}, + {0x0002b064, 0x00000000}, + {0x0002b068, 0x00000000}, + {0x0002b06c, 0x00000000}, + {0x0002b070, 0x00000000}, + {0x0002b074, 0x00000000}, + {0x0002b078, 0x00000000}, + {0x0002b07c, 0x00000000}, + {0x0002b080, 0x32323232}, + {0x0002b084, 0x2f2f3232}, + {0x0002b088, 0x23282a2d}, + {0x0002b08c, 0x1c1e2123}, + {0x0002b090, 0x14171919}, + {0x0002b094, 0x0e0e1214}, + {0x0002b098, 0x03050707}, + {0x0002b09c, 0x00030303}, + {0x0002b0a0, 0x00000000}, + {0x0002b0a4, 0x00000000}, + {0x0002b0a8, 0x00000000}, + {0x0002b0ac, 0x00000000}, + {0x0002b0b0, 0x00000000}, + {0x0002b0b4, 0x00000000}, + {0x0002b0b8, 0x00000000}, + {0x0002b0bc, 0x00000000}, + {0x0002b0c0, 0x003f0020}, + {0x0002b0c4, 0x00400041}, + {0x0002b0c8, 0x0140005f}, + {0x0002b0cc, 0x0160015f}, + {0x0002b0d0, 0x017e017f}, + {0x0002b0d4, 0x02410242}, + {0x0002b0d8, 0x025f0240}, + {0x0002b0dc, 0x027f0260}, + {0x0002b0e0, 0x0341027e}, + {0x0002b0e4, 0x035f0340}, + {0x0002b0e8, 0x037f0360}, + {0x0002b0ec, 0x04400441}, + {0x0002b0f0, 0x0460045f}, + {0x0002b0f4, 0x0541047f}, + {0x0002b0f8, 0x055f0540}, + {0x0002b0fc, 0x057f0560}, + {0x0002b100, 0x06400641}, + {0x0002b104, 0x0660065f}, + {0x0002b108, 0x067e067f}, + {0x0002b10c, 0x07410742}, + {0x0002b110, 0x075f0740}, + {0x0002b114, 0x077f0760}, + {0x0002b118, 0x07800781}, + {0x0002b11c, 0x07a0079f}, + {0x0002b120, 0x07c107bf}, + {0x0002b124, 0x000007c0}, + {0x0002b128, 0x00000000}, + {0x0002b12c, 0x00000000}, + {0x0002b130, 0x00000000}, + {0x0002b134, 0x00000000}, + {0x0002b138, 0x00000000}, + {0x0002b13c, 0x00000000}, + {0x0002b140, 0x003f0020}, + {0x0002b144, 0x00400041}, + {0x0002b148, 0x0140005f}, + {0x0002b14c, 0x0160015f}, + {0x0002b150, 0x017e017f}, + {0x0002b154, 0x02410242}, + {0x0002b158, 0x025f0240}, + {0x0002b15c, 0x027f0260}, + {0x0002b160, 0x0341027e}, + {0x0002b164, 0x035f0340}, + {0x0002b168, 0x037f0360}, + {0x0002b16c, 0x04400441}, + {0x0002b170, 0x0460045f}, + {0x0002b174, 0x0541047f}, + {0x0002b178, 0x055f0540}, + {0x0002b17c, 0x057f0560}, + {0x0002b180, 0x06400641}, + {0x0002b184, 0x0660065f}, + {0x0002b188, 0x067e067f}, + {0x0002b18c, 0x07410742}, + {0x0002b190, 0x075f0740}, + {0x0002b194, 0x077f0760}, + {0x0002b198, 0x07800781}, + {0x0002b19c, 0x07a0079f}, + {0x0002b1a0, 0x07c107bf}, + {0x0002b1a4, 0x000007c0}, + {0x0002b1a8, 0x00000000}, + {0x0002b1ac, 0x00000000}, + {0x0002b1b0, 0x00000000}, + {0x0002b1b4, 0x00000000}, + {0x0002b1b8, 0x00000000}, + {0x0002b1bc, 0x00000000}, + {0x0002b1c0, 0x00000000}, + {0x0002b1c4, 0x00000000}, + {0x0002b1c8, 0x00000000}, + {0x0002b1cc, 0x00000000}, + {0x0002b1d0, 0x00000000}, + {0x0002b1d4, 0x00000000}, + {0x0002b1d8, 0x00000000}, + {0x0002b1dc, 0x00000000}, + {0x0002b1e0, 0x00000000}, + {0x0002b1e4, 0x00000000}, + {0x0002b1e8, 0x00000000}, + {0x0002b1ec, 0x00000000}, + {0x0002b1f0, 0x00000396}, + {0x0002b1f4, 0x00000396}, + {0x0002b1f8, 0x00000396}, + {0x0002b1fc, 0x00000196}, +}; + +static const u32 qcn550x_1p0_baseband_postamble_dfs_channel[][3] = { + /* Addr 5G 2G */ + {0x00029824, 0x5ac668d0, 0x5ac668d0}, + {0x00029e0c, 0x6d4000e2, 0x6d4000e2}, + {0x00029e14, 0x37b9625e, 0x37b9625e}, +}; + +static const u32 qcn550x_1p0_common_wo_xlna_rx_gain_bounds[][5] = { + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + {0x00029e44, 0xfe321e27, 0xfe321e27, 0xfe291e27, 0xfe291e27}, + {0x00029e48, 0x5030201a, 0x5030201a, 0x50302012, 0x50302012}, +}; + +static const u32 qcn550x_1p0_common_rx_gain_bounds[][5] = { + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + {0x00029e44, 0xfe321e27, 0xfe321e27, 0xfe291e27, 0xfe291e27}, + {0x00029e48, 0x5030201a, 0x5030201a, 0x50302018, 0x50302018}, +}; + +static const u32 qcn550x_1p0_modes_fast_clock[][3] = { + /* Addr 5G_HT20 5G_HT40 */ + {0x00001030, 0x00000268, 0x000004d0}, + {0x00001070, 0x0000018c, 0x00000318}, + {0x000010b0, 0x00000fd0, 0x00001fa0}, + {0x00008014, 0x044c044c, 0x08980898}, + {0x0000801c, 0x148ec02b, 0x148ec057}, + {0x00008318, 0x000044c0, 0x00008980}, + {0x00029e00, 0x0372131c, 0x0372131c}, + {0x0002a230, 0x0000400b, 0x00004016}, + {0x0002a254, 0x00000898, 0x00001130}, +}; + +static const u32 qcn550x_1p0_baseband_core[][2] = { + /* Addr allmodes */ + {0x00029800, 0xafe68e30}, + {0x00029804, 0xfd14e000}, + {0x00029808, 0x9c0a9f6b}, + {0x0002980c, 0x04900000}, + {0x00029814, 0x0280c00a}, + {0x00029818, 0x00000000}, + {0x0002981c, 0x00020028}, + {0x00029834, 0x6400a190}, + {0x00029838, 0x0108ecff}, + {0x0002983c, 0x14000600}, + {0x00029880, 0x201fff00}, + {0x00029884, 0x00001042}, + {0x000298a4, 0x00200400}, + {0x000298b0, 0x32840cbf}, + {0x000298bc, 0x00000002}, + {0x000298d0, 0x004b6a8e}, + {0x000298d4, 0x00000820}, + {0x000298dc, 0x00000000}, + {0x000298f0, 0x00000000}, + {0x000298f4, 0x00000000}, + {0x00029c04, 0xff55ff55}, + {0x00029c08, 0x0320ff55}, + {0x00029c0c, 0x00000000}, + {0x00029c10, 0x00000000}, + {0x00029c14, 0x00046384}, + {0x00029c18, 0x05b6b440}, + {0x00029c1c, 0x00b6b440}, + {0x00029d00, 0xc080a333}, + {0x00029d04, 0x40206c10}, + {0x00029d08, 0x009c4060}, + {0x00029d0c, 0x9883800a}, + {0x00029d10, 0x01834061}, + {0x00029d14, 0x00c0040b}, + {0x00029d18, 0x00000000}, + {0x00029e08, 0x0038230c}, + {0x00029e24, 0x990bb514}, + {0x00029e28, 0x0c6f0000}, + {0x00029e30, 0x06336f77}, + {0x00029e34, 0x6af6532f}, + {0x00029e38, 0x0cc80c00}, + {0x00029e40, 0x0d261820}, + {0x00029e4c, 0x00001004}, + {0x00029e50, 0x00ff03f1}, + {0x00029fc0, 0x813e4789}, + {0x00029fc4, 0x0001efb5}, + {0x00029fcc, 0x40000014}, + {0x00029fd0, 0x02993b93}, + {0x0002a20c, 0x00000000}, + {0x0002a218, 0x00000000}, + {0x0002a21c, 0x00000000}, + {0x0002a228, 0x10002310}, + {0x0002a23c, 0x00000000}, + {0x0002a244, 0x0c000000}, + {0x0002a248, 0x00000140}, + {0x0002a2a0, 0x00000007}, + {0x0002a2c0, 0x00000007}, + {0x0002a2c8, 0x00000000}, + {0x0002a2d4, 0x00000000}, + {0x0002a2ec, 0x00000000}, + {0x0002a2f0, 0x00000000}, + {0x0002a2f4, 0x00000000}, + {0x0002a2f8, 0x00000000}, + {0x0002a344, 0x00000000}, + {0x0002a34c, 0x00000000}, + {0x0002a350, 0x0000a000}, + {0x0002a360, 0x00000000}, + {0x0002a36c, 0x00000000}, + {0x0002a384, 0x00000001}, + {0x0002a388, 0x00000444}, + {0x0002a38c, 0x00000000}, + {0x0002a390, 0x210d0401}, + {0x0002a394, 0xab9a7144}, + {0x0002a398, 0x00000201}, + {0x0002a39c, 0x42424848}, + {0x0002a3a0, 0x3c466478}, + {0x0002a3a4, 0x3a363600}, + {0x0002a3a8, 0x0000003a}, + {0x0002a3ac, 0x00000000}, + {0x0002a3b0, 0x009011fe}, + {0x0002a3b4, 0x00000034}, + {0x0002a3b8, 0x00b3ec0a}, + {0x0002a3bc, 0x00000036}, + {0x0002a3c0, 0x20202020}, + {0x0002a3c4, 0x22222220}, + {0x0002a3c8, 0x20200020}, + {0x0002a3cc, 0x20202020}, + {0x0002a3d0, 0x20202020}, + {0x0002a3d4, 0x20202020}, + {0x0002a3d8, 0x20202020}, + {0x0002a3dc, 0x20202020}, + {0x0002a3e0, 0x20202020}, + {0x0002a3e4, 0x20202020}, + {0x0002a3e8, 0x20202020}, + {0x0002a3ec, 0x20202020}, + {0x0002a3f0, 0x00000000}, + {0x0002a3f4, 0x00000000}, + {0x0002a3f8, 0x0c9bd380}, + {0x0002a3fc, 0x000f0f01}, + {0x0002a400, 0x8fa91f01}, + {0x0002a404, 0x00000000}, + {0x0002a408, 0x0e79e5c6}, + {0x0002a40c, 0x00820820}, + {0x0002a414, 0x1ce739ce}, + {0x0002a418, 0x2d0019ce}, + {0x0002a41c, 0x1ce739ce}, + {0x0002a420, 0x000001ce}, + {0x0002a424, 0x1ce739ce}, + {0x0002a428, 0x000001ce}, + {0x0002a42c, 0x1ce739ce}, + {0x0002a430, 0x1ce739ce}, + {0x0002a434, 0x00000000}, + {0x0002a438, 0x00001801}, + {0x0002a43c, 0x00100000}, + {0x0002a444, 0x00000000}, + {0x0002a448, 0x05000080}, + {0x0002a44c, 0x00000001}, + {0x0002a450, 0x00010000}, + {0x0002a454, 0x05000000}, + {0x0002a458, 0x00000000}, + {0x0002a644, 0xbfad9fee}, + {0x0002a648, 0x0048660d}, + {0x0002a64c, 0x00003c37}, + {0x0002a670, 0x03020100}, + {0x0002a674, 0x21200504}, + {0x0002a678, 0x61602322}, + {0x0002a67c, 0x65646362}, + {0x0002a680, 0x6b6a6968}, + {0x0002a684, 0xe2706d6c}, + {0x0002a688, 0x000000e3}, + {0x0002a690, 0x00000838}, + {0x0002a7cc, 0x00000000}, + {0x0002a7d0, 0x00000000}, + {0x0002a7d4, 0x00000004}, + {0x0002a7dc, 0x00000000}, + {0x0002a8d0, 0x004b6a8e}, + {0x0002a8d4, 0x00000820}, + {0x0002a8dc, 0x00000000}, + {0x0002a8f0, 0x00000000}, + {0x0002a8f4, 0x00000000}, + {0x0002b2d0, 0x00000080}, + {0x0002b2d4, 0x00000000}, + {0x0002b2ec, 0x00000000}, + {0x0002b2f0, 0x00000000}, + {0x0002b2f4, 0x00000000}, + {0x0002b2f8, 0x00000000}, + {0x0002b408, 0x0e79e5c0}, + {0x0002b40c, 0x00820820}, + {0x0002b420, 0x00000000}, + {0x0002b8d0, 0x004b6a8e}, + {0x0002b8d4, 0x00000820}, + {0x0002b8dc, 0x00000000}, + {0x0002b8f0, 0x00000000}, + {0x0002b8f4, 0x00000000}, + {0x0002c2d0, 0x00000080}, + {0x0002c2d4, 0x00000000}, + {0x0002c2ec, 0x00000000}, + {0x0002c2f0, 0x00000000}, + {0x0002c2f4, 0x00000000}, + {0x0002c2f8, 0x00000000}, + {0x0002c408, 0x0e79e5c0}, + {0x0002c40c, 0x00820820}, + {0x0002c420, 0x00000000}, +}; + +static const u32 qcn550x_1p0_baseband_postamble[][5] = { + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + {0x00029810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011}, + {0x00029820, 0x206a022e, 0x206a022e, 0x206a01ae, 0x206a01ae}, + {0x00029824, 0x5ac640d0, 0x5ac640d0, 0x5ac621f1, 0x5ac621f1}, + {0x00029828, 0x06903081, 0x06903081, 0x07d43881, 0x07d43881}, + {0x0002982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4}, + {0x00029830, 0x0000059c, 0x0000059c, 0x0000119c, 0x0000119c}, + {0x00029c00, 0x000000c4, 0x000000c4, 0x000000c4, 0x000000c4}, + {0x00029e00, 0x0372111a, 0x0372111a, 0x037216a0, 0x037216a0}, + {0x00029e04, 0x001c2020, 0x001c2020, 0x001c2020, 0x001c2020}, + {0x00029e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000de, 0x6c4000de}, + {0x00029e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec86d2e}, + {0x00029e14, 0x37b95d5e, 0x37b9605e, 0x337d605e, 0x337d5d5e}, + {0x00029e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, + {0x00029e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c}, + {0x00029e20, 0x000003b5, 0x000003b5, 0x000003a6, 0x000003a6}, + {0x00029e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021}, + {0x00029e3c, 0xcfa10820, 0xcfa10820, 0xcf946220, 0xcf946220}, + {0x00029e44, 0xfe321e27, 0xfe321e27, 0xfe291e27, 0xfe291e27}, + {0x00029e48, 0x5030201a, 0x5030201a, 0x50302012, 0x50302012}, + {0x00029fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000}, + {0x0002a204, 0x005c0ec0, 0x005c0ec4, 0x045c0cc4, 0x045c0cc0}, + {0x0002a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004}, + {0x0002a22c, 0x07e26a2f, 0x07e26a2f, 0x01026a2f, 0x01026a2f}, + {0x0002a230, 0x0000400a, 0x00004014, 0x00004016, 0x0000400b}, + {0x0002a234, 0x00000fff, 0x10000fff, 0x10000fff, 0x00000fff}, + {0x0002a238, 0xffb01018, 0xffb01018, 0xffb01018, 0xffb01018}, + {0x0002a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108}, + {0x0002a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898}, + {0x0002a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002}, + {0x0002a25c, 0x01000e0e, 0x01000e0e, 0x01010e0e, 0x01010e0e}, + {0x0002a260, 0x0a021501, 0x0a021501, 0x3a021501, 0x3a021501}, + {0x0002a264, 0x00000e0e, 0x00000e0e, 0x01000e0e, 0x01000e0e}, + {0x0002a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b}, + {0x0002a284, 0x00000000, 0x00000000, 0x00000010, 0x00000010}, + {0x0002a288, 0x00000110, 0x00000110, 0x00000110, 0x00000110}, + {0x0002a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222}, + {0x0002a2c4, 0x00058d18, 0x00058d18, 0x00058d18, 0x00058d18}, + {0x0002a2cc, 0x18c50033, 0x18c43433, 0x18c41033, 0x18c44c33}, + {0x0002a2d0, 0x00041982, 0x00041982, 0x00041982, 0x00041982}, + {0x0002a2d8, 0x7999a83b, 0x7999a83b, 0x7999a83b, 0x7999a83b}, + {0x0002a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, + {0x0002a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c}, + {0x0002ae04, 0x001c0000, 0x001c0000, 0x001c0000, 0x001c0000}, + {0x0002ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, + {0x0002ae1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c}, + {0x0002ae20, 0x000001b5, 0x000001b5, 0x000001a6, 0x000001a6}, + {0x0002b284, 0x00000000, 0x00000000, 0x00000010, 0x00000010}, + {0x0002b830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c}, + {0x0002be04, 0x001c0000, 0x001c0000, 0x001c0000, 0x001c0000}, + {0x0002be18, 0x00000000, 0x00000000, 0x00000000, 0x00000000}, + {0x0002be1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c}, + {0x0002be20, 0x000001b5, 0x000001b5, 0x000001a6, 0x000001a6}, + {0x0002c284, 0x00000000, 0x00000000, 0x00000010, 0x00000010}, +}; + +static const u32 qcn550x_1p0_radio_core[][2] = { + /* Addr allmodes */ + {0x00016000, 0x36db6db6}, + {0x00016004, 0x6db6db40}, + {0x00016008, 0x73f00000}, + {0x0001600c, 0x00000000}, + {0x00016040, 0x3f80fff8}, + {0x0001604c, 0x000f0278}, + {0x00016050, 0x8036db6c}, + {0x00016054, 0x6db60000}, + {0x00016080, 0x00080000}, + {0x00016084, 0x0e48048c}, + {0x00016088, 0x14214514}, + {0x0001608c, 0x119f080a}, + {0x00016090, 0x24926490}, + {0x00016094, 0x00000000}, + {0x000160a0, 0xc2108ffe}, + {0x000160a4, 0x812fc370}, + {0x000160a8, 0x423c8000}, + {0x000160b4, 0x92480000}, + {0x000160c0, 0x006db6d8}, + {0x000160c4, 0x24b6db6c}, + {0x000160c8, 0x6db6db6c}, + {0x000160cc, 0x6db6fb7c}, + {0x000160d0, 0x6db6da44}, + {0x00016100, 0x07ff8001}, + {0x00016108, 0x00080010}, + {0x00016144, 0x01884080}, + {0x00016148, 0x00008058}, + {0x00016288, 0x001c6000}, + {0x0001628c, 0x50000000}, + {0x00016290, 0x4b962100}, + {0x00016294, 0x00000480}, + {0x00016298, 0x04000144}, + {0x00016380, 0x00000000}, + {0x00016384, 0x00000000}, + {0x00016388, 0x00800700}, + {0x0001638c, 0x00800700}, + {0x00016390, 0x00800700}, + {0x00016394, 0x00000000}, + {0x00016398, 0x00000000}, + {0x0001639c, 0x00000000}, + {0x000163a0, 0x00000001}, + {0x000163a4, 0x00000001}, + {0x000163a8, 0x00000000}, + {0x000163ac, 0x00000000}, + {0x000163b0, 0x00000000}, + {0x000163b4, 0x00000000}, + {0x000163b8, 0x00000000}, + {0x000163bc, 0x00000000}, + {0x000163c0, 0x000000a0}, + {0x000163c4, 0x000c0000}, + {0x000163c8, 0x14021402}, + {0x000163cc, 0x00001402}, + {0x000163d0, 0x00000000}, + {0x000163d4, 0x00000000}, + {0x00016400, 0x36db6db6}, + {0x00016404, 0x6db6db40}, + {0x00016408, 0x73f00000}, + {0x0001640c, 0x00000000}, + {0x00016440, 0x3f80fff8}, + {0x0001644c, 0x000f0278}, + {0x00016450, 0x8036db6c}, + {0x00016454, 0x6db60000}, + {0x00016500, 0x07ff8001}, + {0x00016508, 0x00080010}, + {0x00016544, 0x01884080}, + {0x00016548, 0x00008058}, + {0x00016780, 0x00000000}, + {0x00016784, 0x00000000}, + {0x00016788, 0x00800700}, + {0x0001678c, 0x00800700}, + {0x00016790, 0x00800700}, + {0x00016794, 0x00000000}, + {0x00016798, 0x00000000}, + {0x0001679c, 0x00000000}, + {0x000167a0, 0x00000001}, + {0x000167a4, 0x00000001}, + {0x000167a8, 0x00000000}, + {0x000167ac, 0x00000000}, + {0x000167b0, 0x00000000}, + {0x000167b4, 0x00000000}, + {0x000167b8, 0x00000000}, + {0x000167bc, 0x00000000}, + {0x000167c0, 0x000000a0}, + {0x000167c4, 0x000c0000}, + {0x000167c8, 0x14021402}, + {0x000167cc, 0x00001402}, + {0x000167d0, 0x00000000}, + {0x000167d4, 0x00000000}, + {0x00016800, 0x36db6db6}, + {0x00016804, 0x6db6db40}, + {0x00016808, 0x73f00000}, + {0x0001680c, 0x00000000}, + {0x00016840, 0x3f80fff8}, + {0x0001684c, 0x000f0278}, + {0x00016850, 0x8036db6c}, + {0x00016854, 0x6db60000}, + {0x00016900, 0x07ff8001}, + {0x00016908, 0x00080010}, + {0x00016944, 0x01884080}, + {0x00016948, 0x00008058}, + {0x00016b80, 0x00000000}, + {0x00016b84, 0x00000000}, + {0x00016b88, 0x00800700}, + {0x00016b8c, 0x00800700}, + {0x00016b90, 0x00800700}, + {0x00016b94, 0x00000000}, + {0x00016b98, 0x00000000}, + {0x00016b9c, 0x00000000}, + {0x00016ba0, 0x00000001}, + {0x00016ba4, 0x00000001}, + {0x00016ba8, 0x00000000}, + {0x00016bac, 0x00000000}, + {0x00016bb0, 0x00000000}, + {0x00016bb4, 0x00000000}, + {0x00016bb8, 0x00000000}, + {0x00016bbc, 0x00000000}, + {0x00016bc0, 0x000000a0}, + {0x00016bc4, 0x000c0000}, + {0x00016bc8, 0x14021402}, + {0x00016bcc, 0x00001402}, + {0x00016bd0, 0x00000000}, + {0x00016bd4, 0x00000000}, +}; + +#define qcn550x_1p0_radio_postamble qca956x_1p0_radio_postamble + +static const u32 qcn550x_1p0_baseband_core_txfir_coeff_japan_2484[][2] = { + /* Addr allmodes */ + {0x0002a38c, 0x00000000}, + {0x0002a390, 0x6f7f0301}, + {0x0002a394, 0xca9228ee}, +}; + +static const u32 qcn550x_1p0_modes_no_xpa_tx_gain_table[][3] = { + /* Addr 5G 2G */ + {0x0002a2dc, 0xffa9ac94, 0xffa9ac94}, + {0x0002a2e0, 0xff323118, 0xff323118}, + {0x0002a2e4, 0xff3ffe00, 0xff3ffe00}, + {0x0002a2e8, 0xffc00000, 0xffc00000}, + {0x0002a39c, 0x42424242, 0x42424242}, + {0x0002a3a4, 0x3a3e3e00, 0x3a3e3e00}, + {0x0002a3b0, 0x00a01404, 0x00a01404}, + {0x0002a3b4, 0x00000034, 0x00000034}, + {0x0002a3b8, 0x00800408, 0x00800408}, + {0x0002a3bc, 0x00000036, 0x00000036}, + {0x0002a410, 0x000050dc, 0x000050dc}, + {0x0002a500, 0x09000040, 0x09000040}, + {0x0002a504, 0x0b000041, 0x0b000041}, + {0x0002a508, 0x0d000042, 0x0d000042}, + {0x0002a50c, 0x11000044, 0x11000044}, + {0x0002a510, 0x15000046, 0x15000046}, + {0x0002a514, 0x1d000440, 0x1d000440}, + {0x0002a518, 0x1f000441, 0x1f000441}, + {0x0002a51c, 0x23000443, 0x23000443}, + {0x0002a520, 0x25000444, 0x25000444}, + {0x0002a524, 0x280004e0, 0x280004e0}, + {0x0002a528, 0x2c0004e2, 0x2c0004e2}, + {0x0002a52c, 0x2e0004e3, 0x2e0004e3}, + {0x0002a530, 0x300004e4, 0x300004e4}, + {0x0002a534, 0x340004e6, 0x340004e6}, + {0x0002a538, 0x37000ce0, 0x37000ce0}, + {0x0002a53c, 0x3b000ce2, 0x3b000ce2}, + {0x0002a540, 0x3d000ce3, 0x3d000ce3}, + {0x0002a544, 0x3f000ce4, 0x3f000ce4}, + {0x0002a548, 0x45001ee0, 0x45001ee0}, + {0x0002a54c, 0x49001ee2, 0x49001ee2}, + {0x0002a550, 0x4d001ee4, 0x4d001ee4}, + {0x0002a554, 0x51001ee6, 0x51001ee6}, + {0x0002a558, 0x55001eea, 0x55001eea}, + {0x0002a55c, 0x59001eec, 0x59001eec}, + {0x0002a560, 0x5d001ef0, 0x5d001ef0}, + {0x0002a564, 0x5f001ef1, 0x5f001ef1}, + {0x0002a568, 0x60001ef2, 0x60001ef2}, + {0x0002a56c, 0x61001ef3, 0x61001ef3}, + {0x0002a570, 0x62001ef4, 0x62001ef4}, + {0x0002a574, 0x63001ef5, 0x63001ef5}, + {0x0002a578, 0x64001ffc, 0x64001ffc}, + {0x0002a57c, 0x64001ffc, 0x64001ffc}, + {0x0002a600, 0x00000000, 0x00000000}, + {0x0002a604, 0x00000000, 0x00000000}, + {0x0002a608, 0x00000000, 0x00000000}, + {0x0002a60c, 0x00000000, 0x00000000}, + {0x0002a610, 0x00804000, 0x00804000}, + {0x0002a614, 0x00804201, 0x00804201}, + {0x0002a618, 0x00804201, 0x00804201}, + {0x0002a61c, 0x00804201, 0x00804201}, + {0x0002a620, 0x00804201, 0x00804201}, + {0x0002a624, 0x00804201, 0x00804201}, + {0x0002a628, 0x00804201, 0x00804201}, + {0x0002a62c, 0x02808a02, 0x02808a02}, + {0x0002a630, 0x0340cd03, 0x0340cd03}, + {0x0002a634, 0x0340cd03, 0x0340cd03}, + {0x0002a638, 0x0340cd03, 0x0340cd03}, + {0x0002a63c, 0x05011404, 0x05011404}, + {0x0002b2dc, 0xffa9ac94, 0xffa9ac94}, + {0x0002b2e0, 0xff323118, 0xff323118}, + {0x0002b2e4, 0xff3ffe00, 0xff3ffe00}, + {0x0002b2e8, 0xffc00000, 0xffc00000}, + {0x0002c2dc, 0xffa9ac94, 0xffa9ac94}, + {0x0002c2e0, 0xff323118, 0xff323118}, + {0x0002c2e4, 0xff3ffe00, 0xff3ffe00}, + {0x0002c2e8, 0xffc00000, 0xffc00000}, + {0x00016044, 0x049242db, 0x049242db}, + {0x00016048, 0x64925a70, 0x64925a70}, + {0x00016148, 0x00008050, 0x00008050}, + {0x00016280, 0x41110005, 0x41110005}, + {0x00016284, 0x45226000, 0x45226000}, + {0x00016444, 0x049242db, 0x049242db}, + {0x00016448, 0x6c925a70, 0x6c925a70}, + {0x00016548, 0x00008050, 0x00008050}, + {0x00016844, 0x049242db, 0x049242db}, + {0x00016848, 0x6c925a70, 0x6c925a70}, + {0x00016948, 0x00008050, 0x00008050}, +}; + +static const u32 qcn550x_1p0_modes_xpa_tx_gain_table[][3] = { + /* Addr 5G 2G */ + {0x0002a2dc, 0xcc69ac94, 0xcc69ac94}, + {0x0002a2e0, 0xf0b23118, 0xf0b23118}, + {0x0002a2e4, 0xffffc000, 0xffffc000}, + {0x0002a2e8, 0xc0000000, 0xc0000000}, + {0x0002a410, 0x000050d2, 0x000050d2}, + {0x0002a500, 0x0a000040, 0x0a000040}, + {0x0002a504, 0x0c000041, 0x0c000041}, + {0x0002a508, 0x0e000042, 0x0e000042}, + {0x0002a50c, 0x12000044, 0x12000044}, + {0x0002a510, 0x16000046, 0x16000046}, + {0x0002a514, 0x1d000440, 0x1d000440}, + {0x0002a518, 0x1f000441, 0x1f000441}, + {0x0002a51c, 0x23000443, 0x23000443}, + {0x0002a520, 0x25000444, 0x25000444}, + {0x0002a524, 0x29000a40, 0x29000a40}, + {0x0002a528, 0x2d000a42, 0x2d000a42}, + {0x0002a52c, 0x2f000a43, 0x2f000a43}, + {0x0002a530, 0x31000a44, 0x31000a44}, + {0x0002a534, 0x35000a46, 0x35000a46}, + {0x0002a538, 0x38000ce0, 0x38000ce0}, + {0x0002a53c, 0x3c000ce2, 0x3c000ce2}, + {0x0002a540, 0x3e000ce3, 0x3e000ce3}, + {0x0002a544, 0x40000ce4, 0x40000ce4}, + {0x0002a548, 0x46001ee0, 0x46001ee0}, + {0x0002a54c, 0x4a001ee2, 0x4a001ee2}, + {0x0002a550, 0x4e001ee4, 0x4e001ee4}, + {0x0002a554, 0x52001ee6, 0x52001ee6}, + {0x0002a558, 0x56001eea, 0x56001eea}, + {0x0002a55c, 0x5a001eec, 0x5a001eec}, + {0x0002a560, 0x5e001ef0, 0x5e001ef0}, + {0x0002a564, 0x60001ef1, 0x60001ef1}, + {0x0002a568, 0x61001ef2, 0x61001ef2}, + {0x0002a56c, 0x62001ef3, 0x62001ef3}, + {0x0002a570, 0x63001ef4, 0x63001ef4}, + {0x0002a574, 0x64001ef5, 0x64001ef5}, + {0x0002a578, 0x65001ffc, 0x65001ffc}, + {0x0002a57c, 0x65001ffc, 0x65001ffc}, + {0x0002a600, 0x00000000, 0x00000000}, + {0x0002a604, 0x00000000, 0x00000000}, + {0x0002a608, 0x00000000, 0x00000000}, + {0x0002a60c, 0x00000000, 0x00000000}, + {0x0002a610, 0x00000000, 0x00000000}, + {0x0002a614, 0x00000000, 0x00000000}, + {0x0002a618, 0x00000000, 0x00000000}, + {0x0002a61c, 0x00804201, 0x00804201}, + {0x0002a620, 0x00804201, 0x00804201}, + {0x0002a624, 0x00804201, 0x00804201}, + {0x0002a628, 0x00804201, 0x00804201}, + {0x0002a62c, 0x02808a02, 0x02808a02}, + {0x0002a630, 0x0340cd03, 0x0340cd03}, + {0x0002a634, 0x0340cd03, 0x0340cd03}, + {0x0002a638, 0x0340cd03, 0x0340cd03}, + {0x0002a63c, 0x05011404, 0x05011404}, + {0x0002b2dc, 0xcc69ac94, 0xcc69ac94}, + {0x0002b2e0, 0xf0b23118, 0xf0b23118}, + {0x0002b2e4, 0xffffc000, 0xffffc000}, + {0x0002b2e8, 0xc0000000, 0xc0000000}, + {0x0002c2dc, 0xcc69ac94, 0xcc69ac94}, + {0x0002c2e0, 0xf0b23118, 0xf0b23118}, + {0x0002c2e4, 0xffffc000, 0xffffc000}, + {0x0002c2e8, 0xc0000000, 0xc0000000}, + {0x00016044, 0x012492db, 0x012492db}, + {0x00016048, 0x6c927a70, 0x6c927a70}, + {0x00016050, 0x8036d36c, 0x8036d36c}, + {0x00016280, 0x41110005, 0x41110005}, + {0x00016284, 0x45227e00, 0x45227e00}, + {0x00016444, 0x012492db, 0x012492db}, + {0x00016448, 0x6c927a70, 0x6c927a70}, + {0x00016450, 0x8036d36c, 0x8036d36c}, + {0x00016844, 0x012492db, 0x012492db}, + {0x00016848, 0x6c927a70, 0x6c927a70}, + {0x00016850, 0x8036d36c, 0x8036d36c}, +}; + +static const u32 qcn550x_1p0_modes_no_xpa_low_ob_db_tx_gain_table[][3] = { + /* Addr 5G 2G */ + {0x0002a2dc, 0xffa9ac94, 0xffa9ac94}, + {0x0002a2e0, 0xff323118, 0xff323118}, + {0x0002a2e4, 0xff3ffe00, 0xff3ffe00}, + {0x0002a2e8, 0xffc00000, 0xffc00000}, + {0x0002a39c, 0x42424242, 0x42424242}, + {0x0002a3a4, 0x3a3e3e00, 0x3a3e3e00}, + {0x0002a3b0, 0x00a01404, 0x00a01404}, + {0x0002a3b4, 0x00000034, 0x00000034}, + {0x0002a3b8, 0x00800408, 0x00800408}, + {0x0002a3bc, 0x00000036, 0x00000036}, + {0x0002a410, 0x000050dc, 0x000050dc}, + {0x0002a414, 0x16b739ce, 0x16b739ce}, + {0x0002a418, 0x2d00198b, 0x2d00198b}, + {0x0002a41c, 0x16b5adce, 0x16b5adce}, + {0x0002a420, 0x0000014a, 0x0000014a}, + {0x0002a424, 0x14a525cc, 0x14a525cc}, + {0x0002a428, 0x0000012a, 0x0000012a}, + {0x0002a42c, 0x14a5294a, 0x14a5294a}, + {0x0002a430, 0x1294a929, 0x1294a929}, + {0x0002a500, 0x09000040, 0x09000040}, + {0x0002a504, 0x0b000041, 0x0b000041}, + {0x0002a508, 0x0d000042, 0x0d000042}, + {0x0002a50c, 0x11000044, 0x11000044}, + {0x0002a510, 0x15000046, 0x15000046}, + {0x0002a514, 0x1d000440, 0x1d000440}, + {0x0002a518, 0x1f000441, 0x1f000441}, + {0x0002a51c, 0x23000443, 0x23000443}, + {0x0002a520, 0x25000444, 0x25000444}, + {0x0002a524, 0x280004e0, 0x280004e0}, + {0x0002a528, 0x2c0004e2, 0x2c0004e2}, + {0x0002a52c, 0x2e0004e3, 0x2e0004e3}, + {0x0002a530, 0x300004e4, 0x300004e4}, + {0x0002a534, 0x340004e6, 0x340004e6}, + {0x0002a538, 0x37000ce0, 0x37000ce0}, + {0x0002a53c, 0x3b000ce2, 0x3b000ce2}, + {0x0002a540, 0x3d000ce3, 0x3d000ce3}, + {0x0002a544, 0x3f000ce4, 0x3f000ce4}, + {0x0002a548, 0x45001ee0, 0x45001ee0}, + {0x0002a54c, 0x49001ee2, 0x49001ee2}, + {0x0002a550, 0x4d001ee4, 0x4d001ee4}, + {0x0002a554, 0x51001ee6, 0x51001ee6}, + {0x0002a558, 0x55001eea, 0x55001eea}, + {0x0002a55c, 0x59001eec, 0x59001eec}, + {0x0002a560, 0x5d001ef0, 0x5d001ef0}, + {0x0002a564, 0x5f001ef1, 0x5f001ef1}, + {0x0002a568, 0x60001ef2, 0x60001ef2}, + {0x0002a56c, 0x61001ef3, 0x61001ef3}, + {0x0002a570, 0x62001ef4, 0x62001ef4}, + {0x0002a574, 0x63001ef5, 0x63001ef5}, + {0x0002a578, 0x64001ffc, 0x64001ffc}, + {0x0002a57c, 0x64001ffc, 0x64001ffc}, + {0x0002a600, 0x00000000, 0x00000000}, + {0x0002a604, 0x00000000, 0x00000000}, + {0x0002a608, 0x00000000, 0x00000000}, + {0x0002a60c, 0x00000000, 0x00000000}, + {0x0002a610, 0x00804000, 0x00804000}, + {0x0002a614, 0x00804201, 0x00804201}, + {0x0002a618, 0x00804201, 0x00804201}, + {0x0002a61c, 0x00804201, 0x00804201}, + {0x0002a620, 0x00804201, 0x00804201}, + {0x0002a624, 0x00804201, 0x00804201}, + {0x0002a628, 0x00804201, 0x00804201}, + {0x0002a62c, 0x02808a02, 0x02808a02}, + {0x0002a630, 0x0340cd03, 0x0340cd03}, + {0x0002a634, 0x0340cd03, 0x0340cd03}, + {0x0002a638, 0x0340cd03, 0x0340cd03}, + {0x0002a63c, 0x05011404, 0x05011404}, + {0x0002b2dc, 0xffa9ac94, 0xffa9ac94}, + {0x0002b2e0, 0xff323118, 0xff323118}, + {0x0002b2e4, 0xff3ffe00, 0xff3ffe00}, + {0x0002b2e8, 0xffc00000, 0xffc00000}, + {0x0002c2dc, 0xffa9ac94, 0xffa9ac94}, + {0x0002c2e0, 0xff323118, 0xff323118}, + {0x0002c2e4, 0xff3ffe00, 0xff3ffe00}, + {0x0002c2e8, 0xffc00000, 0xffc00000}, + {0x00016044, 0x046e42db, 0x046e42db}, + {0x00016048, 0x64925a70, 0x64925a70}, + {0x00016148, 0x00008050, 0x00008050}, + {0x00016280, 0x41110005, 0x41110005}, + {0x00016284, 0x45226000, 0x45226000}, + {0x00016444, 0x046e42db, 0x046e42db}, + {0x00016448, 0x6c925a70, 0x6c925a70}, + {0x00016548, 0x00008050, 0x00008050}, + {0x00016844, 0x046e42db, 0x046e42db}, + {0x00016848, 0x6c925a70, 0x6c925a70}, + {0x00016948, 0x00008050, 0x00008050}, +}; + +static const u32 qcn550x_1p0_modes_no_xpa_green_tx_gain_table[][3] = { + /* Addr 5G 2G */ + {0x000298bc, 0x00000001, 0x00000001}, + {0x0002a2dc, 0xd3555284, 0xd3555284}, + {0x0002a2e0, 0x1c666318, 0x1c666318}, + {0x0002a2e4, 0xe07bbc00, 0xe07bbc00}, + {0x0002a2e8, 0xff800000, 0xff800000}, + {0x0002a3a4, 0x3a3e3e00, 0x3a3e3e00}, + {0x0002a410, 0x000050dc, 0x000050dc}, + {0x0002a500, 0x02000040, 0x02000040}, + {0x0002a504, 0x04000041, 0x04000041}, + {0x0002a508, 0x06000042, 0x06000042}, + {0x0002a50c, 0x0a000044, 0x0a000044}, + {0x0002a510, 0x0c000045, 0x0c000045}, + {0x0002a514, 0x13000440, 0x13000440}, + {0x0002a518, 0x15000441, 0x15000441}, + {0x0002a51c, 0x19000443, 0x19000443}, + {0x0002a520, 0x1b000444, 0x1b000444}, + {0x0002a524, 0x1e0004e0, 0x1e0004e0}, + {0x0002a528, 0x220004e2, 0x220004e2}, + {0x0002a52c, 0x240004e3, 0x240004e3}, + {0x0002a530, 0x260004e4, 0x260004e4}, + {0x0002a534, 0x2a0004e6, 0x2a0004e6}, + {0x0002a538, 0x32000ce0, 0x32000ce0}, + {0x0002a53c, 0x36000ce2, 0x36000ce2}, + {0x0002a540, 0x3a000ce4, 0x3a000ce4}, + {0x0002a544, 0x3e000ce6, 0x3e000ce6}, + {0x0002a548, 0x45001ee0, 0x45001ee0}, + {0x0002a54c, 0x49001ee2, 0x49001ee2}, + {0x0002a550, 0x4d001ee4, 0x4d001ee4}, + {0x0002a554, 0x51001ee6, 0x51001ee6}, + {0x0002a558, 0x55001eea, 0x55001eea}, + {0x0002a55c, 0x59001eec, 0x59001eec}, + {0x0002a560, 0x5d001ef0, 0x5d001ef0}, + {0x0002a564, 0x5f001ef1, 0x5f001ef1}, + {0x0002a568, 0x60001ef2, 0x60001ef2}, + {0x0002a56c, 0x61001ef3, 0x61001ef3}, + {0x0002a570, 0x62001ef4, 0x62001ef4}, + {0x0002a574, 0x63001ff5, 0x63001ff5}, + {0x0002a578, 0x64001ffc, 0x64001ffc}, + {0x0002a57c, 0x64001ffc, 0x64001ffc}, + {0x0002a600, 0x00000000, 0x00000000}, + {0x0002a604, 0x00000000, 0x00000000}, + {0x0002a608, 0x00000000, 0x00000000}, + {0x0002a60c, 0x00000000, 0x00000000}, + {0x0002a610, 0x00804000, 0x00804000}, + {0x0002a614, 0x00804201, 0x00804201}, + {0x0002a618, 0x00804201, 0x00804201}, + {0x0002a61c, 0x00804201, 0x00804201}, + {0x0002a620, 0x00804201, 0x00804201}, + {0x0002a624, 0x00804201, 0x00804201}, + {0x0002a628, 0x00804201, 0x00804201}, + {0x0002a62c, 0x02808a02, 0x02808a02}, + {0x0002a630, 0x0340cd03, 0x0340cd03}, + {0x0002a634, 0x0340cd03, 0x0340cd03}, + {0x0002a638, 0x0340cd03, 0x0340cd03}, + {0x0002a63c, 0x05011404, 0x05011404}, + {0x0002b2dc, 0xd3555284, 0xd3555284}, + {0x0002b2e0, 0x1c666318, 0x1c666318}, + {0x0002b2e4, 0xe07bbc00, 0xe07bbc00}, + {0x0002b2e8, 0xff800000, 0xff800000}, + {0x0002c2dc, 0xd3555284, 0xd3555284}, + {0x0002c2e0, 0x1c666318, 0x1c666318}, + {0x0002c2e4, 0xe07bbc00, 0xe07bbc00}, + {0x0002c2e8, 0xff800000, 0xff800000}, + {0x00016044, 0x849242db, 0x849242db}, + {0x00016048, 0x64925a70, 0x64925a70}, + {0x00016280, 0x41110005, 0x41110005}, + {0x00016284, 0x45226000, 0x45226000}, + {0x00016444, 0x849242db, 0x849242db}, + {0x00016448, 0x6c925a70, 0x6c925a70}, + {0x00016844, 0x849242db, 0x849242db}, + {0x00016848, 0x6c925a70, 0x6c925a70}, + {0x0002a7f0, 0x800002cc, 0x800002cc}, + {0x0002a7f4, 0x00000018, 0x00000018}, + {0x0002a7f4, 0x00000018, 0x00000018}, + {0x0002a7f4, 0x00000018, 0x00000018}, + {0x0002a7f4, 0x00000018, 0x00000018}, + {0x0002a7f4, 0x00000018, 0x00000018}, + {0x0002a7f4, 0x00000018, 0x00000018}, + {0x0002a7f4, 0x00000018, 0x00000018}, + {0x0002a7f4, 0x00000018, 0x00000018}, + {0x0002a7f4, 0x00000018, 0x00000018}, + {0x0002a7f4, 0x00000018, 0x00000018}, + {0x0002a7f4, 0x00000018, 0x00000018}, + {0x0002a7f4, 0x00000018, 0x00000018}, + {0x0002a7f4, 0x00000018, 0x00000018}, + {0x0002a7f4, 0x00000018, 0x00000018}, + {0x0002a7f4, 0x00000028, 0x00000028}, + {0x0002a7f4, 0x00000028, 0x00000028}, + {0x0002a7f4, 0x00000028, 0x00000028}, + {0x0002a7f4, 0x00000028, 0x00000028}, + {0x0002a7f4, 0x00000048, 0x00000048}, + {0x0002a7f4, 0x00000048, 0x00000048}, + {0x0002a7f4, 0x00000048, 0x00000048}, + {0x0002a7f4, 0x00000048, 0x00000048}, + {0x0002a7f4, 0x00000048, 0x00000048}, + {0x0002a7f4, 0x00000048, 0x00000048}, + {0x0002a7f4, 0x00000048, 0x00000048}, + {0x0002a7f4, 0x00000048, 0x00000048}, + {0x0002a7f4, 0x00000048, 0x00000048}, + {0x0002a7f4, 0x00000048, 0x00000048}, + {0x0002a7f4, 0x00000048, 0x00000048}, + {0x0002a7f4, 0x00000048, 0x00000048}, + {0x0002a7f4, 0x00000048, 0x00000048}, + {0x0002a7f4, 0x00000048, 0x00000048}, +}; + +static const u32 qcn550x_1p0_common_rx_gain_table[][2] = { + /* Addr allmodes */ + {0x0002a000, 0x00010000}, + {0x0002a004, 0x00030002}, + {0x0002a008, 0x00050004}, + {0x0002a00c, 0x00810080}, + {0x0002a010, 0x00830082}, + {0x0002a014, 0x01810180}, + {0x0002a018, 0x01830182}, + {0x0002a01c, 0x01850184}, + {0x0002a020, 0x01890188}, + {0x0002a024, 0x018b018a}, + {0x0002a028, 0x018d018c}, + {0x0002a02c, 0x01910190}, + {0x0002a030, 0x01930192}, + {0x0002a034, 0x01950194}, + {0x0002a038, 0x038a0196}, + {0x0002a03c, 0x038c038b}, + {0x0002a040, 0x0390038d}, + {0x0002a044, 0x03920391}, + {0x0002a048, 0x03940393}, + {0x0002a04c, 0x03960395}, + {0x0002a050, 0x00000000}, + {0x0002a054, 0x00000000}, + {0x0002a058, 0x00000000}, + {0x0002a05c, 0x00000000}, + {0x0002a060, 0x00000000}, + {0x0002a064, 0x00000000}, + {0x0002a068, 0x00000000}, + {0x0002a06c, 0x00000000}, + {0x0002a070, 0x00000000}, + {0x0002a074, 0x00000000}, + {0x0002a078, 0x00000000}, + {0x0002a07c, 0x00000000}, + {0x0002a080, 0x22222222}, + {0x0002a084, 0x1d1d1d1d}, + {0x0002a088, 0x1d1d1d1d}, + {0x0002a08c, 0x1d1d1d1d}, + {0x0002a090, 0x17171717}, + {0x0002a094, 0x11111717}, + {0x0002a098, 0x00030311}, + {0x0002a09c, 0x00000000}, + {0x0002a0a0, 0x00000000}, + {0x0002a0a4, 0x00000000}, + {0x0002a0a8, 0x00000000}, + {0x0002a0ac, 0x00000000}, + {0x0002a0b0, 0x00000000}, + {0x0002a0b4, 0x00000000}, + {0x0002a0b8, 0x00000000}, + {0x0002a0bc, 0x00000000}, + {0x0002a0c0, 0x001f0000}, + {0x0002a0c4, 0x01000101}, + {0x0002a0c8, 0x011e011f}, + {0x0002a0cc, 0x011c011d}, + {0x0002a0d0, 0x02030204}, + {0x0002a0d4, 0x02010202}, + {0x0002a0d8, 0x021f0200}, + {0x0002a0dc, 0x0302021e}, + {0x0002a0e0, 0x03000301}, + {0x0002a0e4, 0x031e031f}, + {0x0002a0e8, 0x0402031d}, + {0x0002a0ec, 0x04000401}, + {0x0002a0f0, 0x041e041f}, + {0x0002a0f4, 0x0502041d}, + {0x0002a0f8, 0x05000501}, + {0x0002a0fc, 0x051e051f}, + {0x0002a100, 0x06010602}, + {0x0002a104, 0x061f0600}, + {0x0002a108, 0x061d061e}, + {0x0002a10c, 0x07020703}, + {0x0002a110, 0x07000701}, + {0x0002a114, 0x00000000}, + {0x0002a118, 0x00000000}, + {0x0002a11c, 0x00000000}, + {0x0002a120, 0x00000000}, + {0x0002a124, 0x00000000}, + {0x0002a128, 0x00000000}, + {0x0002a12c, 0x00000000}, + {0x0002a130, 0x00000000}, + {0x0002a134, 0x00000000}, + {0x0002a138, 0x00000000}, + {0x0002a13c, 0x00000000}, + {0x0002a140, 0x001f0000}, + {0x0002a144, 0x01000101}, + {0x0002a148, 0x011e011f}, + {0x0002a14c, 0x011c011d}, + {0x0002a150, 0x02030204}, + {0x0002a154, 0x02010202}, + {0x0002a158, 0x021f0200}, + {0x0002a15c, 0x0302021e}, + {0x0002a160, 0x03000301}, + {0x0002a164, 0x031e031f}, + {0x0002a168, 0x0402031d}, + {0x0002a16c, 0x04000401}, + {0x0002a170, 0x041e041f}, + {0x0002a174, 0x0502041d}, + {0x0002a178, 0x05000501}, + {0x0002a17c, 0x051e051f}, + {0x0002a180, 0x06010602}, + {0x0002a184, 0x061f0600}, + {0x0002a188, 0x061d061e}, + {0x0002a18c, 0x07020703}, + {0x0002a190, 0x07000701}, + {0x0002a194, 0x00000000}, + {0x0002a198, 0x00000000}, + {0x0002a19c, 0x00000000}, + {0x0002a1a0, 0x00000000}, + {0x0002a1a4, 0x00000000}, + {0x0002a1a8, 0x00000000}, + {0x0002a1ac, 0x00000000}, + {0x0002a1b0, 0x00000000}, + {0x0002a1b4, 0x00000000}, + {0x0002a1b8, 0x00000000}, + {0x0002a1bc, 0x00000000}, + {0x0002a1c0, 0x00000000}, + {0x0002a1c4, 0x00000000}, + {0x0002a1c8, 0x00000000}, + {0x0002a1cc, 0x00000000}, + {0x0002a1d0, 0x00000000}, + {0x0002a1d4, 0x00000000}, + {0x0002a1d8, 0x00000000}, + {0x0002a1dc, 0x00000000}, + {0x0002a1e0, 0x00000000}, + {0x0002a1e4, 0x00000000}, + {0x0002a1e8, 0x00000000}, + {0x0002a1ec, 0x00000000}, + {0x0002a1f0, 0x00000396}, + {0x0002a1f4, 0x00000396}, + {0x0002a1f8, 0x00000396}, + {0x0002a1fc, 0x00000196}, + {0x0002b000, 0x00010000}, + {0x0002b004, 0x00030002}, + {0x0002b008, 0x00050004}, + {0x0002b00c, 0x00810080}, + {0x0002b010, 0x00830082}, + {0x0002b014, 0x01810180}, + {0x0002b018, 0x01830182}, + {0x0002b01c, 0x01850184}, + {0x0002b020, 0x02810280}, + {0x0002b024, 0x02830282}, + {0x0002b028, 0x02850284}, + {0x0002b02c, 0x02890288}, + {0x0002b030, 0x028b028a}, + {0x0002b034, 0x0388028c}, + {0x0002b038, 0x038a0389}, + {0x0002b03c, 0x038c038b}, + {0x0002b040, 0x0390038d}, + {0x0002b044, 0x03920391}, + {0x0002b048, 0x03940393}, + {0x0002b04c, 0x03960395}, + {0x0002b050, 0x00000000}, + {0x0002b054, 0x00000000}, + {0x0002b058, 0x00000000}, + {0x0002b05c, 0x00000000}, + {0x0002b060, 0x00000000}, + {0x0002b064, 0x00000000}, + {0x0002b068, 0x00000000}, + {0x0002b06c, 0x00000000}, + {0x0002b070, 0x00000000}, + {0x0002b074, 0x00000000}, + {0x0002b078, 0x00000000}, + {0x0002b07c, 0x00000000}, + {0x0002b080, 0x23232323}, + {0x0002b084, 0x21232323}, + {0x0002b088, 0x19191c1e}, + {0x0002b08c, 0x12141417}, + {0x0002b090, 0x07070e0e}, + {0x0002b094, 0x03030305}, + {0x0002b098, 0x00000003}, + {0x0002b09c, 0x00000000}, + {0x0002b0a0, 0x00000000}, + {0x0002b0a4, 0x00000000}, + {0x0002b0a8, 0x00000000}, + {0x0002b0ac, 0x00000000}, + {0x0002b0b0, 0x00000000}, + {0x0002b0b4, 0x00000000}, + {0x0002b0b8, 0x00000000}, + {0x0002b0bc, 0x00000000}, + {0x0002b0c0, 0x003f0020}, + {0x0002b0c4, 0x00400041}, + {0x0002b0c8, 0x0140005f}, + {0x0002b0cc, 0x0160015f}, + {0x0002b0d0, 0x017e017f}, + {0x0002b0d4, 0x02410242}, + {0x0002b0d8, 0x025f0240}, + {0x0002b0dc, 0x027f0260}, + {0x0002b0e0, 0x0341027e}, + {0x0002b0e4, 0x035f0340}, + {0x0002b0e8, 0x037f0360}, + {0x0002b0ec, 0x04400441}, + {0x0002b0f0, 0x0460045f}, + {0x0002b0f4, 0x0541047f}, + {0x0002b0f8, 0x055f0540}, + {0x0002b0fc, 0x057f0560}, + {0x0002b100, 0x06400641}, + {0x0002b104, 0x0660065f}, + {0x0002b108, 0x067e067f}, + {0x0002b10c, 0x07410742}, + {0x0002b110, 0x075f0740}, + {0x0002b114, 0x077f0760}, + {0x0002b118, 0x07800781}, + {0x0002b11c, 0x07a0079f}, + {0x0002b120, 0x07c107bf}, + {0x0002b124, 0x000007c0}, + {0x0002b128, 0x00000000}, + {0x0002b12c, 0x00000000}, + {0x0002b130, 0x00000000}, + {0x0002b134, 0x00000000}, + {0x0002b138, 0x00000000}, + {0x0002b13c, 0x00000000}, + {0x0002b140, 0x003f0020}, + {0x0002b144, 0x00400041}, + {0x0002b148, 0x0140005f}, + {0x0002b14c, 0x0160015f}, + {0x0002b150, 0x017e017f}, + {0x0002b154, 0x02410242}, + {0x0002b158, 0x025f0240}, + {0x0002b15c, 0x027f0260}, + {0x0002b160, 0x0341027e}, + {0x0002b164, 0x035f0340}, + {0x0002b168, 0x037f0360}, + {0x0002b16c, 0x04400441}, + {0x0002b170, 0x0460045f}, + {0x0002b174, 0x0541047f}, + {0x0002b178, 0x055f0540}, + {0x0002b17c, 0x057f0560}, + {0x0002b180, 0x06400641}, + {0x0002b184, 0x0660065f}, + {0x0002b188, 0x067e067f}, + {0x0002b18c, 0x07410742}, + {0x0002b190, 0x075f0740}, + {0x0002b194, 0x077f0760}, + {0x0002b198, 0x07800781}, + {0x0002b19c, 0x07a0079f}, + {0x0002b1a0, 0x07c107bf}, + {0x0002b1a4, 0x000007c0}, + {0x0002b1a8, 0x00000000}, + {0x0002b1ac, 0x00000000}, + {0x0002b1b0, 0x00000000}, + {0x0002b1b4, 0x00000000}, + {0x0002b1b8, 0x00000000}, + {0x0002b1bc, 0x00000000}, + {0x0002b1c0, 0x00000000}, + {0x0002b1c4, 0x00000000}, + {0x0002b1c8, 0x00000000}, + {0x0002b1cc, 0x00000000}, + {0x0002b1d0, 0x00000000}, + {0x0002b1d4, 0x00000000}, + {0x0002b1d8, 0x00000000}, + {0x0002b1dc, 0x00000000}, + {0x0002b1e0, 0x00000000}, + {0x0002b1e4, 0x00000000}, + {0x0002b1e8, 0x00000000}, + {0x0002b1ec, 0x00000000}, + {0x0002b1f0, 0x00000396}, + {0x0002b1f4, 0x00000396}, + {0x0002b1f8, 0x00000396}, + {0x0002b1fc, 0x00000196}, +}; + +static const u32 qcn550x_1p0_xlna_only[][5] = { + /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */ + {0x00029820, 0x206a022e, 0x206a022e, 0x206a01ae, 0x206a01ae}, + {0x00029824, 0x5ac640d0, 0x5ac640d0, 0x5ac621f1, 0x5ac621f1}, + {0x00029828, 0x06903081, 0x06903081, 0x07d43881, 0x07d43881}, + {0x00029e00, 0x0372111a, 0x0372111a, 0x037216a0, 0x03721720}, + {0x00029e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000de, 0x6c4000da}, + {0x00029e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec86d2e, 0x7ec8ad2e}, + {0x00029e14, 0x37b95d5e, 0x37b9605e, 0x317a6062, 0x317a5ae2}, + {0x00029e18, 0x00000000, 0x00000000, 0x03c00000, 0x03c00000}, + {0x00029e20, 0x000003b5, 0x000003b5, 0x000003b2, 0x000003b2}, + {0x00029fc0, 0x813e4788, 0x813e4788, 0x813e4789, 0x813e4789}, + {0x0002ae18, 0x00000000, 0x00000000, 0x03c00000, 0x03c00000}, + {0x0002ae20, 0x000001b5, 0x000001b5, 0x000001b2, 0x000001b2}, + {0x0002be18, 0x00000000, 0x00000000, 0x03c00000, 0x03c00000}, + {0x0002be20, 0x000001b5, 0x000001b5, 0x000001b2, 0x000001b2}, +}; + +#endif /* INITVALS_550X_H */ diff --git a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c index 42f00a2a8..54a42da11 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c @@ -30,6 +30,7 @@ #include "ar9565_1p1_initvals.h" #include "ar953x_initvals.h" #include "ar956x_initvals.h" +#include "ar550x_initvals.h" /* General hardware code for the AR9003 hadware family */ @@ -410,6 +411,40 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) qca956x_1p0_baseband_core_txfir_coeff_japan_2484); INIT_INI_ARRAY(&ah->iniModesFastClock, qca956x_1p0_modes_fast_clock); + } else if (AR_SREV_5502(ah)) { + INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], + qcn550x_1p0_mac_core); + INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST], + qcn550x_1p0_mac_postamble); + + INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE], + qcn550x_1p0_baseband_core); + INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST], + qcn550x_1p0_baseband_postamble); + + INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE], + qcn550x_1p0_radio_core); + INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], + qcn550x_1p0_radio_postamble); + + INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE], + qcn550x_1p0_soc_preamble); + INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], + qcn550x_1p0_soc_postamble); + + INIT_INI_ARRAY(&ah->iniModesRxGain, + qcn550x_1p0_common_wo_xlna_rx_gain_table); + INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds, + qcn550x_1p0_common_wo_xlna_rx_gain_bounds); + INIT_INI_ARRAY(&ah->iniModesTxGain, + qcn550x_1p0_modes_no_xpa_tx_gain_table); + + INIT_INI_ARRAY(&ah->ini_dfs, + qcn550x_1p0_baseband_postamble_dfs_channel); + INIT_INI_ARRAY(&ah->iniCckfirJapan2484, + qcn550x_1p0_baseband_core_txfir_coeff_japan_2484); + INIT_INI_ARRAY(&ah->iniModesFastClock, + qcn550x_1p0_modes_fast_clock); } else if (AR_SREV_9580(ah)) { /* mac */ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], @@ -617,6 +652,9 @@ static void ar9003_tx_gain_table_mode0(struct ath_hw *ah) else if (AR_SREV_9561(ah)) INIT_INI_ARRAY(&ah->iniModesTxGain, qca956x_1p0_modes_xpa_tx_gain_table); + else if (AR_SREV_5502(ah)) + INIT_INI_ARRAY(&ah->iniModesTxGain, + qcn550x_1p0_modes_xpa_tx_gain_table); else if (AR_SREV_9580(ah)) INIT_INI_ARRAY(&ah->iniModesTxGain, ar9580_1p0_lowest_ob_db_tx_gain_table); @@ -670,6 +708,9 @@ static void ar9003_tx_gain_table_mode1(struct ath_hw *ah) } else if (AR_SREV_9561(ah)) INIT_INI_ARRAY(&ah->iniModesTxGain, qca956x_1p0_modes_no_xpa_tx_gain_table); + else if (AR_SREV_5502(ah)) + INIT_INI_ARRAY(&ah->iniModesTxGain, + qcn550x_1p0_modes_no_xpa_tx_gain_table); else if (AR_SREV_9462_21(ah)) INIT_INI_ARRAY(&ah->iniModesTxGain, ar9462_2p1_modes_high_ob_db_tx_gain); @@ -710,6 +751,9 @@ static void ar9003_tx_gain_table_mode2(struct ath_hw *ah) else if (AR_SREV_9561(ah)) INIT_INI_ARRAY(&ah->iniModesTxGain, qca956x_1p0_modes_no_xpa_low_ob_db_tx_gain_table); + else if (AR_SREV_5502(ah)) + INIT_INI_ARRAY(&ah->iniModesTxGain, + qcn550x_1p0_modes_no_xpa_low_ob_db_tx_gain_table); else if (AR_SREV_9565_11(ah)) INIT_INI_ARRAY(&ah->iniModesTxGain, ar9565_1p1_modes_low_ob_db_tx_gain_table); @@ -784,6 +828,9 @@ static void ar9003_tx_gain_table_mode5(struct ath_hw *ah) else if (AR_SREV_9561(ah)) INIT_INI_ARRAY(&ah->iniModesTxGain, qca956x_1p0_modes_no_xpa_green_tx_gain_table); + else if (AR_SREV_5502(ah)) + INIT_INI_ARRAY(&ah->iniModesTxGain, + qcn550x_1p0_modes_no_xpa_green_tx_gain_table); else if (AR_SREV_9300_22(ah)) INIT_INI_ARRAY(&ah->iniModesTxGain, ar9300Modes_type5_tx_gain_table_2p2); @@ -862,6 +909,13 @@ static void ar9003_rx_gain_table_mode0(struct ath_hw *ah) qca956x_1p0_common_rx_gain_bounds); INIT_INI_ARRAY(&ah->ini_modes_rxgain_xlna, qca956x_1p0_xlna_only); + } else if (AR_SREV_5502(ah)) { + INIT_INI_ARRAY(&ah->iniModesRxGain, + qcn550x_1p0_common_rx_gain_table); + INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds, + qcn550x_1p0_common_rx_gain_bounds); + INIT_INI_ARRAY(&ah->ini_modes_rxgain_xlna, + qcn550x_1p0_xlna_only); } else if (AR_SREV_9580(ah)) INIT_INI_ARRAY(&ah->iniModesRxGain, ar9580_1p0_rx_gain_table); @@ -922,6 +976,11 @@ static void ar9003_rx_gain_table_mode1(struct ath_hw *ah) qca956x_1p0_common_wo_xlna_rx_gain_table); INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds, qca956x_1p0_common_wo_xlna_rx_gain_bounds); + } else if (AR_SREV_5502(ah)) { + INIT_INI_ARRAY(&ah->iniModesRxGain, + qcn550x_1p0_common_wo_xlna_rx_gain_table); + INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds, + qcn550x_1p0_common_wo_xlna_rx_gain_bounds); } else if (AR_SREV_9580(ah)) INIT_INI_ARRAY(&ah->iniModesRxGain, ar9580_1p0_wo_xlna_rx_gain_table); -- 2.25.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 4/9] ath9k: implement QCN550x rx 2022-04-18 7:13 [PATCH 0/9] ath9k: add support for QCN550x Wenli Looi ` (2 preceding siblings ...) 2022-04-18 7:13 ` [PATCH 3/9] ath9k: add QCN550x initvals Wenli Looi @ 2022-04-18 7:13 ` Wenli Looi 2022-04-18 7:13 ` [PATCH 5/9] ath9k: implement QCN550x tx Wenli Looi ` (5 subsequent siblings) 9 siblings, 0 replies; 15+ messages in thread From: Wenli Looi @ 2022-04-18 7:13 UTC (permalink / raw) To: Toke Høiland-Jørgensen Cc: Kalle Valo, linux-wireless, ath9k-devel, Wenli Looi ar9003_rxs in this device has 2 additional status values. --- drivers/net/wireless/ath/ath9k/ar9003_mac.c | 37 +++++++++++---------- drivers/net/wireless/ath/ath9k/ar9003_mac.h | 6 ++++ drivers/net/wireless/ath/ath9k/hw.c | 4 ++- drivers/net/wireless/ath/ath9k/reg.h | 1 + 4 files changed, 30 insertions(+), 18 deletions(-) diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mac.c b/drivers/net/wireless/ath/ath9k/ar9003_mac.c index ff8ab58e6..059e4bfce 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_mac.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c @@ -483,8 +483,11 @@ int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs, { struct ar9003_rxs *rxsp = buf_addr; unsigned int phyerr; + /* status12 and status13 are only present in ar9300_rxs V2. */ + u32 last_status = + AR_SREV_AR9003_RXS_V2(ah) ? rxsp->status13 : rxsp->status11; - if ((rxsp->status11 & AR_RxDone) == 0) + if ((last_status & AR_RxDone) == 0) return -EINPROGRESS; if (MS(rxsp->ds_info, AR_DescId) != 0x168c) @@ -510,17 +513,17 @@ int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs, rxs->rs_rssi_ext[1] = MS(rxsp->status5, AR_RxRSSIAnt11); rxs->rs_rssi_ext[2] = MS(rxsp->status5, AR_RxRSSIAnt12); - if (rxsp->status11 & AR_RxKeyIdxValid) - rxs->rs_keyix = MS(rxsp->status11, AR_KeyIdx); + if (last_status & AR_RxKeyIdxValid) + rxs->rs_keyix = MS(last_status, AR_KeyIdx); else rxs->rs_keyix = ATH9K_RXKEYIX_INVALID; rxs->rs_rate = MS(rxsp->status1, AR_RxRate); rxs->rs_more = (rxsp->status2 & AR_RxMore) ? 1 : 0; - rxs->rs_firstaggr = (rxsp->status11 & AR_RxFirstAggr) ? 1 : 0; - rxs->rs_isaggr = (rxsp->status11 & AR_RxAggr) ? 1 : 0; - rxs->rs_moreaggr = (rxsp->status11 & AR_RxMoreAggr) ? 1 : 0; + rxs->rs_firstaggr = (last_status & AR_RxFirstAggr) ? 1 : 0; + rxs->rs_isaggr = (last_status & AR_RxAggr) ? 1 : 0; + rxs->rs_moreaggr = (last_status & AR_RxMoreAggr) ? 1 : 0; rxs->rs_antenna = (MS(rxsp->status4, AR_RxAntenna) & 0x7); rxs->enc_flags |= (rxsp->status4 & AR_GI) ? RX_ENC_FLAG_SHORT_GI : 0; rxs->enc_flags |= @@ -533,16 +536,16 @@ int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs, rxs->evm3 = rxsp->status9; rxs->evm4 = (rxsp->status10 & 0xffff); - if (rxsp->status11 & AR_PreDelimCRCErr) + if (last_status & AR_PreDelimCRCErr) rxs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE; - if (rxsp->status11 & AR_PostDelimCRCErr) + if (last_status & AR_PostDelimCRCErr) rxs->rs_flags |= ATH9K_RX_DELIM_CRC_POST; - if (rxsp->status11 & AR_DecryptBusyErr) + if (last_status & AR_DecryptBusyErr) rxs->rs_flags |= ATH9K_RX_DECRYPT_BUSY; - if ((rxsp->status11 & AR_RxFrameOK) == 0) { + if ((last_status & AR_RxFrameOK) == 0) { /* * AR_CRCErr will bet set to true if we're on the last * subframe and the AR_PostDelimCRCErr is caught. @@ -551,14 +554,14 @@ int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs, * possibly be reviewing the last subframe. AR_CRCErr * is the CRC of the actual data. */ - if (rxsp->status11 & AR_CRCErr) + if (last_status & AR_CRCErr) rxs->rs_status |= ATH9K_RXERR_CRC; - else if (rxsp->status11 & AR_DecryptCRCErr) + else if (last_status & AR_DecryptCRCErr) rxs->rs_status |= ATH9K_RXERR_DECRYPT; - else if (rxsp->status11 & AR_MichaelErr) + else if (last_status & AR_MichaelErr) rxs->rs_status |= ATH9K_RXERR_MIC; - if (rxsp->status11 & AR_PHYErr) { - phyerr = MS(rxsp->status11, AR_PHYErrCode); + if (last_status & AR_PHYErr) { + phyerr = MS(last_status, AR_PHYErrCode); /* * If we reach a point here where AR_PostDelimCRCErr is * true it implies we're *not* on the last subframe. In @@ -573,7 +576,7 @@ int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs, * delimiter for an A-MPDU subframe (0x4E = 'N' ASCII). */ if ((phyerr == ATH9K_PHYERR_OFDM_RESTART) && - (rxsp->status11 & AR_PostDelimCRCErr)) { + (last_status & AR_PostDelimCRCErr)) { rxs->rs_phyerr = 0; } else { rxs->rs_status |= ATH9K_RXERR_PHY; @@ -582,7 +585,7 @@ int ath9k_hw_process_rxdesc_edma(struct ath_hw *ah, struct ath_rx_status *rxs, } } - if (rxsp->status11 & AR_KeyMiss) + if (last_status & AR_KeyMiss) rxs->rs_status |= ATH9K_RXERR_KEYMISS; return 0; diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mac.h b/drivers/net/wireless/ath/ath9k/ar9003_mac.h index cbf60b090..07f073821 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_mac.h +++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.h @@ -65,8 +65,14 @@ struct ar9003_rxs { u32 status9; u32 status10; u32 status11; + /* status12 and status13 are only present in ar9003_rxs V2. */ + u32 status12; + u32 status13; } __packed __aligned(4); +#define AR9003_RXS_SIZE_V1 (12 * sizeof(u32)) +#define AR9003_RXS_SIZE_V2 (sizeof(struct ar9003_rxs)) + /* Transmit Control Descriptor */ struct ar9003_txc { u32 info; /* descriptor information */ diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c index c32b201a3..df59bea41 100644 --- a/drivers/net/wireless/ath/ath9k/hw.c +++ b/drivers/net/wireless/ath/ath9k/hw.c @@ -2621,7 +2621,9 @@ int ath9k_hw_fill_cap_info(struct ath_hw *ah) pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH; pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH; - pCap->rx_status_len = sizeof(struct ar9003_rxs); + pCap->rx_status_len = AR_SREV_AR9003_RXS_V2(ah) ? + AR9003_RXS_SIZE_V2 : + AR9003_RXS_SIZE_V1; pCap->tx_desc_len = sizeof(struct ar9003_txc); pCap->txs_len = sizeof(struct ar9003_txs); } else { diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h index d465167ac..5ec263b7f 100644 --- a/drivers/net/wireless/ath/ath9k/reg.h +++ b/drivers/net/wireless/ath/ath9k/reg.h @@ -999,6 +999,7 @@ #define AR_SREV_SOC(_ah) \ (AR_SREV_9340(_ah) || AR_SREV_9531(_ah) || AR_SREV_9550(_ah) || \ AR_SREV_9561(_ah) || AR_SREV_5502(_ah)) +#define AR_SREV_AR9003_RXS_V2(_ah) (AR_SREV_5502(_ah)) /* NOTE: When adding chips newer than Peacock, add chip check here */ #define AR_SREV_9580_10_OR_LATER(_ah) \ -- 2.25.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 5/9] ath9k: implement QCN550x tx 2022-04-18 7:13 [PATCH 0/9] ath9k: add support for QCN550x Wenli Looi ` (3 preceding siblings ...) 2022-04-18 7:13 ` [PATCH 4/9] ath9k: implement QCN550x rx Wenli Looi @ 2022-04-18 7:13 ` Wenli Looi 2022-04-18 7:13 ` [PATCH 6/9] ath9k: group some ar9300 eeprom functions at the top Wenli Looi ` (4 subsequent siblings) 9 siblings, 0 replies; 15+ messages in thread From: Wenli Looi @ 2022-04-18 7:13 UTC (permalink / raw) To: Toke Høiland-Jørgensen Cc: Kalle Valo, linux-wireless, ath9k-devel, Wenli Looi --- drivers/net/wireless/ath/ath9k/ar9003_mac.c | 42 +++++++++++++++------ drivers/net/wireless/ath/ath9k/ar9003_mac.h | 4 ++ drivers/net/wireless/ath/ath9k/mac.h | 12 ++++++ 3 files changed, 47 insertions(+), 11 deletions(-) diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mac.c b/drivers/net/wireless/ath/ath9k/ar9003_mac.c index 059e4bfce..6f63dc940 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_mac.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.c @@ -28,7 +28,7 @@ ar9003_set_txdesc(struct ath_hw *ah, void *ds, struct ath_tx_info *i) { struct ar9003_txc *ads = ds; int checksum = 0; - u32 val, ctl12, ctl17; + u32 val, ctl12, ctl17, ctl18; u8 desc_len; desc_len = ((AR_SREV_9462(ah) || AR_SREV_9565(ah)) ? 0x18 : 0x17); @@ -132,8 +132,21 @@ ar9003_set_txdesc(struct ath_hw *ah, void *ds, struct ath_tx_info *i) break; } + ctl18 = set11nRateFlags(i->rates, 0) + | set11nRateFlags(i->rates, 1) + | set11nRateFlags(i->rates, 2) + | set11nRateFlags(i->rates, 3) + | SM(i->rtscts_rate, AR_RTSCTSRate); + val = (i->flags & ATH9K_TXDESC_PAPRD) >> ATH9K_TXDESC_PAPRD_S; - ctl12 |= SM(val, AR_PAPRDChainMask); + + if (!AR_SREV_5502(ah)) { + ctl12 |= SM(val, AR_PAPRDChainMask); + ctl18 |= set11nChainSel(i->rates, 0) + | set11nChainSel(i->rates, 1) + | set11nChainSel(i->rates, 2) + | set11nChainSel(i->rates, 3); + } WRITE_ONCE(ads->ctl12, ctl12); WRITE_ONCE(ads->ctl17, ctl17); @@ -144,18 +157,20 @@ ar9003_set_txdesc(struct ath_hw *ah, void *ds, struct ath_tx_info *i) WRITE_ONCE(ads->ctl16, set11nPktDurRTSCTS(i->rates, 2) | set11nPktDurRTSCTS(i->rates, 3)); - WRITE_ONCE(ads->ctl18, - set11nRateFlags(i->rates, 0) | set11nChainSel(i->rates, 0) - | set11nRateFlags(i->rates, 1) | set11nChainSel(i->rates, 1) - | set11nRateFlags(i->rates, 2) | set11nChainSel(i->rates, 2) - | set11nRateFlags(i->rates, 3) | set11nChainSel(i->rates, 3) - | SM(i->rtscts_rate, AR_RTSCTSRate)); + WRITE_ONCE(ads->ctl18, ctl18); WRITE_ONCE(ads->ctl19, AR_Not_Sounding); WRITE_ONCE(ads->ctl20, SM(i->txpower[1], AR_XmitPower1)); WRITE_ONCE(ads->ctl21, SM(i->txpower[2], AR_XmitPower2)); WRITE_ONCE(ads->ctl22, SM(i->txpower[3], AR_XmitPower3)); + + if (AR_SREV_5502(ah)) + WRITE_ONCE(ads->ctl23, set11nChainSelV2(i->rates, 0) + | set11nChainSelV2(i->rates, 1) + | set11nChainSelV2(i->rates, 2) + | set11nChainSelV2(i->rates, 3) + | SM(val, AR_PAPRDChainMaskV2)); } static u16 ar9003_calc_ptr_chksum(struct ar9003_txc *ads) @@ -357,6 +372,7 @@ static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds, { struct ar9003_txs *ads; u32 status; + bool tx_ba_status; ads = &ah->ts_ring[ah->ts_tail]; @@ -390,13 +406,17 @@ static int ar9003_hw_proc_txdesc(struct ath_hw *ah, void *ds, ts->ts_rssi_ctl0 = MS(status, AR_TxRSSIAnt00); ts->ts_rssi_ctl1 = MS(status, AR_TxRSSIAnt01); ts->ts_rssi_ctl2 = MS(status, AR_TxRSSIAnt02); - if (status & AR_TxBaStatus) { + if (!AR_SREV_5502(ah)) + tx_ba_status = (status & AR_TxBaStatus) != 0; + + status = READ_ONCE(ads->status3); + if (AR_SREV_5502(ah)) + tx_ba_status = (status & AR_TxBaStatusV2) != 0; + if (tx_ba_status) { ts->ts_flags |= ATH9K_TX_BA; ts->ba_low = ads->status5; ts->ba_high = ads->status6; } - - status = READ_ONCE(ads->status3); if (status & AR_ExcessiveRetries) ts->ts_status |= ATH9K_TXERR_XRETRY; if (status & AR_Filtered) diff --git a/drivers/net/wireless/ath/ath9k/ar9003_mac.h b/drivers/net/wireless/ath/ath9k/ar9003_mac.h index 07f073821..23614b4ce 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_mac.h +++ b/drivers/net/wireless/ath/ath9k/ar9003_mac.h @@ -41,6 +41,10 @@ #define AR_PAPRDChainMask 0x00000e00 #define AR_PAPRDChainMask_S 9 +/* ctl 23 */ +#define AR_PAPRDChainMaskV2 0x0000f000 +#define AR_PAPRDChainMaskV2_S 16 + #define MAP_ISR_S2_CST 6 #define MAP_ISR_S2_GTT 6 #define MAP_ISR_S2_TIM 3 diff --git a/drivers/net/wireless/ath/ath9k/mac.h b/drivers/net/wireless/ath/ath9k/mac.h index af44b3381..fb4318dd2 100644 --- a/drivers/net/wireless/ath/ath9k/mac.h +++ b/drivers/net/wireless/ath/ath9k/mac.h @@ -40,6 +40,9 @@ #define set11nChainSel(_series, _index) \ (SM((_series)[_index].ChSel, AR_ChainSel##_index)) +#define set11nChainSelV2(_series, _index) \ + (SM((_series)[_index].ChSel, AR_ChainSelV2_##_index)) + #define CCK_SIFS_TIME 10 #define CCK_PREAMBLE_BITS 144 #define CCK_PLCP_BITS 48 @@ -429,18 +432,26 @@ struct ar5416_desc { #define AR_GI0 0x00000002 #define AR_ChainSel0 0x0000001c #define AR_ChainSel0_S 2 +#define AR_ChainSelV2_0 0x0000000f +#define AR_ChainSelV2_0_S 0 #define AR_2040_1 0x00000020 #define AR_GI1 0x00000040 #define AR_ChainSel1 0x00000380 #define AR_ChainSel1_S 7 +#define AR_ChainSelV2_1 0x000000f0 +#define AR_ChainSelV2_1_S 4 #define AR_2040_2 0x00000400 #define AR_GI2 0x00000800 #define AR_ChainSel2 0x00007000 #define AR_ChainSel2_S 12 +#define AR_ChainSelV2_2 0x00000f00 +#define AR_ChainSelV2_2_S 8 #define AR_2040_3 0x00008000 #define AR_GI3 0x00010000 #define AR_ChainSel3 0x000e0000 #define AR_ChainSel3_S 17 +#define AR_ChainSelV2_3 0x0000f000 +#define AR_ChainSelV2_3_S 12 #define AR_RTSCTSRate 0x0ff00000 #define AR_RTSCTSRate_S 20 #define AR_STBC0 0x10000000 @@ -477,6 +488,7 @@ struct ar5416_desc { #define AR_TxDataUnderrun 0x00020000 #define AR_DescCfgErr 0x00040000 #define AR_TxTimerExpired 0x00080000 +#define AR_TxBaStatusV2 0x00200000 #define AR_TxStatusRsvd10 0xfff00000 #define AR_SendTimestamp ds_txstatus2 -- 2.25.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 6/9] ath9k: group some ar9300 eeprom functions at the top 2022-04-18 7:13 [PATCH 0/9] ath9k: add support for QCN550x Wenli Looi ` (4 preceding siblings ...) 2022-04-18 7:13 ` [PATCH 5/9] ath9k: implement QCN550x tx Wenli Looi @ 2022-04-18 7:13 ` Wenli Looi 2022-04-18 7:13 ` [PATCH 7/9] ath9k: add abstractions over ar9300 eeprom Wenli Looi ` (3 subsequent siblings) 9 siblings, 0 replies; 15+ messages in thread From: Wenli Looi @ 2022-04-18 7:13 UTC (permalink / raw) To: Toke Høiland-Jørgensen Cc: Kalle Valo, linux-wireless, ath9k-devel, Wenli Looi These functions will be part of an abstraction layer that works with both old and new AR9300 eeprom formats. Signed-off-by: Wenli Looi <wlooi@ucalgary.ca> --- .../net/wireless/ath/ath9k/ar9003_eeprom.c | 90 +++++++++---------- 1 file changed, 45 insertions(+), 45 deletions(-) diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c index 49be3a315..6257d74c6 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c @@ -2970,6 +2970,51 @@ static int interpolate(int x, int xa, int xb, int ya, int yb) return ya + factor + plus; } +/* XXX: review hardware docs */ +static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah) +{ + return ah->eeprom.ar9300_eep.eepromVersion; +} + +/* XXX: could be read from the eepromVersion, not sure yet */ +static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah) +{ + return 0; +} + +static struct ar9300_modal_eep_header *ar9003_modal_header(struct ath_hw *ah, + bool is2ghz) +{ + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; + + if (is2ghz) + return &eep->modalHeader2G; + else + return &eep->modalHeader5G; +} + +static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah, int chain, + bool is2ghz) +{ + __le16 val = ar9003_modal_header(ah, is2ghz)->antCtrlChain[chain]; + return le16_to_cpu(val); +} + +u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz) +{ + return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon); +} + +u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz) +{ + return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon2); +} + +static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is2ghz) +{ + return le16_to_cpu(ar9003_modal_header(ah, is2ghz)->switchcomspdt); +} + static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah, enum eeprom_param param) { @@ -3578,29 +3623,6 @@ static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr, } #endif -/* XXX: review hardware docs */ -static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah) -{ - return ah->eeprom.ar9300_eep.eepromVersion; -} - -/* XXX: could be read from the eepromVersion, not sure yet */ -static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah) -{ - return 0; -} - -static struct ar9300_modal_eep_header *ar9003_modal_header(struct ath_hw *ah, - bool is2ghz) -{ - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; - - if (is2ghz) - return &eep->modalHeader2G; - else - return &eep->modalHeader5G; -} - static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz) { int bias = ar9003_modal_header(ah, is2ghz)->xpaBiasLvl; @@ -3622,28 +3644,6 @@ static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz) } } -static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is2ghz) -{ - return le16_to_cpu(ar9003_modal_header(ah, is2ghz)->switchcomspdt); -} - -u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz) -{ - return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon); -} - -u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz) -{ - return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon2); -} - -static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah, int chain, - bool is2ghz) -{ - __le16 val = ar9003_modal_header(ah, is2ghz)->antCtrlChain[chain]; - return le16_to_cpu(val); -} - static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz) { struct ath_common *common = ath9k_hw_common(ah); -- 2.25.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 7/9] ath9k: add abstractions over ar9300 eeprom 2022-04-18 7:13 [PATCH 0/9] ath9k: add support for QCN550x Wenli Looi ` (5 preceding siblings ...) 2022-04-18 7:13 ` [PATCH 6/9] ath9k: group some ar9300 eeprom functions at the top Wenli Looi @ 2022-04-18 7:13 ` Wenli Looi 2022-04-18 7:13 ` [PATCH 8/9] ath9k: rename ar9300_eeprom to ar9300_eeprom_v1 Wenli Looi ` (2 subsequent siblings) 9 siblings, 0 replies; 15+ messages in thread From: Wenli Looi @ 2022-04-18 7:13 UTC (permalink / raw) To: Toke Høiland-Jørgensen Cc: Kalle Valo, linux-wireless, ath9k-devel, Wenli Looi This will allow the code to handle both old and new AR9300 eeprom formats. Signed-off-by: Wenli Looi <wlooi@ucalgary.ca> --- .../net/wireless/ath/ath9k/ar9003_eeprom.c | 633 +++++++++++------- 1 file changed, 409 insertions(+), 224 deletions(-) diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c index 6257d74c6..03eeee767 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c @@ -2982,6 +2982,16 @@ static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah) return 0; } +static struct ar9300_base_eep_hdr *ar9003_base_header(struct ath_hw *ah) +{ + return &ah->eeprom.ar9300_eep.baseEepHeader; +} + +static struct ar9300_BaseExtension_1 *ar9003_base_ext1(struct ath_hw *ah) +{ + return &ah->eeprom.ar9300_eep.base_ext1; +} + static struct ar9300_modal_eep_header *ar9003_modal_header(struct ath_hw *ah, bool is2ghz) { @@ -2993,6 +3003,105 @@ static struct ar9300_modal_eep_header *ar9003_modal_header(struct ath_hw *ah, return &eep->modalHeader5G; } +static int8_t ar9003_ant_gain(struct ath_hw *ah, bool is2ghz) +{ + return ar9003_modal_header(ah, is2ghz)->antennaGain; +} + +static u8 ar9003_cal_freq_pier(struct ath_hw *ah, int idx, bool is2ghz) +{ + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; + return is2ghz ? eep->calFreqPier2G[idx] : eep->calFreqPier5G[idx]; +} + +static struct ar9300_cal_data_per_freq_op_loop * +ar9003_cal_pier_data(struct ath_hw *ah, int chain, int idx, bool is2ghz) +{ + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; + return is2ghz ? &eep->calPierData2G[chain][idx] : + &eep->calPierData5G[chain][idx]; +} + +static u8 ar9003_cal_target_freqbin(struct ath_hw *ah, int idx, bool is2ghz) +{ + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; + return is2ghz ? eep->calTarget_freqbin_2G[idx] : + eep->calTarget_freqbin_5G[idx]; +} + +static u8 ar9003_cal_target_freqbin_cck(struct ath_hw *ah, int idx) +{ + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; + return eep->calTarget_freqbin_Cck[idx]; +} + +static u8 ar9003_cal_target_freqbin_ht20(struct ath_hw *ah, int idx, + bool is2ghz) +{ + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; + return is2ghz ? eep->calTarget_freqbin_2GHT20[idx] : + eep->calTarget_freqbin_5GHT20[idx]; +} + +static u8 ar9003_cal_target_freqbin_ht40(struct ath_hw *ah, int idx, + bool is2ghz) +{ + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; + return is2ghz ? eep->calTarget_freqbin_2GHT40[idx] : + eep->calTarget_freqbin_5GHT40[idx]; +} + +static u8 ar9003_cal_target_power(struct ath_hw *ah, int idx, int rateIndex, + bool is2ghz) +{ + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; + return is2ghz ? eep->calTargetPower2G[idx].tPow2x[rateIndex] : + eep->calTargetPower5G[idx].tPow2x[rateIndex]; +} + +static u8 ar9003_cal_target_power_cck(struct ath_hw *ah, int idx, int rateIndex) +{ + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; + return eep->calTargetPowerCck[idx].tPow2x[rateIndex]; +} + +static u8 ar9003_cal_target_power_ht20(struct ath_hw *ah, int idx, + int rateIndex, bool is2ghz) +{ + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; + return is2ghz ? eep->calTargetPower2GHT20[idx].tPow2x[rateIndex] : + eep->calTargetPower5GHT20[idx].tPow2x[rateIndex]; +} + +static u8 ar9003_cal_target_power_ht40(struct ath_hw *ah, int idx, + int rateIndex, bool is2ghz) +{ + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; + return is2ghz ? eep->calTargetPower2GHT40[idx].tPow2x[rateIndex] : + eep->calTargetPower5GHT40[idx].tPow2x[rateIndex]; +} + +static u8 ar9003_ctl_freqbin(struct ath_hw *ah, int idx, int edge, bool is2ghz) +{ + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; + return is2ghz ? eep->ctl_freqbin_2G[idx][edge] : + eep->ctl_freqbin_5G[idx][edge]; +} + +static u8 ar9003_ctl_index(struct ath_hw *ah, int idx, bool is2ghz) +{ + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; + return is2ghz ? eep->ctlIndex_2G[idx] : eep->ctlIndex_5G[idx]; +} + +static u8 ar9003_ctl_power_data(struct ath_hw *ah, int idx, int edge, + bool is2ghz) +{ + struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; + return is2ghz ? eep->ctlPowerData_2G[idx].ctlEdges[edge] : + eep->ctlPowerData_5G[idx].ctlEdges[edge]; +} + static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah, int chain, bool is2ghz) { @@ -3010,6 +3119,87 @@ u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz) return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon2); } +static int8_t ar9003_noise_floor_thres(struct ath_hw *ah, int chain, + bool is2ghz) +{ + return ar9003_modal_header(ah, is2ghz)->noiseFloorThreshCh[chain]; +} + +static int8_t ar9003_quick_drop(struct ath_hw *ah, bool is2ghz) +{ + return ar9003_modal_header(ah, is2ghz)->quick_drop; +} + +static int8_t ar9003_temp_slope(struct ath_hw *ah, bool is2ghz) +{ + return ar9003_modal_header(ah, is2ghz)->tempSlope; +} + +static int8_t ar9003_temp_slope_high(struct ath_hw *ah) +{ + return ah->eeprom.ar9300_eep.base_ext2.tempSlopeHigh; +} + +static int8_t ar9003_temp_slope_low(struct ath_hw *ah) +{ + return ah->eeprom.ar9300_eep.base_ext2.tempSlopeLow; +} + +static u8 ar9003_tx_end_to_xpa_off(struct ath_hw *ah, bool is2ghz) +{ + return ar9003_modal_header(ah, is2ghz)->txEndToXpaOff; +} + +static u8 ar9003_tx_frame_to_xpa_on(struct ath_hw *ah, bool is2ghz) +{ + return ar9003_modal_header(ah, is2ghz)->txFrameToXpaOn; +} + +static u8 ar9003_xatten1_db_high(struct ath_hw *ah, int chain) +{ + return ah->eeprom.ar9300_eep.base_ext2.xatten1DBHigh[chain]; +} + +static u8 ar9003_xatten1_db_low(struct ath_hw *ah, int chain) +{ + return ah->eeprom.ar9300_eep.base_ext2.xatten1DBLow[chain]; +} + +static u8 ar9003_xatten1_db_margin_high(struct ath_hw *ah, int chain) +{ + return ah->eeprom.ar9300_eep.base_ext2.xatten1MarginHigh[chain]; +} + +static u8 ar9003_xatten1_db_margin_low(struct ath_hw *ah, int chain) +{ + return ah->eeprom.ar9300_eep.base_ext2.xatten1MarginLow[chain]; +} + +static u8 ar9003_xatten1_db(struct ath_hw *ah, int chain, bool is2ghz) +{ + return ar9003_modal_header(ah, is2ghz)->xatten1DB[chain]; +} + +static u8 ar9003_xatten1_margin(struct ath_hw *ah, int chain, bool is2ghz) +{ + return ar9003_modal_header(ah, is2ghz)->xatten1Margin[chain]; +} + +static u8 ar9003_xlna_bias_strength(struct ath_hw *ah, bool is2ghz) +{ + return ar9003_modal_header(ah, is2ghz)->xlna_bias_strength; +} + +static u8 ar9003_xpa_bias_lvl(struct ath_hw *ah, bool is2ghz) +{ + return ar9003_modal_header(ah, is2ghz)->xpaBiasLvl; +} + +static u8 *ar9003_mac_addr(struct ath_hw *ah) +{ + return ah->eeprom.ar9300_eep.macAddr; +} + static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is2ghz) { return le16_to_cpu(ar9003_modal_header(ah, is2ghz)->switchcomspdt); @@ -3018,16 +3208,17 @@ static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is2ghz) static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah, enum eeprom_param param) { - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; - struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader; + struct ar9300_base_eep_hdr *pBase = ar9003_base_header(ah); + struct ar9300_BaseExtension_1 *base_ext1 = ar9003_base_ext1(ah); + u8 *mac_addr = ar9003_mac_addr(ah); switch (param) { case EEP_MAC_LSW: - return get_unaligned_be16(eep->macAddr); + return get_unaligned_be16(mac_addr); case EEP_MAC_MID: - return get_unaligned_be16(eep->macAddr + 2); + return get_unaligned_be16(mac_addr + 2); case EEP_MAC_MSW: - return get_unaligned_be16(eep->macAddr + 4); + return get_unaligned_be16(mac_addr + 4); case EEP_REG_0: return le16_to_cpu(pBase->regDmn[0]); case EEP_OP_CAP: @@ -3048,11 +3239,11 @@ static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah, if (AR_SREV_9565(ah)) return AR9300_EEP_ANTDIV_CONTROL_DEFAULT_VALUE; else - return eep->base_ext1.ant_div_control; + return base_ext1->ant_div_control; case EEP_ANTENNA_GAIN_5G: - return eep->modalHeader5G.antennaGain; + return ar9003_ant_gain(ah, /*is2ghz=*/false); case EEP_ANTENNA_GAIN_2G: - return eep->modalHeader2G.antennaGain; + return ar9003_ant_gain(ah, /*is2ghz=*/true); default: return 0; } @@ -3444,40 +3635,79 @@ static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah) } #if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS) -static u32 ar9003_dump_modal_eeprom(char *buf, u32 len, u32 size, - struct ar9300_modal_eep_header *modal_hdr) + +static int8_t ar9003_adc_desired_size(struct ath_hw *ah, bool is2ghz) { - PR_EEP("Chain0 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[0])); - PR_EEP("Chain1 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[1])); - PR_EEP("Chain2 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[2])); - PR_EEP("Ant. Common Control", le32_to_cpu(modal_hdr->antCtrlCommon)); - PR_EEP("Ant. Common Control2", le32_to_cpu(modal_hdr->antCtrlCommon2)); - PR_EEP("Ant. Gain", modal_hdr->antennaGain); - PR_EEP("Switch Settle", modal_hdr->switchSettling); - PR_EEP("Chain0 xatten1DB", modal_hdr->xatten1DB[0]); - PR_EEP("Chain1 xatten1DB", modal_hdr->xatten1DB[1]); - PR_EEP("Chain2 xatten1DB", modal_hdr->xatten1DB[2]); - PR_EEP("Chain0 xatten1Margin", modal_hdr->xatten1Margin[0]); - PR_EEP("Chain1 xatten1Margin", modal_hdr->xatten1Margin[1]); - PR_EEP("Chain2 xatten1Margin", modal_hdr->xatten1Margin[2]); - PR_EEP("Temp Slope", modal_hdr->tempSlope); - PR_EEP("Volt Slope", modal_hdr->voltSlope); - PR_EEP("spur Channels0", modal_hdr->spurChans[0]); - PR_EEP("spur Channels1", modal_hdr->spurChans[1]); - PR_EEP("spur Channels2", modal_hdr->spurChans[2]); - PR_EEP("spur Channels3", modal_hdr->spurChans[3]); - PR_EEP("spur Channels4", modal_hdr->spurChans[4]); - PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]); - PR_EEP("Chain1 NF Threshold", modal_hdr->noiseFloorThreshCh[1]); - PR_EEP("Chain2 NF Threshold", modal_hdr->noiseFloorThreshCh[2]); - PR_EEP("Quick Drop", modal_hdr->quick_drop); - PR_EEP("txEndToXpaOff", modal_hdr->txEndToXpaOff); - PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl); - PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart); - PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn); - PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn); - PR_EEP("txClip", modal_hdr->txClip); - PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize); + return ar9003_modal_header(ah, is2ghz)->adcDesiredSize; +} + +static u8 ar9003_switch_settling(struct ath_hw *ah, bool is2ghz) +{ + return ar9003_modal_header(ah, is2ghz)->switchSettling; +} + +static u8 ar9003_tx_clip(struct ath_hw *ah, bool is2ghz) +{ + return ar9003_modal_header(ah, is2ghz)->txClip; +} + +static u8 ar9003_tx_frame_to_data_start(struct ath_hw *ah, bool is2ghz) +{ + return ar9003_modal_header(ah, is2ghz)->txFrameToDataStart; +} + +static u8 ar9003_tx_frame_to_pa_on(struct ath_hw *ah, bool is2ghz) +{ + return ar9003_modal_header(ah, is2ghz)->txFrameToPaOn; +} + +static int8_t ar9003_volt_slope(struct ath_hw *ah, bool is2ghz) +{ + return ar9003_modal_header(ah, is2ghz)->voltSlope; +} + +static u32 ar9003_dump_modal_eeprom(struct ath_hw *ah, char *buf, u32 len, + u32 size, bool is_2g) +{ + PR_EEP("Chain0 Ant. Control", + ar9003_hw_ant_ctrl_chain_get(ah, 0, is_2g)); + PR_EEP("Chain1 Ant. Control", + ar9003_hw_ant_ctrl_chain_get(ah, 1, is_2g)); + PR_EEP("Chain2 Ant. Control", + ar9003_hw_ant_ctrl_chain_get(ah, 2, is_2g)); + PR_EEP("Ant. Common Control", ar9003_hw_ant_ctrl_common_get(ah, is_2g)); + PR_EEP("Ant. Common Control2", + ar9003_hw_ant_ctrl_common_2_get(ah, is_2g)); + PR_EEP("Ant. Gain", ar9003_ant_gain(ah, is_2g)); + PR_EEP("Switch Settle", ar9003_switch_settling(ah, is_2g)); + PR_EEP("Chain0 xatten1DB", ar9003_xatten1_db(ah, 0, is_2g)); + PR_EEP("Chain1 xatten1DB", ar9003_xatten1_db(ah, 1, is_2g)); + PR_EEP("Chain2 xatten1DB", ar9003_xatten1_db(ah, 2, is_2g)); + PR_EEP("Chain0 xatten1Margin", ar9003_xatten1_margin(ah, 0, is_2g)); + PR_EEP("Chain1 xatten1Margin", ar9003_xatten1_margin(ah, 1, is_2g)); + PR_EEP("Chain2 xatten1Margin", ar9003_xatten1_margin(ah, 2, is_2g)); + PR_EEP("Temp Slope", ar9003_temp_slope(ah, is_2g)); + PR_EEP("Volt Slope", ar9003_volt_slope(ah, is_2g)); + PR_EEP("spur Channels0", ar9003_get_spur_chan_ptr(ah, is_2g)[0]); + PR_EEP("spur Channels1", ar9003_get_spur_chan_ptr(ah, is_2g)[1]); + PR_EEP("spur Channels2", ar9003_get_spur_chan_ptr(ah, is_2g)[2]); + PR_EEP("spur Channels3", ar9003_get_spur_chan_ptr(ah, is_2g)[3]); + PR_EEP("spur Channels4", ar9003_get_spur_chan_ptr(ah, is_2g)[4]); + PR_EEP("Chain0 NF Threshold", + ar9003_noise_floor_thres(ah, 0, is_2g)); + PR_EEP("Chain1 NF Threshold", + ar9003_noise_floor_thres(ah, 1, is_2g)); + PR_EEP("Chain2 NF Threshold", + ar9003_noise_floor_thres(ah, 2, is_2g)); + PR_EEP("Quick Drop", ar9003_quick_drop(ah, is_2g)); + PR_EEP("txEndToXpaOff", ar9003_tx_end_to_xpa_off(ah, is_2g)); + PR_EEP("xPA Bias Level", ar9003_xpa_bias_lvl(ah, is_2g)); + PR_EEP("txFrameToDataStart", + ar9003_tx_frame_to_data_start(ah, is_2g)); + PR_EEP("txFrameToPaOn", ar9003_tx_frame_to_pa_on(ah, is_2g)); + PR_EEP("txFrameToXpaOn", ar9003_tx_frame_to_xpa_on(ah, is_2g)); + PR_EEP("txClip", ar9003_tx_clip(ah, is_2g)); + PR_EEP("ADC Desired size", ar9003_adc_desired_size(ah, is_2g)); return len; } @@ -3485,15 +3715,12 @@ static u32 ar9003_dump_modal_eeprom(char *buf, u32 len, u32 size, static u32 ar9003_dump_cal_data(struct ath_hw *ah, char *buf, u32 len, u32 size, bool is_2g) { - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; - struct ar9300_base_eep_hdr *pBase; + struct ar9300_base_eep_hdr *pBase = ar9003_base_header(ah); struct ar9300_cal_data_per_freq_op_loop *cal_pier; int cal_pier_nr; int freq; int i, j; - pBase = &eep->baseEepHeader; - if (is_2g) cal_pier_nr = AR9300_NUM_2G_CAL_PIERS; else @@ -3509,12 +3736,11 @@ static u32 ar9003_dump_cal_data(struct ath_hw *ah, char *buf, u32 len, u32 size, "Freq\t ref\tvolt\ttemp\tnf_cal\tnf_pow\trx_temp\n"); for (j = 0; j < cal_pier_nr; j++) { + cal_pier = ar9003_cal_pier_data(ah, i, j, is_2g); if (is_2g) { - cal_pier = &eep->calPierData2G[i][j]; - freq = 2300 + eep->calFreqPier2G[j]; + freq = 2300 + ar9003_cal_freq_pier(ah, j, is_2g); } else { - cal_pier = &eep->calPierData5G[i][j]; - freq = 4800 + eep->calFreqPier5G[j] * 5; + freq = 4800 + ar9003_cal_freq_pier(ah, j, is_2g) * 5; } len += scnprintf(buf + len, size - len, @@ -3539,22 +3765,19 @@ static u32 ar9003_dump_cal_data(struct ath_hw *ah, char *buf, u32 len, u32 size, static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr, u8 *buf, u32 len, u32 size) { - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; - struct ar9300_base_eep_hdr *pBase; + struct ar9300_base_eep_hdr *pBase = ar9003_base_header(ah); if (!dump_base_hdr) { len += scnprintf(buf + len, size - len, "%20s :\n", "2GHz modal Header"); - len = ar9003_dump_modal_eeprom(buf, len, size, - &eep->modalHeader2G); + len = ar9003_dump_modal_eeprom(ah, buf, len, size, true); len += scnprintf(buf + len, size - len, "Calibration data\n"); len = ar9003_dump_cal_data(ah, buf, len, size, true); len += scnprintf(buf + len, size - len, "%20s :\n", "5GHz modal Header"); - len = ar9003_dump_modal_eeprom(buf, len, size, - &eep->modalHeader5G); + len = ar9003_dump_modal_eeprom(ah, buf, len, size, false); len += scnprintf(buf + len, size - len, "Calibration data\n"); len = ar9003_dump_cal_data(ah, buf, len, size, false); @@ -3562,9 +3785,7 @@ static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr, goto out; } - pBase = &eep->baseEepHeader; - - PR_EEP("EEPROM Version", ah->eeprom.ar9300_eep.eepromVersion); + PR_EEP("EEPROM Version", ath9k_hw_ar9300_get_eeprom_ver(ah)); PR_EEP("RegDomain1", le16_to_cpu(pBase->regDmn[0])); PR_EEP("RegDomain2", le16_to_cpu(pBase->regDmn[1])); PR_EEP("TX Mask", (pBase->txrxMask >> 4)); @@ -3608,7 +3829,7 @@ static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr, PR_EEP("SW Reg", le32_to_cpu(pBase->swreg)); len += scnprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress", - ah->eeprom.ar9300_eep.macAddr); + ar9003_mac_addr(ah)); out: if (len > size) len = size; @@ -3625,7 +3846,7 @@ static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr, static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz) { - int bias = ar9003_modal_header(ah, is2ghz)->xpaBiasLvl; + int bias = ar9003_xpa_bias_lvl(ah, is2ghz); if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah)) @@ -3798,8 +4019,7 @@ static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz) static void ar9003_hw_drive_strength_apply(struct ath_hw *ah) { - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; - struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader; + struct ar9300_base_eep_hdr *pBase = ar9003_base_header(ah); int drive_strength; unsigned long reg; @@ -3843,23 +4063,23 @@ static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain, { int f[3], t[3]; u16 value; - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; + bool is2ghz = IS_CHAN_2GHZ(chan); if (chain >= 0 && chain < 3) { - if (IS_CHAN_2GHZ(chan)) - return eep->modalHeader2G.xatten1DB[chain]; - else if (eep->base_ext2.xatten1DBLow[chain] != 0) { - t[0] = eep->base_ext2.xatten1DBLow[chain]; + if (is2ghz) + return ar9003_xatten1_db(ah, chain, is2ghz); + else if (ar9003_xatten1_db_low(ah, chain) != 0) { + t[0] = ar9003_xatten1_db_low(ah, chain); f[0] = 5180; - t[1] = eep->modalHeader5G.xatten1DB[chain]; + t[1] = ar9003_xatten1_db(ah, chain, is2ghz); f[1] = 5500; - t[2] = eep->base_ext2.xatten1DBHigh[chain]; + t[2] = ar9003_xatten1_db_high(ah, chain); f[2] = 5785; value = ar9003_hw_power_interpolate((s32) chan->channel, f, t, 3); return value; } else - return eep->modalHeader5G.xatten1DB[chain]; + return ar9003_xatten1_db(ah, chain, is2ghz); } return 0; @@ -3871,23 +4091,23 @@ static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain, { int f[3], t[3]; u16 value; - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; + bool is2ghz = IS_CHAN_2GHZ(chan); if (chain >= 0 && chain < 3) { - if (IS_CHAN_2GHZ(chan)) - return eep->modalHeader2G.xatten1Margin[chain]; - else if (eep->base_ext2.xatten1MarginLow[chain] != 0) { - t[0] = eep->base_ext2.xatten1MarginLow[chain]; + if (is2ghz) + return ar9003_xatten1_margin(ah, chain, is2ghz); + else if (ar9003_xatten1_db_margin_low(ah, chain) != 0) { + t[0] = ar9003_xatten1_db_margin_low(ah, chain); f[0] = 5180; - t[1] = eep->modalHeader5G.xatten1Margin[chain]; + t[1] = ar9003_xatten1_margin(ah, chain, is2ghz); f[1] = 5500; - t[2] = eep->base_ext2.xatten1MarginHigh[chain]; + t[2] = ar9003_xatten1_db_margin_high(ah, chain); f[2] = 5785; value = ar9003_hw_power_interpolate((s32) chan->channel, f, t, 3); return value; } else - return eep->modalHeader5G.xatten1Margin[chain]; + return ar9003_xatten1_margin(ah, chain, is2ghz); } return 0; @@ -3955,8 +4175,7 @@ static bool is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set) void ar9003_hw_internal_regulator_apply(struct ath_hw *ah) { - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; - struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader; + struct ar9300_base_eep_hdr *pBase = ar9003_base_header(ah); u32 reg_val; if (pBase->featureEnable & BIT(4)) { @@ -4050,13 +4269,13 @@ void ar9003_hw_internal_regulator_apply(struct ath_hw *ah) static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah) { - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; - u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0]; + struct ar9300_base_eep_hdr *pBase = ar9003_base_header(ah); + u8 tuning_caps_param = pBase->params_for_tuning_caps[0]; if (AR_SREV_9340(ah) || AR_SREV_9531(ah)) return; - if (eep->baseEepHeader.featureEnable & 0x40) { + if (pBase->featureEnable & 0x40) { tuning_caps_param &= 0x7f; REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC, tuning_caps_param); @@ -4067,21 +4286,22 @@ static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah) static void ar9003_hw_quick_drop_apply(struct ath_hw *ah, u16 freq) { - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; - struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader; + struct ar9300_base_eep_hdr *pBase = ar9003_base_header(ah); + struct ar9300_BaseExtension_1 *base_ext1 = ar9003_base_ext1(ah); int quick_drop; s32 t[3], f[3] = {5180, 5500, 5785}; + bool is2ghz = freq < 4000; if (!(pBase->miscConfiguration & BIT(4))) return; if (AR_SREV_9300(ah) || AR_SREV_9580(ah) || AR_SREV_9340(ah)) { - if (freq < 4000) { - quick_drop = eep->modalHeader2G.quick_drop; + if (is2ghz) { + quick_drop = ar9003_quick_drop(ah, is2ghz); } else { - t[0] = eep->base_ext1.quick_drop_low; - t[1] = eep->modalHeader5G.quick_drop; - t[2] = eep->base_ext1.quick_drop_high; + t[0] = base_ext1->quick_drop_low; + t[1] = ar9003_quick_drop(ah, is2ghz); + t[2] = base_ext1->quick_drop_high; quick_drop = ar9003_hw_power_interpolate(freq, f, t, 3); } REG_RMW_FIELD(ah, AR_PHY_AGC, AR_PHY_AGC_QUICK_DROP, quick_drop); @@ -4092,7 +4312,7 @@ static void ar9003_hw_txend_to_xpa_off_apply(struct ath_hw *ah, bool is2ghz) { u32 value; - value = ar9003_modal_header(ah, is2ghz)->txEndToXpaOff; + value = ar9003_tx_end_to_xpa_off(ah, is2ghz); REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL, AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF, value); @@ -4102,10 +4322,10 @@ static void ar9003_hw_txend_to_xpa_off_apply(struct ath_hw *ah, bool is2ghz) static void ar9003_hw_xpa_timing_control_apply(struct ath_hw *ah, bool is2ghz) { - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; + struct ar9300_base_eep_hdr *pBase = ar9003_base_header(ah); u8 xpa_ctl; - if (!(eep->baseEepHeader.featureEnable & 0x80)) + if (!(pBase->featureEnable & 0x80)) return; if (!AR_SREV_9300(ah) && @@ -4116,7 +4336,7 @@ static void ar9003_hw_xpa_timing_control_apply(struct ath_hw *ah, bool is2ghz) !AR_SREV_5502(ah)) return; - xpa_ctl = ar9003_modal_header(ah, is2ghz)->txFrameToXpaOn; + xpa_ctl = ar9003_tx_frame_to_xpa_on(ah, is2ghz); if (is2ghz) REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL, AR_PHY_XPA_TIMING_CTL_FRAME_XPAB_ON, xpa_ctl); @@ -4127,16 +4347,16 @@ static void ar9003_hw_xpa_timing_control_apply(struct ath_hw *ah, bool is2ghz) static void ar9003_hw_xlna_bias_strength_apply(struct ath_hw *ah, bool is2ghz) { - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; + struct ar9300_base_eep_hdr *pBase = ar9003_base_header(ah); u8 bias; - if (!(eep->baseEepHeader.miscConfiguration & 0x40)) + if (!(pBase->miscConfiguration & 0x40)) return; if (!AR_SREV_9300(ah)) return; - bias = ar9003_modal_header(ah, is2ghz)->xlna_bias_strength; + bias = ar9003_xlna_bias_strength(ah, is2ghz); REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_RXTX4, AR_PHY_65NM_RXTX4_XLNA_BIAS, bias & 0x3); bias >>= 2; @@ -4149,8 +4369,7 @@ static void ar9003_hw_xlna_bias_strength_apply(struct ath_hw *ah, bool is2ghz) static int ar9003_hw_get_thermometer(struct ath_hw *ah) { - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; - struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader; + struct ar9300_base_eep_hdr *pBase = ar9003_base_header(ah); int thermometer = (pBase->miscConfiguration >> 1) & 0x3; return --thermometer; @@ -4208,7 +4427,7 @@ static void ar9003_hw_thermo_cal_apply(struct ath_hw *ah) static void ar9003_hw_apply_minccapwr_thresh(struct ath_hw *ah, bool is2ghz) { - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; + struct ar9300_BaseExtension_1 *base_ext1 = ar9003_base_ext1(ah); const u_int32_t cca_ctrl[AR9300_MAX_CHAINS] = { AR_PHY_CCA_CTRL_0, AR_PHY_CCA_CTRL_1, @@ -4218,10 +4437,10 @@ static void ar9003_hw_apply_minccapwr_thresh(struct ath_hw *ah, u32 val; if (is2ghz) { - if (!(eep->base_ext1.misc_enable & BIT(2))) + if (!(base_ext1->misc_enable & BIT(2))) return; } else { - if (!(eep->base_ext1.misc_enable & BIT(3))) + if (!(base_ext1->misc_enable & BIT(3))) return; } @@ -4229,7 +4448,7 @@ static void ar9003_hw_apply_minccapwr_thresh(struct ath_hw *ah, if (!(ah->caps.tx_chainmask & BIT(chain))) continue; - val = ar9003_modal_header(ah, is2ghz)->noiseFloorThreshCh[chain]; + val = ar9003_noise_floor_thres(ah, chain, is2ghz); REG_RMW_FIELD(ah, cca_ctrl[chain], AR_PHY_EXT_CCA0_THRESH62_1, val); } @@ -4330,18 +4549,11 @@ static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah, u16 numPiers, i; s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS]; s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS]; - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; - struct cal_tgt_pow_legacy *pEepromTargetPwr; - u8 *pFreqBin; if (is2GHz) { numPiers = AR9300_NUM_2G_20_TARGET_POWERS; - pEepromTargetPwr = eep->calTargetPower2G; - pFreqBin = eep->calTarget_freqbin_2G; } else { numPiers = AR9300_NUM_5G_20_TARGET_POWERS; - pEepromTargetPwr = eep->calTargetPower5G; - pFreqBin = eep->calTarget_freqbin_5G; } /* @@ -4349,8 +4561,10 @@ static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah, * targetpower piers stored on eeprom */ for (i = 0; i < numPiers; i++) { - freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz); - targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex]; + freqArray[i] = ath9k_hw_fbin2freq( + ar9003_cal_target_freqbin(ah, i, is2GHz), is2GHz); + targetPowerArray[i] = + ar9003_cal_target_power(ah, i, rateIndex, is2GHz); } /* interpolate to get target power for given frequency */ @@ -4366,18 +4580,11 @@ static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah, u16 numPiers, i; s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS]; s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS]; - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; - struct cal_tgt_pow_ht *pEepromTargetPwr; - u8 *pFreqBin; if (is2GHz) { numPiers = AR9300_NUM_2G_20_TARGET_POWERS; - pEepromTargetPwr = eep->calTargetPower2GHT20; - pFreqBin = eep->calTarget_freqbin_2GHT20; } else { numPiers = AR9300_NUM_5G_20_TARGET_POWERS; - pEepromTargetPwr = eep->calTargetPower5GHT20; - pFreqBin = eep->calTarget_freqbin_5GHT20; } /* @@ -4385,8 +4592,11 @@ static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah, * from targetpower piers stored on eeprom */ for (i = 0; i < numPiers; i++) { - freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz); - targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex]; + freqArray[i] = ath9k_hw_fbin2freq( + ar9003_cal_target_freqbin_ht20(ah, i, is2GHz), + is2GHz); + targetPowerArray[i] = ar9003_cal_target_power_ht20( + ah, i, rateIndex, is2GHz); } /* interpolate to get target power for given frequency */ @@ -4402,18 +4612,11 @@ static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah, u16 numPiers, i; s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS]; s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS]; - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; - struct cal_tgt_pow_ht *pEepromTargetPwr; - u8 *pFreqBin; if (is2GHz) { numPiers = AR9300_NUM_2G_40_TARGET_POWERS; - pEepromTargetPwr = eep->calTargetPower2GHT40; - pFreqBin = eep->calTarget_freqbin_2GHT40; } else { numPiers = AR9300_NUM_5G_40_TARGET_POWERS; - pEepromTargetPwr = eep->calTargetPower5GHT40; - pFreqBin = eep->calTarget_freqbin_5GHT40; } /* @@ -4421,8 +4624,11 @@ static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah, * targetpower piers stored on eeprom */ for (i = 0; i < numPiers; i++) { - freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz); - targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex]; + freqArray[i] = ath9k_hw_fbin2freq( + ar9003_cal_target_freqbin_ht40(ah, i, is2GHz), + is2GHz); + targetPowerArray[i] = ar9003_cal_target_power_ht40( + ah, i, rateIndex, is2GHz); } /* interpolate to get target power for given frequency */ @@ -4437,17 +4643,16 @@ static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah, u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i; s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS]; s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS]; - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; - struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck; - u8 *pFreqBin = eep->calTarget_freqbin_Cck; /* * create array of channels and targetpower from * targetpower piers stored on eeprom */ for (i = 0; i < numPiers; i++) { - freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], 1); - targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex]; + freqArray[i] = ath9k_hw_fbin2freq( + ar9003_cal_target_freqbin_cck(ah, i), 1); + targetPowerArray[i] = + ar9003_cal_target_power_cck(ah, i, rateIndex); } /* interpolate to get target power for given frequency */ @@ -4759,9 +4964,8 @@ static int ar9003_hw_cal_pier_get(struct ath_hw *ah, int *ptemperature, int *pvoltage, int *pnf_cal, int *pnf_power) { - u8 *pCalPier; + u8 calPier; struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct; - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; struct ath_common *common = ath9k_hw_common(ah); if (ichain >= AR9300_MAX_CHAINS) { @@ -4778,9 +4982,8 @@ static int ar9003_hw_cal_pier_get(struct ath_hw *ah, AR9300_NUM_2G_CAL_PIERS); return -1; } - - pCalPier = &(eep->calFreqPier2G[ipier]); - pCalPierStruct = &(eep->calPierData2G[ichain][ipier]); + calPier = ar9003_cal_freq_pier(ah, ipier, is2ghz); + pCalPierStruct = ar9003_cal_pier_data(ah, ichain, ipier, is2ghz); } else { if (ipier >= AR9300_NUM_5G_CAL_PIERS) { ath_dbg(common, EEPROM, @@ -4788,11 +4991,11 @@ static int ar9003_hw_cal_pier_get(struct ath_hw *ah, AR9300_NUM_5G_CAL_PIERS); return -1; } - pCalPier = &(eep->calFreqPier5G[ipier]); - pCalPierStruct = &(eep->calPierData5G[ichain][ipier]); + calPier = ar9003_cal_freq_pier(ah, ipier, is2ghz); + pCalPierStruct = ar9003_cal_pier_data(ah, ichain, ipier, is2ghz); } - *pfrequency = ath9k_hw_fbin2freq(*pCalPier, is2ghz); + *pfrequency = ath9k_hw_fbin2freq(calPier, is2ghz); *pcorrection = pCalPierStruct->refPower; *ptemperature = pCalPierStruct->tempMeas; *pvoltage = pCalPierStruct->voltMeas; @@ -4810,7 +5013,12 @@ static void ar9003_hw_power_control_override(struct ath_hw *ah, int *voltage, int *temperature) { int temp_slope = 0, temp_slope1 = 0, temp_slope2 = 0; - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; + struct ar9300_base_eep_hdr *pBase = ar9003_base_header(ah); + struct ar9300_BaseExtension_1 *base_ext1 = ar9003_base_ext1(ah); + bool is2ghz = frequency < 4000; + int8_t eep_temp_slope = ar9003_temp_slope(ah, is2ghz); + int8_t eep_temp_slope_low = ar9003_temp_slope_low(ah); + int8_t eep_temp_slope_high = ar9003_temp_slope_high(ah); int f[8], t[8], t1[3], t2[3], i; REG_RMW(ah, AR_PHY_TPC_11_B0, @@ -4842,23 +5050,23 @@ static void ar9003_hw_power_control_override(struct ath_hw *ah, * enable temperature compensation * Need to use register names */ - if (frequency < 4000) { - temp_slope = eep->modalHeader2G.tempSlope; + if (is2ghz) { + temp_slope = eep_temp_slope; } else { if (AR_SREV_9550(ah)) { - t[0] = eep->base_ext1.tempslopextension[2]; - t1[0] = eep->base_ext1.tempslopextension[3]; - t2[0] = eep->base_ext1.tempslopextension[4]; + t[0] = base_ext1->tempslopextension[2]; + t1[0] = base_ext1->tempslopextension[3]; + t2[0] = base_ext1->tempslopextension[4]; f[0] = 5180; - t[1] = eep->modalHeader5G.tempSlope; - t1[1] = eep->base_ext1.tempslopextension[0]; - t2[1] = eep->base_ext1.tempslopextension[1]; + t[1] = eep_temp_slope; + t1[1] = base_ext1->tempslopextension[0]; + t2[1] = base_ext1->tempslopextension[1]; f[1] = 5500; - t[2] = eep->base_ext1.tempslopextension[5]; - t1[2] = eep->base_ext1.tempslopextension[6]; - t2[2] = eep->base_ext1.tempslopextension[7]; + t[2] = base_ext1->tempslopextension[5]; + t1[2] = base_ext1->tempslopextension[6]; + t2[2] = base_ext1->tempslopextension[7]; f[2] = 5785; temp_slope = ar9003_hw_power_interpolate(frequency, @@ -4871,42 +5079,44 @@ static void ar9003_hw_power_control_override(struct ath_hw *ah, goto tempslope; } - if ((eep->baseEepHeader.miscConfiguration & 0x20) != 0) { + if ((pBase->miscConfiguration & 0x20) != 0) { for (i = 0; i < 8; i++) { - t[i] = eep->base_ext1.tempslopextension[i]; - f[i] = FBIN2FREQ(eep->calFreqPier5G[i], 0); + t[i] = base_ext1->tempslopextension[i]; + f[i] = FBIN2FREQ( + ar9003_cal_freq_pier(ah, i, is2ghz), + 0); } temp_slope = ar9003_hw_power_interpolate((s32) frequency, f, t, 8); - } else if (eep->base_ext2.tempSlopeLow != 0) { - t[0] = eep->base_ext2.tempSlopeLow; + } else if (eep_temp_slope_low != 0) { + t[0] = eep_temp_slope_low; f[0] = 5180; - t[1] = eep->modalHeader5G.tempSlope; + t[1] = eep_temp_slope; f[1] = 5500; - t[2] = eep->base_ext2.tempSlopeHigh; + t[2] = eep_temp_slope_high; f[2] = 5785; temp_slope = ar9003_hw_power_interpolate((s32) frequency, f, t, 3); } else { - temp_slope = eep->modalHeader5G.tempSlope; + temp_slope = eep_temp_slope; } } tempslope: if (AR_SREV_9550(ah) || AR_SREV_9531(ah) || AR_SREV_9561(ah) || AR_SREV_5502(ah)) { - u8 txmask = (eep->baseEepHeader.txrxMask & 0xf0) >> 4; + u8 txmask = (pBase->txrxMask & 0xf0) >> 4; /* * AR955x has tempSlope register for each chain. * Check whether temp_compensation feature is enabled or not. */ - if (eep->baseEepHeader.featureEnable & 0x1) { - if (frequency < 4000) { + if (pBase->featureEnable & 0x1) { + if (is2ghz) { if (txmask & BIT(0)) REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, - eep->base_ext2.tempSlopeLow); + eep_temp_slope_low); if (txmask & BIT(1)) REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1, AR_PHY_TPC_19_ALPHA_THERM, @@ -4914,7 +5124,7 @@ static void ar9003_hw_power_control_override(struct ath_hw *ah, if (txmask & BIT(2)) REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2, AR_PHY_TPC_19_ALPHA_THERM, - eep->base_ext2.tempSlopeHigh); + eep_temp_slope_high); } else { if (txmask & BIT(0)) REG_RMW_FIELD(ah, AR_PHY_TPC_19, @@ -5139,42 +5349,25 @@ static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency) return 0; } -static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep, +static u16 ar9003_hw_get_direct_edge_power(struct ath_hw *ah, int idx, int edge, bool is2GHz) { - struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G; - struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G; - - if (is2GHz) - return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge]); - else - return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge]); + return CTL_EDGE_TPOWER(ar9003_ctl_power_data(ah, idx, edge, is2GHz)); } -static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep, +static u16 ar9003_hw_get_indirect_edge_power(struct ath_hw *ah, int idx, unsigned int edge, u16 freq, bool is2GHz) { - struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G; - struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G; - - u8 *ctl_freqbin = is2GHz ? - &eep->ctl_freqbin_2G[idx][0] : - &eep->ctl_freqbin_5G[idx][0]; - - if (is2GHz) { - if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq && - CTL_EDGE_FLAGS(ctl_2g[idx].ctlEdges[edge - 1])) - return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge - 1]); - } else { - if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq && - CTL_EDGE_FLAGS(ctl_5g[idx].ctlEdges[edge - 1])) - return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]); - } + if (ath9k_hw_fbin2freq(ar9003_ctl_freqbin(ah, idx, edge - 1, is2GHz), + is2GHz) < freq && + CTL_EDGE_FLAGS(ar9003_ctl_power_data(ah, idx, edge - 1, is2GHz))) + return CTL_EDGE_TPOWER( + ar9003_ctl_power_data(ah, idx, edge - 1, is2GHz)); return MAX_RATE_POWER; } @@ -5182,37 +5375,36 @@ static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep, /* * Find the maximum conformance test limit for the given channel and CTL info */ -static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep, +static u16 ar9003_hw_get_max_edge_power(struct ath_hw *ah, u16 freq, int idx, bool is2GHz) { u16 twiceMaxEdgePower = MAX_RATE_POWER; - u8 *ctl_freqbin = is2GHz ? - &eep->ctl_freqbin_2G[idx][0] : - &eep->ctl_freqbin_5G[idx][0]; u16 num_edges = is2GHz ? AR9300_NUM_BAND_EDGES_2G : AR9300_NUM_BAND_EDGES_5G; unsigned int edge; /* Get the edge power */ for (edge = 0; - (edge < num_edges) && (ctl_freqbin[edge] != AR5416_BCHAN_UNUSED); + (edge < num_edges) && + (ar9003_ctl_freqbin(ah, idx, edge, is2GHz) != AR5416_BCHAN_UNUSED); edge++) { /* * If there's an exact channel match or an inband flag set * on the lower channel use the given rdEdgePower */ - if (freq == ath9k_hw_fbin2freq(ctl_freqbin[edge], is2GHz)) { - twiceMaxEdgePower = - ar9003_hw_get_direct_edge_power(eep, idx, - edge, is2GHz); + if (freq == ath9k_hw_fbin2freq(ar9003_ctl_freqbin(ah, idx, edge, + is2GHz), + is2GHz)) { + twiceMaxEdgePower = ar9003_hw_get_direct_edge_power( + ah, idx, edge, is2GHz); break; } else if ((edge > 0) && - (freq < ath9k_hw_fbin2freq(ctl_freqbin[edge], - is2GHz))) { - twiceMaxEdgePower = - ar9003_hw_get_indirect_edge_power(eep, idx, - edge, freq, - is2GHz); + (freq < + ath9k_hw_fbin2freq(ar9003_ctl_freqbin(ah, idx, edge, + is2GHz), + is2GHz))) { + twiceMaxEdgePower = ar9003_hw_get_indirect_edge_power( + ah, idx, edge, freq, is2GHz); /* * Leave loop - no more affecting edges possible in * this monotonic increasing list @@ -5234,7 +5426,6 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah, u16 powerLimit) { struct ath_common *common = ath9k_hw_common(ah); - struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep; u16 twiceMaxEdgePower; int i; u16 scaledPower = 0, minCtlPower; @@ -5249,7 +5440,6 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah, const u16 *pCtlMode; u16 ctlMode, freq; struct chan_centers centers; - u8 *ctlIndex; u8 ctlNum; u16 twiceMinEdgePower; bool is2ghz = IS_CHAN_2GHZ(chan); @@ -5304,18 +5494,17 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah, /* walk through each CTL index stored in EEPROM */ if (is2ghz) { - ctlIndex = pEepData->ctlIndex_2G; ctlNum = AR9300_NUM_CTLS_2G; } else { - ctlIndex = pEepData->ctlIndex_5G; ctlNum = AR9300_NUM_CTLS_5G; } twiceMaxEdgePower = MAX_RATE_POWER; - for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) { + for (i = 0; (i < ctlNum) && ar9003_ctl_index(ah, i, is2ghz); + i++) { ath_dbg(common, REGULATORY, "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n", - i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i], + i, cfgCtl, pCtlMode[ctlMode], ar9003_ctl_index(ah, i, is2ghz), chan->channel); /* @@ -5325,13 +5514,13 @@ static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah, */ if ((((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == - ctlIndex[i]) || + ar9003_ctl_index(ah, i, is2ghz)) || (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == - ((ctlIndex[i] & CTL_MODE_M) | + ((ar9003_ctl_index(ah, i, is2ghz) & CTL_MODE_M) | SD_NO_CTL))) { twiceMinEdgePower = - ar9003_hw_get_max_edge_power(pEepData, + ar9003_hw_get_max_edge_power(ah, freq, i, is2ghz); @@ -5569,16 +5758,12 @@ static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah, s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah) { - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; - - return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */ + return (ar9003_base_header(ah)->txrxgain >> 4) & 0xf; /* bits 7:4 */ } s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah) { - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; - - return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */ + return (ar9003_base_header(ah)->txrxgain) & 0xf; /* bits 3:0 */ } u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is2ghz) @@ -5619,7 +5804,7 @@ unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah, static u8 ar9003_get_eepmisc(struct ath_hw *ah) { - return ah->eeprom.ar9300_eep.baseEepHeader.opCapFlags.eepMisc; + return ar9003_base_header(ah)->opCapFlags.eepMisc; } const struct eeprom_ops eep_ar9300_ops = { -- 2.25.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 8/9] ath9k: rename ar9300_eeprom to ar9300_eeprom_v1 2022-04-18 7:13 [PATCH 0/9] ath9k: add support for QCN550x Wenli Looi ` (6 preceding siblings ...) 2022-04-18 7:13 ` [PATCH 7/9] ath9k: add abstractions over ar9300 eeprom Wenli Looi @ 2022-04-18 7:13 ` Wenli Looi 2022-04-18 7:13 ` [PATCH 9/9] ath9k: add ar9300_eeprom_v2 Wenli Looi 2022-05-10 18:39 ` [PATCH 0/9] ath9k: add support for QCN550x Wenli Looi 9 siblings, 0 replies; 15+ messages in thread From: Wenli Looi @ 2022-04-18 7:13 UTC (permalink / raw) To: Toke Høiland-Jørgensen Cc: Kalle Valo, linux-wireless, ath9k-devel, Wenli Looi This clearly distinguishes it from ar9300_eeprom_v2 which will be introduced next. It will break external patches involving ar9300_eeprom, which is desired because those patches will probably be no longer correct. The number of chains in the eeprom is also decoupled from AR9300_MAX_CHAINS, which is the number of chains supported by the driver. Signed-off-by: Wenli Looi <wlooi@ucalgary.ca> --- .../net/wireless/ath/ath9k/ar9003_eeprom.c | 74 +++++++++---------- .../net/wireless/ath/ath9k/ar9003_eeprom.h | 44 +++++------ drivers/net/wireless/ath/ath9k/hw.h | 2 +- 3 files changed, 60 insertions(+), 60 deletions(-) diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c index 03eeee767..11c7b57a1 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c @@ -43,7 +43,7 @@ static int ar9003_hw_power_interpolate(int32_t x, int32_t *px, int32_t *py, u_int16_t np); -static const struct ar9300_eeprom ar9300_default = { +static const struct ar9300_eeprom_v1 ar9300_default = { .eepromVersion = 2, .templateVersion = 2, .macAddr = {0, 2, 3, 4, 5, 6}, @@ -622,7 +622,7 @@ static const struct ar9300_eeprom ar9300_default = { } }; -static const struct ar9300_eeprom ar9300_x113 = { +static const struct ar9300_eeprom_v1 ar9300_x113 = { .eepromVersion = 2, .templateVersion = 6, .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0}, @@ -1201,7 +1201,7 @@ static const struct ar9300_eeprom ar9300_x113 = { }; -static const struct ar9300_eeprom ar9300_h112 = { +static const struct ar9300_eeprom_v1 ar9300_h112 = { .eepromVersion = 2, .templateVersion = 3, .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0}, @@ -1780,7 +1780,7 @@ static const struct ar9300_eeprom ar9300_h112 = { }; -static const struct ar9300_eeprom ar9300_x112 = { +static const struct ar9300_eeprom_v1 ar9300_x112 = { .eepromVersion = 2, .templateVersion = 5, .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0}, @@ -2358,7 +2358,7 @@ static const struct ar9300_eeprom ar9300_x112 = { } }; -static const struct ar9300_eeprom ar9300_h116 = { +static const struct ar9300_eeprom_v1 ar9300_h116 = { .eepromVersion = 2, .templateVersion = 4, .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0}, @@ -2937,7 +2937,7 @@ static const struct ar9300_eeprom ar9300_h116 = { }; -static const struct ar9300_eeprom *ar9300_eep_templates[] = { +static const struct ar9300_eeprom_v1 *ar9300_eep_templates[] = { &ar9300_default, &ar9300_x112, &ar9300_h116, @@ -2945,7 +2945,7 @@ static const struct ar9300_eeprom *ar9300_eep_templates[] = { &ar9300_x113, }; -static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id) +static const struct ar9300_eeprom_v1 *ar9003_eeprom_struct_find_by_id(int id) { int it; @@ -2973,7 +2973,7 @@ static int interpolate(int x, int xa, int xb, int ya, int yb) /* XXX: review hardware docs */ static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah) { - return ah->eeprom.ar9300_eep.eepromVersion; + return ah->eeprom.ar9300_eep_v1.eepromVersion; } /* XXX: could be read from the eepromVersion, not sure yet */ @@ -2984,18 +2984,18 @@ static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah) static struct ar9300_base_eep_hdr *ar9003_base_header(struct ath_hw *ah) { - return &ah->eeprom.ar9300_eep.baseEepHeader; + return &ah->eeprom.ar9300_eep_v1.baseEepHeader; } static struct ar9300_BaseExtension_1 *ar9003_base_ext1(struct ath_hw *ah) { - return &ah->eeprom.ar9300_eep.base_ext1; + return &ah->eeprom.ar9300_eep_v1.base_ext1; } -static struct ar9300_modal_eep_header *ar9003_modal_header(struct ath_hw *ah, +static struct ar9300_modal_eep_header_v1 *ar9003_modal_header(struct ath_hw *ah, bool is2ghz) { - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; + struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; if (is2ghz) return &eep->modalHeader2G; @@ -3010,35 +3010,35 @@ static int8_t ar9003_ant_gain(struct ath_hw *ah, bool is2ghz) static u8 ar9003_cal_freq_pier(struct ath_hw *ah, int idx, bool is2ghz) { - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; + struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; return is2ghz ? eep->calFreqPier2G[idx] : eep->calFreqPier5G[idx]; } static struct ar9300_cal_data_per_freq_op_loop * ar9003_cal_pier_data(struct ath_hw *ah, int chain, int idx, bool is2ghz) { - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; + struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; return is2ghz ? &eep->calPierData2G[chain][idx] : &eep->calPierData5G[chain][idx]; } static u8 ar9003_cal_target_freqbin(struct ath_hw *ah, int idx, bool is2ghz) { - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; + struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; return is2ghz ? eep->calTarget_freqbin_2G[idx] : eep->calTarget_freqbin_5G[idx]; } static u8 ar9003_cal_target_freqbin_cck(struct ath_hw *ah, int idx) { - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; + struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; return eep->calTarget_freqbin_Cck[idx]; } static u8 ar9003_cal_target_freqbin_ht20(struct ath_hw *ah, int idx, bool is2ghz) { - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; + struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; return is2ghz ? eep->calTarget_freqbin_2GHT20[idx] : eep->calTarget_freqbin_5GHT20[idx]; } @@ -3046,7 +3046,7 @@ static u8 ar9003_cal_target_freqbin_ht20(struct ath_hw *ah, int idx, static u8 ar9003_cal_target_freqbin_ht40(struct ath_hw *ah, int idx, bool is2ghz) { - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; + struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; return is2ghz ? eep->calTarget_freqbin_2GHT40[idx] : eep->calTarget_freqbin_5GHT40[idx]; } @@ -3054,21 +3054,21 @@ static u8 ar9003_cal_target_freqbin_ht40(struct ath_hw *ah, int idx, static u8 ar9003_cal_target_power(struct ath_hw *ah, int idx, int rateIndex, bool is2ghz) { - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; + struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; return is2ghz ? eep->calTargetPower2G[idx].tPow2x[rateIndex] : eep->calTargetPower5G[idx].tPow2x[rateIndex]; } static u8 ar9003_cal_target_power_cck(struct ath_hw *ah, int idx, int rateIndex) { - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; + struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; return eep->calTargetPowerCck[idx].tPow2x[rateIndex]; } static u8 ar9003_cal_target_power_ht20(struct ath_hw *ah, int idx, int rateIndex, bool is2ghz) { - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; + struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; return is2ghz ? eep->calTargetPower2GHT20[idx].tPow2x[rateIndex] : eep->calTargetPower5GHT20[idx].tPow2x[rateIndex]; } @@ -3076,28 +3076,28 @@ static u8 ar9003_cal_target_power_ht20(struct ath_hw *ah, int idx, static u8 ar9003_cal_target_power_ht40(struct ath_hw *ah, int idx, int rateIndex, bool is2ghz) { - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; + struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; return is2ghz ? eep->calTargetPower2GHT40[idx].tPow2x[rateIndex] : eep->calTargetPower5GHT40[idx].tPow2x[rateIndex]; } static u8 ar9003_ctl_freqbin(struct ath_hw *ah, int idx, int edge, bool is2ghz) { - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; + struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; return is2ghz ? eep->ctl_freqbin_2G[idx][edge] : eep->ctl_freqbin_5G[idx][edge]; } static u8 ar9003_ctl_index(struct ath_hw *ah, int idx, bool is2ghz) { - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; + struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; return is2ghz ? eep->ctlIndex_2G[idx] : eep->ctlIndex_5G[idx]; } static u8 ar9003_ctl_power_data(struct ath_hw *ah, int idx, int edge, bool is2ghz) { - struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep; + struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; return is2ghz ? eep->ctlPowerData_2G[idx].ctlEdges[edge] : eep->ctlPowerData_5G[idx].ctlEdges[edge]; } @@ -3137,12 +3137,12 @@ static int8_t ar9003_temp_slope(struct ath_hw *ah, bool is2ghz) static int8_t ar9003_temp_slope_high(struct ath_hw *ah) { - return ah->eeprom.ar9300_eep.base_ext2.tempSlopeHigh; + return ah->eeprom.ar9300_eep_v1.base_ext2.tempSlopeHigh; } static int8_t ar9003_temp_slope_low(struct ath_hw *ah) { - return ah->eeprom.ar9300_eep.base_ext2.tempSlopeLow; + return ah->eeprom.ar9300_eep_v1.base_ext2.tempSlopeLow; } static u8 ar9003_tx_end_to_xpa_off(struct ath_hw *ah, bool is2ghz) @@ -3157,22 +3157,22 @@ static u8 ar9003_tx_frame_to_xpa_on(struct ath_hw *ah, bool is2ghz) static u8 ar9003_xatten1_db_high(struct ath_hw *ah, int chain) { - return ah->eeprom.ar9300_eep.base_ext2.xatten1DBHigh[chain]; + return ah->eeprom.ar9300_eep_v1.base_ext2.xatten1DBHigh[chain]; } static u8 ar9003_xatten1_db_low(struct ath_hw *ah, int chain) { - return ah->eeprom.ar9300_eep.base_ext2.xatten1DBLow[chain]; + return ah->eeprom.ar9300_eep_v1.base_ext2.xatten1DBLow[chain]; } static u8 ar9003_xatten1_db_margin_high(struct ath_hw *ah, int chain) { - return ah->eeprom.ar9300_eep.base_ext2.xatten1MarginHigh[chain]; + return ah->eeprom.ar9300_eep_v1.base_ext2.xatten1MarginHigh[chain]; } static u8 ar9003_xatten1_db_margin_low(struct ath_hw *ah, int chain) { - return ah->eeprom.ar9300_eep.base_ext2.xatten1MarginLow[chain]; + return ah->eeprom.ar9300_eep_v1.base_ext2.xatten1MarginLow[chain]; } static u8 ar9003_xatten1_db(struct ath_hw *ah, int chain, bool is2ghz) @@ -3197,7 +3197,7 @@ static u8 ar9003_xpa_bias_lvl(struct ath_hw *ah, bool is2ghz) static u8 *ar9003_mac_addr(struct ath_hw *ah) { - return ah->eeprom.ar9300_eep.macAddr; + return ah->eeprom.ar9300_eep_v1.macAddr; } static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is2ghz) @@ -3421,7 +3421,7 @@ static int ar9300_compress_decision(struct ath_hw *ah, u8 *word, int length, int mdata_size) { struct ath_common *common = ath9k_hw_common(ah); - const struct ar9300_eeprom *eep = NULL; + const struct ar9300_eeprom_v1 *eep = NULL; switch (code) { case _CompressNone: @@ -3512,7 +3512,7 @@ static int ar9300_eeprom_restore_internal(struct ath_hw *ah, int it; u16 checksum, mchecksum; struct ath_common *common = ath9k_hw_common(ah); - struct ar9300_eeprom *eep; + struct ar9300_eeprom_v1 *eep; eeprom_read_op read; if (ath9k_hw_use_flash(ah)) { @@ -3522,7 +3522,7 @@ static int ar9300_eeprom_restore_internal(struct ath_hw *ah, return -EIO; /* check if eeprom contains valid data */ - eep = (struct ar9300_eeprom *) mptr; + eep = (struct ar9300_eeprom_v1 *) mptr; txrx = eep->baseEepHeader.txrxMask; if (txrx != 0 && txrx != 0xff) return 0; @@ -3625,10 +3625,10 @@ static int ar9300_eeprom_restore_internal(struct ath_hw *ah, */ static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah) { - u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep; + u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep_v1; if (ar9300_eeprom_restore_internal(ah, mptr, - sizeof(struct ar9300_eeprom)) < 0) + sizeof(struct ar9300_eeprom_v1)) < 0) return false; return true; diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h index f8ae20318..b020092e8 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h @@ -41,7 +41,7 @@ #define AR9300_EEPMISC_WOW 0x02 #define AR9300_CUSTOMER_DATA_SIZE 20 -#define AR9300_MAX_CHAINS 3 +#define AR9300_EEPROM_V1_MAX_CHAINS 3 #define AR9300_ANT_16S 25 #define AR9300_FUTURE_MODAL_SZ 6 @@ -215,23 +215,23 @@ struct ar9300_base_eep_hdr { __le32 swreg; } __packed; -struct ar9300_modal_eep_header { +struct ar9300_modal_eep_header_v1 { /* 4 idle, t1, t2, b (4 bits per setting) */ __le32 antCtrlCommon; /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */ __le32 antCtrlCommon2; /* 6 idle, t, r, rx1, rx12, b (2 bits each) */ - __le16 antCtrlChain[AR9300_MAX_CHAINS]; + __le16 antCtrlChain[AR9300_EEPROM_V1_MAX_CHAINS]; /* 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */ - u8 xatten1DB[AR9300_MAX_CHAINS]; + u8 xatten1DB[AR9300_EEPROM_V1_MAX_CHAINS]; /* 3 xatten1_margin for merlin (0xa20c/b20c 16:12 */ - u8 xatten1Margin[AR9300_MAX_CHAINS]; + u8 xatten1Margin[AR9300_EEPROM_V1_MAX_CHAINS]; int8_t tempSlope; int8_t voltSlope; /* spur channels in usual fbin coding format */ u8 spurChans[AR_EEPROM_MODAL_SPURS]; /* 3 Check if the register is per chain */ - int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS]; + int8_t noiseFloorThreshCh[AR9300_EEPROM_V1_MAX_CHAINS]; u8 reserved[11]; int8_t quick_drop; u8 xpaBiasLvl; @@ -270,7 +270,7 @@ struct cal_tgt_pow_legacy { u8 tPow2x[4]; } __packed; -struct cal_tgt_pow_ht { +struct cal_tgt_pow_ht_v1 { u8 tPow2x[14]; } __packed; @@ -300,16 +300,16 @@ struct ar9300_BaseExtension_1 { int8_t quick_drop_high; } __packed; -struct ar9300_BaseExtension_2 { +struct ar9300_BaseExtension_2_v1 { int8_t tempSlopeLow; int8_t tempSlopeHigh; - u8 xatten1DBLow[AR9300_MAX_CHAINS]; - u8 xatten1MarginLow[AR9300_MAX_CHAINS]; - u8 xatten1DBHigh[AR9300_MAX_CHAINS]; - u8 xatten1MarginHigh[AR9300_MAX_CHAINS]; + u8 xatten1DBLow[AR9300_EEPROM_V1_MAX_CHAINS]; + u8 xatten1MarginLow[AR9300_EEPROM_V1_MAX_CHAINS]; + u8 xatten1DBHigh[AR9300_EEPROM_V1_MAX_CHAINS]; + u8 xatten1MarginHigh[AR9300_EEPROM_V1_MAX_CHAINS]; } __packed; -struct ar9300_eeprom { +struct ar9300_eeprom_v1 { u8 eepromVersion; u8 templateVersion; u8 macAddr[6]; @@ -317,11 +317,11 @@ struct ar9300_eeprom { struct ar9300_base_eep_hdr baseEepHeader; - struct ar9300_modal_eep_header modalHeader2G; + struct ar9300_modal_eep_header_v1 modalHeader2G; struct ar9300_BaseExtension_1 base_ext1; u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS]; struct ar9300_cal_data_per_freq_op_loop - calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS]; + calPierData2G[AR9300_EEPROM_V1_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS]; u8 calTarget_freqbin_Cck[AR9300_NUM_2G_CCK_TARGET_POWERS]; u8 calTarget_freqbin_2G[AR9300_NUM_2G_20_TARGET_POWERS]; u8 calTarget_freqbin_2GHT20[AR9300_NUM_2G_20_TARGET_POWERS]; @@ -330,26 +330,26 @@ struct ar9300_eeprom { calTargetPowerCck[AR9300_NUM_2G_CCK_TARGET_POWERS]; struct cal_tgt_pow_legacy calTargetPower2G[AR9300_NUM_2G_20_TARGET_POWERS]; - struct cal_tgt_pow_ht + struct cal_tgt_pow_ht_v1 calTargetPower2GHT20[AR9300_NUM_2G_20_TARGET_POWERS]; - struct cal_tgt_pow_ht + struct cal_tgt_pow_ht_v1 calTargetPower2GHT40[AR9300_NUM_2G_40_TARGET_POWERS]; u8 ctlIndex_2G[AR9300_NUM_CTLS_2G]; u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G]; struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G]; - struct ar9300_modal_eep_header modalHeader5G; - struct ar9300_BaseExtension_2 base_ext2; + struct ar9300_modal_eep_header_v1 modalHeader5G; + struct ar9300_BaseExtension_2_v1 base_ext2; u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS]; struct ar9300_cal_data_per_freq_op_loop - calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS]; + calPierData5G[AR9300_EEPROM_V1_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS]; u8 calTarget_freqbin_5G[AR9300_NUM_5G_20_TARGET_POWERS]; u8 calTarget_freqbin_5GHT20[AR9300_NUM_5G_20_TARGET_POWERS]; u8 calTarget_freqbin_5GHT40[AR9300_NUM_5G_40_TARGET_POWERS]; struct cal_tgt_pow_legacy calTargetPower5G[AR9300_NUM_5G_20_TARGET_POWERS]; - struct cal_tgt_pow_ht + struct cal_tgt_pow_ht_v1 calTargetPower5GHT20[AR9300_NUM_5G_20_TARGET_POWERS]; - struct cal_tgt_pow_ht + struct cal_tgt_pow_ht_v1 calTargetPower5GHT40[AR9300_NUM_5G_40_TARGET_POWERS]; u8 ctlIndex_5G[AR9300_NUM_CTLS_5G]; u8 ctl_freqbin_5G[AR9300_NUM_CTLS_5G][AR9300_NUM_BAND_EDGES_5G]; diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h index 759a5991a..22349c2b7 100644 --- a/drivers/net/wireless/ath/ath9k/hw.h +++ b/drivers/net/wireless/ath/ath9k/hw.h @@ -789,7 +789,7 @@ struct ath_hw { struct ar5416_eeprom_def def; struct ar5416_eeprom_4k map4k; struct ar9287_eeprom map9287; - struct ar9300_eeprom ar9300_eep; + struct ar9300_eeprom_v1 ar9300_eep_v1; } eeprom; const struct eeprom_ops *eep_ops; -- 2.25.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 9/9] ath9k: add ar9300_eeprom_v2 2022-04-18 7:13 [PATCH 0/9] ath9k: add support for QCN550x Wenli Looi ` (7 preceding siblings ...) 2022-04-18 7:13 ` [PATCH 8/9] ath9k: rename ar9300_eeprom to ar9300_eeprom_v1 Wenli Looi @ 2022-04-18 7:13 ` Wenli Looi 2022-05-10 18:39 ` [PATCH 0/9] ath9k: add support for QCN550x Wenli Looi 9 siblings, 0 replies; 15+ messages in thread From: Wenli Looi @ 2022-04-18 7:13 UTC (permalink / raw) To: Toke Høiland-Jørgensen Cc: Kalle Valo, linux-wireless, ath9k-devel, Wenli Looi This adds support for the 4-chain eeprom used by QCN550x. The abstraction layer over the eeprom allows the code to work with both V1 and V2 eeprom types. Signed-off-by: Wenli Looi <wlooi@ucalgary.ca> --- .../net/wireless/ath/ath9k/ar9003_eeprom.c | 325 ++++++++++++++---- .../net/wireless/ath/ath9k/ar9003_eeprom.h | 100 ++++++ drivers/net/wireless/ath/ath9k/hw.h | 1 + drivers/net/wireless/ath/ath9k/reg.h | 1 + 4 files changed, 352 insertions(+), 75 deletions(-) diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c index 11c7b57a1..4f5b753d7 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c @@ -2984,16 +2984,20 @@ static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah) static struct ar9300_base_eep_hdr *ar9003_base_header(struct ath_hw *ah) { - return &ah->eeprom.ar9300_eep_v1.baseEepHeader; + return AR_SREV_AR9300_EEPROM_V2(ah) ? + &ah->eeprom.ar9300_eep_v2.baseEepHeader : + &ah->eeprom.ar9300_eep_v1.baseEepHeader; } static struct ar9300_BaseExtension_1 *ar9003_base_ext1(struct ath_hw *ah) { - return &ah->eeprom.ar9300_eep_v1.base_ext1; + return AR_SREV_AR9300_EEPROM_V2(ah) ? + &ah->eeprom.ar9300_eep_v2.base_ext1 : + &ah->eeprom.ar9300_eep_v1.base_ext1; } -static struct ar9300_modal_eep_header_v1 *ar9003_modal_header(struct ath_hw *ah, - bool is2ghz) +static struct ar9300_modal_eep_header_v1 * +ar9003_modal_header_v1(struct ath_hw *ah, bool is2ghz) { struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; @@ -3003,206 +3007,348 @@ static struct ar9300_modal_eep_header_v1 *ar9003_modal_header(struct ath_hw *ah, return &eep->modalHeader5G; } +static struct ar9300_modal_eep_header_v2 * +ar9003_modal_header_v2(struct ath_hw *ah, bool is2ghz) +{ + struct ar9300_eeprom_v2 *eep = &ah->eeprom.ar9300_eep_v2; + + if (is2ghz) + return &eep->modalHeader2G; + else + return &eep->modalHeader5G; +} + static int8_t ar9003_ant_gain(struct ath_hw *ah, bool is2ghz) { - return ar9003_modal_header(ah, is2ghz)->antennaGain; + return AR_SREV_AR9300_EEPROM_V2(ah) ? + ar9003_modal_header_v2(ah, is2ghz)->antennaGain : + ar9003_modal_header_v1(ah, is2ghz)->antennaGain; } static u8 ar9003_cal_freq_pier(struct ath_hw *ah, int idx, bool is2ghz) { - struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; - return is2ghz ? eep->calFreqPier2G[idx] : eep->calFreqPier5G[idx]; + if (AR_SREV_AR9300_EEPROM_V2(ah)) { + struct ar9300_eeprom_v2 *eep = &ah->eeprom.ar9300_eep_v2; + return is2ghz ? eep->calFreqPier2G[idx] : + eep->calFreqPier5G[idx]; + } else { + struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; + return is2ghz ? eep->calFreqPier2G[idx] : + eep->calFreqPier5G[idx]; + } } static struct ar9300_cal_data_per_freq_op_loop * ar9003_cal_pier_data(struct ath_hw *ah, int chain, int idx, bool is2ghz) { - struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; - return is2ghz ? &eep->calPierData2G[chain][idx] : - &eep->calPierData5G[chain][idx]; + if (AR_SREV_AR9300_EEPROM_V2(ah)) { + struct ar9300_eeprom_v2 *eep = &ah->eeprom.ar9300_eep_v2; + return is2ghz ? &eep->calPierData2G[chain][idx] : + &eep->calPierData5G[chain][idx]; + } else { + struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; + return is2ghz ? &eep->calPierData2G[chain][idx] : + &eep->calPierData5G[chain][idx]; + } } static u8 ar9003_cal_target_freqbin(struct ath_hw *ah, int idx, bool is2ghz) { - struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; - return is2ghz ? eep->calTarget_freqbin_2G[idx] : - eep->calTarget_freqbin_5G[idx]; + if (AR_SREV_AR9300_EEPROM_V2(ah)) { + struct ar9300_eeprom_v2 *eep = &ah->eeprom.ar9300_eep_v2; + return is2ghz ? eep->calTarget_freqbin_2G[idx] : + eep->calTarget_freqbin_5G[idx]; + } else { + struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; + return is2ghz ? eep->calTarget_freqbin_2G[idx] : + eep->calTarget_freqbin_5G[idx]; + } } static u8 ar9003_cal_target_freqbin_cck(struct ath_hw *ah, int idx) { - struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; - return eep->calTarget_freqbin_Cck[idx]; + if (AR_SREV_AR9300_EEPROM_V2(ah)) { + struct ar9300_eeprom_v2 *eep = &ah->eeprom.ar9300_eep_v2; + return eep->calTarget_freqbin_Cck[idx]; + } else { + struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; + return eep->calTarget_freqbin_Cck[idx]; + } } static u8 ar9003_cal_target_freqbin_ht20(struct ath_hw *ah, int idx, bool is2ghz) { - struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; - return is2ghz ? eep->calTarget_freqbin_2GHT20[idx] : - eep->calTarget_freqbin_5GHT20[idx]; + if (AR_SREV_AR9300_EEPROM_V2(ah)) { + struct ar9300_eeprom_v2 *eep = &ah->eeprom.ar9300_eep_v2; + return is2ghz ? eep->calTarget_freqbin_2GHT20[idx] : + eep->calTarget_freqbin_5GHT20[idx]; + } else { + struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; + return is2ghz ? eep->calTarget_freqbin_2GHT20[idx] : + eep->calTarget_freqbin_5GHT20[idx]; + } } static u8 ar9003_cal_target_freqbin_ht40(struct ath_hw *ah, int idx, bool is2ghz) { - struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; - return is2ghz ? eep->calTarget_freqbin_2GHT40[idx] : - eep->calTarget_freqbin_5GHT40[idx]; + if (AR_SREV_AR9300_EEPROM_V2(ah)) { + struct ar9300_eeprom_v2 *eep = &ah->eeprom.ar9300_eep_v2; + return is2ghz ? eep->calTarget_freqbin_2GHT40[idx] : + eep->calTarget_freqbin_5GHT40[idx]; + } else { + struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; + return is2ghz ? eep->calTarget_freqbin_2GHT40[idx] : + eep->calTarget_freqbin_5GHT40[idx]; + } } static u8 ar9003_cal_target_power(struct ath_hw *ah, int idx, int rateIndex, bool is2ghz) { - struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; - return is2ghz ? eep->calTargetPower2G[idx].tPow2x[rateIndex] : - eep->calTargetPower5G[idx].tPow2x[rateIndex]; + if (AR_SREV_AR9300_EEPROM_V2(ah)) { + struct ar9300_eeprom_v2 *eep = &ah->eeprom.ar9300_eep_v2; + return is2ghz ? eep->calTargetPower2G[idx].tPow2x[rateIndex] : + eep->calTargetPower5G[idx].tPow2x[rateIndex]; + } else { + struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; + return is2ghz ? eep->calTargetPower2G[idx].tPow2x[rateIndex] : + eep->calTargetPower5G[idx].tPow2x[rateIndex]; + } } static u8 ar9003_cal_target_power_cck(struct ath_hw *ah, int idx, int rateIndex) { - struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; - return eep->calTargetPowerCck[idx].tPow2x[rateIndex]; + if (AR_SREV_AR9300_EEPROM_V2(ah)) { + struct ar9300_eeprom_v2 *eep = &ah->eeprom.ar9300_eep_v2; + return eep->calTargetPowerCck[idx].tPow2x[rateIndex]; + } else { + struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; + return eep->calTargetPowerCck[idx].tPow2x[rateIndex]; + } } static u8 ar9003_cal_target_power_ht20(struct ath_hw *ah, int idx, int rateIndex, bool is2ghz) { - struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; - return is2ghz ? eep->calTargetPower2GHT20[idx].tPow2x[rateIndex] : - eep->calTargetPower5GHT20[idx].tPow2x[rateIndex]; + if (AR_SREV_AR9300_EEPROM_V2(ah)) { + struct ar9300_eeprom_v2 *eep = &ah->eeprom.ar9300_eep_v2; + return is2ghz ? + eep->calTargetPower2GHT20[idx].tPow2x[rateIndex] : + eep->calTargetPower5GHT20[idx].tPow2x[rateIndex]; + } else { + struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; + return is2ghz ? + eep->calTargetPower2GHT20[idx].tPow2x[rateIndex] : + eep->calTargetPower5GHT20[idx].tPow2x[rateIndex]; + } } static u8 ar9003_cal_target_power_ht40(struct ath_hw *ah, int idx, int rateIndex, bool is2ghz) { - struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; - return is2ghz ? eep->calTargetPower2GHT40[idx].tPow2x[rateIndex] : - eep->calTargetPower5GHT40[idx].tPow2x[rateIndex]; + if (AR_SREV_AR9300_EEPROM_V2(ah)) { + struct ar9300_eeprom_v2 *eep = &ah->eeprom.ar9300_eep_v2; + return is2ghz ? + eep->calTargetPower2GHT40[idx].tPow2x[rateIndex] : + eep->calTargetPower5GHT40[idx].tPow2x[rateIndex]; + } else { + struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; + return is2ghz ? + eep->calTargetPower2GHT40[idx].tPow2x[rateIndex] : + eep->calTargetPower5GHT40[idx].tPow2x[rateIndex]; + } } static u8 ar9003_ctl_freqbin(struct ath_hw *ah, int idx, int edge, bool is2ghz) { - struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; - return is2ghz ? eep->ctl_freqbin_2G[idx][edge] : - eep->ctl_freqbin_5G[idx][edge]; + if (AR_SREV_AR9300_EEPROM_V2(ah)) { + struct ar9300_eeprom_v2 *eep = &ah->eeprom.ar9300_eep_v2; + return is2ghz ? eep->ctl_freqbin_2G[idx][edge] : + eep->ctl_freqbin_5G[idx][edge]; + } else { + struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; + return is2ghz ? eep->ctl_freqbin_2G[idx][edge] : + eep->ctl_freqbin_5G[idx][edge]; + } } static u8 ar9003_ctl_index(struct ath_hw *ah, int idx, bool is2ghz) { - struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; - return is2ghz ? eep->ctlIndex_2G[idx] : eep->ctlIndex_5G[idx]; + if (AR_SREV_AR9300_EEPROM_V2(ah)) { + struct ar9300_eeprom_v2 *eep = &ah->eeprom.ar9300_eep_v2; + return is2ghz ? eep->ctlIndex_2G[idx] : eep->ctlIndex_5G[idx]; + } else { + struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; + return is2ghz ? eep->ctlIndex_2G[idx] : eep->ctlIndex_5G[idx]; + } } static u8 ar9003_ctl_power_data(struct ath_hw *ah, int idx, int edge, bool is2ghz) { - struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; - return is2ghz ? eep->ctlPowerData_2G[idx].ctlEdges[edge] : - eep->ctlPowerData_5G[idx].ctlEdges[edge]; + if (AR_SREV_AR9300_EEPROM_V2(ah)) { + struct ar9300_eeprom_v2 *eep = &ah->eeprom.ar9300_eep_v2; + return is2ghz ? eep->ctlPowerData_2G[idx].ctlEdges[edge] : + eep->ctlPowerData_5G[idx].ctlEdges[edge]; + } else { + struct ar9300_eeprom_v1 *eep = &ah->eeprom.ar9300_eep_v1; + return is2ghz ? eep->ctlPowerData_2G[idx].ctlEdges[edge] : + eep->ctlPowerData_5G[idx].ctlEdges[edge]; + } } static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah, int chain, bool is2ghz) { - __le16 val = ar9003_modal_header(ah, is2ghz)->antCtrlChain[chain]; + __le16 val = + AR_SREV_AR9300_EEPROM_V2(ah) ? + ar9003_modal_header_v2(ah, is2ghz)->antCtrlChain[chain] : + ar9003_modal_header_v1(ah, is2ghz)->antCtrlChain[chain]; return le16_to_cpu(val); } u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz) { - return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon); + __le32 val = AR_SREV_AR9300_EEPROM_V2(ah) ? + ar9003_modal_header_v2(ah, is2ghz)->antCtrlCommon : + ar9003_modal_header_v1(ah, is2ghz)->antCtrlCommon; + return le32_to_cpu(val); } u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz) { - return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->antCtrlCommon2); + __le32 val = + AR_SREV_AR9300_EEPROM_V2(ah) ? + ar9003_modal_header_v2(ah, is2ghz)->antCtrlCommon2 : + ar9003_modal_header_v1(ah, is2ghz)->antCtrlCommon2; + return le32_to_cpu(val); } static int8_t ar9003_noise_floor_thres(struct ath_hw *ah, int chain, bool is2ghz) { - return ar9003_modal_header(ah, is2ghz)->noiseFloorThreshCh[chain]; + return AR_SREV_AR9300_EEPROM_V2(ah) ? + ar9003_modal_header_v2(ah, is2ghz) + ->noiseFloorThreshCh[chain] : + ar9003_modal_header_v1(ah, is2ghz) + ->noiseFloorThreshCh[chain]; } static int8_t ar9003_quick_drop(struct ath_hw *ah, bool is2ghz) { - return ar9003_modal_header(ah, is2ghz)->quick_drop; + return AR_SREV_AR9300_EEPROM_V2(ah) ? + ar9003_modal_header_v2(ah, is2ghz)->quick_drop : + ar9003_modal_header_v1(ah, is2ghz)->quick_drop; } static int8_t ar9003_temp_slope(struct ath_hw *ah, bool is2ghz) { - return ar9003_modal_header(ah, is2ghz)->tempSlope; + return AR_SREV_AR9300_EEPROM_V2(ah) ? + ar9003_modal_header_v2(ah, is2ghz)->tempSlope : + ar9003_modal_header_v1(ah, is2ghz)->tempSlope; } static int8_t ar9003_temp_slope_high(struct ath_hw *ah) { - return ah->eeprom.ar9300_eep_v1.base_ext2.tempSlopeHigh; + return AR_SREV_AR9300_EEPROM_V2(ah) ? + ah->eeprom.ar9300_eep_v2.base_ext2.tempSlopeHigh : + ah->eeprom.ar9300_eep_v1.base_ext2.tempSlopeHigh; } static int8_t ar9003_temp_slope_low(struct ath_hw *ah) { - return ah->eeprom.ar9300_eep_v1.base_ext2.tempSlopeLow; + return AR_SREV_AR9300_EEPROM_V2(ah) ? + ah->eeprom.ar9300_eep_v2.base_ext2.tempSlopeLow : + ah->eeprom.ar9300_eep_v1.base_ext2.tempSlopeLow; } static u8 ar9003_tx_end_to_xpa_off(struct ath_hw *ah, bool is2ghz) { - return ar9003_modal_header(ah, is2ghz)->txEndToXpaOff; + return AR_SREV_AR9300_EEPROM_V2(ah) ? + ar9003_modal_header_v2(ah, is2ghz)->txEndToXpaOff : + ar9003_modal_header_v1(ah, is2ghz)->txEndToXpaOff; } static u8 ar9003_tx_frame_to_xpa_on(struct ath_hw *ah, bool is2ghz) { - return ar9003_modal_header(ah, is2ghz)->txFrameToXpaOn; + return AR_SREV_AR9300_EEPROM_V2(ah) ? + ar9003_modal_header_v2(ah, is2ghz)->txFrameToXpaOn : + ar9003_modal_header_v1(ah, is2ghz)->txFrameToXpaOn; } static u8 ar9003_xatten1_db_high(struct ath_hw *ah, int chain) { - return ah->eeprom.ar9300_eep_v1.base_ext2.xatten1DBHigh[chain]; + return AR_SREV_AR9300_EEPROM_V2(ah) ? + ah->eeprom.ar9300_eep_v2.base_ext2.xatten1DBHigh[chain] : + ah->eeprom.ar9300_eep_v1.base_ext2.xatten1DBHigh[chain]; } static u8 ar9003_xatten1_db_low(struct ath_hw *ah, int chain) { - return ah->eeprom.ar9300_eep_v1.base_ext2.xatten1DBLow[chain]; + return AR_SREV_AR9300_EEPROM_V2(ah) ? + ah->eeprom.ar9300_eep_v2.base_ext2.xatten1DBLow[chain] : + ah->eeprom.ar9300_eep_v1.base_ext2.xatten1DBLow[chain]; } static u8 ar9003_xatten1_db_margin_high(struct ath_hw *ah, int chain) { - return ah->eeprom.ar9300_eep_v1.base_ext2.xatten1MarginHigh[chain]; + return AR_SREV_AR9300_EEPROM_V2(ah) ? + ah->eeprom.ar9300_eep_v2.base_ext2 + .xatten1MarginHigh[chain] : + ah->eeprom.ar9300_eep_v1.base_ext2 + .xatten1MarginHigh[chain]; } static u8 ar9003_xatten1_db_margin_low(struct ath_hw *ah, int chain) { - return ah->eeprom.ar9300_eep_v1.base_ext2.xatten1MarginLow[chain]; + return AR_SREV_AR9300_EEPROM_V2(ah) ? ah->eeprom.ar9300_eep_v2.base_ext2 + .xatten1MarginLow[chain] : + ah->eeprom.ar9300_eep_v1.base_ext2 + .xatten1MarginLow[chain]; } static u8 ar9003_xatten1_db(struct ath_hw *ah, int chain, bool is2ghz) { - return ar9003_modal_header(ah, is2ghz)->xatten1DB[chain]; + return AR_SREV_AR9300_EEPROM_V2(ah) ? + ar9003_modal_header_v2(ah, is2ghz)->xatten1DB[chain] : + ar9003_modal_header_v1(ah, is2ghz)->xatten1DB[chain]; } static u8 ar9003_xatten1_margin(struct ath_hw *ah, int chain, bool is2ghz) { - return ar9003_modal_header(ah, is2ghz)->xatten1Margin[chain]; + return AR_SREV_AR9300_EEPROM_V2(ah) ? + ar9003_modal_header_v2(ah, is2ghz)->xatten1Margin[chain] : + ar9003_modal_header_v1(ah, is2ghz)->xatten1Margin[chain]; } static u8 ar9003_xlna_bias_strength(struct ath_hw *ah, bool is2ghz) { - return ar9003_modal_header(ah, is2ghz)->xlna_bias_strength; + return AR_SREV_AR9300_EEPROM_V2(ah) ? + ar9003_modal_header_v2(ah, is2ghz)->xlna_bias_strength : + ar9003_modal_header_v1(ah, is2ghz)->xlna_bias_strength; } static u8 ar9003_xpa_bias_lvl(struct ath_hw *ah, bool is2ghz) { - return ar9003_modal_header(ah, is2ghz)->xpaBiasLvl; + return AR_SREV_AR9300_EEPROM_V2(ah) ? + ar9003_modal_header_v2(ah, is2ghz)->xpaBiasLvl : + ar9003_modal_header_v1(ah, is2ghz)->xpaBiasLvl; } static u8 *ar9003_mac_addr(struct ath_hw *ah) { - return ah->eeprom.ar9300_eep_v1.macAddr; + return AR_SREV_AR9300_EEPROM_V2(ah) ? ah->eeprom.ar9300_eep_v2.macAddr : + ah->eeprom.ar9300_eep_v1.macAddr; } static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is2ghz) { - return le16_to_cpu(ar9003_modal_header(ah, is2ghz)->switchcomspdt); + __le16 val = AR_SREV_AR9300_EEPROM_V2(ah) ? + ar9003_modal_header_v2(ah, is2ghz)->switchcomspdt : + ar9003_modal_header_v1(ah, is2ghz)->switchcomspdt; + return le16_to_cpu(val); } static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah, @@ -3512,7 +3658,10 @@ static int ar9300_eeprom_restore_internal(struct ath_hw *ah, int it; u16 checksum, mchecksum; struct ath_common *common = ath9k_hw_common(ah); - struct ar9300_eeprom_v1 *eep; + union { + struct ar9300_eeprom_v1 v1; + struct ar9300_eeprom_v2 v2; + } *eep; eeprom_read_op read; if (ath9k_hw_use_flash(ah)) { @@ -3522,8 +3671,10 @@ static int ar9300_eeprom_restore_internal(struct ath_hw *ah, return -EIO; /* check if eeprom contains valid data */ - eep = (struct ar9300_eeprom_v1 *) mptr; - txrx = eep->baseEepHeader.txrxMask; + eep = (void *)mptr; + txrx = AR_SREV_AR9300_EEPROM_V2(ah) ? + eep->v2.baseEepHeader.txrxMask : + eep->v1.baseEepHeader.txrxMask; if (txrx != 0 && txrx != 0xff) return 0; } @@ -3625,10 +3776,12 @@ static int ar9300_eeprom_restore_internal(struct ath_hw *ah, */ static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah) { - u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep_v1; + u8 *mptr = (u8 *)&ah->eeprom; + int mdata_size = AR_SREV_AR9300_EEPROM_V2(ah) ? + sizeof(struct ar9300_eeprom_v2) : + sizeof(struct ar9300_eeprom_v1); - if (ar9300_eeprom_restore_internal(ah, mptr, - sizeof(struct ar9300_eeprom_v1)) < 0) + if (ar9300_eeprom_restore_internal(ah, mptr, mdata_size) < 0) return false; return true; @@ -3638,32 +3791,44 @@ static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah) static int8_t ar9003_adc_desired_size(struct ath_hw *ah, bool is2ghz) { - return ar9003_modal_header(ah, is2ghz)->adcDesiredSize; + return AR_SREV_AR9300_EEPROM_V2(ah) ? + ar9003_modal_header_v2(ah, is2ghz)->adcDesiredSize : + ar9003_modal_header_v1(ah, is2ghz)->adcDesiredSize; } static u8 ar9003_switch_settling(struct ath_hw *ah, bool is2ghz) { - return ar9003_modal_header(ah, is2ghz)->switchSettling; + return AR_SREV_AR9300_EEPROM_V2(ah) ? + ar9003_modal_header_v2(ah, is2ghz)->switchSettling : + ar9003_modal_header_v1(ah, is2ghz)->switchSettling; } static u8 ar9003_tx_clip(struct ath_hw *ah, bool is2ghz) { - return ar9003_modal_header(ah, is2ghz)->txClip; + return AR_SREV_AR9300_EEPROM_V2(ah) ? + ar9003_modal_header_v2(ah, is2ghz)->txClip : + ar9003_modal_header_v1(ah, is2ghz)->txClip; } static u8 ar9003_tx_frame_to_data_start(struct ath_hw *ah, bool is2ghz) { - return ar9003_modal_header(ah, is2ghz)->txFrameToDataStart; + return AR_SREV_AR9300_EEPROM_V2(ah) ? + ar9003_modal_header_v2(ah, is2ghz)->txFrameToDataStart : + ar9003_modal_header_v1(ah, is2ghz)->txFrameToDataStart; } static u8 ar9003_tx_frame_to_pa_on(struct ath_hw *ah, bool is2ghz) { - return ar9003_modal_header(ah, is2ghz)->txFrameToPaOn; + return AR_SREV_AR9300_EEPROM_V2(ah) ? + ar9003_modal_header_v2(ah, is2ghz)->txFrameToPaOn : + ar9003_modal_header_v1(ah, is2ghz)->txFrameToPaOn; } static int8_t ar9003_volt_slope(struct ath_hw *ah, bool is2ghz) { - return ar9003_modal_header(ah, is2ghz)->voltSlope; + return AR_SREV_AR9300_EEPROM_V2(ah) ? + ar9003_modal_header_v2(ah, is2ghz)->voltSlope : + ar9003_modal_header_v1(ah, is2ghz)->voltSlope; } static u32 ar9003_dump_modal_eeprom(struct ath_hw *ah, char *buf, u32 len, @@ -5768,17 +5933,27 @@ s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah) u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is2ghz) { - return ar9003_modal_header(ah, is2ghz)->spurChans; + return AR_SREV_AR9300_EEPROM_V2(ah) ? + ar9003_modal_header_v2(ah, is2ghz)->spurChans : + ar9003_modal_header_v1(ah, is2ghz)->spurChans; } u32 ar9003_get_paprd_rate_mask_ht20(struct ath_hw *ah, bool is2ghz) { - return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->papdRateMaskHt20); + __le32 val = + AR_SREV_AR9300_EEPROM_V2(ah) ? + ar9003_modal_header_v2(ah, is2ghz)->papdRateMaskHt20 : + ar9003_modal_header_v1(ah, is2ghz)->papdRateMaskHt20; + return le32_to_cpu(val); } u32 ar9003_get_paprd_rate_mask_ht40(struct ath_hw *ah, bool is2ghz) { - return le32_to_cpu(ar9003_modal_header(ah, is2ghz)->papdRateMaskHt40); + __le32 val = + AR_SREV_AR9300_EEPROM_V2(ah) ? + ar9003_modal_header_v2(ah, is2ghz)->papdRateMaskHt40 : + ar9003_modal_header_v1(ah, is2ghz)->papdRateMaskHt40; + return le32_to_cpu(val); } unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah, diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h index b020092e8..8516d9705 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h +++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h @@ -42,6 +42,7 @@ #define AR9300_CUSTOMER_DATA_SIZE 20 #define AR9300_EEPROM_V1_MAX_CHAINS 3 +#define AR9300_EEPROM_V2_MAX_CHAINS 4 #define AR9300_ANT_16S 25 #define AR9300_FUTURE_MODAL_SZ 6 @@ -252,6 +253,45 @@ struct ar9300_modal_eep_header_v1 { u8 futureModal[7]; } __packed; +struct ar9300_modal_eep_header_v2 { + /* 4 idle, t1, t2, b (4 bits per setting) */ + __le32 antCtrlCommon; + /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */ + __le32 antCtrlCommon2; + /* 6 idle, t, r, rx1, rx12, b (2 bits each) */ + __le16 antCtrlChain[AR9300_EEPROM_V2_MAX_CHAINS]; + /* 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */ + u8 xatten1DB[AR9300_EEPROM_V2_MAX_CHAINS]; + /* 3 xatten1_margin for merlin (0xa20c/b20c 16:12 */ + u8 xatten1Margin[AR9300_EEPROM_V2_MAX_CHAINS]; + int8_t tempSlope; + int8_t voltSlope; + /* spur channels in usual fbin coding format */ + u8 spurChans[AR_EEPROM_MODAL_SPURS]; + /* 3 Check if the register is per chain */ + int8_t noiseFloorThreshCh[AR9300_EEPROM_V2_MAX_CHAINS]; + u8 reserved[13]; + int8_t quick_drop; + u8 xpaBiasLvl; + u8 txFrameToDataStart; + u8 txFrameToPaOn; + u8 txClip; + int8_t antennaGain; + u8 switchSettling; + int8_t adcDesiredSize; + u8 txEndToXpaOff; + u8 txEndToRxOn; + u8 txFrameToXpaOn; + u8 thresh62; + __le32 papdRateMaskHt20; + __le32 reserved2; + __le32 papdRateMaskHt40; + __le32 reserved3; + __le16 switchcomspdt; + u8 xlna_bias_strength; + u8 futureModal[7]; +} __packed; + struct ar9300_cal_data_per_freq_op_loop { int8_t refPower; /* pdadc voltage at power measurement */ @@ -274,6 +314,10 @@ struct cal_tgt_pow_ht_v1 { u8 tPow2x[14]; } __packed; +struct cal_tgt_pow_ht_v2 { + u8 tPow2x[18]; +} __packed; + struct cal_ctl_data_2g { u8 ctlEdges[AR9300_NUM_BAND_EDGES_2G]; } __packed; @@ -309,6 +353,15 @@ struct ar9300_BaseExtension_2_v1 { u8 xatten1MarginHigh[AR9300_EEPROM_V1_MAX_CHAINS]; } __packed; +struct ar9300_BaseExtension_2_v2 { + int8_t tempSlopeLow; + int8_t tempSlopeHigh; + u8 xatten1DBLow[AR9300_EEPROM_V2_MAX_CHAINS]; + u8 xatten1MarginLow[AR9300_EEPROM_V2_MAX_CHAINS]; + u8 xatten1DBHigh[AR9300_EEPROM_V2_MAX_CHAINS]; + u8 xatten1MarginHigh[AR9300_EEPROM_V2_MAX_CHAINS]; +} __packed; + struct ar9300_eeprom_v1 { u8 eepromVersion; u8 templateVersion; @@ -356,6 +409,53 @@ struct ar9300_eeprom_v1 { struct cal_ctl_data_5g ctlPowerData_5G[AR9300_NUM_CTLS_5G]; } __packed; +struct ar9300_eeprom_v2 { + u8 eepromVersion; + u8 templateVersion; + u8 macAddr[6]; + u8 custData[AR9300_CUSTOMER_DATA_SIZE]; + + struct ar9300_base_eep_hdr baseEepHeader; + + struct ar9300_modal_eep_header_v2 modalHeader2G; + struct ar9300_BaseExtension_1 base_ext1; + u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS]; + struct ar9300_cal_data_per_freq_op_loop + calPierData2G[AR9300_EEPROM_V2_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS]; + u8 calTarget_freqbin_Cck[AR9300_NUM_2G_CCK_TARGET_POWERS]; + u8 calTarget_freqbin_2G[AR9300_NUM_2G_20_TARGET_POWERS]; + u8 calTarget_freqbin_2GHT20[AR9300_NUM_2G_20_TARGET_POWERS]; + u8 calTarget_freqbin_2GHT40[AR9300_NUM_2G_40_TARGET_POWERS]; + struct cal_tgt_pow_legacy + calTargetPowerCck[AR9300_NUM_2G_CCK_TARGET_POWERS]; + struct cal_tgt_pow_legacy + calTargetPower2G[AR9300_NUM_2G_20_TARGET_POWERS]; + struct cal_tgt_pow_ht_v2 + calTargetPower2GHT20[AR9300_NUM_2G_20_TARGET_POWERS]; + struct cal_tgt_pow_ht_v2 + calTargetPower2GHT40[AR9300_NUM_2G_40_TARGET_POWERS]; + u8 ctlIndex_2G[AR9300_NUM_CTLS_2G]; + u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G]; + struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G]; + struct ar9300_modal_eep_header_v2 modalHeader5G; + struct ar9300_BaseExtension_2_v2 base_ext2; + u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS]; + struct ar9300_cal_data_per_freq_op_loop + calPierData5G[AR9300_EEPROM_V2_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS]; + u8 calTarget_freqbin_5G[AR9300_NUM_5G_20_TARGET_POWERS]; + u8 calTarget_freqbin_5GHT20[AR9300_NUM_5G_20_TARGET_POWERS]; + u8 calTarget_freqbin_5GHT40[AR9300_NUM_5G_40_TARGET_POWERS]; + struct cal_tgt_pow_legacy + calTargetPower5G[AR9300_NUM_5G_20_TARGET_POWERS]; + struct cal_tgt_pow_ht_v2 + calTargetPower5GHT20[AR9300_NUM_5G_20_TARGET_POWERS]; + struct cal_tgt_pow_ht_v2 + calTargetPower5GHT40[AR9300_NUM_5G_40_TARGET_POWERS]; + u8 ctlIndex_5G[AR9300_NUM_CTLS_5G]; + u8 ctl_freqbin_5G[AR9300_NUM_CTLS_5G][AR9300_NUM_BAND_EDGES_5G]; + struct cal_ctl_data_5g ctlPowerData_5G[AR9300_NUM_CTLS_5G]; +} __packed; + s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah); s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah); u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz); diff --git a/drivers/net/wireless/ath/ath9k/hw.h b/drivers/net/wireless/ath/ath9k/hw.h index 22349c2b7..c5111735c 100644 --- a/drivers/net/wireless/ath/ath9k/hw.h +++ b/drivers/net/wireless/ath/ath9k/hw.h @@ -790,6 +790,7 @@ struct ath_hw { struct ar5416_eeprom_4k map4k; struct ar9287_eeprom map9287; struct ar9300_eeprom_v1 ar9300_eep_v1; + struct ar9300_eeprom_v2 ar9300_eep_v2; } eeprom; const struct eeprom_ops *eep_ops; diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h index 5ec263b7f..38cf3f576 100644 --- a/drivers/net/wireless/ath/ath9k/reg.h +++ b/drivers/net/wireless/ath/ath9k/reg.h @@ -1000,6 +1000,7 @@ (AR_SREV_9340(_ah) || AR_SREV_9531(_ah) || AR_SREV_9550(_ah) || \ AR_SREV_9561(_ah) || AR_SREV_5502(_ah)) #define AR_SREV_AR9003_RXS_V2(_ah) (AR_SREV_5502(_ah)) +#define AR_SREV_AR9300_EEPROM_V2(_ah) (AR_SREV_5502(_ah)) /* NOTE: When adding chips newer than Peacock, add chip check here */ #define AR_SREV_9580_10_OR_LATER(_ah) \ -- 2.25.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 0/9] ath9k: add support for QCN550x 2022-04-18 7:13 [PATCH 0/9] ath9k: add support for QCN550x Wenli Looi ` (8 preceding siblings ...) 2022-04-18 7:13 ` [PATCH 9/9] ath9k: add ar9300_eeprom_v2 Wenli Looi @ 2022-05-10 18:39 ` Wenli Looi 2022-05-11 4:39 ` Kalle Valo 9 siblings, 1 reply; 15+ messages in thread From: Wenli Looi @ 2022-05-10 18:39 UTC (permalink / raw) To: Toke Høiland-Jørgensen, Kalle Valo; +Cc: linux-wireless Thanks Kalle for the comments. Please let me know if I should resend the patch with the minor changes or if there are additional comments. It would probably be ideal if this patch could be reviewed by someone who is familiar with this device and could provide official initvals like described here: https://wireless.wiki.kernel.org/en/users/drivers/ath9k/initvals-tool#synch_initvals_from_the_atheros_hal I would be happy to test other initvals on my device. The hacked QCA956x initvals do appear to work stably for me though so this could be done later. ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 0/9] ath9k: add support for QCN550x 2022-05-10 18:39 ` [PATCH 0/9] ath9k: add support for QCN550x Wenli Looi @ 2022-05-11 4:39 ` Kalle Valo 2022-05-11 9:54 ` Toke Høiland-Jørgensen 0 siblings, 1 reply; 15+ messages in thread From: Kalle Valo @ 2022-05-11 4:39 UTC (permalink / raw) To: Wenli Looi; +Cc: Toke Høiland-Jørgensen, linux-wireless Wenli Looi <wlooi@ucalgary.ca> writes: > Thanks Kalle for the comments. > > Please let me know if I should resend the patch with the minor changes > or if there are additional comments. The patchset is set to 'Changes Requested' in patchwork: https://patchwork.kernel.org/project/linux-wireless/list/?series=632942&state=*&order=date This means you need to submit v2. -- https://patchwork.kernel.org/project/linux-wireless/list/ https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 0/9] ath9k: add support for QCN550x 2022-05-11 4:39 ` Kalle Valo @ 2022-05-11 9:54 ` Toke Høiland-Jørgensen 0 siblings, 0 replies; 15+ messages in thread From: Toke Høiland-Jørgensen @ 2022-05-11 9:54 UTC (permalink / raw) To: Kalle Valo, Wenli Looi; +Cc: linux-wireless Kalle Valo <kvalo@kernel.org> writes: > Wenli Looi <wlooi@ucalgary.ca> writes: > >> Thanks Kalle for the comments. >> >> Please let me know if I should resend the patch with the minor changes >> or if there are additional comments. > > The patchset is set to 'Changes Requested' in patchwork: > > https://patchwork.kernel.org/project/linux-wireless/list/?series=632942&state=*&order=date > > This means you need to submit v2. Yes, please resubmit with Kalle's comments addressed :) -Toke ^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2022-05-11 9:55 UTC | newest] Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-04-18 7:13 [PATCH 0/9] ath9k: add support for QCN550x Wenli Looi 2022-04-18 7:13 ` [PATCH 1/9] ath9k: add QCN550x device IDs Wenli Looi 2022-04-20 12:00 ` Kalle Valo 2022-04-18 7:13 ` [PATCH 2/9] ath9k: basic support for QCN550x Wenli Looi 2022-04-20 12:01 ` Kalle Valo 2022-04-18 7:13 ` [PATCH 3/9] ath9k: add QCN550x initvals Wenli Looi 2022-04-18 7:13 ` [PATCH 4/9] ath9k: implement QCN550x rx Wenli Looi 2022-04-18 7:13 ` [PATCH 5/9] ath9k: implement QCN550x tx Wenli Looi 2022-04-18 7:13 ` [PATCH 6/9] ath9k: group some ar9300 eeprom functions at the top Wenli Looi 2022-04-18 7:13 ` [PATCH 7/9] ath9k: add abstractions over ar9300 eeprom Wenli Looi 2022-04-18 7:13 ` [PATCH 8/9] ath9k: rename ar9300_eeprom to ar9300_eeprom_v1 Wenli Looi 2022-04-18 7:13 ` [PATCH 9/9] ath9k: add ar9300_eeprom_v2 Wenli Looi 2022-05-10 18:39 ` [PATCH 0/9] ath9k: add support for QCN550x Wenli Looi 2022-05-11 4:39 ` Kalle Valo 2022-05-11 9:54 ` Toke Høiland-Jørgensen
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