RE: AW: PowerPC PCI DMA issues (prefetch/coherency?)

["Prodyut Hazarika" <phazarika@amcc.com>]

> We have found that using flush_dcache_range() after each DMA solves
the
> problem. Ideally, we'd like to be able to allocate the virtual page in
> cache inhibited memory to avoid the performance loss from all the
flush
> calls. To do this, we'd have to change our TLB sizes and reserve a TLB
> in memory as cache inhibited (using the 'I' bit). Will update if this
> works as well. Thanks for your help in this.

Aren't you using dma_alloc_coherent to get buffers that are shared
between CPU and external devices?

Thanks
Prodyut

On Tue, 2009-09-08 at 11:59 -0700, Prodyut Hazarika wrote:
> Hi Adam,
>=20
> > Yes, I am using the 440EPx (same as the sequoia board).=20
> > Our ideDriver is DMA'ing blocks of 192-byte data over the PCI bus
> (using
> > the Sil0680A PCI-IDE bridge). Most of the DMA's (depending on
timing)
> > end up being partially corrupted when we try to parse the data in
the
> > virtual page. We have confirmed the data is good before the PCI-IDE
> > bridge. We are creating two 8K pages and map them to physical DMA
> memory
> > using single-entry scatter/gather structs. When a DMA block is
> > corrupted, we see a random portion of it (always a multiple of
16byte
> > cache lines) is overwritten with old data from the last time the
> buffer
> > was used.=20
>=20
> This looks like a cache coherency problem.
> Can you ensure that the TLB entries corresponding to the DMA region
has
> the CacheInhibit bit set.
> You will need a BDI connected to your system.
>=20
> Also, you will need to invalidate and flush the lines appropriately,
> since in 440 cores,
> L1Cache coherency is managed entirely by software.
> Please look at drivers/net/ibm_newemac/mal.c and core.c for example on
> how to do it.
>=20
> Thanks
> Prodyut
>=20
> On Thu, 2009-09-03 at 13:27 -0700, Prodyut Hazarika wrote:
> > Hi Adam,
> >=20
> > > Are you sure there is L2 cache on the 440?
> >=20
> > It depends on the SoC you are using. SoC like 460EX (Canyonlands
> board)
> > have L2Cache.
> > It seems you are using a Sequoia board, which has a 440EPx SoC.
440EPx
> > has a 440 cpu core, but no L2Cache.
> > Could you please tell me which SoC you are using?
> > You can also refer to the appropriate dts file to see if there is
L2C.
> > For example, in canyonlands.dts (460EX based board), we have the L2C
> > entry.
> >         L2C0: l2c {
> >               ...
> >         }
> >=20
> > >I am seeing this problem with our custom IDE driver which is based
on
>=20
> > >pretty old code. Our driver uses pci_alloc_consistent() to allocate
> the
> >=20
> > >physical DMA memory and alloc_pages() to allocate a virtual page.
It=20
> > >then uses pci_map_sg() to map to a scatter/gather buffer. Perhaps I

> > >should convert these to the DMA API calls as you suggest.
> >=20
> > Could you give more details on the consistency problem? It is a good
> > idea to change to the new DMA APIs, but pci_alloc_consistent()
should
> > work too
> >=20
> > Thanks
> > Prodyut=09
> >=20
> > On Thu, 2009-09-03 at 19:57 +1000, Benjamin Herrenschmidt wrote:
> > > On Thu, 2009-09-03 at 09:05 +0100, Chris Pringle wrote:
> > > > Hi Adam,
> > > >=20
> > > > If you have a look in include/asm-ppc/pgtable.h for the
following
> > section:
> > > > #ifdef CONFIG_44x
> > > > #define _PAGE_BASE    (_PAGE_PRESENT | _PAGE_ACCESSED |
> > _PAGE_GUARDED)
> > > > #else
> > > > #define _PAGE_BASE    (_PAGE_PRESENT | _PAGE_ACCESSED)
> > > > #endif
> > > >=20
> > > > Try adding _PAGE_COHERENT to the appropriate line above and see
if
> > that=20
> > > > fixes your issue - this causes the 'M' bit to be set on the page
> > which=20
> > > > sure enforce cache coherency. If it doesn't, you'll need to
check
> > the=20
> > > > 'M' bit isn't being masked out in head_44x.S (it was originally
> > masked=20
> > > > out on arch/powerpc, but was fixed in later kernels when the
cache
>=20
> > > > coherency issues with non-SMP systems were resolved).
> > >=20
> > > I have some doubts about the usefulness of doing that for 4xx.
> AFAIK,
> > > the 440 core just ignores M.
> > >=20
> > > The problem lies probably elsewhere. Maybe the L2 cache coherency
> > isn't
> > > enabled or not working ?
> > >=20
> > > The L1 cache on 440 is simply not coherent, so drivers have to
make
> > sure
> > > they use the appropriate DMA APIs which will do cache flushing
when
> > > needed.
> > >=20
> > > Adam, what driver is causing you that sort of problems ?
> > >=20
> > > Cheers,
> > > Ben.
> > >=20
> > >=20
> --=20
> Adam Zilkie
> Software Designer,
> International Datacasting Corp.
>=20
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>=20
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Adam Zilkie
Software Designer,
International Datacasting Corp.

This message and the documents attached hereto are intended only for the
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