Re: AW: PowerPC PCI DMA issues (prefetch/coherency?)

[Benjamin Herrenschmidt <benh@kernel.crashing.org>]

On Thu, 2009-09-03 at 09:05 +0100, Chris Pringle wrote:
> Hi Adam,
> 
> If you have a look in include/asm-ppc/pgtable.h for the following section:
> #ifdef CONFIG_44x
> #define _PAGE_BASE    (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_GUARDED)
> #else
> #define _PAGE_BASE    (_PAGE_PRESENT | _PAGE_ACCESSED)
> #endif
> 
> Try adding _PAGE_COHERENT to the appropriate line above and see if that 
> fixes your issue - this causes the 'M' bit to be set on the page which 
> sure enforce cache coherency. If it doesn't, you'll need to check the 
> 'M' bit isn't being masked out in head_44x.S (it was originally masked 
> out on arch/powerpc, but was fixed in later kernels when the cache 
> coherency issues with non-SMP systems were resolved).

I have some doubts about the usefulness of doing that for 4xx. AFAIK,
the 440 core just ignores M.

The problem lies probably elsewhere. Maybe the L2 cache coherency isn't
enabled or not working ?

The L1 cache on 440 is simply not coherent, so drivers have to make sure
they use the appropriate DMA APIs which will do cache flushing when
needed.

Adam, what driver is causing you that sort of problems ?

Cheers,
Ben.