From: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
To: Benjamin Herrenschmidt <benh@kernel.crashing.org>,
"linuxppc-dev@ozlabs.org" <linuxppc-dev@ozlabs.org>,
Rex Feany <RFeany@mrv.com>, Scott Wood <scottwood@freescale.com>
Subject: [PATCH 7/8] 8xx: Restore _PAGE_WRITETHRU
Date: Sun, 11 Oct 2009 18:35:11 +0200 [thread overview]
Message-ID: <1255278912-8042-8-git-send-email-Joakim.Tjernlund@transmode.se> (raw)
In-Reply-To: <1255278912-8042-7-git-send-email-Joakim.Tjernlund@transmode.se>
8xx has not had WRITETHRU due to lack of bits in the pte.
After the recent rewrite of the 8xx TLB code, there are
two bits left. Use one of them to WRITETHRU.
Perhaps use the last SW bit to PAGE_SPECIAL or PAGE_FILE?
---
arch/powerpc/include/asm/pte-8xx.h | 5 +++--
arch/powerpc/kernel/head_8xx.S | 8 ++++++++
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/include/asm/pte-8xx.h b/arch/powerpc/include/asm/pte-8xx.h
index f23cd15..9349d83 100644
--- a/arch/powerpc/include/asm/pte-8xx.h
+++ b/arch/powerpc/include/asm/pte-8xx.h
@@ -34,12 +34,13 @@
#define _PAGE_SHARED 0x0004 /* No ASID (context) compare */
#define _PAGE_DIRTY 0x0100 /* C: page changed */
-/* These 3 software bits must be masked out when the entry is loaded
- * into the TLB, 2 SW bits left.
+/* These 4 software bits must be masked out when the entry is loaded
+ * into the TLB, 1 SW bit left(0x0080).
*/
#define _PAGE_EXEC 0x0008 /* software: i-cache coherency required */
#define _PAGE_GUARDED 0x0010 /* software: guarded access */
#define _PAGE_ACCESSED 0x0020 /* software: page referenced */
+#define _PAGE_WRITETHRU 0x0040 /* software: caching is write through */
/* Setting any bits in the nibble with the follow two controls will
* require a TLB exception handler change. It is assumed unused bits
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 371b606..db5207e 100644
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -422,6 +422,10 @@ DataStoreTLBMiss:
* above.
*/
rlwimi r11, r10, 0, 27, 27
+ /* Insert the WriteThru flag into the TWC from the Linux PTE.
+ * It is bit 25 in the Linux PTE and bit 30 in the TWC
+ */
+ rlwimi r11, r10, 32-5, 30, 30
DO_8xx_CPU6(0x3b80, r3)
mtspr SPRN_MD_TWC, r11
@@ -559,6 +563,10 @@ DARFix: /* Return from dcbx instruction bug workaround, r10 holds value of DAR *
* It is bit 27 of both the Linux PTE and the TWC
*/
rlwimi r11, r10, 0, 27, 27
+ /* Insert the WriteThru flag into the TWC from the Linux PTE.
+ * It is bit 25 in the Linux PTE and bit 30 in the TWC
+ */
+ rlwimi r11, r10, 32-5, 30, 30
DO_8xx_CPU6(0x3b80, r3)
mtspr SPRN_MD_TWC, r11
mfspr r11, SPRN_MD_TWC /* get the pte address again */
--
1.6.4.4
next prev parent reply other threads:[~2009-10-11 16:35 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-10-11 16:35 [PATCH 0/8] Fix 8xx MMU/TLB Joakim Tjernlund
2009-10-11 16:35 ` [PATCH 1/8] 8xx: invalidate non present TLBs Joakim Tjernlund
2009-10-11 16:35 ` [PATCH 2/8] 8xx: Update TLB asm so it behaves as linux mm expects Joakim Tjernlund
2009-10-11 16:35 ` [PATCH 3/8] 8xx: Tag DAR with 0x00f0 to catch buggy instructions Joakim Tjernlund
2009-10-11 16:35 ` [PATCH 4/8] 8xx: Fixup DAR from buggy dcbX instructions Joakim Tjernlund
2009-10-11 16:35 ` [PATCH 5/8] 8xx: dcbst sets store bit in DTLB error, workaround Joakim Tjernlund
2009-10-11 16:35 ` [PATCH 6/8] 8xx: Add missing Guarded setting in DTLB Error Joakim Tjernlund
2009-10-11 16:35 ` Joakim Tjernlund [this message]
2009-10-11 16:35 ` [PATCH 8/8] 8xx: start using dcbX instructions in various copy routines Joakim Tjernlund
2009-10-11 21:26 ` [PATCH 7/8] 8xx: Restore _PAGE_WRITETHRU Benjamin Herrenschmidt
2009-10-11 22:21 ` Joakim Tjernlund
2009-10-11 22:45 ` Benjamin Herrenschmidt
2009-10-11 21:25 ` [PATCH 6/8] 8xx: Add missing Guarded setting in DTLB Error Benjamin Herrenschmidt
2009-10-11 22:19 ` Joakim Tjernlund
2009-10-11 22:44 ` Benjamin Herrenschmidt
2009-10-12 5:36 ` Joakim Tjernlund
2009-10-12 5:46 ` Benjamin Herrenschmidt
2009-10-12 6:59 ` Joakim Tjernlund
2009-10-14 17:02 ` [PATCH 5/8] 8xx: dcbst sets store bit in DTLB error, workaround Scott Wood
2009-10-14 17:20 ` [PATCH 4/8] 8xx: Fixup DAR from buggy dcbX instructions Scott Wood
2009-10-14 19:05 ` Joakim Tjernlund
2009-10-14 19:23 ` Scott Wood
2009-10-14 20:03 ` Joakim Tjernlund
2009-10-14 20:22 ` Scott Wood
2009-10-14 21:10 ` Joakim Tjernlund
2009-10-14 21:14 ` Scott Wood
2009-10-14 21:17 ` Benjamin Herrenschmidt
2009-10-14 21:41 ` Joakim Tjernlund
2009-10-14 21:52 ` Benjamin Herrenschmidt
2009-10-14 22:09 ` Joakim Tjernlund
2009-10-11 21:25 ` [PATCH 2/8] 8xx: Update TLB asm so it behaves as linux mm expects Benjamin Herrenschmidt
2009-10-14 16:57 ` Scott Wood
2009-10-14 16:56 ` [PATCH 1/8] 8xx: invalidate non present TLBs Scott Wood
2009-10-14 17:23 ` [PATCH 0/8] Fix 8xx MMU/TLB Scott Wood
2009-10-14 18:46 ` Joakim Tjernlund
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