From: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
To: Benjamin Herrenschmidt <benh@kernel.crashing.org>,
"linuxppc-dev@ozlabs.org" <linuxppc-dev@ozlabs.org>,
Rex Feany <RFeany@mrv.com>, Scott Wood <scottwood@freescale.com>
Subject: [PATCH 8/8] 8xx: start using dcbX instructions in various copy routines
Date: Sun, 11 Oct 2009 18:35:12 +0200 [thread overview]
Message-ID: <1255278912-8042-9-git-send-email-Joakim.Tjernlund@transmode.se> (raw)
In-Reply-To: <1255278912-8042-8-git-send-email-Joakim.Tjernlund@transmode.se>
Now that 8xx can fixup dcbX instructions, start using them
where possible like every other PowerPc arch do.
---
arch/powerpc/kernel/misc_32.S | 18 ------------------
arch/powerpc/lib/copy_32.S | 24 ------------------------
2 files changed, 0 insertions(+), 42 deletions(-)
diff --git a/arch/powerpc/kernel/misc_32.S b/arch/powerpc/kernel/misc_32.S
index 15f28e0..b92095e 100644
--- a/arch/powerpc/kernel/misc_32.S
+++ b/arch/powerpc/kernel/misc_32.S
@@ -495,15 +495,7 @@ _GLOBAL(clear_pages)
li r0,PAGE_SIZE/L1_CACHE_BYTES
slw r0,r0,r4
mtctr r0
-#ifdef CONFIG_8xx
- li r4, 0
-1: stw r4, 0(r3)
- stw r4, 4(r3)
- stw r4, 8(r3)
- stw r4, 12(r3)
-#else
1: dcbz 0,r3
-#endif
addi r3,r3,L1_CACHE_BYTES
bdnz 1b
blr
@@ -528,15 +520,6 @@ _GLOBAL(copy_page)
addi r3,r3,-4
addi r4,r4,-4
-#ifdef CONFIG_8xx
- /* don't use prefetch on 8xx */
- li r0,4096/L1_CACHE_BYTES
- mtctr r0
-1: COPY_16_BYTES
- bdnz 1b
- blr
-
-#else /* not 8xx, we can prefetch */
li r5,4
#if MAX_COPY_PREFETCH > 1
@@ -577,7 +560,6 @@ _GLOBAL(copy_page)
li r0,MAX_COPY_PREFETCH
li r11,4
b 2b
-#endif /* CONFIG_8xx */
/*
* void atomic_clear_mask(atomic_t mask, atomic_t *addr)
diff --git a/arch/powerpc/lib/copy_32.S b/arch/powerpc/lib/copy_32.S
index c657de5..74a7f41 100644
--- a/arch/powerpc/lib/copy_32.S
+++ b/arch/powerpc/lib/copy_32.S
@@ -98,20 +98,7 @@ _GLOBAL(cacheable_memzero)
bdnz 4b
3: mtctr r9
li r7,4
-#if !defined(CONFIG_8xx)
10: dcbz r7,r6
-#else
-10: stw r4, 4(r6)
- stw r4, 8(r6)
- stw r4, 12(r6)
- stw r4, 16(r6)
-#if CACHE_LINE_SIZE >= 32
- stw r4, 20(r6)
- stw r4, 24(r6)
- stw r4, 28(r6)
- stw r4, 32(r6)
-#endif /* CACHE_LINE_SIZE */
-#endif
addi r6,r6,CACHELINE_BYTES
bdnz 10b
clrlwi r5,r8,32-LG_CACHELINE_BYTES
@@ -200,9 +187,7 @@ _GLOBAL(cacheable_memcpy)
mtctr r0
beq 63f
53:
-#if !defined(CONFIG_8xx)
dcbz r11,r6
-#endif
COPY_16_BYTES
#if L1_CACHE_BYTES >= 32
COPY_16_BYTES
@@ -356,14 +341,6 @@ _GLOBAL(__copy_tofrom_user)
li r11,4
beq 63f
-#ifdef CONFIG_8xx
- /* Don't use prefetch on 8xx */
- mtctr r0
- li r0,0
-53: COPY_16_BYTES_WITHEX(0)
- bdnz 53b
-
-#else /* not CONFIG_8xx */
/* Here we decide how far ahead to prefetch the source */
li r3,4
cmpwi r0,1
@@ -416,7 +393,6 @@ _GLOBAL(__copy_tofrom_user)
li r3,4
li r7,0
bne 114b
-#endif /* CONFIG_8xx */
63: srwi. r0,r5,2
mtctr r0
--
1.6.4.4
next prev parent reply other threads:[~2009-10-11 16:35 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-10-11 16:35 [PATCH 0/8] Fix 8xx MMU/TLB Joakim Tjernlund
2009-10-11 16:35 ` [PATCH 1/8] 8xx: invalidate non present TLBs Joakim Tjernlund
2009-10-11 16:35 ` [PATCH 2/8] 8xx: Update TLB asm so it behaves as linux mm expects Joakim Tjernlund
2009-10-11 16:35 ` [PATCH 3/8] 8xx: Tag DAR with 0x00f0 to catch buggy instructions Joakim Tjernlund
2009-10-11 16:35 ` [PATCH 4/8] 8xx: Fixup DAR from buggy dcbX instructions Joakim Tjernlund
2009-10-11 16:35 ` [PATCH 5/8] 8xx: dcbst sets store bit in DTLB error, workaround Joakim Tjernlund
2009-10-11 16:35 ` [PATCH 6/8] 8xx: Add missing Guarded setting in DTLB Error Joakim Tjernlund
2009-10-11 16:35 ` [PATCH 7/8] 8xx: Restore _PAGE_WRITETHRU Joakim Tjernlund
2009-10-11 16:35 ` Joakim Tjernlund [this message]
2009-10-11 21:26 ` Benjamin Herrenschmidt
2009-10-11 22:21 ` Joakim Tjernlund
2009-10-11 22:45 ` Benjamin Herrenschmidt
2009-10-11 21:25 ` [PATCH 6/8] 8xx: Add missing Guarded setting in DTLB Error Benjamin Herrenschmidt
2009-10-11 22:19 ` Joakim Tjernlund
2009-10-11 22:44 ` Benjamin Herrenschmidt
2009-10-12 5:36 ` Joakim Tjernlund
2009-10-12 5:46 ` Benjamin Herrenschmidt
2009-10-12 6:59 ` Joakim Tjernlund
2009-10-14 17:02 ` [PATCH 5/8] 8xx: dcbst sets store bit in DTLB error, workaround Scott Wood
2009-10-14 17:20 ` [PATCH 4/8] 8xx: Fixup DAR from buggy dcbX instructions Scott Wood
2009-10-14 19:05 ` Joakim Tjernlund
2009-10-14 19:23 ` Scott Wood
2009-10-14 20:03 ` Joakim Tjernlund
2009-10-14 20:22 ` Scott Wood
2009-10-14 21:10 ` Joakim Tjernlund
2009-10-14 21:14 ` Scott Wood
2009-10-14 21:17 ` Benjamin Herrenschmidt
2009-10-14 21:41 ` Joakim Tjernlund
2009-10-14 21:52 ` Benjamin Herrenschmidt
2009-10-14 22:09 ` Joakim Tjernlund
2009-10-11 21:25 ` [PATCH 2/8] 8xx: Update TLB asm so it behaves as linux mm expects Benjamin Herrenschmidt
2009-10-14 16:57 ` Scott Wood
2009-10-14 16:56 ` [PATCH 1/8] 8xx: invalidate non present TLBs Scott Wood
2009-10-14 17:23 ` [PATCH 0/8] Fix 8xx MMU/TLB Scott Wood
2009-10-14 18:46 ` Joakim Tjernlund
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