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From: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
To: linuxppc-dev <linuxppc-dev@ozlabs.org>,
	Scott Wood <scottwood@freescale.com>, Willy Tarreau <w@1wt.eu>,
	Dan Malek <ppc6dev@digitaldans.com>
Subject: [PATCH 00/14] Backport 8xx TLB to 2.4
Date: Mon, 10 Oct 2011 13:30:06 +0200	[thread overview]
Message-ID: <1318246220-4839-1-git-send-email-Joakim.Tjernlund@transmode.se> (raw)

This is a backport from 2.6 which I did to overcome 8xx CPU
bugs. 8xx does not update the DAR register when taking a TLB
error caused by dcbX and icbi insns which makes it very
tricky to use these insns. Also the dcbst wrongly sets the
the store bit when faulting into DTLB error.
A few more bugs very found during development.

I know 2.4 is in strict maintenance mode and 8xx is obsolete
but as it is still in use I wanted 8xx to age with grace.

Addendum:
I have now ported our 8xx custom board to 2.4.37.11 and
tested these patches there.

V2:
 - Remove mandatory pinning of kernel ITLB. It is not
   needed in 2.4

8 MB Large page support will follow.

Joakim Tjernlund (14):
  8xx: Use a macro to simpliy CPU6 errata code.
  8xx: Tag DAR with 0x00f0 to catch buggy instructions.
  8xx: invalidate non present TLBs
  8xx: Fix CONFIG_PIN_TLB
  8xx: Update TLB asm so it behaves as linux mm expects.
  8xx: Fixup DAR from buggy dcbX instructions.
  8xx: CPU6 errata make DTLB error too big to fit.
  8xx: Add missing Guarded setting in DTLB Error.
  8xx: Restore _PAGE_WRITETHRU
  8xx: Set correct HW pte flags in DTLB Error too
  8xx: start using dcbX instructions in various copy routines
  8xx: Use symbolic constants in TLB asm
  8xx: Optimize TLB Miss handlers
  8xx: The TLB miss handler manages ACCESSED correctly.

 arch/ppc/kernel/head_8xx.S |  367 ++++++++++++++++++++++++++++++-------------
 arch/ppc/kernel/misc.S     |   18 --
 arch/ppc/lib/string.S      |   17 --
 include/asm-ppc/pgtable.h  |   26 +--
 4 files changed, 264 insertions(+), 164 deletions(-)

-- 
1.7.3.4

             reply	other threads:[~2011-10-10 11:30 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-10-10 11:30 Joakim Tjernlund [this message]
2011-10-10 11:30 ` [PATCH 01/14] 8xx: Use a macro to simpliy CPU6 errata code Joakim Tjernlund
2011-10-10 11:30 ` [PATCH 02/14] 8xx: Tag DAR with 0x00f0 to catch buggy instructions Joakim Tjernlund
2011-10-10 11:30 ` [PATCH 03/14] 8xx: invalidate non present TLBs Joakim Tjernlund
2011-10-10 11:30 ` [PATCH 04/14] 8xx: Fix CONFIG_PIN_TLB Joakim Tjernlund
2011-10-10 11:30 ` [PATCH 05/14] 8xx: Update TLB asm so it behaves as linux mm expects Joakim Tjernlund
2011-10-10 11:30 ` [PATCH 06/14] 8xx: Fixup DAR from buggy dcbX instructions Joakim Tjernlund
2011-10-10 11:30 ` [PATCH 07/14] 8xx: CPU6 errata make DTLB error too big to fit Joakim Tjernlund
2011-10-10 11:30 ` [PATCH 08/14] 8xx: Add missing Guarded setting in DTLB Error Joakim Tjernlund
2011-10-10 11:30 ` [PATCH 09/14] 8xx: Restore _PAGE_WRITETHRU Joakim Tjernlund
2011-10-10 11:30 ` [PATCH 10/14] 8xx: Set correct HW pte flags in DTLB Error too Joakim Tjernlund
2011-10-10 11:30 ` [PATCH 11/14] 8xx: start using dcbX instructions in various copy routines Joakim Tjernlund
2011-10-10 11:30 ` [PATCH 12/14] 8xx: Use symbolic constants in TLB asm Joakim Tjernlund
2011-10-10 11:30 ` [PATCH 13/14] 8xx: Optimize TLB Miss handlers Joakim Tjernlund
2011-10-10 11:30 ` [PATCH 14/14] 8xx: The TLB miss handler manages ACCESSED correctly Joakim Tjernlund
2011-10-10 12:30 ` [PATCH 00/14] Backport 8xx TLB to 2.4 Willy Tarreau
2011-12-11 17:19 ` Joakim Tjernlund
2011-12-11 17:33   ` Willy Tarreau
2012-02-08  8:44     ` Joakim Tjernlund
2012-02-08  9:44       ` Willy Tarreau
2012-02-08 11:39         ` Joakim Tjernlund
2012-02-08 12:26           ` Willy Tarreau
2012-04-09 13:08           ` Willy Tarreau

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