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From: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
To: linuxppc-dev <linuxppc-dev@ozlabs.org>,
	Scott Wood <scottwood@freescale.com>, Willy Tarreau <w@1wt.eu>,
	Dan Malek <ppc6dev@digitaldans.com>
Subject: [PATCH 10/14] 8xx: Set correct HW pte flags in DTLB Error too
Date: Mon, 10 Oct 2011 13:30:16 +0200	[thread overview]
Message-ID: <1318246220-4839-11-git-send-email-Joakim.Tjernlund@transmode.se> (raw)
In-Reply-To: <1318246220-4839-1-git-send-email-Joakim.Tjernlund@transmode.se>

DTLB Error needs to adjust the HW PTE bits as DTLB Miss
does.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
---
 arch/ppc/kernel/head_8xx.S |    7 ++++++-
 1 files changed, 6 insertions(+), 1 deletions(-)

diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S
index 402158d..4bcd9b3 100644
--- a/arch/ppc/kernel/head_8xx.S
+++ b/arch/ppc/kernel/head_8xx.S
@@ -592,7 +592,12 @@ DARFixed:
 	mfspr	r21, MD_TWC		/* get the pte address again */
 	ori	r20, r20, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
 	stw	r20, 0(r21)		/* and update pte in table */
-	xori	r20, r20, _PAGE_RW	/* RW bit is inverted */
+	rlwimi	r20, r20, 32-2, _PAGE_USER>>2 /* Copy USER to Encoding */
+	/* r21 =  (r20 & _PAGE_RW) >> 1 */
+	rlwinm	r21, r20, 32-1, _PAGE_RW>>1
+	or	r20, r21, r20
+	/* invert RW and 0x200 bits */
+	xori	r20, r20, _PAGE_RW | 0x200
 	b	finish_DTLB
 2:
 	mfspr	r20, M_TW	/* Restore registers */
-- 
1.7.3.4

  parent reply	other threads:[~2011-10-10 11:30 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-10-10 11:30 [PATCH 00/14] Backport 8xx TLB to 2.4 Joakim Tjernlund
2011-10-10 11:30 ` [PATCH 01/14] 8xx: Use a macro to simpliy CPU6 errata code Joakim Tjernlund
2011-10-10 11:30 ` [PATCH 02/14] 8xx: Tag DAR with 0x00f0 to catch buggy instructions Joakim Tjernlund
2011-10-10 11:30 ` [PATCH 03/14] 8xx: invalidate non present TLBs Joakim Tjernlund
2011-10-10 11:30 ` [PATCH 04/14] 8xx: Fix CONFIG_PIN_TLB Joakim Tjernlund
2011-10-10 11:30 ` [PATCH 05/14] 8xx: Update TLB asm so it behaves as linux mm expects Joakim Tjernlund
2011-10-10 11:30 ` [PATCH 06/14] 8xx: Fixup DAR from buggy dcbX instructions Joakim Tjernlund
2011-10-10 11:30 ` [PATCH 07/14] 8xx: CPU6 errata make DTLB error too big to fit Joakim Tjernlund
2011-10-10 11:30 ` [PATCH 08/14] 8xx: Add missing Guarded setting in DTLB Error Joakim Tjernlund
2011-10-10 11:30 ` [PATCH 09/14] 8xx: Restore _PAGE_WRITETHRU Joakim Tjernlund
2011-10-10 11:30 ` Joakim Tjernlund [this message]
2011-10-10 11:30 ` [PATCH 11/14] 8xx: start using dcbX instructions in various copy routines Joakim Tjernlund
2011-10-10 11:30 ` [PATCH 12/14] 8xx: Use symbolic constants in TLB asm Joakim Tjernlund
2011-10-10 11:30 ` [PATCH 13/14] 8xx: Optimize TLB Miss handlers Joakim Tjernlund
2011-10-10 11:30 ` [PATCH 14/14] 8xx: The TLB miss handler manages ACCESSED correctly Joakim Tjernlund
2011-10-10 12:30 ` [PATCH 00/14] Backport 8xx TLB to 2.4 Willy Tarreau
2011-12-11 17:19 ` Joakim Tjernlund
2011-12-11 17:33   ` Willy Tarreau
2012-02-08  8:44     ` Joakim Tjernlund
2012-02-08  9:44       ` Willy Tarreau
2012-02-08 11:39         ` Joakim Tjernlund
2012-02-08 12:26           ` Willy Tarreau
2012-04-09 13:08           ` Willy Tarreau

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