[PATCH V2 2/2] powerpc/85xx: add the P1020RDB-PD DTS support

[PATCH V2 2/2] powerpc/85xx: add the P1020RDB-PD DTS support

[Haijun Zhang]

Overview of P1020RDB-PD device:
- DDR3 2GB
- NOR flash 64MB
- NAND flash 128MB
- SPI flash 16MB
- I2C EEPROM 256Kb
- eTSEC1 (RGMII PHY) connected to VSC7385 L2 switch
- eTSEC2 (SGMII PHY)
- eTSEC3 (RGMII PHY)
- SDHC
- 2 USB ports
- 4 TDM ports
- PCIe

Signed-off-by: Haijun Zhang <Haijun.Zhang@freescale.com>
Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
CC: Scott Wood <scottwood@freescale.com>
---
changes for v2:
	- Remove address cells and size cells for pc/pd board

 arch/powerpc/boot/dts/p1020rdb-pc.dtsi    |   4 +-
 arch/powerpc/boot/dts/p1020rdb-pd.dtsi    | 253 ++++++++++++++++++++++++++++++
 arch/powerpc/boot/dts/p1020rdb-pd_32b.dts |  90 +++++++++++
 3 files changed, 344 insertions(+), 3 deletions(-)
 create mode 100644 arch/powerpc/boot/dts/p1020rdb-pd.dtsi
 create mode 100644 arch/powerpc/boot/dts/p1020rdb-pd_32b.dts

diff --git a/arch/powerpc/boot/dts/p1020rdb-pc.dtsi b/arch/powerpc/boot/dts/p1020rdb-pc.dtsi
index c952cd3..9d24501 100644
--- a/arch/powerpc/boot/dts/p1020rdb-pc.dtsi
+++ b/arch/powerpc/boot/dts/p1020rdb-pc.dtsi
@@ -131,9 +131,7 @@
 	};
 
 	cpld@3,0 {
-		#address-cells = <1>;
-		#size-cells = <1>;
-		compatible = "cpld";
+		compatible = "fsl, p1020rdb-cpld";
 		reg = <0x3 0x0 0x20000>;
 		read-only;
 	};
diff --git a/arch/powerpc/boot/dts/p1020rdb-pd.dtsi b/arch/powerpc/boot/dts/p1020rdb-pd.dtsi
new file mode 100644
index 0000000..03b308d
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb-pd.dtsi
@@ -0,0 +1,253 @@
+/*
+ * P1020RDB-PD Device Tree Source stub (no addresses or top-level ranges)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+&lbc {
+	nor@0,0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "cfi-flash";
+		reg = <0x0 0x0 0x4000000>;
+		bank-width = <2>;
+		device-width = <1>;
+
+		partition@0 {
+			/* 128KB for DTB Image */
+			reg = <0x0 0x00020000>;
+			label = "NOR DTB Image";
+		};
+
+		partition@20000 {
+			/* 3.875 MB for Linux Kernel Image */
+			reg = <0x00020000 0x003e0000>;
+			label = "NOR Linux Kernel Image";
+		};
+
+		partition@400000 {
+			/* 58MB for Root file System */
+			reg = <0x00400000 0x03a00000>;
+			label = "NOR Root File System";
+		};
+
+		partition@3e00000 {
+			/* This location must not be altered  */
+			/* 1M for Vitesse 7385 Switch firmware */
+			reg = <0x3e00000 0x00100000>;
+			label = "NOR Vitesse-7385 Firmware";
+			read-only;
+		};
+
+		partition@3f00000 {
+			/* This location must not be altered  */
+			/* 512KB for u-boot Bootloader Image */
+			/* 512KB for u-boot Environment Variables */
+			reg = <0x03f00000 0x00100000>;
+			label = "NOR U-Boot Image";
+			read-only;
+		};
+	};
+
+	nand@1,0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "fsl,p1020-fcm-nand",
+			     "fsl,elbc-fcm-nand";
+		reg = <0x1 0x0 0x40000>;
+
+		partition@0 {
+			/* This location must not be altered  */
+			/* 1MB for u-boot Bootloader Image */
+			reg = <0x0 0x00100000>;
+			label = "NAND U-Boot Image";
+			read-only;
+		};
+
+		partition@100000 {
+			/* 1MB for DTB Image */
+			reg = <0x00100000 0x00100000>;
+			label = "NAND DTB Image";
+		};
+
+		partition@200000 {
+			/* 4MB for Linux Kernel Image */
+			reg = <0x00200000 0x00400000>;
+			label = "NAND Linux Kernel Image";
+		};
+
+		partition@600000 {
+			/* 4MB for Compressed Root file System Image */
+			reg = <0x00600000 0x00400000>;
+			label = "NAND Compressed RFS Image";
+		};
+
+		partition@a00000 {
+			/* 22MB for JFFS2 based Root file System */
+			reg = <0x00a00000 0x01600000>;
+			label = "NAND JFFS2 Root File System";
+		};
+
+		partition@2000000 {
+			/* 96MB for RAMDISK based Root file System */
+			reg = <0x02000000 0x06000000>;
+			label = "NAND Writable User area";
+		};
+	};
+
+	cpld@2,0 {
+		compatible = "fsl, p1020rdb-cpld";
+		reg = <0x2 0x0 0x20000>;
+		read-only;
+	};
+
+	L2switch@3,0 {
+		compatible = "vitesse-7385";
+		reg = <0x3 0x0 0x20000>;
+	};
+};
+
+&soc {
+	i2c@3000 {
+		rtc@68 {
+			compatible = "dallas,ds1339";
+			reg = <0x68>;
+		};
+	};
+
+	spi@7000 {
+		flash@0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "spansion,s25sl12801";
+			reg = <0>;
+			spi-max-frequency = <40000000>; /* input clock */
+
+			partition@u-boot {
+				/* 512KB for u-boot Bootloader Image */
+				reg = <0x0 0x00080000>;
+				label = "u-boot";
+				read-only;
+			};
+
+			partition@dtb {
+				/* 512KB for DTB Image*/
+				reg = <0x00080000 0x00080000>;
+				label = "dtb";
+			};
+
+			partition@kernel {
+				/* 4MB for Linux Kernel Image */
+				reg = <0x00100000 0x00400000>;
+				label = "kernel";
+			};
+
+			partition@fs {
+				/* 4MB for Compressed RFS Image */
+				reg = <0x00500000 0x00400000>;
+				label = "file system";
+			};
+
+			partition@jffs-fs {
+				/* 7MB for JFFS2 based RFS */
+				reg = <0x00900000 0x00700000>;
+				label = "file system jffs2";
+			};
+		};
+		slic@0 {
+			compatible = "zarlink,le88266";
+			reg = <1>;
+			spi-max-frequency = <8000000>;
+		};
+		slic@1 {
+			compatible = "zarlink,le88266";
+			reg = <2>;
+			spi-max-frequency = <8000000>;
+		};
+
+	};
+
+	mdio@24000 {
+		phy0: ethernet-phy@0 {
+			interrupts = <3 1 0 0>;
+			reg = <0x0>;
+		};
+		phy1: ethernet-phy@1 {
+			interrupts = <2 1 0 0>;
+			reg = <0x1>;
+		};
+	};
+
+	mdio@25000 {
+		tbi1: tbi-phy@11 {
+			reg = <0x11>;
+			device_type = "tbi-phy";
+		};
+	};
+
+	mdio@26000 {
+		tbi2: tbi-phy@11 {
+			reg = <0x11>;
+			device_type = "tbi-phy";
+		};
+	};
+
+	enet0: ethernet@b0000 {
+		fixed-link = <1 1 1000 0 0>;
+		phy-connection-type = "rgmii-id";
+	};
+
+	enet1: ethernet@b1000 {
+		phy-handle = <&phy0>;
+		tbi-handle = <&tbi1>;
+		phy-connection-type = "sgmii";
+	};
+
+	enet2: ethernet@b2000 {
+		phy-handle = <&phy1>;
+		phy-connection-type = "rgmii-id";
+	};
+
+	usb@22000 {
+		phy_type = "ulpi";
+	};
+
+	/* USB2 is shared with localbus, so it must be disabled
+	   by default. We can't put 'status = "disabled";' here
+	   since U-Boot doesn't clear the status property when
+	   it enables USB2. OTOH, U-Boot does create a new node
+	   when there isn't any. So, just comment it out.
+	*/
+	usb@23000 {
+		status = "disabled";
+		phy_type = "ulpi";
+	};
+};
diff --git a/arch/powerpc/boot/dts/p1020rdb-pd_32b.dts b/arch/powerpc/boot/dts/p1020rdb-pd_32b.dts
new file mode 100644
index 0000000..160702b
--- /dev/null
+++ b/arch/powerpc/boot/dts/p1020rdb-pd_32b.dts
@@ -0,0 +1,90 @@
+/*
+ * P1020 RDB-PD Device Tree Source (32-bit address map)
+ *
+ * Copyright 2013 Freescale Semiconductor Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in the
+ *       documentation and/or other materials provided with the distribution.
+ *     * Neither the name of Freescale Semiconductor nor the
+ *       names of its contributors may be used to endorse or promote products
+ *       derived from this software without specific prior written permission.
+ *
+ *
+ * ALTERNATIVELY, this software may be distributed under the terms of the
+ * GNU General Public License ("GPL") as published by the Free Software
+ * Foundation, either version 2 of that License or (at your option) any
+ * later version.
+ *
+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/include/ "fsl/p1020si-pre.dtsi"
+/ {
+	model = "fsl,P1020RDB-PD";
+	compatible = "fsl,P1020RDB-PD";
+
+	memory {
+		device_type = "memory";
+	};
+
+	lbc: localbus@ffe05000 {
+		reg = <0x0 0xffe05000 0x0 0x1000>;
+
+		/* NOR, NAND flash and L2 switch */
+		ranges = <0x0 0x0 0x0 0xec000000 0x04000000
+			  0x1 0x0 0x0 0xff800000 0x00040000
+			  0x2 0x0 0x0 0xffa00000 0x00020000
+			  0x3 0x0 0x0 0xffb00000 0x00020000>;
+	};
+
+	soc: soc@ffe00000 {
+		ranges = <0x0 0x0 0xffe00000 0x100000>;
+	};
+
+	pci0: pcie@ffe09000 {
+		reg = <0x0 0xffe09000 0x0 0x1000>;
+		ranges = <0x2000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x10000>;
+		pcie@0 {
+			ranges = <0x2000000 0x0 0xa0000000
+				  0x2000000 0x0 0xa0000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+		};
+	};
+
+	pci1: pcie@ffe0a000 {
+		reg = <0x0 0xffe0a000 0x0 0x1000>;
+		ranges = <0x2000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000
+			  0x1000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x10000>;
+		pcie@0 {
+			ranges = <0x2000000 0x0 0x80000000
+				  0x2000000 0x0 0x80000000
+				  0x0 0x20000000
+
+				  0x1000000 0x0 0x0
+				  0x1000000 0x0 0x0
+				  0x0 0x100000>;
+		};
+	};
+};
+
+/include/ "p1020rdb-pd.dtsi"
+/include/ "fsl/p1020si-post.dtsi"
-- 
1.8.0

Re: [PATCH V2 2/2] powerpc/85xx: add the P1020RDB-PD DTS support

[Scott Wood]

On 07/04/2013 07:05:00 PM, Haijun Zhang wrote:
> diff --git a/arch/powerpc/boot/dts/p1020rdb-pc.dtsi =20
> b/arch/powerpc/boot/dts/p1020rdb-pc.dtsi
> index c952cd3..9d24501 100644
> --- a/arch/powerpc/boot/dts/p1020rdb-pc.dtsi
> +++ b/arch/powerpc/boot/dts/p1020rdb-pc.dtsi
> @@ -131,9 +131,7 @@
>  	};
>=20
>  	cpld@3,0 {
> -		#address-cells =3D <1>;
> -		#size-cells =3D <1>;
> -		compatible =3D "cpld";
> +		compatible =3D "fsl, p1020rdb-cpld";

No space after "fsl,".

> +			partition@fs {
> +				/* 4MB for Compressed RFS Image */
> +				reg =3D <0x00500000 0x00400000>;
> +				label =3D "file system";
> +			};
> +
> +			partition@jffs-fs {
> +				/* 7MB for JFFS2 based RFS */
> +				reg =3D <0x00900000 0x00700000>;
> +				label =3D "file system jffs2";
> +			};
> +		};
> +		slic@0 {
> +			compatible =3D "zarlink,le88266";
> +			reg =3D <1>;
> +			spi-max-frequency =3D <8000000>;
> +		};
> +		slic@1 {
> +			compatible =3D "zarlink,le88266";
> +			reg =3D <2>;
> +			spi-max-frequency =3D <8000000>;
> +		};
> +
> +	};

Remove that last blank line, and insert a blank line before each =20
"slic@..." (like you do between the partition nodes).

> +	/* USB2 is shared with localbus, so it must be disabled
> +	   by default. We can't put 'status =3D "disabled";' here
> +	   since U-Boot doesn't clear the status property when
> +	   it enables USB2. OTOH, U-Boot does create a new node
> +	   when there isn't any. So, just comment it out.
> +	*/

/*
  * Linux multi-line
  * comment style
  * is like this.
  */

> +	usb@23000 {
> +		status =3D "disabled";
> +		phy_type =3D "ulpi";
> +	};

Didn't you just say above that you can't use status =3D "disabled"?

And can U-Boot be fixed to set status =3D "disabled" on whichever I/O is =20
not usable?

> +/include/ "fsl/p1020si-pre.dtsi"
> +/ {
> +	model =3D "fsl,P1020RDB-PD";
> +	compatible =3D "fsl,P1020RDB-PD";
> +
> +	memory {
> +		device_type =3D "memory";
> +	};
> +
> +	lbc: localbus@ffe05000 {
> +		reg =3D <0x0 0xffe05000 0x0 0x1000>;
> +
> +		/* NOR, NAND flash and L2 switch */
> +		ranges =3D <0x0 0x0 0x0 0xec000000 0x04000000
> +			  0x1 0x0 0x0 0xff800000 0x00040000
> +			  0x2 0x0 0x0 0xffa00000 0x00020000
> +			  0x3 0x0 0x0 0xffb00000 0x00020000>;

If you're going to have a comment here about what is mapped by the =20
ranges, why exclude the CPLD?

-Scott=

答复: [PATCH V2 2/2] powerpc/85xx: add the P1020RDB-PD DTS support

[Zhang Haijun-B42677]

CgpSZWdhcmRzICYgVGhhbmtzCgpIYWlqdW4uCgpfX19fX19fX19fX19fX19fX19fX19fX19fX19f
X19fX19fX19fX19fCreivP7IyzogV29vZCBTY290dC1CMDc0MjEKt6LLzcqxvOQ6IDIwMTPE6jfU
wjjI1SAxNzoxMArK1bz+yMs6IFpoYW5nIEhhaWp1bi1CNDI2NzcKs63LzTogbGludXhwcGMtZGV2
QGxpc3RzLm96bGFicy5vcmc7IGdhbGFrQGtlcm5lbC5jcmFzaGluZy5vcmc7IEZsZW1pbmcgQW5k
eS1BRkxFTUlORzsgWmhhbmcgSGFpanVuLUI0MjY3NzsgSHVhbmcgQ2hhbmdtaW5nLVI2NjA5MwrW
98ziOiBSZTogW1BBVENIIFYyIDIvMl0gcG93ZXJwYy84NXh4OiBhZGQgdGhlIFAxMDIwUkRCLVBE
IERUUyBzdXBwb3J0CgpPbiAwNy8wNC8yMDEzIDA3OjA1OjAwIFBNLCBIYWlqdW4gWmhhbmcgd3Jv
dGU6Cj4gZGlmZiAtLWdpdCBhL2FyY2gvcG93ZXJwYy9ib290L2R0cy9wMTAyMHJkYi1wYy5kdHNp
Cj4gYi9hcmNoL3Bvd2VycGMvYm9vdC9kdHMvcDEwMjByZGItcGMuZHRzaQo+IGluZGV4IGM5NTJj
ZDMuLjlkMjQ1MDEgMTAwNjQ0Cj4gLS0tIGEvYXJjaC9wb3dlcnBjL2Jvb3QvZHRzL3AxMDIwcmRi
LXBjLmR0c2kKPiArKysgYi9hcmNoL3Bvd2VycGMvYm9vdC9kdHMvcDEwMjByZGItcGMuZHRzaQo+
IEBAIC0xMzEsOSArMTMxLDcgQEAKPiAgICAgICB9Owo+Cj4gICAgICAgY3BsZEAzLDAgewo+IC0g
ICAgICAgICAgICAgI2FkZHJlc3MtY2VsbHMgPSA8MT47Cj4gLSAgICAgICAgICAgICAjc2l6ZS1j
ZWxscyA9IDwxPjsKPiAtICAgICAgICAgICAgIGNvbXBhdGlibGUgPSAiY3BsZCI7Cj4gKyAgICAg
ICAgICAgICBjb21wYXRpYmxlID0gImZzbCwgcDEwMjByZGItY3BsZCI7CgpObyBzcGFjZSBhZnRl
ciAiZnNsLCIuCgpJJ2xsIGNoYW5nZSBpdCB0aGFua3MuCgo+ICsgICAgICAgICAgICAgICAgICAg
ICBwYXJ0aXRpb25AZnMgewo+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgIC8qIDRNQiBm
b3IgQ29tcHJlc3NlZCBSRlMgSW1hZ2UgKi8KPiArICAgICAgICAgICAgICAgICAgICAgICAgICAg
ICByZWcgPSA8MHgwMDUwMDAwMCAweDAwNDAwMDAwPjsKPiArICAgICAgICAgICAgICAgICAgICAg
ICAgICAgICBsYWJlbCA9ICJmaWxlIHN5c3RlbSI7Cj4gKyAgICAgICAgICAgICAgICAgICAgIH07
Cj4gKwo+ICsgICAgICAgICAgICAgICAgICAgICBwYXJ0aXRpb25AamZmcy1mcyB7Cj4gKyAgICAg
ICAgICAgICAgICAgICAgICAgICAgICAgLyogN01CIGZvciBKRkZTMiBiYXNlZCBSRlMgKi8KPiAr
ICAgICAgICAgICAgICAgICAgICAgICAgICAgICByZWcgPSA8MHgwMDkwMDAwMCAweDAwNzAwMDAw
PjsKPiArICAgICAgICAgICAgICAgICAgICAgICAgICAgICBsYWJlbCA9ICJmaWxlIHN5c3RlbSBq
ZmZzMiI7Cj4gKyAgICAgICAgICAgICAgICAgICAgIH07Cj4gKyAgICAgICAgICAgICB9Owo+ICsg
ICAgICAgICAgICAgc2xpY0AwIHsKPiArICAgICAgICAgICAgICAgICAgICAgY29tcGF0aWJsZSA9
ICJ6YXJsaW5rLGxlODgyNjYiOwo+ICsgICAgICAgICAgICAgICAgICAgICByZWcgPSA8MT47Cj4g
KyAgICAgICAgICAgICAgICAgICAgIHNwaS1tYXgtZnJlcXVlbmN5ID0gPDgwMDAwMDA+Owo+ICsg
ICAgICAgICAgICAgfTsKPiArICAgICAgICAgICAgIHNsaWNAMSB7Cj4gKyAgICAgICAgICAgICAg
ICAgICAgIGNvbXBhdGlibGUgPSAiemFybGluayxsZTg4MjY2IjsKPiArICAgICAgICAgICAgICAg
ICAgICAgcmVnID0gPDI+Owo+ICsgICAgICAgICAgICAgICAgICAgICBzcGktbWF4LWZyZXF1ZW5j
eSA9IDw4MDAwMDAwPjsKPiArICAgICAgICAgICAgIH07Cj4gKwo+ICsgICAgIH07CgpSZW1vdmUg
dGhhdCBsYXN0IGJsYW5rIGxpbmUsIGFuZCBpbnNlcnQgYSBibGFuayBsaW5lIGJlZm9yZSBlYWNo
CiJzbGljQC4uLiIgKGxpa2UgeW91IGRvIGJldHdlZW4gdGhlIHBhcnRpdGlvbiBub2RlcykuCgpJ
J2xsIGNoYW5nZSBpdCB0aGFua3MuCgo+ICsgICAgIC8qIFVTQjIgaXMgc2hhcmVkIHdpdGggbG9j
YWxidXMsIHNvIGl0IG11c3QgYmUgZGlzYWJsZWQKPiArICAgICAgICBieSBkZWZhdWx0LiBXZSBj
YW4ndCBwdXQgJ3N0YXR1cyA9ICJkaXNhYmxlZCI7JyBoZXJlCj4gKyAgICAgICAgc2luY2UgVS1C
b290IGRvZXNuJ3QgY2xlYXIgdGhlIHN0YXR1cyBwcm9wZXJ0eSB3aGVuCj4gKyAgICAgICAgaXQg
ZW5hYmxlcyBVU0IyLiBPVE9ILCBVLUJvb3QgZG9lcyBjcmVhdGUgYSBuZXcgbm9kZQo+ICsgICAg
ICAgIHdoZW4gdGhlcmUgaXNuJ3QgYW55LiBTbywganVzdCBjb21tZW50IGl0IG91dC4KPiArICAg
ICAqLwoKLyoKICAqIExpbnV4IG11bHRpLWxpbmUKICAqIGNvbW1lbnQgc3R5bGUKICAqIGlzIGxp
a2UgdGhpcy4KICAqLwoKPiArICAgICB1c2JAMjMwMDAgewo+ICsgICAgICAgICAgICAgc3RhdHVz
ID0gImRpc2FibGVkIjsKPiArICAgICAgICAgICAgIHBoeV90eXBlID0gInVscGkiOwo+ICsgICAg
IH07CgpEaWRuJ3QgeW91IGp1c3Qgc2F5IGFib3ZlIHRoYXQgeW91IGNhbid0IHVzZSBzdGF0dXMg
PSAiZGlzYWJsZWQiPwoKQW5kIGNhbiBVLUJvb3QgYmUgZml4ZWQgdG8gc2V0IHN0YXR1cyA9ICJk
aXNhYmxlZCIgb24gd2hpY2hldmVyIEkvTyBpcwpub3QgdXNhYmxlPwoKSSBoYWQgY2hlY2tlZCB3
aXRoIGlwIG93bmVyLCB0aGlzIG5vZGUgaXMgbm90IG5lZWRlZC4gSSdsbCBtYXNrIGl0LgoKPiAr
L2luY2x1ZGUvICJmc2wvcDEwMjBzaS1wcmUuZHRzaSIKPiArLyB7Cj4gKyAgICAgbW9kZWwgPSAi
ZnNsLFAxMDIwUkRCLVBEIjsKPiArICAgICBjb21wYXRpYmxlID0gImZzbCxQMTAyMFJEQi1QRCI7
Cj4gKwo+ICsgICAgIG1lbW9yeSB7Cj4gKyAgICAgICAgICAgICBkZXZpY2VfdHlwZSA9ICJtZW1v
cnkiOwo+ICsgICAgIH07Cj4gKwo+ICsgICAgIGxiYzogbG9jYWxidXNAZmZlMDUwMDAgewo+ICsg
ICAgICAgICAgICAgcmVnID0gPDB4MCAweGZmZTA1MDAwIDB4MCAweDEwMDA+Owo+ICsKPiArICAg
ICAgICAgICAgIC8qIE5PUiwgTkFORCBmbGFzaCBhbmQgTDIgc3dpdGNoICovCj4gKyAgICAgICAg
ICAgICByYW5nZXMgPSA8MHgwIDB4MCAweDAgMHhlYzAwMDAwMCAweDA0MDAwMDAwCj4gKyAgICAg
ICAgICAgICAgICAgICAgICAgMHgxIDB4MCAweDAgMHhmZjgwMDAwMCAweDAwMDQwMDAwCj4gKyAg
ICAgICAgICAgICAgICAgICAgICAgMHgyIDB4MCAweDAgMHhmZmEwMDAwMCAweDAwMDIwMDAwCj4g
KyAgICAgICAgICAgICAgICAgICAgICAgMHgzIDB4MCAweDAgMHhmZmIwMDAwMCAweDAwMDIwMDAw
PjsKCklmIHlvdSdyZSBnb2luZyB0byBoYXZlIGEgY29tbWVudCBoZXJlIGFib3V0IHdoYXQgaXMg
bWFwcGVkIGJ5IHRoZQpyYW5nZXMsIHdoeSBleGNsdWRlIHRoZSBDUExEPwoKSSdsbCBhZGQgaXQu
CgotU2NvdHQK