* [PATCH] dt/bindings: qoriq-clock: Update core PLL binding
@ 2015-04-14 9:42 Igal.Liberman
2015-04-14 20:19 ` Scott Wood
0 siblings, 1 reply; 2+ messages in thread
From: Igal.Liberman @ 2015-04-14 9:42 UTC (permalink / raw)
To: devicetree, linuxppc-dev; +Cc: scottwood, Igal Liberman
From: Igal Liberman <Igal.Liberman@freescale.com>
Added optional divider to "fsl,qoriq-core-pll-2.0".
This option might be used by Freescale hardware accelerators.
Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com>
---
.../devicetree/bindings/clock/qoriq-clock.txt | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
index df4a259..b0d7b73 100644
--- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
+++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
@@ -68,11 +68,17 @@ Required properties:
- #clock-cells: From common clock binding. The number of cells in a
clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
- For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
+ For "fsl,qoriq-core-pll-1.0" clocks, the single
clock-specifier cell may take the following values:
* 0 - equal to the PLL frequency
* 1 - equal to the PLL frequency divided by 2
* 2 - equal to the PLL frequency divided by 4
+ For "fsl,qoriq-core-pll-2.0" clocks, the single
+ clock-specifier cell may take the following values:
+ * 0 - equal to the PLL frequency
+ * 1 - equal to the PLL frequency divided by 2
+ * 2 - equal to the PLL frequency divided by 3
+ * 3 - equal to the PLL frequency divided by 4
Recommended properties:
- clocks: Should be the phandle of input parent clock
--
1.7.9.5
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH] dt/bindings: qoriq-clock: Update core PLL binding
2015-04-14 9:42 [PATCH] dt/bindings: qoriq-clock: Update core PLL binding Igal.Liberman
@ 2015-04-14 20:19 ` Scott Wood
0 siblings, 0 replies; 2+ messages in thread
From: Scott Wood @ 2015-04-14 20:19 UTC (permalink / raw)
To: Igal.Liberman; +Cc: devicetree, linuxppc-dev
On Tue, 2015-04-14 at 12:42 +0300, Igal.Liberman wrote:
> From: Igal Liberman <Igal.Liberman@freescale.com>
>
> Added optional divider to "fsl,qoriq-core-pll-2.0".
> This option might be used by Freescale hardware accelerators.
>
> Signed-off-by: Igal Liberman <Igal.Liberman@freescale.com>
> ---
> .../devicetree/bindings/clock/qoriq-clock.txt | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/qoriq-clock.txt b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> index df4a259..b0d7b73 100644
> --- a/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/qoriq-clock.txt
> @@ -68,11 +68,17 @@ Required properties:
> - #clock-cells: From common clock binding. The number of cells in a
> clock-specifier. Should be <0> for "fsl,qoriq-sysclk-[1,2].0"
> clocks, or <1> for "fsl,qoriq-core-pll-[1,2].0" clocks.
> - For "fsl,qoriq-core-pll-[1,2].0" clocks, the single
> + For "fsl,qoriq-core-pll-1.0" clocks, the single
> clock-specifier cell may take the following values:
> * 0 - equal to the PLL frequency
> * 1 - equal to the PLL frequency divided by 2
> * 2 - equal to the PLL frequency divided by 4
> + For "fsl,qoriq-core-pll-2.0" clocks, the single
> + clock-specifier cell may take the following values:
> + * 0 - equal to the PLL frequency
> + * 1 - equal to the PLL frequency divided by 2
> + * 2 - equal to the PLL frequency divided by 3
> + * 3 - equal to the PLL frequency divided by 4
Thanks. Please update the driver to use the compatible to distinguish
as documented above, rather than the number of clock-output-names.
-Scott
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