* [PATCH v3 1/2] powerpc: Define PVR value for POWER8NVL processor
@ 2016-03-31 9:19 Philippe Bergheaud
2016-03-31 9:19 ` [PATCH v3 2/2] cxl: Configure the PSL for two CAPI ports on POWER8NVL Philippe Bergheaud
2016-04-11 12:35 ` [v3,1/2] powerpc: Define PVR value for POWER8NVL processor Michael Ellerman
0 siblings, 2 replies; 4+ messages in thread
From: Philippe Bergheaud @ 2016-03-31 9:19 UTC (permalink / raw)
To: linuxppc-dev; +Cc: mpe, imunsie, mikey, Philippe Bergheaud
Signed-off-by: Philippe Bergheaud <felix@linux.vnet.ibm.com>
---
V2:
- New patch, added to patch set
V3:
- no change
arch/powerpc/include/asm/reg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index f5f4c66..cf09c6e 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -1182,6 +1182,7 @@
#define PVR_970GX 0x0045
#define PVR_POWER7p 0x004A
#define PVR_POWER8E 0x004B
+#define PVR_POWER8NVL 0x004C
#define PVR_POWER8 0x004D
#define PVR_BE 0x0070
#define PVR_PA6T 0x0090
--
2.1.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v3 2/2] cxl: Configure the PSL for two CAPI ports on POWER8NVL
2016-03-31 9:19 [PATCH v3 1/2] powerpc: Define PVR value for POWER8NVL processor Philippe Bergheaud
@ 2016-03-31 9:19 ` Philippe Bergheaud
2016-04-11 12:35 ` [v3,2/2] " Michael Ellerman
2016-04-11 12:35 ` [v3,1/2] powerpc: Define PVR value for POWER8NVL processor Michael Ellerman
1 sibling, 1 reply; 4+ messages in thread
From: Philippe Bergheaud @ 2016-03-31 9:19 UTC (permalink / raw)
To: linuxppc-dev; +Cc: mpe, imunsie, mikey, Philippe Bergheaud
The POWER8NVL chip has two CAPI ports. Configure the PSL to route
data to the port corresponding to the CAPP unit.
Signed-off-by: Philippe Bergheaud <felix@linux.vnet.ibm.com>
---
V2:
- Complete rewrite after Mikey's review
V3:
Fixes suggested by Michael:
- s/capp_unit_id(/get_capp_unit_id(/
- Fix block commenting style
- Remove extra space
- Use of_property_read_u32
- Add blank line after return
- Fix logic for phb_index > 1 on POWERNVL
- s/cappunitid/capp_unit_id/
- Add error message for -ENODEV
drivers/misc/cxl/pci.c | 41 ++++++++++++++++++++++++++++++++++++++++-
1 file changed, 40 insertions(+), 1 deletion(-)
diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c
index 2844e97..94fd3f7 100644
--- a/drivers/misc/cxl/pci.c
+++ b/drivers/misc/cxl/pci.c
@@ -21,6 +21,7 @@
#include <asm/msi_bitmap.h>
#include <asm/pnv-pci.h>
#include <asm/io.h>
+#include <asm/reg.h>
#include "cxl.h"
#include <misc/cxl.h>
@@ -321,12 +322,43 @@ static void dump_afu_descriptor(struct cxl_afu *afu)
#undef show_reg
}
+#define CAPP_UNIT0_ID 0xBA
+#define CAPP_UNIT1_ID 0XBE
+
+static u64 get_capp_unit_id(struct device_node *np)
+{
+ u32 phb_index;
+
+ /*
+ * For chips other than POWER8NVL, we only have CAPP 0,
+ * irrespective of which PHB is used.
+ */
+ if (!pvr_version_is(PVR_POWER8NVL))
+ return CAPP_UNIT0_ID;
+
+ /*
+ * For POWER8NVL, assume CAPP 0 is attached to PHB0 and
+ * CAPP 1 is attached to PHB1.
+ */
+ if (of_property_read_u32(np, "ibm,phb-index", &phb_index))
+ return 0;
+
+ if (phb_index == 0)
+ return CAPP_UNIT0_ID;
+
+ if (phb_index == 1)
+ return CAPP_UNIT1_ID;
+
+ return 0;
+}
+
static int init_implementation_adapter_regs(struct cxl *adapter, struct pci_dev *dev)
{
struct device_node *np;
const __be32 *prop;
u64 psl_dsnctl;
u64 chipid;
+ u64 capp_unit_id;
if (!(np = pnv_pci_get_phb_node(dev)))
return -ENODEV;
@@ -336,10 +368,17 @@ static int init_implementation_adapter_regs(struct cxl *adapter, struct pci_dev
if (!np)
return -ENODEV;
chipid = be32_to_cpup(prop);
+ capp_unit_id = get_capp_unit_id(np);
of_node_put(np);
+ if (!capp_unit_id) {
+ pr_err("cxl: invalid capp unit id\n");
+ return -ENODEV;
+ }
/* Tell PSL where to route data to */
- psl_dsnctl = 0x02E8900002000000ULL | (chipid << (63-5));
+ psl_dsnctl = 0x0000900002000000ULL | (chipid << (63-5));
+ psl_dsnctl |= (capp_unit_id << (63-13));
+
cxl_p1_write(adapter, CXL_PSL_DSNDCTL, psl_dsnctl);
cxl_p1_write(adapter, CXL_PSL_RESLCKTO, 0x20000000200ULL);
/* snoop write mask */
--
2.1.0
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [v3,1/2] powerpc: Define PVR value for POWER8NVL processor
2016-03-31 9:19 [PATCH v3 1/2] powerpc: Define PVR value for POWER8NVL processor Philippe Bergheaud
2016-03-31 9:19 ` [PATCH v3 2/2] cxl: Configure the PSL for two CAPI ports on POWER8NVL Philippe Bergheaud
@ 2016-04-11 12:35 ` Michael Ellerman
1 sibling, 0 replies; 4+ messages in thread
From: Michael Ellerman @ 2016-04-11 12:35 UTC (permalink / raw)
To: Philippe Bergheaud, linuxppc-dev; +Cc: Philippe Bergheaud, mikey, imunsie
On Thu, 2016-31-03 at 09:19:27 UTC, Philippe Bergheaud wrote:
> Signed-off-by: Philippe Bergheaud <felix@linux.vnet.ibm.com>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/86c9ffcc1ed17497a5df473232
cheers
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [v3,2/2] cxl: Configure the PSL for two CAPI ports on POWER8NVL
2016-03-31 9:19 ` [PATCH v3 2/2] cxl: Configure the PSL for two CAPI ports on POWER8NVL Philippe Bergheaud
@ 2016-04-11 12:35 ` Michael Ellerman
0 siblings, 0 replies; 4+ messages in thread
From: Michael Ellerman @ 2016-04-11 12:35 UTC (permalink / raw)
To: Philippe Bergheaud, linuxppc-dev; +Cc: Philippe Bergheaud, mikey, imunsie
On Thu, 2016-31-03 at 09:19:28 UTC, Philippe Bergheaud wrote:
> The POWER8NVL chip has two CAPI ports. Configure the PSL to route
> data to the port corresponding to the CAPP unit.
>
> Signed-off-by: Philippe Bergheaud <felix@linux.vnet.ibm.com>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/aa14138a51ca42eada706d4b96
cheers
^ permalink raw reply [flat|nested] 4+ messages in thread
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2016-03-31 9:19 [PATCH v3 1/2] powerpc: Define PVR value for POWER8NVL processor Philippe Bergheaud
2016-03-31 9:19 ` [PATCH v3 2/2] cxl: Configure the PSL for two CAPI ports on POWER8NVL Philippe Bergheaud
2016-04-11 12:35 ` [v3,2/2] " Michael Ellerman
2016-04-11 12:35 ` [v3,1/2] powerpc: Define PVR value for POWER8NVL processor Michael Ellerman
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