From: Nicholas Piggin <npiggin@gmail.com>
To: linuxppc-dev@lists.ozlabs.org, Michael Ellerman <mpe@ellerman.id.au>
Subject: Re: [PATCH] powerpc/powernv: Enable HAIL (HV AIL) for ISA v3.1 processors
Date: Wed, 07 Apr 2021 22:13:22 +1000 [thread overview]
Message-ID: <1617797140.zqn9fqbd4y.astroid@bobo.none> (raw)
In-Reply-To: <87v98ye3cn.fsf@mpe.ellerman.id.au>
Excerpts from Michael Ellerman's message of April 7, 2021 9:33 pm:
> Nicholas Piggin <npiggin@gmail.com> writes:
>> Starting with ISA v3.1, LPCR[AIL] no longer controls the interrupt
>> mode for HV=1 interrupts. Instead, a new LPCR[HAIL] bit is defined
>> which behaves like AIL=3 for HV interrupts when set.
>>
>> Set HAIL on bare metal to give us mmu-on interrupts and improve
>> performance.
>>
>> This also fixes an scv bug: we don't implement scv real mode (AIL=0)
>> vectors because they are at an inconvenient location, so we just
>> disable scv support when AIL can not be set. However powernv assumes
>> that LPCR[AIL] will enable AIL mode so it enables scv support despite
>> HV interrupts being AIL=0, which causes scv interrupts to go off into
>> the weeds.
>
> Should we tag this as fixing the initial P10 support, or the scv
> support? Or neither?
Good question. It does fix a nasty crash with scv so at least it should
be tagged I guess.
I don't know of anything else that assumes AIL on bare metal, so I don't
know of a crashy bug it fixes with initial P10 support. But it is a bit
odd for a HV OS running a v3.1 processor to set the old LPCR AIL bits,
so it is some kind of bug fix (performance at least).
Could go either way I guess.
Thanks,
Nick
>
> cheers
>
>> diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
>> index 1be20bc8dce2..9086a2644c89 100644
>> --- a/arch/powerpc/include/asm/reg.h
>> +++ b/arch/powerpc/include/asm/reg.h
>> @@ -441,6 +441,7 @@
>> #define LPCR_VRMA_LP1 ASM_CONST(0x0000800000000000)
>> #define LPCR_RMLS 0x1C000000 /* Implementation dependent RMO limit sel */
>> #define LPCR_RMLS_SH 26
>> +#define LPCR_HAIL ASM_CONST(0x0000000004000000) /* HV AIL (ISAv3.1) */
>> #define LPCR_ILE ASM_CONST(0x0000000002000000) /* !HV irqs set MSR:LE */
>> #define LPCR_AIL ASM_CONST(0x0000000001800000) /* Alternate interrupt location */
>> #define LPCR_AIL_0 ASM_CONST(0x0000000000000000) /* MMU off exception offset 0x0 */
>> diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c
>> index 04a31586f760..671192afcdfd 100644
>> --- a/arch/powerpc/kernel/setup_64.c
>> +++ b/arch/powerpc/kernel/setup_64.c
>> @@ -233,10 +233,23 @@ static void cpu_ready_for_interrupts(void)
>> * If we are not in hypervisor mode the job is done once for
>> * the whole partition in configure_exceptions().
>> */
>> - if (cpu_has_feature(CPU_FTR_HVMODE) &&
>> - cpu_has_feature(CPU_FTR_ARCH_207S)) {
>> + if (cpu_has_feature(CPU_FTR_HVMODE)) {
>> unsigned long lpcr = mfspr(SPRN_LPCR);
>> - mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3);
>> + unsigned long new_lpcr = lpcr;
>> +
>> + if (cpu_has_feature(CPU_FTR_ARCH_31)) {
>> + /* P10 DD1 does not have HAIL */
>> + if (pvr_version_is(PVR_POWER10) &&
>> + (mfspr(SPRN_PVR) & 0xf00) == 0x100)
>> + new_lpcr |= LPCR_AIL_3;
>> + else
>> + new_lpcr |= LPCR_HAIL;
>> + } else if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
>> + new_lpcr |= LPCR_AIL_3;
>> + }
>> +
>> + if (new_lpcr != lpcr)
>> + mtspr(SPRN_LPCR, new_lpcr);
>> }
>>
>> /*
>> --
>> 2.23.0
>
next prev parent reply other threads:[~2021-04-07 12:14 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-02 2:41 [PATCH] powerpc/powernv: Enable HAIL (HV AIL) for ISA v3.1 processors Nicholas Piggin
2021-04-02 6:10 ` Cédric Le Goater
2021-04-02 8:00 ` Nicholas Piggin
2021-04-07 11:33 ` Michael Ellerman
2021-04-07 12:13 ` Nicholas Piggin [this message]
2021-04-19 4:00 ` Michael Ellerman
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1617797140.zqn9fqbd4y.astroid@bobo.none \
--to=npiggin@gmail.com \
--cc=linuxppc-dev@lists.ozlabs.org \
--cc=mpe@ellerman.id.au \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).