[PATCH 1/2] powerpc/64s/interrupt: Change must-hard-mask interrupt check from BUG to WARN

[PATCH 1/2] powerpc/64s/interrupt: Change must-hard-mask interrupt check from BUG to WARN

[Nicholas Piggin]

This new assertion added is generally harmless and gets fixed up
naturally, but it does indicate a problem with MSR manipulation
somewhere.

Fixes: c39fb71a54f0 ("powerpc/64s/interrupt: masked handler debug check for previous hard disable")
Reported-by: Sachin Sant <sachinp@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 arch/powerpc/kernel/exceptions-64s.S | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index dafa275f18bc..d5d35f3a824e 100644
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -2797,12 +2797,16 @@ masked_interrupt:
 #ifdef CONFIG_PPC_IRQ_SOFT_MASK_DEBUG
 	/*
 	 * Ensure there was no previous MUST_HARD_MASK interrupt or
-	 * HARD_DIS setting.
+	 * HARD_DIS setting. If this does fire, the interrupt is still
+	 * masked and MSR[EE] will be cleared on return, so no need to
+	 * panic, but somebody probably enabled MSR[EE] under
+	 * PACA_IRQ_HARD_DIS, mtmsr(mfmsr() | MSR_x) being a common
+	 * cause.
 	 */
 	lbz	r9,PACAIRQHAPPENED(r13)
 	andi.	r9,r9,(PACA_IRQ_MUST_HARD_MASK|PACA_IRQ_HARD_DIS)
 0:	tdnei	r9,0
-	EMIT_BUG_ENTRY 0b,__FILE__,__LINE__,0
+	EMIT_WARN_ENTRY 0b,__FILE__,__LINE__,(BUGFLAG_WARNING | BUGFLAG_ONCE)
 #endif
 	lbz	r9,PACAIRQHAPPENED(r13)
 	or	r9,r9,r10
-- 
2.37.2

[PATCH 2/2] powerpc/64: Fix msr_check_and_set/clear MSR[EE] race

[Nicholas Piggin]

irq soft-masking means that when Linux irqs are disabled, the MSR[EE]
value can change from 1 to 0 asynchronously: if a masked interrupt of
the PACA_IRQ_MUST_HARD_MASK variety fires while irqs are disabled,
the masked handler will return with MSR[EE]=0.

This means a sequence like mtmsr(mfmsr() | MSR_FP) is racy if it can
be called with local irqs disabled, unless a hard_irq_disable has been
done.

Reported-by: Sachin Sant <sachinp@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 arch/powerpc/include/asm/hw_irq.h | 24 ++++++++++++++++++++++++
 arch/powerpc/kernel/process.c     |  4 ++--
 2 files changed, 26 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/include/asm/hw_irq.h b/arch/powerpc/include/asm/hw_irq.h
index 26ede09c521d..db139deb4466 100644
--- a/arch/powerpc/include/asm/hw_irq.h
+++ b/arch/powerpc/include/asm/hw_irq.h
@@ -459,6 +459,30 @@ static inline void irq_soft_mask_regs_set_state(struct pt_regs *regs, unsigned l
 }
 #endif /* CONFIG_PPC64 */
 
+static inline unsigned long mtmsr_isync_irqsafe(unsigned long msr)
+{
+#ifdef CONFIG_PPC64
+	if (arch_irqs_disabled()) {
+		/*
+		 * With soft-masking, MSR[EE] can change from 1 to 0
+		 * asynchronously when irqs are disabled, and we don't want to
+		 * set MSR[EE] back to 1 here if that has happened. A race-free
+		 * way to do this is ensure EE is already 0. Another way it
+		 * could be done is with a RESTART_TABLE handler, but that's
+		 * probably overkill here.
+		 */
+		msr &= ~MSR_EE;
+		mtmsr_isync(msr);
+		irq_soft_mask_set(IRQS_ALL_DISABLED);
+		local_paca->irq_happened |= PACA_IRQ_HARD_DIS;
+	} else
+#endif
+		mtmsr_isync(msr);
+
+	return msr;
+}
+
+
 #define ARCH_IRQ_INIT_FLAGS	IRQ_NOREQUEST
 
 #endif  /* __ASSEMBLY__ */
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 0fbda89cd1bb..37df0428e4fb 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -127,7 +127,7 @@ unsigned long notrace msr_check_and_set(unsigned long bits)
 		newmsr |= MSR_VSX;
 
 	if (oldmsr != newmsr)
-		mtmsr_isync(newmsr);
+		newmsr = mtmsr_isync_irqsafe(newmsr);
 
 	return newmsr;
 }
@@ -145,7 +145,7 @@ void notrace __msr_check_and_clear(unsigned long bits)
 		newmsr &= ~MSR_VSX;
 
 	if (oldmsr != newmsr)
-		mtmsr_isync(newmsr);
+		mtmsr_isync_irqsafe(newmsr);
 }
 EXPORT_SYMBOL(__msr_check_and_clear);
 
-- 
2.37.2

Re: [PATCH 1/2] powerpc/64s/interrupt: Change must-hard-mask interrupt check from BUG to WARN

[Sachin Sant]

> On 04-Oct-2022, at 10:41 AM, Nicholas Piggin <npiggin@gmail.com> wrote:
> 
> This new assertion added is generally harmless and gets fixed up
> naturally, but it does indicate a problem with MSR manipulation
> somewhere.
> 
> Fixes: c39fb71a54f0 ("powerpc/64s/interrupt: masked handler debug check for previous hard disable")
> Reported-by: Sachin Sant <sachinp@linux.ibm.com>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---

Thanks Nick. Tested both the patches on Power9 and Power10. I no longer
see the reported problem.

Tested-by: Sachin Sant <sachinp@linux.ibm.com>

- Sachin

Re: [PATCH 1/2] powerpc/64s/interrupt: Change must-hard-mask interrupt check from BUG to WARN

[Michael Ellerman]

On Tue, 4 Oct 2022 15:11:56 +1000, Nicholas Piggin wrote:
> This new assertion added is generally harmless and gets fixed up
> naturally, but it does indicate a problem with MSR manipulation
> somewhere.
> 
> 

Applied to powerpc/next.

[1/2] powerpc/64s/interrupt: Change must-hard-mask interrupt check from BUG to WARN
      https://git.kernel.org/powerpc/c/8154850b28bd57a35ea73a7518ffcb9ccd5e43bc
[2/2] powerpc/64: Fix msr_check_and_set/clear MSR[EE] race
      https://git.kernel.org/powerpc/c/0fa6831811f62cfc10415d731bcf9fde2647ad81

cheers