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* PCI Bus Mapping for MPC8548 with multiple PCI interfaces
@ 2008-09-29  9:35 Ralf Trübenbach
  2008-09-29 12:35 ` Arnd Bergmann
  0 siblings, 1 reply; 2+ messages in thread
From: Ralf Trübenbach @ 2008-09-29  9:35 UTC (permalink / raw)
  To: linuxppc-embedded

Hello,
=20
I'm currently developing a bootloader for a MPC8548 based board. This =
board has got three PCI interfaces (PCI1, PCI2 and PCIe). At the PCIe =
interface the MPC8548 appears as PCI-Bridge (at bus 0 device 0), at the =
PCI1/2 interfaces the MPC8548 appears as normal devices (bus 0 device =
0).

And now I'm a little bit unshure about how Linux expects the PCI bus =
mapping. I see two ways:


A)
--------
MPC8548:   PCI1         PCI2         PCIe
             |           |             |
             |           |             3
             |           |           bridge
             0           2             4
--------     |           |             |
extern:   -------      ------        ------
          |  |  |      |    |        |    |
         dev | dev     dev dev...   dev  dev ...
             0
           bridge
             1
             |
          ---------
          |   |   |
         dev dev dev...

Since I have to create Type 0 Config Read/Writes to access the first bus =
of an interface, my PciConfigRead/Write functions would have to convert =
the bus no. from 0->0 2->0 3->0 (for the example). And PCIe bridge's =
primary bus no. has to be set to 0.



or B)
--------
MPC8548:   PCI1         PCI2         PCIe
             |           |             |
             |           |             0
             |           |           bridge
             0           0             1
--------     |           |             |
extern:   -------      ------        ------
          |  |  |      |    |        |    |
         dev | dev     dev dev...   dev  dev ...
             0
           bridge
             1
             |
          ---------
          |   |   |
         dev dev dev...

Every bus is mapped independently. And PciConfigRead/Write functions =
convert the bus no. so that upper layers (and user) see a bus mapping =
similar to A).

Maybe someone knows how U-Boot or Linux would map the interfaces?

Thank you for your Help.

Ralf


Best Regards/Mit freundlichen Gruessen
=20

Ralf Tr=FCbenbach, Software Design
MEN Mikro Elektronik GmbH
Neuwieder Stra=DFe 5-7
90411 Nuremberg, Germany
Phone +49-911-99 33 5-0
Fax +49-911-99 33 5-910
E-Mail Ralf.Truebenbach@men.de <mailto:Ralf.Truebenbach@men.de>=20
www.men.de <http://www.men.de/>=20

----------------------------------------------------------------------

MEN Mikro Elektronik GmbH - Gesch=E4ftsf=FChrer Manfred Schmitz, Udo =
Fuchs - Handelsregister N=FCrnberg HRB 5540 - UST-ID-Nr./VAT DE 133 528 =
744 - Umsatzsteuer-Nr./Turnover Tax No 238/159/58551 - WEEE-Reg.-Nr. DE =
49081198 - Deutsche Bank AG Kto. Nr. 0390 211, BLZ 760 700 12 - =
HypoVereinsbank Kto. Nr. 1560 224 300, BLZ 760 200 70

^ permalink raw reply	[flat|nested] 2+ messages in thread

* Re: PCI Bus Mapping for MPC8548 with multiple PCI interfaces
  2008-09-29  9:35 PCI Bus Mapping for MPC8548 with multiple PCI interfaces Ralf Trübenbach
@ 2008-09-29 12:35 ` Arnd Bergmann
  0 siblings, 0 replies; 2+ messages in thread
From: Arnd Bergmann @ 2008-09-29 12:35 UTC (permalink / raw)
  To: linuxppc-embedded; +Cc: Ralf Trübenbach

On Monday 29 September 2008, Ralf Tr=FCbenbach wrote:
> Every bus is mapped independently. And PciConfigRead/Write functions
> convert the bus no. so that upper layers (and user) see a bus mapping
> similar to A). =20
>=20
> Maybe someone knows how U-Boot or Linux would map the interfaces?
>=20

You should use your option B) in the firmware, i.e. set up every PCI
independently from the others, startig at bus 0.

You should not fake the bus mapping but rather show the pci domains
separately to user space.

	Arnd <><

^ permalink raw reply	[flat|nested] 2+ messages in thread

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