[PATCH 0/5] Few patches for galak/powerpc.git next

[PATCH 0/5] Few patches for galak/powerpc.git next

[Anton Vorontsov]

Hi Kumar,

Here are few patches queued for the next branch. The patches are
mostly USB related. Plus a trivial patch that fixes some sparse
warnings.

[PATCH 1/5] powerpc/qe: Implement QE Pin Multiplexing API
[PATCH 2/5] powerpc: Implement GPIO driver for simple memory-mapped banks
[PATCH 3/5] powerpc/83xx: Add USB Host/Gadget support for MPC8360E-MDS boards
[PATCH 4/5] powerpc/83xx: Add USB Host support for MPC8360E-RDK boards
[PATCH 5/5] powerpc/83xx: Fix sparse warnings in mpc836x_mds.c

Thanks,

-- 
Anton Vorontsov
email: cbouatmailru@gmail.com
irc://irc.freenode.net/bd2

[PATCH 1/5] powerpc/qe: Implement QE Pin Multiplexing API

[Anton Vorontsov]

With this API we're able to set a QE pin to the GPIO mode or a dedicated
peripheral function.

The API relies on the fact that QE gpio controllers are registered. If
they aren't, the API won't work (gracefully though).

There is one caveat though: if anybody occupied the node->data before us,
or overwrote it, then bad things will happen. Luckily this is all in the
platform code that we fully control, so this should never happen.

I could implement more checks (for example we could create a list of
successfully registered QE controllers, and compare the node->data in the
qe_pin_request()), but this is unneeded if nobody is going to do silly
things behind our back.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
 arch/powerpc/include/asm/qe.h     |   21 ++++
 arch/powerpc/sysdev/qe_lib/gpio.c |  195 +++++++++++++++++++++++++++++++++++++
 2 files changed, 216 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/include/asm/qe.h b/arch/powerpc/include/asm/qe.h
index edee15d..3227440 100644
--- a/arch/powerpc/include/asm/qe.h
+++ b/arch/powerpc/include/asm/qe.h
@@ -17,6 +17,8 @@
 #ifdef __KERNEL__
 
 #include <linux/spinlock.h>
+#include <linux/errno.h>
+#include <linux/err.h>
 #include <asm/cpm.h>
 #include <asm/immap_qe.h>
 
@@ -112,6 +114,25 @@ extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
 			     int assignment, int has_irq);
 extern int par_io_data_set(u8 port, u8 pin, u8 val);
 
+/*
+ * Pin multiplexing functions.
+ */
+struct qe_pin;
+#ifdef CONFIG_QE_GPIO
+extern struct qe_pin *qe_pin_request(struct device_node *np, int index);
+extern void qe_pin_free(struct qe_pin *qe_pin);
+extern void qe_pin_set_gpio(struct qe_pin *qe_pin);
+extern void qe_pin_set_dedicated(struct qe_pin *pin);
+#else
+static inline struct qe_pin *qe_pin_request(struct device_node *np, int index)
+{
+	return ERR_PTR(-ENOSYS);
+}
+static inline void qe_pin_free(struct qe_pin *qe_pin) {}
+static inline void qe_pin_set_gpio(struct qe_pin *qe_pin) {}
+static inline void qe_pin_set_dedicated(struct qe_pin *pin) {}
+#endif /* CONFIG_QE_GPIO */
+
 /* QE internal API */
 int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
 enum qe_clock qe_clock_source(const char *source);
diff --git a/arch/powerpc/sysdev/qe_lib/gpio.c b/arch/powerpc/sysdev/qe_lib/gpio.c
index 8e5a0bc..3485288 100644
--- a/arch/powerpc/sysdev/qe_lib/gpio.c
+++ b/arch/powerpc/sysdev/qe_lib/gpio.c
@@ -14,6 +14,7 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/spinlock.h>
+#include <linux/err.h>
 #include <linux/io.h>
 #include <linux/of.h>
 #include <linux/of_gpio.h>
@@ -24,8 +25,14 @@ struct qe_gpio_chip {
 	struct of_mm_gpio_chip mm_gc;
 	spinlock_t lock;
 
+	unsigned long pin_flags[QE_PIO_PINS];
+#define QE_PIN_REQUESTED 0
+
 	/* shadowed data register to clear/set bits safely */
 	u32 cpdata;
+
+	/* saved_regs used to restore dedicated functions */
+	struct qe_pio_regs saved_regs;
 };
 
 static inline struct qe_gpio_chip *
@@ -40,6 +47,12 @@ static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
 	struct qe_pio_regs __iomem *regs = mm_gc->regs;
 
 	qe_gc->cpdata = in_be32(&regs->cpdata);
+	qe_gc->saved_regs.cpdata = qe_gc->cpdata;
+	qe_gc->saved_regs.cpdir1 = in_be32(&regs->cpdir1);
+	qe_gc->saved_regs.cpdir2 = in_be32(&regs->cpdir2);
+	qe_gc->saved_regs.cppar1 = in_be32(&regs->cppar1);
+	qe_gc->saved_regs.cppar2 = in_be32(&regs->cppar2);
+	qe_gc->saved_regs.cpodr = in_be32(&regs->cpodr);
 }
 
 static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
@@ -103,6 +116,188 @@ static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
 	return 0;
 }
 
+struct qe_pin {
+	/*
+	 * The qe_gpio_chip name is unfortunate, we should change that to
+	 * something like qe_pio_controller. Someday.
+	 */
+	struct qe_gpio_chip *controller;
+	int num;
+};
+
+/**
+ * qe_pin_request - Request a QE pin
+ * @np:		device node to get a pin from
+ * @index:	index of a pin in the device tree
+ * Context:	non-atomic
+ *
+ * This function return qe_pin so that you could use it with the rest of
+ * the QE Pin Multiplexing API.
+ */
+struct qe_pin *qe_pin_request(struct device_node *np, int index)
+{
+	struct qe_pin *qe_pin;
+	struct device_node *gc;
+	struct of_gpio_chip *of_gc = NULL;
+	struct of_mm_gpio_chip *mm_gc;
+	struct qe_gpio_chip *qe_gc;
+	int err;
+	int size;
+	const void *gpio_spec;
+	const u32 *gpio_cells;
+	unsigned long flags;
+
+	qe_pin = kzalloc(sizeof(*qe_pin), GFP_KERNEL);
+	if (!qe_pin) {
+		pr_debug("%s: can't allocate memory\n", __func__);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	err = of_parse_phandles_with_args(np, "gpios", "#gpio-cells", index,
+					  &gc, &gpio_spec);
+	if (err) {
+		pr_debug("%s: can't parse gpios property\n", __func__);
+		goto err0;
+	}
+
+	if (!of_device_is_compatible(gc, "fsl,mpc8323-qe-pario-bank")) {
+		pr_debug("%s: tried to get a non-qe pin\n", __func__);
+		err = -EINVAL;
+		goto err1;
+	}
+
+	of_gc = gc->data;
+	if (!of_gc) {
+		pr_debug("%s: gpio controller %s isn't registered\n",
+			 np->full_name, gc->full_name);
+		err = -ENODEV;
+		goto err1;
+	}
+
+	gpio_cells = of_get_property(gc, "#gpio-cells", &size);
+	if (!gpio_cells || size != sizeof(*gpio_cells) ||
+			*gpio_cells != of_gc->gpio_cells) {
+		pr_debug("%s: wrong #gpio-cells for %s\n",
+			 np->full_name, gc->full_name);
+		err = -EINVAL;
+		goto err1;
+	}
+
+	err = of_gc->xlate(of_gc, np, gpio_spec, NULL);
+	if (err < 0)
+		goto err1;
+
+	mm_gc = to_of_mm_gpio_chip(&of_gc->gc);
+	qe_gc = to_qe_gpio_chip(mm_gc);
+
+	spin_lock_irqsave(&qe_gc->lock, flags);
+
+	if (test_and_set_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[err]) == 0) {
+		qe_pin->controller = qe_gc;
+		qe_pin->num = err;
+		err = 0;
+	} else {
+		err = -EBUSY;
+	}
+
+	spin_unlock_irqrestore(&qe_gc->lock, flags);
+
+	if (!err)
+		return qe_pin;
+err1:
+	of_node_put(gc);
+err0:
+	kfree(qe_pin);
+	pr_debug("%s failed with status %d\n", __func__, err);
+	return ERR_PTR(err);
+}
+EXPORT_SYMBOL(qe_pin_request);
+
+/**
+ * qe_pin_free - Free a pin
+ * @qe_pin:	pointer to the qe_pin structure
+ * Context:	any
+ *
+ * This function frees the qe_pin structure and makes a pin available
+ * for further qe_pin_request() calls.
+ */
+void qe_pin_free(struct qe_pin *qe_pin)
+{
+	struct qe_gpio_chip *qe_gc = qe_pin->controller;
+	unsigned long flags;
+	const int pin = qe_pin->num;
+
+	spin_lock_irqsave(&qe_gc->lock, flags);
+	test_and_clear_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[pin]);
+	spin_unlock_irqrestore(&qe_gc->lock, flags);
+
+	kfree(qe_pin);
+}
+EXPORT_SYMBOL(qe_pin_free);
+
+/**
+ * qe_pin_set_dedicated - Revert a pin to a dedicated peripheral function mode
+ * @qe_pin:	pointer to the qe_pin structure
+ * Context:	any
+ *
+ * This function resets a pin to a dedicated peripheral function that
+ * has been set up by the firmware.
+ */
+void qe_pin_set_dedicated(struct qe_pin *qe_pin)
+{
+	struct qe_gpio_chip *qe_gc = qe_pin->controller;
+	struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
+	struct qe_pio_regs *sregs = &qe_gc->saved_regs;
+	int pin = qe_pin->num;
+	u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1));
+	u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2);
+	bool second_reg = pin > (QE_PIO_PINS / 2) - 1;
+	unsigned long flags;
+
+	spin_lock_irqsave(&qe_gc->lock, flags);
+
+	if (second_reg) {
+		clrsetbits_be32(&regs->cpdir2, mask2, sregs->cpdir2 & mask2);
+		clrsetbits_be32(&regs->cppar2, mask2, sregs->cppar2 & mask2);
+	} else {
+		clrsetbits_be32(&regs->cpdir1, mask2, sregs->cpdir1 & mask2);
+		clrsetbits_be32(&regs->cppar1, mask2, sregs->cppar1 & mask2);
+	}
+
+	if (sregs->cpdata & mask1)
+		qe_gc->cpdata |= mask1;
+	else
+		qe_gc->cpdata &= ~mask1;
+
+	out_be32(&regs->cpdata, qe_gc->cpdata);
+	clrsetbits_be32(&regs->cpodr, mask1, sregs->cpodr & mask1);
+
+	spin_unlock_irqrestore(&qe_gc->lock, flags);
+}
+EXPORT_SYMBOL(qe_pin_set_dedicated);
+
+/**
+ * qe_pin_set_gpio - Set a pin to the GPIO mode
+ * @qe_pin:	pointer to the qe_pin structure
+ * Context:	any
+ *
+ * This function sets a pin to the GPIO mode.
+ */
+void qe_pin_set_gpio(struct qe_pin *qe_pin)
+{
+	struct qe_gpio_chip *qe_gc = qe_pin->controller;
+	struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
+	unsigned long flags;
+
+	spin_lock_irqsave(&qe_gc->lock, flags);
+
+	/* Let's make it input by default, GPIO API is able to change that. */
+	__par_io_config_pin(regs, qe_pin->num, QE_PIO_DIR_IN, 0, 0, 0);
+
+	spin_unlock_irqrestore(&qe_gc->lock, flags);
+}
+EXPORT_SYMBOL(qe_pin_set_gpio);
+
 static int __init qe_add_gpiochips(void)
 {
 	struct device_node *np;
-- 
1.5.6.5

[PATCH 2/5] powerpc: Implement GPIO driver for simple memory-mapped banks

[Anton Vorontsov]

The driver supports very simple GPIO controllers, that is, when a
controller provides just a 'data' register. Such controllers may be
found in various BCSRs (Board's FPGAs used to control board's
switches, LEDs, chip-selects, Ethernet/USB PHY power, etc).

So far we support only 1-byte GPIO banks. Support for other widths may
be implemented when/if needed.

p.s.
To avoid "made up" compatible entries (like compatible = "simple-gpio"),
boards must call the simple_gpiochip_init() to pass the compatible
string.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
 Documentation/powerpc/dts-bindings/fsl/board.txt |   30 ++++
 arch/powerpc/platforms/Kconfig                   |   10 ++
 arch/powerpc/sysdev/Makefile                     |    1 +
 arch/powerpc/sysdev/simple_gpio.c                |  156 ++++++++++++++++++++++
 arch/powerpc/sysdev/simple_gpio.h                |   15 ++
 5 files changed, 212 insertions(+), 0 deletions(-)
 create mode 100644 arch/powerpc/sysdev/simple_gpio.c
 create mode 100644 arch/powerpc/sysdev/simple_gpio.h

diff --git a/Documentation/powerpc/dts-bindings/fsl/board.txt b/Documentation/powerpc/dts-bindings/fsl/board.txt
index 81a917e..2bd9888 100644
--- a/Documentation/powerpc/dts-bindings/fsl/board.txt
+++ b/Documentation/powerpc/dts-bindings/fsl/board.txt
@@ -27,3 +27,33 @@ Example (MPC8610HPCD):
 		compatible = "fsl,fpga-pixis";
 		reg = <0xe8000000 32>;
 	};
+
+* Freescale BCSR GPIO banks
+
+Some BCSR registers act as simple GPIO controllers, each such
+register can be represented by the gpio-controller node.
+
+Required properities:
+- compatible : Should be "fsl,<board>-bcsr-gpio";
+- reg : Should contain the address and the lenght of the GPIO bank
+  register;
+- #gpio-cells : Should be two. The first cell is the pin number and the
+  second cell is used to specify optional paramters (currently unused);
+- gpio-controller : Marks the port as GPIO controller.
+
+Example:
+
+	bcsr@1,0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "fsl,mpc8360mds-bcsr";
+		reg = <1 0 0x8000>;
+		ranges = <0 1 0 0x8000>;
+
+		bcsr13: gpio-controller@d {
+			#gpio-cells = <2>;
+			compatible = "fsl,mpc8360mds-bcsr-gpio";
+			reg = <0xd 1>;
+			gpio-controller;
+		};
+	};
diff --git a/arch/powerpc/platforms/Kconfig b/arch/powerpc/platforms/Kconfig
index 47e956c..63780c8 100644
--- a/arch/powerpc/platforms/Kconfig
+++ b/arch/powerpc/platforms/Kconfig
@@ -312,4 +312,14 @@ config MPC8xxx_GPIO
 	  Say Y here if you're going to use hardware that connects to the
 	  MPC831x/834x/837x/8572/8610 GPIOs.
 
+config SIMPLE_GPIO
+	bool "Support for simple, memory-mapped GPIO controllers"
+	depends on PPC
+	select GENERIC_GPIO
+	select ARCH_REQUIRE_GPIOLIB
+	help
+	  Say Y here to support simple, memory-mapped GPIO controllers.
+	  These are usually BCSRs used to control board's switches, LEDs,
+	  chip-selects, Ethernet/USB PHY's power and various other small
+	  on-board peripherals.
 endmenu
diff --git a/arch/powerpc/sysdev/Makefile b/arch/powerpc/sysdev/Makefile
index 5afce11..b33b28a 100644
--- a/arch/powerpc/sysdev/Makefile
+++ b/arch/powerpc/sysdev/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_FSL_PCI)		+= fsl_pci.o $(fsl-msi-obj-y)
 obj-$(CONFIG_FSL_LBC)		+= fsl_lbc.o
 obj-$(CONFIG_FSL_GTM)		+= fsl_gtm.o
 obj-$(CONFIG_MPC8xxx_GPIO)	+= mpc8xxx_gpio.o
+obj-$(CONFIG_SIMPLE_GPIO)	+= simple_gpio.o
 obj-$(CONFIG_RAPIDIO)		+= fsl_rio.o
 obj-$(CONFIG_TSI108_BRIDGE)	+= tsi108_pci.o tsi108_dev.o
 obj-$(CONFIG_QUICC_ENGINE)	+= qe_lib/
diff --git a/arch/powerpc/sysdev/simple_gpio.c b/arch/powerpc/sysdev/simple_gpio.c
new file mode 100644
index 0000000..d62c85a
--- /dev/null
+++ b/arch/powerpc/sysdev/simple_gpio.c
@@ -0,0 +1,156 @@
+/*
+ * Simple Memory-Mapped GPIOs
+ *
+ * Copyright (c) MontaVista Software, Inc. 2008.
+ *
+ * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+#include <linux/ioport.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_gpio.h>
+#include <linux/gpio.h>
+#include <asm/prom.h>
+#include "simple_gpio.h"
+
+struct u8_gpio_chip {
+	struct of_mm_gpio_chip mm_gc;
+	spinlock_t lock;
+
+	/* shadowed data register to clear/set bits safely */
+	u8 data;
+};
+
+static struct u8_gpio_chip *to_u8_gpio_chip(struct of_mm_gpio_chip *mm_gc)
+{
+	return container_of(mm_gc, struct u8_gpio_chip, mm_gc);
+}
+
+static u8 u8_pin2mask(unsigned int pin)
+{
+	return 1 << (8 - 1 - pin);
+}
+
+static int u8_gpio_get(struct gpio_chip *gc, unsigned int gpio)
+{
+	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+
+	return in_8(mm_gc->regs) & u8_pin2mask(gpio);
+}
+
+static void u8_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
+{
+	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+	struct u8_gpio_chip *u8_gc = to_u8_gpio_chip(mm_gc);
+	unsigned long flags;
+
+	spin_lock_irqsave(&u8_gc->lock, flags);
+
+	if (val)
+		u8_gc->data |= u8_pin2mask(gpio);
+	else
+		u8_gc->data &= ~u8_pin2mask(gpio);
+
+	out_8(mm_gc->regs, u8_gc->data);
+
+	spin_unlock_irqrestore(&u8_gc->lock, flags);
+}
+
+static int u8_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
+{
+	return 0;
+}
+
+static int u8_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
+{
+	u8_gpio_set(gc, gpio, val);
+	return 0;
+}
+
+static void u8_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
+{
+	struct u8_gpio_chip *u8_gc = to_u8_gpio_chip(mm_gc);
+
+	u8_gc->data = in_8(mm_gc->regs);
+}
+
+static int __init u8_simple_gpiochip_add(struct device_node *np)
+{
+	int ret;
+	struct u8_gpio_chip *u8_gc;
+	struct of_mm_gpio_chip *mm_gc;
+	struct of_gpio_chip *of_gc;
+	struct gpio_chip *gc;
+
+	u8_gc = kzalloc(sizeof(*u8_gc), GFP_KERNEL);
+	if (!u8_gc)
+		return -ENOMEM;
+
+	spin_lock_init(&u8_gc->lock);
+
+	mm_gc = &u8_gc->mm_gc;
+	of_gc = &mm_gc->of_gc;
+	gc = &of_gc->gc;
+
+	mm_gc->save_regs = u8_gpio_save_regs;
+	of_gc->gpio_cells = 2;
+	gc->ngpio = 8;
+	gc->direction_input = u8_gpio_dir_in;
+	gc->direction_output = u8_gpio_dir_out;
+	gc->get = u8_gpio_get;
+	gc->set = u8_gpio_set;
+
+	ret = of_mm_gpiochip_add(np, mm_gc);
+	if (ret)
+		goto err;
+	return 0;
+err:
+	kfree(u8_gc);
+	return ret;
+}
+
+int __init simple_gpiochip_init(const char *compatible)
+{
+	struct device_node *np;
+
+	for_each_compatible_node(np, NULL, compatible) {
+		int ret;
+		struct resource r;
+
+		ret = of_address_to_resource(np, 0, &r);
+		if (ret)
+			goto err;
+
+		switch (resource_size(&r)) {
+		case 1:
+			ret = u8_simple_gpiochip_add(np);
+			if (ret)
+				goto err;
+			break;
+		default:
+			/*
+			 * Whenever you need support for GPIO bank width > 1,
+			 * please just turn u8_ code into huge macros, and
+			 * construct needed uX_ code with it.
+			 */
+			ret = -ENOSYS;
+			goto err;
+		}
+		continue;
+err:
+		pr_err("%s: registration failed, status %d\n",
+		       np->full_name, ret);
+	}
+	return 0;
+}
diff --git a/arch/powerpc/sysdev/simple_gpio.h b/arch/powerpc/sysdev/simple_gpio.h
new file mode 100644
index 0000000..4d0e64d
--- /dev/null
+++ b/arch/powerpc/sysdev/simple_gpio.h
@@ -0,0 +1,15 @@
+#ifndef __SYSDEV_SIMPLE_GPIO_H
+#define __SYSDEV_SIMPLE_GPIO_H
+
+#include <linux/errno.h>
+
+#ifdef CONFIG_SIMPLE_GPIO
+extern int simple_gpiochip_init(const char *compatible);
+#else
+static inline int simple_gpiochip_init(const char *compatible)
+{
+	return -ENODEV;
+}
+#endif /* CONFIG_SIMPLE_GPIO */
+
+#endif /* __SYSDEV_SIMPLE_GPIO_H */
-- 
1.5.6.5

[PATCH 3/5] powerpc/83xx: Add USB Host/Gadget support for MPC8360E-MDS boards

[Anton Vorontsov]

- Update the device tree per QE USB bindings;
- Add timer (FSL GTM) node;
- Add gpio-controller node for BCSR13 bank (GPIOs on that bank
  are used to control the USB transceiver);
- Set up other BCSR registers;
- Configure the QE Par IO.

The work is loosely based on Li Yang's patch[1], which was used
to support peripheral mode only.

[1] http://ozlabs.org/pipermail/linuxppc-dev/2008-August/061357.html

The s-o-b line of the original patch preserved here.

Signed-off-by: Li Yang <leoli@freescale.com>
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
 arch/powerpc/boot/dts/mpc836x_mds.dts     |   43 ++++++++++++++++-
 arch/powerpc/platforms/83xx/mpc836x_mds.c |   75 +++++++++++++++++++++++++++++
 2 files changed, 116 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/boot/dts/mpc836x_mds.dts b/arch/powerpc/boot/dts/mpc836x_mds.dts
index 14534d0..6e34f17 100644
--- a/arch/powerpc/boot/dts/mpc836x_mds.dts
+++ b/arch/powerpc/boot/dts/mpc836x_mds.dts
@@ -69,8 +69,18 @@
 		};
 
 		bcsr@1,0 {
+			#address-cells = <1>;
+			#size-cells = <1>;
  			compatible = "fsl,mpc8360mds-bcsr";
 			reg = <1 0 0x8000>;
+			ranges = <0 1 0 0x8000>;
+
+			bcsr13: gpio-controller@d {
+				#gpio-cells = <2>;
+				compatible = "fsl,mpc8360mds-bcsr-gpio";
+				reg = <0xd 1>;
+				gpio-controller;
+			};
 		};
 	};
 
@@ -195,10 +205,21 @@
 		};
 
 		par_io@1400 {
+			#address-cells = <1>;
+			#size-cells = <1>;
 			reg = <0x1400 0x100>;
+			ranges = <0 0x1400 0x100>;
 			device_type = "par_io";
 			num-ports = <7>;
 
+			qe_pio_b: gpio-controller@18 {
+				#gpio-cells = <2>;
+				compatible = "fsl,mpc8360-qe-pario-bank",
+					     "fsl,mpc8323-qe-pario-bank";
+				reg = <0x18 0x18>;
+				gpio-controller;
+			};
+
 			pio1: ucc_pin@01 {
 				pio-map = <
 			/* port  pin  dir  open_drain  assignment  has_irq */
@@ -282,6 +303,15 @@
 			};
 		};
 
+		timer@440 {
+			compatible = "fsl,mpc8360-qe-gtm",
+				     "fsl,qe-gtm", "fsl,gtm";
+			reg = <0x440 0x40>;
+			clock-frequency = <132000000>;
+			interrupts = <12 13 14 15>;
+			interrupt-parent = <&qeic>;
+		};
+
 		spi@4c0 {
 			cell-index = <0>;
 			compatible = "fsl,spi";
@@ -301,11 +331,20 @@
 		};
 
 		usb@6c0 {
-			compatible = "qe_udc";
+			compatible = "fsl,mpc8360-qe-usb",
+				     "fsl,mpc8323-qe-usb";
 			reg = <0x6c0 0x40 0x8b00 0x100>;
 			interrupts = <11>;
 			interrupt-parent = <&qeic>;
-			mode = "slave";
+			fsl,fullspeed-clock = "clk21";
+			fsl,lowspeed-clock = "brg9";
+			gpios = <&qe_pio_b  2 0   /* USBOE */
+				 &qe_pio_b  3 0   /* USBTP */
+				 &qe_pio_b  8 0   /* USBTN */
+				 &qe_pio_b  9 0   /* USBRP */
+				 &qe_pio_b 11 0   /* USBRN */
+				 &bcsr13    5 0   /* SPEED */
+				 &bcsr13    4 1>; /* POWER */
 		};
 
 		enet0: ucc@2000 {
diff --git a/arch/powerpc/platforms/83xx/mpc836x_mds.c b/arch/powerpc/platforms/83xx/mpc836x_mds.c
index 9d46e5b..fbcca19 100644
--- a/arch/powerpc/platforms/83xx/mpc836x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc836x_mds.c
@@ -43,6 +43,7 @@
 #include <asm/udbg.h>
 #include <sysdev/fsl_soc.h>
 #include <sysdev/fsl_pci.h>
+#include <sysdev/simple_gpio.h>
 #include <asm/qe.h>
 #include <asm/qe_ic.h>
 
@@ -93,6 +94,16 @@ static void __init mpc836x_mds_setup_arch(void)
 
 		for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
 			par_io_of_config(np);
+#ifdef CONFIG_QE_USB
+		/* Must fixup Par IO before QE GPIO chips are registered. */
+		par_io_config_pin(1,  2, 1, 0, 3, 0); /* USBOE  */
+		par_io_config_pin(1,  3, 1, 0, 3, 0); /* USBTP  */
+		par_io_config_pin(1,  8, 1, 0, 1, 0); /* USBTN  */
+		par_io_config_pin(1, 10, 2, 0, 3, 0); /* USBRXD */
+		par_io_config_pin(1,  9, 2, 1, 3, 0); /* USBRP  */
+		par_io_config_pin(1, 11, 2, 1, 3, 0); /* USBRN  */
+		par_io_config_pin(2, 20, 2, 0, 1, 0); /* CLK21  */
+#endif /* CONFIG_QE_USB */
 	}
 
 	if ((np = of_find_compatible_node(NULL, "network", "ucc_geth"))
@@ -151,6 +162,70 @@ static int __init mpc836x_declare_of_platform_devices(void)
 }
 machine_device_initcall(mpc836x_mds, mpc836x_declare_of_platform_devices);
 
+#ifdef CONFIG_QE_USB
+static int __init mpc836x_usb_cfg(void)
+{
+	u8 __iomem *bcsr;
+	struct device_node *np;
+	const char *mode;
+	int ret = 0;
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,mpc8360mds-bcsr");
+	if (!np)
+		return -ENODEV;
+
+	bcsr = of_iomap(np, 0);
+	of_node_put(np);
+	if (!bcsr)
+		return -ENOMEM;
+
+	np = of_find_compatible_node(NULL, NULL, "fsl,mpc8323-qe-usb");
+	if (!np) {
+		ret = -ENODEV;
+		goto err;
+	}
+
+#define BCSR8_TSEC1M_MASK	(0x3 << 6)
+#define BCSR8_TSEC1M_RGMII	(0x0 << 6)
+#define BCSR8_TSEC2M_MASK	(0x3 << 4)
+#define BCSR8_TSEC2M_RGMII	(0x0 << 4)
+	/*
+	 * Default is GMII (2), but we should set it to RGMII (0) if we use
+	 * USB (Eth PHY is in RGMII mode anyway).
+	 */
+	clrsetbits_8(&bcsr[8], BCSR8_TSEC1M_MASK | BCSR8_TSEC2M_MASK,
+			       BCSR8_TSEC1M_RGMII | BCSR8_TSEC2M_RGMII);
+
+#define BCSR13_USBMASK	0x0f
+#define BCSR13_nUSBEN	0x08 /* 1 - Disable, 0 - Enable			*/
+#define BCSR13_USBSPEED	0x04 /* 1 - Full, 0 - Low			*/
+#define BCSR13_USBMODE	0x02 /* 1 - Host, 0 - Function			*/
+#define BCSR13_nUSBVCC	0x01 /* 1 - gets VBUS, 0 - supplies VBUS 	*/
+
+	clrsetbits_8(&bcsr[13], BCSR13_USBMASK, BCSR13_USBSPEED);
+
+	mode = of_get_property(np, "mode", NULL);
+	if (mode && !strcmp(mode, "peripheral")) {
+		setbits8(&bcsr[13], BCSR13_nUSBVCC);
+		qe_usb_clock_set(QE_CLK21, 48000000);
+	} else {
+		setbits8(&bcsr[13], BCSR13_USBMODE);
+		/*
+		 * The BCSR GPIOs are used to control power and
+		 * speed of the USB transceiver. This is needed for
+		 * the USB Host only.
+		 */
+		simple_gpiochip_init("fsl,mpc8360mds-bcsr-gpio");
+	}
+
+	of_node_put(np);
+err:
+	iounmap(bcsr);
+	return ret;
+}
+machine_arch_initcall(mpc836x_mds, mpc836x_usb_cfg);
+#endif /* CONFIG_QE_USB */
+
 static void __init mpc836x_mds_init_IRQ(void)
 {
 	struct device_node *np;
-- 
1.5.6.5

[PATCH 4/5] powerpc/83xx: Add USB Host support for MPC8360E-RDK boards

[Anton Vorontsov]

Simply add the usb node to support USB host on the MPC8360E-RDK
boards.

Currently U-Boot doesn't fill the clock-frequency property for
timer nodes, so for now we have to fill it manually.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
 arch/powerpc/boot/dts/mpc836x_rdk.dts |   19 +++++++++++++++++--
 1 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/arch/powerpc/boot/dts/mpc836x_rdk.dts b/arch/powerpc/boot/dts/mpc836x_rdk.dts
index decadf3..37b7895 100644
--- a/arch/powerpc/boot/dts/mpc836x_rdk.dts
+++ b/arch/powerpc/boot/dts/mpc836x_rdk.dts
@@ -218,8 +218,23 @@
 				reg = <0x440 0x40>;
 				interrupts = <12 13 14 15>;
 				interrupt-parent = <&qeic>;
-				/* filled by u-boot */
-				clock-frequency = <0>;
+				clock-frequency = <166666666>;
+			};
+
+			usb@6c0 {
+				compatible = "fsl,mpc8360-qe-usb",
+					     "fsl,mpc8323-qe-usb";
+				reg = <0x6c0 0x40 0x8b00 0x100>;
+				interrupts = <11>;
+				interrupt-parent = <&qeic>;
+				fsl,fullspeed-clock = "clk21";
+				gpios = <&qe_pio_b  2 0 /* USBOE */
+					 &qe_pio_b  3 0 /* USBTP */
+					 &qe_pio_b  8 0 /* USBTN */
+					 &qe_pio_b  9 0 /* USBRP */
+					 &qe_pio_b 11 0 /* USBRN */
+					 &qe_pio_e 20 0 /* SPEED */
+					 &qe_pio_e 21 1 /* POWER */>;
 			};
 
 			spi@4c0 {
-- 
1.5.6.5

[PATCH 5/5] powerpc/83xx: Fix sparse warnings in mpc836x_mds.c

[Anton Vorontsov]

This patch fixes following sparse warnings:

  CHECK   mpc836x_mds.c
mpc836x_mds.c:75:12: warning: Using plain integer as NULL pointer
mpc836x_mds.c:79:13: warning: incorrect type in assignment (different address spaces)
mpc836x_mds.c:79:13:    expected unsigned char [usertype] *static [toplevel] bcsr_regs
mpc836x_mds.c:79:13:    got void [noderef] <asn:2>*
mpc836x_mds.c:105:3: warning: incorrect type in argument 1 (different address spaces)
mpc836x_mds.c:105:3:    expected unsigned char volatile [noderef] [usertype] <asn:2>*addr
mpc836x_mds.c:105:3:    got unsigned char [usertype] *
mpc836x_mds.c:105:3: warning: incorrect type in argument 1 (different address spaces)
mpc836x_mds.c:105:3:    expected unsigned char const volatile [noderef] [usertype] <asn:2>*addr
mpc836x_mds.c:105:3:    got unsigned char [usertype] *
mpc836x_mds.c:107:3: warning: incorrect type in argument 1 (different address spaces)
mpc836x_mds.c:107:3:    expected unsigned char volatile [noderef] [usertype] <asn:2>*addr
mpc836x_mds.c:107:3:    got unsigned char [usertype] *
mpc836x_mds.c:107:3: warning: incorrect type in argument 1 (different address spaces)
mpc836x_mds.c:107:3:    expected unsigned char const volatile [noderef] [usertype] <asn:2>*addr
mpc836x_mds.c:107:3:    got unsigned char [usertype] *
mpc836x_mds.c:131:11: warning: incorrect type in argument 1 (different address spaces)
mpc836x_mds.c:131:11:    expected void volatile [noderef] <asn:2>*addr
mpc836x_mds.c:131:11:    got unsigned char [usertype] *static [toplevel] bcsr_regs

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
---
 arch/powerpc/platforms/83xx/mpc836x_mds.c |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/powerpc/platforms/83xx/mpc836x_mds.c b/arch/powerpc/platforms/83xx/mpc836x_mds.c
index fbcca19..09e9d6f 100644
--- a/arch/powerpc/platforms/83xx/mpc836x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc836x_mds.c
@@ -18,6 +18,7 @@
 
 #include <linux/stddef.h>
 #include <linux/kernel.h>
+#include <linux/compiler.h>
 #include <linux/init.h>
 #include <linux/errno.h>
 #include <linux/reboot.h>
@@ -56,8 +57,6 @@
 #define DBG(fmt...)
 #endif
 
-static u8 *bcsr_regs = NULL;
-
 /* ************************************************************************
  *
  * Setup the architecture
@@ -66,13 +65,14 @@ static u8 *bcsr_regs = NULL;
 static void __init mpc836x_mds_setup_arch(void)
 {
 	struct device_node *np;
+	u8 __iomem *bcsr_regs = NULL;
 
 	if (ppc_md.progress)
 		ppc_md.progress("mpc836x_mds_setup_arch()", 0);
 
 	/* Map BCSR area */
 	np = of_find_node_by_name(NULL, "bcsr");
-	if (np != 0) {
+	if (np) {
 		struct resource res;
 
 		of_address_to_resource(np, 0, &res);
-- 
1.5.6.5

Re: [PATCH 0/5] Few patches for galak/powerpc.git next

[Kumar Gala]

On Dec 3, 2008, at 1:26 PM, Anton Vorontsov wrote:

> Hi Kumar,
>
> Here are few patches queued for the next branch. The patches are
> mostly USB related. Plus a trivial patch that fixes some sparse
> warnings.
>
> [PATCH 1/5] powerpc/qe: Implement QE Pin Multiplexing API
> [PATCH 2/5] powerpc: Implement GPIO driver for simple memory-mapped  
> banks
> [PATCH 3/5] powerpc/83xx: Add USB Host/Gadget support for MPC8360E- 
> MDS boards
> [PATCH 4/5] powerpc/83xx: Add USB Host support for MPC8360E-RDK boards
> [PATCH 5/5] powerpc/83xx: Fix sparse warnings in mpc836x_mds.c
>
> Thanks,

Thanks.. Do you mind doing me a favor and updating the status of any  
patches that are superceded on http://patchwork.ozlabs.org/

- k

Re: [PATCH 0/5] Few patches for galak/powerpc.git next

[Anton Vorontsov]

On Wed, Dec 03, 2008 at 01:53:26PM -0600, Kumar Gala wrote:
>
> On Dec 3, 2008, at 1:26 PM, Anton Vorontsov wrote:
>
>> Hi Kumar,
>>
>> Here are few patches queued for the next branch. The patches are
>> mostly USB related. Plus a trivial patch that fixes some sparse
>> warnings.
>>
>> [PATCH 1/5] powerpc/qe: Implement QE Pin Multiplexing API
>> [PATCH 2/5] powerpc: Implement GPIO driver for simple memory-mapped  
>> banks
>> [PATCH 3/5] powerpc/83xx: Add USB Host/Gadget support for MPC8360E-MDS 
>> boards
>> [PATCH 4/5] powerpc/83xx: Add USB Host support for MPC8360E-RDK boards
>> [PATCH 5/5] powerpc/83xx: Fix sparse warnings in mpc836x_mds.c
>>
>> Thanks,
>
> Thanks.. Do you mind doing me a favor and updating the status of any  
> patches that are superceded on http://patchwork.ozlabs.org/

Wow, I can change status of my own patches.. super.

Done, plus I also set 'accepted' state for some patches that
were already merged in powerpc or other trees. Hope this is ok.

-- 
Anton Vorontsov
email: cbouatmailru@gmail.com
irc://irc.freenode.net/bd2

Re: [PATCH 5/5] powerpc/83xx: Fix sparse warnings in mpc836x_mds.c

[Kumar Gala]

On Dec 3, 2008, at 1:27 PM, Anton Vorontsov wrote:

> This patch fixes following sparse warnings:
>
>  CHECK   mpc836x_mds.c
> mpc836x_mds.c:75:12: warning: Using plain integer as NULL pointer
> mpc836x_mds.c:79:13: warning: incorrect type in assignment  
> (different address spaces)
> mpc836x_mds.c:79:13:    expected unsigned char [usertype] *static  
> [toplevel] bcsr_regs
> mpc836x_mds.c:79:13:    got void [noderef] <asn:2>*
> mpc836x_mds.c:105:3: warning: incorrect type in argument 1  
> (different address spaces)
> mpc836x_mds.c:105:3:    expected unsigned char volatile [noderef]  
> [usertype] <asn:2>*addr
> mpc836x_mds.c:105:3:    got unsigned char [usertype] *
> mpc836x_mds.c:105:3: warning: incorrect type in argument 1  
> (different address spaces)
> mpc836x_mds.c:105:3:    expected unsigned char const volatile  
> [noderef] [usertype] <asn:2>*addr
> mpc836x_mds.c:105:3:    got unsigned char [usertype] *
> mpc836x_mds.c:107:3: warning: incorrect type in argument 1  
> (different address spaces)
> mpc836x_mds.c:107:3:    expected unsigned char volatile [noderef]  
> [usertype] <asn:2>*addr
> mpc836x_mds.c:107:3:    got unsigned char [usertype] *
> mpc836x_mds.c:107:3: warning: incorrect type in argument 1  
> (different address spaces)
> mpc836x_mds.c:107:3:    expected unsigned char const volatile  
> [noderef] [usertype] <asn:2>*addr
> mpc836x_mds.c:107:3:    got unsigned char [usertype] *
> mpc836x_mds.c:131:11: warning: incorrect type in argument 1  
> (different address spaces)
> mpc836x_mds.c:131:11:    expected void volatile [noderef] <asn:2>*addr
> mpc836x_mds.c:131:11:    got unsigned char [usertype] *static  
> [toplevel] bcsr_regs
>
> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
> ---
> arch/powerpc/platforms/83xx/mpc836x_mds.c |    6 +++---
> 1 files changed, 3 insertions(+), 3 deletions(-)

applied to next

- k

Re: [PATCH 1/5] powerpc/qe: Implement QE Pin Multiplexing API

[Anton Vorontsov]

On Wed, Dec 03, 2008 at 10:27:38PM +0300, Anton Vorontsov wrote:
> With this API we're able to set a QE pin to the GPIO mode or a dedicated
> peripheral function.
> 
> The API relies on the fact that QE gpio controllers are registered. If
> they aren't, the API won't work (gracefully though).
> 
> There is one caveat though: if anybody occupied the node->data before us,
> or overwrote it, then bad things will happen. Luckily this is all in the
> platform code that we fully control, so this should never happen.
> 
> I could implement more checks (for example we could create a list of
> successfully registered QE controllers, and compare the node->data in the
> qe_pin_request()), but this is unneeded if nobody is going to do silly
> things behind our back.
> 
> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
> ---

Kumar, can you please merge this patch? It is the last patch that
holds the FHCI USB driver.

Thanks,

>  arch/powerpc/include/asm/qe.h     |   21 ++++
>  arch/powerpc/sysdev/qe_lib/gpio.c |  195 +++++++++++++++++++++++++++++++++++++
>  2 files changed, 216 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/powerpc/include/asm/qe.h b/arch/powerpc/include/asm/qe.h
> index edee15d..3227440 100644
> --- a/arch/powerpc/include/asm/qe.h
> +++ b/arch/powerpc/include/asm/qe.h
> @@ -17,6 +17,8 @@
>  #ifdef __KERNEL__
>  
>  #include <linux/spinlock.h>
> +#include <linux/errno.h>
> +#include <linux/err.h>
>  #include <asm/cpm.h>
>  #include <asm/immap_qe.h>
>  
> @@ -112,6 +114,25 @@ extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain,
>  			     int assignment, int has_irq);
>  extern int par_io_data_set(u8 port, u8 pin, u8 val);
>  
> +/*
> + * Pin multiplexing functions.
> + */
> +struct qe_pin;
> +#ifdef CONFIG_QE_GPIO
> +extern struct qe_pin *qe_pin_request(struct device_node *np, int index);
> +extern void qe_pin_free(struct qe_pin *qe_pin);
> +extern void qe_pin_set_gpio(struct qe_pin *qe_pin);
> +extern void qe_pin_set_dedicated(struct qe_pin *pin);
> +#else
> +static inline struct qe_pin *qe_pin_request(struct device_node *np, int index)
> +{
> +	return ERR_PTR(-ENOSYS);
> +}
> +static inline void qe_pin_free(struct qe_pin *qe_pin) {}
> +static inline void qe_pin_set_gpio(struct qe_pin *qe_pin) {}
> +static inline void qe_pin_set_dedicated(struct qe_pin *pin) {}
> +#endif /* CONFIG_QE_GPIO */
> +
>  /* QE internal API */
>  int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input);
>  enum qe_clock qe_clock_source(const char *source);
> diff --git a/arch/powerpc/sysdev/qe_lib/gpio.c b/arch/powerpc/sysdev/qe_lib/gpio.c
> index 8e5a0bc..3485288 100644
> --- a/arch/powerpc/sysdev/qe_lib/gpio.c
> +++ b/arch/powerpc/sysdev/qe_lib/gpio.c
> @@ -14,6 +14,7 @@
>  #include <linux/kernel.h>
>  #include <linux/init.h>
>  #include <linux/spinlock.h>
> +#include <linux/err.h>
>  #include <linux/io.h>
>  #include <linux/of.h>
>  #include <linux/of_gpio.h>
> @@ -24,8 +25,14 @@ struct qe_gpio_chip {
>  	struct of_mm_gpio_chip mm_gc;
>  	spinlock_t lock;
>  
> +	unsigned long pin_flags[QE_PIO_PINS];
> +#define QE_PIN_REQUESTED 0
> +
>  	/* shadowed data register to clear/set bits safely */
>  	u32 cpdata;
> +
> +	/* saved_regs used to restore dedicated functions */
> +	struct qe_pio_regs saved_regs;
>  };
>  
>  static inline struct qe_gpio_chip *
> @@ -40,6 +47,12 @@ static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
>  	struct qe_pio_regs __iomem *regs = mm_gc->regs;
>  
>  	qe_gc->cpdata = in_be32(&regs->cpdata);
> +	qe_gc->saved_regs.cpdata = qe_gc->cpdata;
> +	qe_gc->saved_regs.cpdir1 = in_be32(&regs->cpdir1);
> +	qe_gc->saved_regs.cpdir2 = in_be32(&regs->cpdir2);
> +	qe_gc->saved_regs.cppar1 = in_be32(&regs->cppar1);
> +	qe_gc->saved_regs.cppar2 = in_be32(&regs->cppar2);
> +	qe_gc->saved_regs.cpodr = in_be32(&regs->cpodr);
>  }
>  
>  static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
> @@ -103,6 +116,188 @@ static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
>  	return 0;
>  }
>  
> +struct qe_pin {
> +	/*
> +	 * The qe_gpio_chip name is unfortunate, we should change that to
> +	 * something like qe_pio_controller. Someday.
> +	 */
> +	struct qe_gpio_chip *controller;
> +	int num;
> +};
> +
> +/**
> + * qe_pin_request - Request a QE pin
> + * @np:		device node to get a pin from
> + * @index:	index of a pin in the device tree
> + * Context:	non-atomic
> + *
> + * This function return qe_pin so that you could use it with the rest of
> + * the QE Pin Multiplexing API.
> + */
> +struct qe_pin *qe_pin_request(struct device_node *np, int index)
> +{
> +	struct qe_pin *qe_pin;
> +	struct device_node *gc;
> +	struct of_gpio_chip *of_gc = NULL;
> +	struct of_mm_gpio_chip *mm_gc;
> +	struct qe_gpio_chip *qe_gc;
> +	int err;
> +	int size;
> +	const void *gpio_spec;
> +	const u32 *gpio_cells;
> +	unsigned long flags;
> +
> +	qe_pin = kzalloc(sizeof(*qe_pin), GFP_KERNEL);
> +	if (!qe_pin) {
> +		pr_debug("%s: can't allocate memory\n", __func__);
> +		return ERR_PTR(-ENOMEM);
> +	}
> +
> +	err = of_parse_phandles_with_args(np, "gpios", "#gpio-cells", index,
> +					  &gc, &gpio_spec);
> +	if (err) {
> +		pr_debug("%s: can't parse gpios property\n", __func__);
> +		goto err0;
> +	}
> +
> +	if (!of_device_is_compatible(gc, "fsl,mpc8323-qe-pario-bank")) {
> +		pr_debug("%s: tried to get a non-qe pin\n", __func__);
> +		err = -EINVAL;
> +		goto err1;
> +	}
> +
> +	of_gc = gc->data;
> +	if (!of_gc) {
> +		pr_debug("%s: gpio controller %s isn't registered\n",
> +			 np->full_name, gc->full_name);
> +		err = -ENODEV;
> +		goto err1;
> +	}
> +
> +	gpio_cells = of_get_property(gc, "#gpio-cells", &size);
> +	if (!gpio_cells || size != sizeof(*gpio_cells) ||
> +			*gpio_cells != of_gc->gpio_cells) {
> +		pr_debug("%s: wrong #gpio-cells for %s\n",
> +			 np->full_name, gc->full_name);
> +		err = -EINVAL;
> +		goto err1;
> +	}
> +
> +	err = of_gc->xlate(of_gc, np, gpio_spec, NULL);
> +	if (err < 0)
> +		goto err1;
> +
> +	mm_gc = to_of_mm_gpio_chip(&of_gc->gc);
> +	qe_gc = to_qe_gpio_chip(mm_gc);
> +
> +	spin_lock_irqsave(&qe_gc->lock, flags);
> +
> +	if (test_and_set_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[err]) == 0) {
> +		qe_pin->controller = qe_gc;
> +		qe_pin->num = err;
> +		err = 0;
> +	} else {
> +		err = -EBUSY;
> +	}
> +
> +	spin_unlock_irqrestore(&qe_gc->lock, flags);
> +
> +	if (!err)
> +		return qe_pin;
> +err1:
> +	of_node_put(gc);
> +err0:
> +	kfree(qe_pin);
> +	pr_debug("%s failed with status %d\n", __func__, err);
> +	return ERR_PTR(err);
> +}
> +EXPORT_SYMBOL(qe_pin_request);
> +
> +/**
> + * qe_pin_free - Free a pin
> + * @qe_pin:	pointer to the qe_pin structure
> + * Context:	any
> + *
> + * This function frees the qe_pin structure and makes a pin available
> + * for further qe_pin_request() calls.
> + */
> +void qe_pin_free(struct qe_pin *qe_pin)
> +{
> +	struct qe_gpio_chip *qe_gc = qe_pin->controller;
> +	unsigned long flags;
> +	const int pin = qe_pin->num;
> +
> +	spin_lock_irqsave(&qe_gc->lock, flags);
> +	test_and_clear_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[pin]);
> +	spin_unlock_irqrestore(&qe_gc->lock, flags);
> +
> +	kfree(qe_pin);
> +}
> +EXPORT_SYMBOL(qe_pin_free);
> +
> +/**
> + * qe_pin_set_dedicated - Revert a pin to a dedicated peripheral function mode
> + * @qe_pin:	pointer to the qe_pin structure
> + * Context:	any
> + *
> + * This function resets a pin to a dedicated peripheral function that
> + * has been set up by the firmware.
> + */
> +void qe_pin_set_dedicated(struct qe_pin *qe_pin)
> +{
> +	struct qe_gpio_chip *qe_gc = qe_pin->controller;
> +	struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
> +	struct qe_pio_regs *sregs = &qe_gc->saved_regs;
> +	int pin = qe_pin->num;
> +	u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1));
> +	u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2);
> +	bool second_reg = pin > (QE_PIO_PINS / 2) - 1;
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&qe_gc->lock, flags);
> +
> +	if (second_reg) {
> +		clrsetbits_be32(&regs->cpdir2, mask2, sregs->cpdir2 & mask2);
> +		clrsetbits_be32(&regs->cppar2, mask2, sregs->cppar2 & mask2);
> +	} else {
> +		clrsetbits_be32(&regs->cpdir1, mask2, sregs->cpdir1 & mask2);
> +		clrsetbits_be32(&regs->cppar1, mask2, sregs->cppar1 & mask2);
> +	}
> +
> +	if (sregs->cpdata & mask1)
> +		qe_gc->cpdata |= mask1;
> +	else
> +		qe_gc->cpdata &= ~mask1;
> +
> +	out_be32(&regs->cpdata, qe_gc->cpdata);
> +	clrsetbits_be32(&regs->cpodr, mask1, sregs->cpodr & mask1);
> +
> +	spin_unlock_irqrestore(&qe_gc->lock, flags);
> +}
> +EXPORT_SYMBOL(qe_pin_set_dedicated);
> +
> +/**
> + * qe_pin_set_gpio - Set a pin to the GPIO mode
> + * @qe_pin:	pointer to the qe_pin structure
> + * Context:	any
> + *
> + * This function sets a pin to the GPIO mode.
> + */
> +void qe_pin_set_gpio(struct qe_pin *qe_pin)
> +{
> +	struct qe_gpio_chip *qe_gc = qe_pin->controller;
> +	struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&qe_gc->lock, flags);
> +
> +	/* Let's make it input by default, GPIO API is able to change that. */
> +	__par_io_config_pin(regs, qe_pin->num, QE_PIO_DIR_IN, 0, 0, 0);
> +
> +	spin_unlock_irqrestore(&qe_gc->lock, flags);
> +}
> +EXPORT_SYMBOL(qe_pin_set_gpio);
> +
>  static int __init qe_add_gpiochips(void)
>  {
>  	struct device_node *np;
> -- 
> 1.5.6.5
> 
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev

-- 
Anton Vorontsov
email: cbouatmailru@gmail.com
irc://irc.freenode.net/bd2

Re: [PATCH 1/5] powerpc/qe: Implement QE Pin Multiplexing API

[Kumar Gala]

On Dec 17, 2008, at 9:41 AM, Anton Vorontsov wrote:

> On Wed, Dec 03, 2008 at 10:27:38PM +0300, Anton Vorontsov wrote:
>> With this API we're able to set a QE pin to the GPIO mode or a  
>> dedicated
>> peripheral function.
>>
>> The API relies on the fact that QE gpio controllers are registered.  
>> If
>> they aren't, the API won't work (gracefully though).
>>
>> There is one caveat though: if anybody occupied the node->data  
>> before us,
>> or overwrote it, then bad things will happen. Luckily this is all  
>> in the
>> platform code that we fully control, so this should never happen.
>>
>> I could implement more checks (for example we could create a list of
>> successfully registered QE controllers, and compare the node->data  
>> in the
>> qe_pin_request()), but this is unneeded if nobody is going to do  
>> silly
>> things behind our back.
>>
>> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
>> ---
>
> Kumar, can you please merge this patch? It is the last patch that
> holds the FHCI USB driver.
>
> Thanks,

Will do.  Can I get you to add kdoc comments for the API functions:

+extern struct qe_pin *qe_pin_request(struct device_node *np, int  
index);
+extern void qe_pin_free(struct qe_pin *qe_pin);
+extern void qe_pin_set_gpio(struct qe_pin *qe_pin);
+extern void qe_pin_set_dedicated(struct qe_pin *pin);

- k

Re: [PATCH 1/5] powerpc/qe: Implement QE Pin Multiplexing API

[Kumar Gala]

On Dec 3, 2008, at 1:27 PM, Anton Vorontsov wrote:

> With this API we're able to set a QE pin to the GPIO mode or a  
> dedicated
> peripheral function.
>
> The API relies on the fact that QE gpio controllers are registered. If
> they aren't, the API won't work (gracefully though).
>
> There is one caveat though: if anybody occupied the node->data  
> before us,
> or overwrote it, then bad things will happen. Luckily this is all in  
> the
> platform code that we fully control, so this should never happen.
>
> I could implement more checks (for example we could create a list of
> successfully registered QE controllers, and compare the node->data  
> in the
> qe_pin_request()), but this is unneeded if nobody is going to do silly
> things behind our back.
>
> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
> ---
> arch/powerpc/include/asm/qe.h     |   21 ++++
> arch/powerpc/sysdev/qe_lib/gpio.c |  195 ++++++++++++++++++++++++++++ 
> +++++++++
> 2 files changed, 216 insertions(+), 0 deletions(-)

applied to next

- k

Re: [PATCH 1/5] powerpc/qe: Implement QE Pin Multiplexing API

[Anton Vorontsov]

On Wed, Dec 17, 2008 at 10:46:17AM -0600, Kumar Gala wrote:
>
> On Dec 17, 2008, at 9:41 AM, Anton Vorontsov wrote:
>
>> On Wed, Dec 03, 2008 at 10:27:38PM +0300, Anton Vorontsov wrote:
>>> With this API we're able to set a QE pin to the GPIO mode or a  
>>> dedicated
>>> peripheral function.
>>>
>>> The API relies on the fact that QE gpio controllers are registered.  
>>> If
>>> they aren't, the API won't work (gracefully though).
>>>
>>> There is one caveat though: if anybody occupied the node->data  
>>> before us,
>>> or overwrote it, then bad things will happen. Luckily this is all in 
>>> the
>>> platform code that we fully control, so this should never happen.
>>>
>>> I could implement more checks (for example we could create a list of
>>> successfully registered QE controllers, and compare the node->data  
>>> in the
>>> qe_pin_request()), but this is unneeded if nobody is going to do  
>>> silly
>>> things behind our back.
>>>
>>> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
>>> ---
>>
>> Kumar, can you please merge this patch? It is the last patch that
>> holds the FHCI USB driver.
>>
>> Thanks,
>
> Will do.  Can I get you to add kdoc comments for the API functions:

The functions already have kdoc comments (see qe_lib/gpio.c changes).

> +extern struct qe_pin *qe_pin_request(struct device_node *np, int  
> index);
> +extern void qe_pin_free(struct qe_pin *qe_pin);
> +extern void qe_pin_set_gpio(struct qe_pin *qe_pin);
> +extern void qe_pin_set_dedicated(struct qe_pin *pin);

-- 
Anton Vorontsov
email: cbouatmailru@gmail.com
irc://irc.freenode.net/bd2

Re: [PATCH 2/5] powerpc: Implement GPIO driver for simple memory-mapped banks

[Kumar Gala]

On Dec 3, 2008, at 1:27 PM, Anton Vorontsov wrote:

> The driver supports very simple GPIO controllers, that is, when a
> controller provides just a 'data' register. Such controllers may be
> found in various BCSRs (Board's FPGAs used to control board's
> switches, LEDs, chip-selects, Ethernet/USB PHY power, etc).
>
> So far we support only 1-byte GPIO banks. Support for other widths may
> be implemented when/if needed.
>
> p.s.
> To avoid "made up" compatible entries (like compatible = "simple- 
> gpio"),
> boards must call the simple_gpiochip_init() to pass the compatible
> string.
>
> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
> ---
> Documentation/powerpc/dts-bindings/fsl/board.txt |   30 ++++

can we pull this out of this patch.  Since the fsl board specific  
binding its 100% relevant to the generic support for simple_gpio.  We  
can also update the .dts for just gpio and Kconfig in that patch.

>
> arch/powerpc/platforms/Kconfig                   |   10 ++
> arch/powerpc/sysdev/Makefile                     |    1 +
> arch/powerpc/sysdev/simple_gpio.c                |  156 +++++++++++++ 
> +++++++++
> arch/powerpc/sysdev/simple_gpio.h                |   15 ++
> 5 files changed, 212 insertions(+), 0 deletions(-)
> create mode 100644 arch/powerpc/sysdev/simple_gpio.c
> create mode 100644 arch/powerpc/sysdev/simple_gpio.h
>
> diff --git a/Documentation/powerpc/dts-bindings/fsl/board.txt b/ 
> Documentation/powerpc/dts-bindings/fsl/board.txt
> index 81a917e..2bd9888 100644
> --- a/Documentation/powerpc/dts-bindings/fsl/board.txt
> +++ b/Documentation/powerpc/dts-bindings/fsl/board.txt
> @@ -27,3 +27,33 @@ Example (MPC8610HPCD):
> 		compatible = "fsl,fpga-pixis";
> 		reg = <0xe8000000 32>;
> 	};
> +
> +* Freescale BCSR GPIO banks
> +
> +Some BCSR registers act as simple GPIO controllers, each such
> +register can be represented by the gpio-controller node.
> +
> +Required properities:
> +- compatible : Should be "fsl,<board>-bcsr-gpio";
> +- reg : Should contain the address and the lenght of the GPIO bank
> +  register;

spelling - length
semicolon at add of register can be dropped.

>
> +- #gpio-cells : Should be two. The first cell is the pin number and  
> the
> +  second cell is used to specify optional paramters (currently  
> unused);
> +- gpio-controller : Marks the port as GPIO controller.
> +
> +Example:
> +
> +	bcsr@1,0 {
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		compatible = "fsl,mpc8360mds-bcsr";
> +		reg = <1 0 0x8000>;
> +		ranges = <0 1 0 0x8000>;
> +
> +		bcsr13: gpio-controller@d {
> +			#gpio-cells = <2>;
> +			compatible = "fsl,mpc8360mds-bcsr-gpio";
> +			reg = <0xd 1>;
> +			gpio-controller;
> +		};
> +	};

> diff --git a/arch/powerpc/sysdev/simple_gpio.c b/arch/powerpc/sysdev/ 
> simple_gpio.c
> new file mode 100644
> index 0000000..d62c85a
> --- /dev/null
> +++ b/arch/powerpc/sysdev/simple_gpio.c
> @@ -0,0 +1,156 @@
> +/*
> + * Simple Memory-Mapped GPIOs
> + *
> + * Copyright (c) MontaVista Software, Inc. 2008.
> + *
> + * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
> + *
> + * This program is free software; you can redistribute  it and/or  
> modify it
> + * under  the terms of  the GNU General  Public License as  
> published by the
> + * Free Software Foundation;  either version 2 of the  License, or  
> (at your
> + * option) any later version.
> + */
> +
> +#include <linux/init.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/spinlock.h>
> +#include <linux/types.h>
> +#include <linux/ioport.h>
> +#include <linux/io.h>
> +#include <linux/of.h>
> +#include <linux/of_gpio.h>
> +#include <linux/gpio.h>
> +#include <asm/prom.h>
> +#include "simple_gpio.h"
> +
> +struct u8_gpio_chip {
> +	struct of_mm_gpio_chip mm_gc;
> +	spinlock_t lock;
> +
> +	/* shadowed data register to clear/set bits safely */
> +	u8 data;
> +};
> +
> +static struct u8_gpio_chip *to_u8_gpio_chip(struct of_mm_gpio_chip  
> *mm_gc)
> +{
> +	return container_of(mm_gc, struct u8_gpio_chip, mm_gc);
> +}
> +
> +static u8 u8_pin2mask(unsigned int pin)
> +{
> +	return 1 << (8 - 1 - pin);
> +}
> +
> +static int u8_gpio_get(struct gpio_chip *gc, unsigned int gpio)
> +{
> +	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
> +
> +	return in_8(mm_gc->regs) & u8_pin2mask(gpio);
> +}
> +
> +static void u8_gpio_set(struct gpio_chip *gc, unsigned int gpio,  
> int val)
> +{
> +	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
> +	struct u8_gpio_chip *u8_gc = to_u8_gpio_chip(mm_gc);
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&u8_gc->lock, flags);
> +
> +	if (val)
> +		u8_gc->data |= u8_pin2mask(gpio);
> +	else
> +		u8_gc->data &= ~u8_pin2mask(gpio);
> +
> +	out_8(mm_gc->regs, u8_gc->data);
> +
> +	spin_unlock_irqrestore(&u8_gc->lock, flags);
> +}
> +
> +static int u8_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
> +{
> +	return 0;
> +}
> +
> +static int u8_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio,  
> int val)
> +{
> +	u8_gpio_set(gc, gpio, val);
> +	return 0;
> +}
> +
> +static void u8_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
> +{
> +	struct u8_gpio_chip *u8_gc = to_u8_gpio_chip(mm_gc);
> +
> +	u8_gc->data = in_8(mm_gc->regs);
> +}
> +
> +static int __init u8_simple_gpiochip_add(struct device_node *np)
> +{
> +	int ret;
> +	struct u8_gpio_chip *u8_gc;
> +	struct of_mm_gpio_chip *mm_gc;
> +	struct of_gpio_chip *of_gc;
> +	struct gpio_chip *gc;
> +
> +	u8_gc = kzalloc(sizeof(*u8_gc), GFP_KERNEL);
> +	if (!u8_gc)
> +		return -ENOMEM;
> +
> +	spin_lock_init(&u8_gc->lock);
> +
> +	mm_gc = &u8_gc->mm_gc;
> +	of_gc = &mm_gc->of_gc;
> +	gc = &of_gc->gc;
> +
> +	mm_gc->save_regs = u8_gpio_save_regs;
> +	of_gc->gpio_cells = 2;
> +	gc->ngpio = 8;
> +	gc->direction_input = u8_gpio_dir_in;
> +	gc->direction_output = u8_gpio_dir_out;
> +	gc->get = u8_gpio_get;
> +	gc->set = u8_gpio_set;
> +
> +	ret = of_mm_gpiochip_add(np, mm_gc);
> +	if (ret)
> +		goto err;
> +	return 0;
> +err:
> +	kfree(u8_gc);
> +	return ret;
> +}
> +
> +int __init simple_gpiochip_init(const char *compatible)
> +{
> +	struct device_node *np;
> +
> +	for_each_compatible_node(np, NULL, compatible) {
> +		int ret;
> +		struct resource r;
> +
> +		ret = of_address_to_resource(np, 0, &r);
> +		if (ret)
> +			goto err;
> +
> +		switch (resource_size(&r)) {
> +		case 1:
> +			ret = u8_simple_gpiochip_add(np);
> +			if (ret)
> +				goto err;
> +			break;
> +		default:
> +			/*
> +			 * Whenever you need support for GPIO bank width > 1,
> +			 * please just turn u8_ code into huge macros, and
> +			 * construct needed uX_ code with it.
> +			 */
> +			ret = -ENOSYS;
> +			goto err;
> +		}
> +		continue;
> +err:
> +		pr_err("%s: registration failed, status %d\n",
> +		       np->full_name, ret);
> +	}
> +	return 0;
> +}
> diff --git a/arch/powerpc/sysdev/simple_gpio.h b/arch/powerpc/sysdev/ 
> simple_gpio.h
> new file mode 100644
> index 0000000..4d0e64d
> --- /dev/null
> +++ b/arch/powerpc/sysdev/simple_gpio.h
> @@ -0,0 +1,15 @@
> +#ifndef __SYSDEV_SIMPLE_GPIO_H
> +#define __SYSDEV_SIMPLE_GPIO_H
> +
> +#include <linux/errno.h>
> +
> +#ifdef CONFIG_SIMPLE_GPIO
> +extern int simple_gpiochip_init(const char *compatible);
> +#else
> +static inline int simple_gpiochip_init(const char *compatible)
> +{
> +	return -ENODEV;
> +}
> +#endif /* CONFIG_SIMPLE_GPIO */
> +
> +#endif /* __SYSDEV_SIMPLE_GPIO_H */

Can I call simple_gpiochip_init() multiple times w/different  
compatibles?

- k

Re: [PATCH 1/5] powerpc/qe: Implement QE Pin Multiplexing API

[Kumar Gala]

>>>>
>>>
>>> Kumar, can you please merge this patch? It is the last patch that
>>> holds the FHCI USB driver.
>>>
>>> Thanks,
>>
>> Will do.  Can I get you to add kdoc comments for the API functions:
>
> The functions already have kdoc comments (see qe_lib/gpio.c changes).


Yeah, I noticed that.. sorry about the noise.

- k

Re: [PATCH 3/5] powerpc/83xx: Add USB Host/Gadget support for MPC8360E-MDS boards

[Kumar Gala]

On Dec 3, 2008, at 1:27 PM, Anton Vorontsov wrote:

> - Update the device tree per QE USB bindings;
> - Add timer (FSL GTM) node;
> - Add gpio-controller node for BCSR13 bank (GPIOs on that bank
>  are used to control the USB transceiver);
> - Set up other BCSR registers;
> - Configure the QE Par IO.

Of these are they all in the kernel tree already?  What I mean is QE  
usb bindings in linus's tree?  I know GTM timers is and this patch  
series had the bcsr gpio.  Similar question for qe par io.  I think we  
are good but clearly I leave much of QE to you & timur.

- k

Re: [PATCH 3/5] powerpc/83xx: Add USB Host/Gadget support for MPC8360E-MDS boards

[Timur Tabi]

Kumar Gala wrote:

> Of these are they all in the kernel tree already?  What I mean is QE  
> usb bindings in linus's tree?  I know GTM timers is and this patch  
> series had the bcsr gpio.  Similar question for qe par io.  I think we  
> are good but clearly I leave much of QE to you & timur.

These QE GPIO and USB patches have been floating around so long, that I think
it's important to get them in so that the functionality is available.  I
reviewed them a while go and gave them my thumbs up, and I trust Anton, so I'm
sure these latest patches are OK.

-- 
Timur Tabi
Linux kernel developer at Freescale

Re: [PATCH 2/5] powerpc: Implement GPIO driver for simple memory-mapped banks

[Anton Vorontsov]

On Wed, Dec 17, 2008 at 10:56:08AM -0600, Kumar Gala wrote:
>
> On Dec 3, 2008, at 1:27 PM, Anton Vorontsov wrote:
>
>> The driver supports very simple GPIO controllers, that is, when a
>> controller provides just a 'data' register. Such controllers may be
>> found in various BCSRs (Board's FPGAs used to control board's
>> switches, LEDs, chip-selects, Ethernet/USB PHY power, etc).
>>
>> So far we support only 1-byte GPIO banks. Support for other widths may
>> be implemented when/if needed.
>>
>> p.s.
>> To avoid "made up" compatible entries (like compatible = "simple- 
>> gpio"),
>> boards must call the simple_gpiochip_init() to pass the compatible
>> string.
>>
>> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
>> ---
>> Documentation/powerpc/dts-bindings/fsl/board.txt |   30 ++++
>
> can we pull this out of this patch.

Will do.

[...]
>> +#ifdef CONFIG_SIMPLE_GPIO
>> +extern int simple_gpiochip_init(const char *compatible);
>> +#else
>> +static inline int simple_gpiochip_init(const char *compatible)
>> +{
>> +	return -ENODEV;
>> +}
>> +#endif /* CONFIG_SIMPLE_GPIO */
>> +
>> +#endif /* __SYSDEV_SIMPLE_GPIO_H */
>
> Can I call simple_gpiochip_init() multiple times w/different  
> compatibles?

Yes, sure.

-- 
Anton Vorontsov
email: cbouatmailru@gmail.com
irc://irc.freenode.net/bd2

Re: [PATCH 3/5] powerpc/83xx: Add USB Host/Gadget support for MPC8360E-MDS boards

[Anton Vorontsov]

On Wed, Dec 17, 2008 at 10:59:09AM -0600, Kumar Gala wrote:
>
> On Dec 3, 2008, at 1:27 PM, Anton Vorontsov wrote:
>
>> - Update the device tree per QE USB bindings;
>> - Add timer (FSL GTM) node;
>> - Add gpio-controller node for BCSR13 bank (GPIOs on that bank
>>  are used to control the USB transceiver);
>> - Set up other BCSR registers;
>> - Configure the QE Par IO.
>
> Of these are they all in the kernel tree already?  What I mean is QE usb 
> bindings in linus's tree?

Yes, they're all in the Linus' tree already (except for simple/bcsr
gpio bindings, which are in this patch series).

Thanks,

-- 
Anton Vorontsov
email: cbouatmailru@gmail.com
irc://irc.freenode.net/bd2

Re: [PATCH 3/5] powerpc/83xx: Add USB Host/Gadget support for MPC8360E-MDS boards

[Kumar Gala]

On Dec 17, 2008, at 11:15 AM, Anton Vorontsov wrote:

> On Wed, Dec 17, 2008 at 10:59:09AM -0600, Kumar Gala wrote:
>>
>> On Dec 3, 2008, at 1:27 PM, Anton Vorontsov wrote:
>>
>>> - Update the device tree per QE USB bindings;
>>> - Add timer (FSL GTM) node;
>>> - Add gpio-controller node for BCSR13 bank (GPIOs on that bank
>>> are used to control the USB transceiver);
>>> - Set up other BCSR registers;
>>> - Configure the QE Par IO.
>>
>> Of these are they all in the kernel tree already?  What I mean is  
>> QE usb
>> bindings in linus's tree?
>
> Yes, they're all in the Linus' tree already (except for simple/bcsr
> gpio bindings, which are in this patch series).

Ok.  If you fixup my comment about splitting up patch 2/5 & 3/5 w/ 
regards to BCSR GPIO and repost the patch series (excluding 1/5 since  
that is in my tree) I'll apply all these since they look good.

- k