[PATCH 00/16] Add support for MPC512x

[PATCH 00/16] Add support for MPC512x

[Wolfgang Denk]

The following patch series brings support for the Freescale MPC512x
processsors up to date:

[PATCH 01/12] fs_enet: Use defines to set driver tunables.
	      Cc: <netdev@vger.kernel.org>
[PATCH 02/12] fs_enet: Add MPC5121 FEC support.
	      Cc: <netdev@vger.kernel.org>
[PATCH 03/12] fs_enet: Add FEC TX Alignment workaround for MPC5121.
	      Cc: <netdev@vger.kernel.org>
[PATCH 04/12] mpc5121: Added reset module registers representation.
[PATCH 05/12] mpc5121ads: Added Reset Module node to DTS.
[PATCH 06/12] mpc5121: Added NAND Flash Controller driver.
	      Cc: <linux-mtd@lists.infradead.org>
[PATCH 07/12] mpc5121ads: Clean up and fix NAND description in mpc5121ads DTS.
[PATCH 08/12] mpc5121: Added I2C support.
	      Cc: <linux-i2c@vger.kernel.org>
[PATCH 09/12] mpc5121ads: Added I2C RTC node to mpc5121ads DTS.
[PATCH 10/12] mpc5121: Add MPC5121 Real time clock driver.
	      Cc: <rtc-linux@googlegroups.com>
[PATCH 11/12] mpc5121: Added MPC512x DMA driver.
[PATCH 12/12] mpc5121: Added default config for MPC5121.

The patches are based on v2.6.30-rc4 and cover the following
items:

- platform, DTS
- DMA
- FEC Ethernet
- UART (without h/w flow control)
- I2C
- NAND
- RTC

The code has been tested on the Freescale/STX "MPC5121ADS" board
(board rev. 4) with a MPC5121e Rev. 2. No attempt was made to provide
backward compatibility to older silicon revisions or older revisions
of the board.

The work for this project has been approved as OSADL project by a
majority of OSADL members and funded by OSADL membership fees in 2009;
for details please see www.osadl.org.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: John Rigby <jcrigby@gmail.com>
---
Summary statistics:

 arch/powerpc/boot/dts/aria.dts                 |  410 ++++++
 arch/powerpc/boot/dts/mpc5121ads.dts           |   25 +-
 arch/powerpc/configs/512x/aria_defconfig       | 1789 ++++++++++++++++++++++++
 arch/powerpc/configs/512x/mpc5121ads_defconfig | 1190 ++++++++++++++++
 arch/powerpc/configs/mpc5121_defconfig         | 1158 +++++++++++++++
 arch/powerpc/include/asm/mpc5121_fec.h         |  111 ++
 arch/powerpc/include/asm/mpc5121_nfc.h         |  100 ++
 arch/powerpc/include/asm/mpc512x.h             |   13 +
 arch/powerpc/platforms/512x/Kconfig            |    9 +
 arch/powerpc/platforms/512x/Makefile           |    1 +
 arch/powerpc/platforms/512x/aria.c             |   73 +
 arch/powerpc/platforms/512x/mpc5121_ads.c      |    2 +
 arch/powerpc/platforms/512x/mpc5121_generic.c  |    1 +
 arch/powerpc/platforms/512x/mpc512x.h          |    1 +
 arch/powerpc/platforms/512x/mpc512x_shared.c   |   26 +
 drivers/dma/Kconfig                            |    7 +
 drivers/dma/Makefile                           |    1 +
 drivers/dma/mpc512x_dma.c                      |  642 +++++++++
 drivers/dma/mpc512x_dma.h                      |  192 +++
 drivers/i2c/busses/Kconfig                     |    9 +-
 drivers/mtd/nand/Kconfig                       |    7 +
 drivers/mtd/nand/Makefile                      |    1 +
 drivers/mtd/nand/mpc5121_nfc.c                 |  855 +++++++++++
 drivers/net/fs_enet/Kconfig                    |   13 +-
 drivers/net/fs_enet/fs_enet-main.c             |   67 +-
 drivers/net/fs_enet/fs_enet.h                  |    6 +
 drivers/net/fs_enet/mac-fec.c                  |   30 +-
 drivers/net/fs_enet/mii-fec.c                  |   13 +-
 drivers/rtc/Kconfig                            |   10 +
 drivers/rtc/Makefile                           |    1 +
 drivers/rtc/rtc-mpc5121.c                      |  408 ++++++
 31 files changed, 7146 insertions(+), 25 deletions(-)

[PATCH 01/12] fs_enet: Use defines to set driver tunables.

[Wolfgang Denk]

From: Piotr Ziecik <kosmo@semihalf.com>

Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: <netdev@vger.kernel.org>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: John Rigby <jcrigby@gmail.com>
---
 drivers/net/fs_enet/fs_enet-main.c |   19 ++++++++++++++-----
 1 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/drivers/net/fs_enet/fs_enet-main.c b/drivers/net/fs_enet/fs_enet-main.c
index a9cbc31..f996a1a 100644
--- a/drivers/net/fs_enet/fs_enet-main.c
+++ b/drivers/net/fs_enet/fs_enet-main.c
@@ -46,6 +46,15 @@
 
 #include "fs_enet.h"
 
+/* Driver tunables */
+
+#define ENET_RX_RING_SIZE	32
+#define ENET_TX_RING_SIZE	32
+#define ENET_RX_COPYBREAK	240
+
+#define ENET_USE_NAPI		1
+#define ENET_NAPI_WEIGHT	17
+
 /*************************************************/
 
 MODULE_AUTHOR("Pantelis Antoniou <panto@intracom.gr>");
@@ -1057,11 +1066,11 @@ static int __devinit fs_enet_probe(struct of_device *ofdev,
 		fpi->cp_command = *data;
 	}
 
-	fpi->rx_ring = 32;
-	fpi->tx_ring = 32;
-	fpi->rx_copybreak = 240;
-	fpi->use_napi = 1;
-	fpi->napi_weight = 17;
+	fpi->rx_ring = ENET_RX_RING_SIZE;
+	fpi->tx_ring = ENET_TX_RING_SIZE;
+	fpi->rx_copybreak = ENET_RX_COPYBREAK;
+	fpi->use_napi = ENET_USE_NAPI;
+	fpi->napi_weight = ENET_NAPI_WEIGHT;
 
 	ret = find_phy(ofdev->node, fpi);
 	if (ret)
-- 
1.6.0.6

[PATCH 02/12] fs_enet: Add MPC5121 FEC support.

[Wolfgang Denk]

From: John Rigby <jrigby@freescale.com>

Add support for MPC512x to fs_enet driver

    drivers/net/fs_enet/*
        Enable fs_enet driver to work 5121 FEC
        Enable it with CONFIG_FS_ENET_MPC5121_FEC

Signed-off-by: John Rigby <jrigby@freescale.com>
Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: <netdev@vger.kernel.org>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: John Rigby <jcrigby@gmail.com>
---
 arch/powerpc/include/asm/mpc5121_fec.h |  111 ++++++++++++++++++++++++++++++++
 drivers/net/fs_enet/Kconfig            |   10 ++-
 drivers/net/fs_enet/fs_enet-main.c     |    7 ++
 drivers/net/fs_enet/fs_enet.h          |    6 ++
 drivers/net/fs_enet/mac-fec.c          |   30 ++++++++-
 drivers/net/fs_enet/mii-fec.c          |    7 ++
 6 files changed, 166 insertions(+), 5 deletions(-)
 create mode 100644 arch/powerpc/include/asm/mpc5121_fec.h

diff --git a/arch/powerpc/include/asm/mpc5121_fec.h b/arch/powerpc/include/asm/mpc5121_fec.h
new file mode 100644
index 0000000..6bddf0b
--- /dev/null
+++ b/arch/powerpc/include/asm/mpc5121_fec.h
@@ -0,0 +1,111 @@
+/*
+ * Copyright (C) 2007,2008 Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * Author: John Rigby, <jrigby@freescale.com>
+ *
+ * Modified version of drivers/net/fec.h:
+ *
+ *	fec.h  --  Fast Ethernet Controller for Motorola ColdFire SoC
+ *		   processors.
+ *
+ *	(C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com)
+ *	(C) Copyright 2000-2001, Lineo (www.lineo.com)
+ *
+ * This is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef MPC5121_FEC_H
+#define MPC5121_FEC_H
+
+typedef struct fec {
+	u32 fec_reserved0;
+	u32 fec_ievent;			/* Interrupt event reg */
+	u32 fec_imask;			/* Interrupt mask reg */
+	u32 fec_reserved1;
+	u32 fec_r_des_active;		/* Receive descriptor reg */
+	u32 fec_x_des_active;		/* Transmit descriptor reg */
+	u32 fec_reserved2[3];
+	u32 fec_ecntrl;			/* Ethernet control reg */
+	u32 fec_reserved3[6];
+	u32 fec_mii_data;		/* MII manage frame reg */
+	u32 fec_mii_speed;		/* MII speed control reg */
+	u32 fec_reserved4[7];
+	u32 fec_mib_ctrlstat;		/* MIB control/status reg */
+	u32 fec_reserved5[7];
+	u32 fec_r_cntrl;		/* Receive control reg */
+	u32 fec_reserved6[15];
+	u32 fec_x_cntrl;		/* Transmit Control reg */
+	u32 fec_reserved7[7];
+	u32 fec_addr_low;		/* Low 32bits MAC address */
+	u32 fec_addr_high;		/* High 16bits MAC address */
+	u32 fec_opd;			/* Opcode + Pause duration */
+	u32 fec_reserved8[10];
+	u32 fec_hash_table_high;	/* High 32bits hash table */
+	u32 fec_hash_table_low;		/* Low 32bits hash table */
+	u32 fec_grp_hash_table_high;	/* High 32bits hash table */
+	u32 fec_grp_hash_table_low;	/* Low 32bits hash table */
+	u32 fec_reserved9[7];
+	u32 fec_x_wmrk;			/* FIFO transmit water mark */
+	u32 fec_reserved10;
+	u32 fec_r_bound;		/* FIFO receive bound reg */
+	u32 fec_r_fstart;		/* FIFO receive start reg */
+	u32 fec_reserved11[11];
+	u32 fec_r_des_start;		/* Receive descriptor ring */
+	u32 fec_x_des_start;		/* Transmit descriptor ring */
+	u32 fec_r_buff_size;		/* Maximum receive buff size */
+	u32 fec_reserved12[26];
+	u32 fec_dma_control;		/* DMA Endian and other ctrl */
+} fec_t;
+
+/*
+ *	Define the buffer descriptor structure.
+ */
+typedef struct bufdesc {
+	ushort	cbd_sc;			/* Control and status info */
+	ushort	cbd_datlen;		/* Data length */
+	uint	cbd_bufaddr;		/* Buffer address */
+} cbd_t;
+
+/*
+ *	The following definitions courtesy of commproc.h, which where
+ *	Copyright (c) 1997 Dan Malek (dmalek@jlc.net).
+ */
+#define BD_SC_WRAP		((ushort)0x2000)
+
+/*
+ * Buffer descriptor control/status used by Ethernet receive.
+ */
+#define BD_ENET_RX_EMPTY	((ushort)0x8000)
+#define BD_ENET_RX_WRAP		((ushort)0x2000)
+#define BD_ENET_RX_INTR		((ushort)0x1000)
+#define BD_ENET_RX_LAST		((ushort)0x0800)
+#define BD_ENET_RX_FIRST	((ushort)0x0400)
+#define BD_ENET_RX_MISS		((ushort)0x0100)
+#define BD_ENET_RX_LG		((ushort)0x0020)
+#define BD_ENET_RX_NO		((ushort)0x0010)
+#define BD_ENET_RX_SH		((ushort)0x0008)
+#define BD_ENET_RX_CR		((ushort)0x0004)
+#define BD_ENET_RX_OV		((ushort)0x0002)
+#define BD_ENET_RX_CL		((ushort)0x0001)
+#define BD_ENET_RX_STATS	((ushort)0x013f)	/* All status bits */
+
+/*
+ * Buffer descriptor control/status used by Ethernet transmit.
+ */
+#define BD_ENET_TX_READY	((ushort)0x8000)
+#define BD_ENET_TX_PAD		((ushort)0x4000)
+#define BD_ENET_TX_WRAP		((ushort)0x2000)
+#define BD_ENET_TX_INTR		((ushort)0x1000)
+#define BD_ENET_TX_LAST		((ushort)0x0800)
+#define BD_ENET_TX_TC		((ushort)0x0400)
+#define BD_ENET_TX_DEF		((ushort)0x0200)
+#define BD_ENET_TX_HB		((ushort)0x0100)
+#define BD_ENET_TX_LC		((ushort)0x0080)
+#define BD_ENET_TX_RL		((ushort)0x0040)
+#define BD_ENET_TX_UN		((ushort)0x0002)
+#define BD_ENET_TX_CSL		((ushort)0x0001)
+#define BD_ENET_TX_STATS	((ushort)0x03ff)	/* All status bits */
+
+#endif /* MPC5121_FEC_H */
diff --git a/drivers/net/fs_enet/Kconfig b/drivers/net/fs_enet/Kconfig
index 562ea68..fc073b5 100644
--- a/drivers/net/fs_enet/Kconfig
+++ b/drivers/net/fs_enet/Kconfig
@@ -1,9 +1,13 @@
 config FS_ENET
        tristate "Freescale Ethernet Driver"
-       depends on CPM1 || CPM2
+       depends on CPM1 || CPM2 || PPC_MPC512x
        select MII
        select PHYLIB
 
+config FS_ENET_MPC5121_FEC
+	def_bool y if (FS_ENET && PPC_MPC512x)
+	select FS_ENET_HAS_FEC
+
 config FS_ENET_HAS_SCC
 	bool "Chip has an SCC usable for ethernet"
 	depends on FS_ENET && (CPM1 || CPM2)
@@ -16,13 +20,13 @@ config FS_ENET_HAS_FCC
 
 config FS_ENET_HAS_FEC
 	bool "Chip has an FEC usable for ethernet"
-	depends on FS_ENET && CPM1
+	depends on FS_ENET && (CPM1 || FS_ENET_MPC5121_FEC)
 	select FS_ENET_MDIO_FEC
 	default y
 
 config FS_ENET_MDIO_FEC
 	tristate "MDIO driver for FEC"
-	depends on FS_ENET && CPM1
+	depends on FS_ENET && (CPM1 || FS_ENET_MPC5121_FEC)
 
 config FS_ENET_MDIO_FCC
 	tristate "MDIO driver for FCC"
diff --git a/drivers/net/fs_enet/fs_enet-main.c b/drivers/net/fs_enet/fs_enet-main.c
index f996a1a..4170d33 100644
--- a/drivers/net/fs_enet/fs_enet-main.c
+++ b/drivers/net/fs_enet/fs_enet-main.c
@@ -1183,11 +1183,18 @@ static struct of_device_id fs_enet_match[] = {
 	},
 #endif
 #ifdef CONFIG_FS_ENET_HAS_FEC
+#ifdef CONFIG_FS_ENET_MPC5121_FEC
+	{
+		.compatible = "fsl,mpc5121-fec",
+		.data = (void *)&fs_fec_ops,
+	},
+#else
 	{
 		.compatible = "fsl,pq1-fec-enet",
 		.data = (void *)&fs_fec_ops,
 	},
 #endif
+#endif
 	{}
 };
 
diff --git a/drivers/net/fs_enet/fs_enet.h b/drivers/net/fs_enet/fs_enet.h
index 85a4bab..5d8258e 100644
--- a/drivers/net/fs_enet/fs_enet.h
+++ b/drivers/net/fs_enet/fs_enet.h
@@ -13,7 +13,13 @@
 
 #ifdef CONFIG_CPM1
 #include <asm/cpm1.h>
+#endif
+
+#ifdef CONFIG_FS_ENET_MPC5121_FEC
+#include <asm/mpc5121_fec.h>
+#endif
 
+#if defined(CONFIG_CPM1) || defined(CONFIG_FS_ENET_MPC5121_FEC)
 struct fec_info {
 	fec_t __iomem *fecp;
 	u32 mii_speed;
diff --git a/drivers/net/fs_enet/mac-fec.c b/drivers/net/fs_enet/mac-fec.c
index 14e5753..b069088 100644
--- a/drivers/net/fs_enet/mac-fec.c
+++ b/drivers/net/fs_enet/mac-fec.c
@@ -44,6 +44,10 @@
 #include <asm/cpm1.h>
 #endif
 
+#ifdef CONFIG_FS_ENET_MPC5121_FEC
+#include <asm/mpc5121_fec.h>
+#endif
+
 #include "fs_enet.h"
 #include "fec.h"
 
@@ -285,7 +289,11 @@ static void restart(struct net_device *dev)
 	 * Set maximum receive buffer size.
 	 */
 	FW(fecp, r_buff_size, PKT_MAXBLR_SIZE);
+#ifdef CONFIG_FS_ENET_MPC5121_FEC
+	FW(fecp, r_cntrl, PKT_MAXBUF_SIZE << 16);
+#else
 	FW(fecp, r_hash, PKT_MAXBUF_SIZE);
+#endif
 
 	/* get physical address */
 	rx_bd_base_phys = fep->ring_mem_addr;
@@ -300,9 +308,14 @@ static void restart(struct net_device *dev)
 	fs_init_bds(dev);
 
 	/*
-	 * Enable big endian and don't care about SDMA FC.
+	 * Enable big endian.
 	 */
+#ifndef CONFIG_FS_ENET_MPC5121_FEC
+	/* Don't care about SDMA FC. */
 	FW(fecp, fun_code, 0x78000000);
+#else
+	FS(fecp, dma_control, 0xC0000000);
+#endif
 
 	/*
 	 * Set MII speed.
@@ -313,7 +326,9 @@ static void restart(struct net_device *dev)
 	 * Clear any outstanding interrupt.
 	 */
 	FW(fecp, ievent, 0xffc0);
+#ifndef CONFIG_FS_ENET_MPC5121_FEC
 	FW(fecp, ivec, (virq_to_hw(fep->interrupt) / 2) << 29);
+#endif
 
 	/*
 	 * adjust to speed (only for DUET & RMII)
@@ -344,8 +359,19 @@ static void restart(struct net_device *dev)
 	}
 #endif
 
+	/*
+	 * Enable MII
+	 */
+#ifdef CONFIG_FS_ENET_MPC5121_FEC
+	/*
+	 * Only set requested bit - do not touch maximum packet size
+	 * configured earlier.
+	 */
+	FS(fecp, r_cntrl, FEC_RCNTRL_MII_MODE);
+#else
+	FW(fecp, r_cntrl, FEC_RCNTRL_MII_MODE);
+#endif
 
-	FW(fecp, r_cntrl, FEC_RCNTRL_MII_MODE);	/* MII enable */
 	/*
 	 * adjust to duplex mode
 	 */
diff --git a/drivers/net/fs_enet/mii-fec.c b/drivers/net/fs_enet/mii-fec.c
index 28077cc..9d8bd97 100644
--- a/drivers/net/fs_enet/mii-fec.c
+++ b/drivers/net/fs_enet/mii-fec.c
@@ -32,6 +32,7 @@
 #include <linux/bitops.h>
 #include <linux/platform_device.h>
 #include <linux/of_platform.h>
+#include <linux/time.h>
 
 #include <asm/pgtable.h>
 #include <asm/irq.h>
@@ -211,9 +212,15 @@ static int fs_enet_mdio_remove(struct of_device *ofdev)
 }
 
 static struct of_device_id fs_enet_mdio_fec_match[] = {
+#ifdef CONFIG_FS_ENET_MPC5121_FEC
+	{
+		.compatible = "fsl,mpc5121-fec-mdio",
+	},
+#else
 	{
 		.compatible = "fsl,pq1-fec-mdio",
 	},
+#endif
 	{},
 };
 
-- 
1.6.0.6

[PATCH 03/12] fs_enet: Add FEC TX Alignment workaround for MPC5121.

[Wolfgang Denk]

From: John Rigby <jrigby@freescale.com>

The FEC on 5121 has problems with misaligned tx buffers.
The RM says any alignment is ok but empirical results
show that packet buffers ending in 0x1E will sometimes
hang the FEC.  Other bad alignment does not hang but will
cause silent TX failures resulting in about a 1% packet
loss as tested by ping -f from a remote host.

This patch is a work around that copies every tx packet
to an aligned skb before sending.

Signed-off-by: John Rigby <jrigby@freescale.com>
Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: <netdev@vger.kernel.org>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: John Rigby <jcrigby@gmail.com>
---
 drivers/net/fs_enet/Kconfig        |    3 ++
 drivers/net/fs_enet/fs_enet-main.c |   41 ++++++++++++++++++++++++++++++++++++
 drivers/net/fs_enet/mac-fec.c      |    2 +-
 3 files changed, 45 insertions(+), 1 deletions(-)

diff --git a/drivers/net/fs_enet/Kconfig b/drivers/net/fs_enet/Kconfig
index fc073b5..79afd07 100644
--- a/drivers/net/fs_enet/Kconfig
+++ b/drivers/net/fs_enet/Kconfig
@@ -8,6 +8,9 @@ config FS_ENET_MPC5121_FEC
 	def_bool y if (FS_ENET && PPC_MPC512x)
 	select FS_ENET_HAS_FEC
 
+config FS_ENET_FEC_TX_ALIGN_WORKAROUND
+	def_bool y if FS_ENET_MPC5121_FEC
+
 config FS_ENET_HAS_SCC
 	bool "Chip has an SCC usable for ethernet"
 	depends on FS_ENET && (CPM1 || CPM2)
diff --git a/drivers/net/fs_enet/fs_enet-main.c b/drivers/net/fs_enet/fs_enet-main.c
index 4170d33..c83ffc3 100644
--- a/drivers/net/fs_enet/fs_enet-main.c
+++ b/drivers/net/fs_enet/fs_enet-main.c
@@ -594,6 +594,37 @@ void fs_cleanup_bds(struct net_device *dev)
 
 /**********************************************************************************/
 
+#ifdef CONFIG_FS_ENET_FEC_TX_ALIGN_WORKAROUND
+static struct sk_buff *tx_skb_align_workaround(struct net_device *dev,
+							struct sk_buff *skb)
+{
+	struct sk_buff *new_skb;
+
+	/* Alloc new skb */
+	new_skb = dev_alloc_skb(ENET_RX_FRSIZE + 32);
+	if (!new_skb) {
+		printk(KERN_WARNING DRV_MODULE_NAME
+				": %s Memory squeeze, dropping tx packet.\n",
+								dev->name);
+		return NULL;
+	}
+
+	/* Make sure new skb is properly aligned */
+	skb_align(new_skb, 32);
+
+	/* Copy data to new skb ... */
+	skb_copy_from_linear_data(skb, new_skb->data, skb->len);
+	skb_put(new_skb, skb->len);
+
+	/* ... and free an old one */
+	dev_kfree_skb_any(skb);
+
+	return new_skb;
+}
+#else
+#define tx_skb_align_workaround(dev, skb) (skb)
+#endif
+
 static int fs_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
 {
 	struct fs_enet_private *fep = netdev_priv(dev);
@@ -602,6 +633,16 @@ static int fs_enet_start_xmit(struct sk_buff *skb, struct net_device *dev)
 	u16 sc;
 	unsigned long flags;
 
+	skb = tx_skb_align_workaround(dev, skb);
+	if (!skb) {
+		/*
+		 * We have lost packet due to memory allocation error in
+		 * tx_skb_align_workaround(). Hopefully original skb is still
+		 * valid, so try transmit it later.
+		 */
+		return NETDEV_TX_BUSY;
+	}
+
 	spin_lock_irqsave(&fep->tx_lock, flags);
 
 	/*
diff --git a/drivers/net/fs_enet/mac-fec.c b/drivers/net/fs_enet/mac-fec.c
index b069088..3e86498 100644
--- a/drivers/net/fs_enet/mac-fec.c
+++ b/drivers/net/fs_enet/mac-fec.c
@@ -311,7 +311,7 @@ static void restart(struct net_device *dev)
 	 * Enable big endian.
 	 */
 #ifndef CONFIG_FS_ENET_MPC5121_FEC
-	/* Don't care about SDMA FC. */
+	/* Don't care about SDMA Function Code. */
 	FW(fecp, fun_code, 0x78000000);
 #else
 	FS(fecp, dma_control, 0xC0000000);
-- 
1.6.0.6

[PATCH 04/12] mpc5121: Added reset module registers representation.

[Wolfgang Denk]

From: Piotr Ziecik <kosmo@semihalf.com>

Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: John Rigby <jcrigby@gmail.com>
---
 arch/powerpc/include/asm/mpc512x.h |   13 +++++++++++++
 1 files changed, 13 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/include/asm/mpc512x.h b/arch/powerpc/include/asm/mpc512x.h
index c48a165..ea50d8d 100644
--- a/arch/powerpc/include/asm/mpc512x.h
+++ b/arch/powerpc/include/asm/mpc512x.h
@@ -16,6 +16,19 @@
 #ifndef __ASM_POWERPC_MPC512x_H__
 #define __ASM_POWERPC_MPC512x_H__
 
+/* MPC512x Reset module registers */
+struct mpc512x_reset_module {
+	u32	rcwlr;	/* Reset Configuration Word Low Register */
+	u32	rcwhr;	/* Reset Configuration Word High Register */
+	u32	reserved1;
+	u32	reserved2;
+	u32	rsr;	/* Reset Status Register */
+	u32	rmr;	/* Reset Mode Register */
+	u32	rpr;	/* Reset Protection Register */
+	u32	rcr;	/* Reset Control Register */
+	u32	rcer;	/* Reset Control Enable Register */
+} __attribute__ ((__packed__));
+
 extern unsigned long mpc512x_find_ips_freq(struct device_node *node);
 
 #endif /* __ASM_POWERPC_MPC512x_H__ */
-- 
1.6.0.6

[PATCH 05/12] mpc5121ads: Added Reset Module node to DTS.

[Wolfgang Denk]

From: Piotr Ziecik <kosmo@semihalf.com>

Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: John Rigby <jcrigby@gmail.com>
---
 arch/powerpc/boot/dts/mpc5121ads.dts |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/boot/dts/mpc5121ads.dts b/arch/powerpc/boot/dts/mpc5121ads.dts
index c2b8dbf..1b83a9d 100644
--- a/arch/powerpc/boot/dts/mpc5121ads.dts
+++ b/arch/powerpc/boot/dts/mpc5121ads.dts
@@ -166,6 +166,11 @@
 			interrupt-parent = < &ipic >;
 		};
 
+		reset@e00 {	// Reset module
+			compatible = "fsl,mpc5121-reset";
+			reg = <0xe00 0x100>;
+		};
+
 		clock@f00 {	// Clock control
 			compatible = "fsl,mpc5121-clock";
 			reg = <0xf00 0x100>;
-- 
1.6.0.6

[PATCH 06/12] mpc5121: Added NAND Flash Controller driver.

[Wolfgang Denk]

From: Piotr Ziecik <kosmo@semihalf.com>

This patch adds NAND Flash Controller driver for MPC5121
revision 2. All device features, except hardware ECC and
power management, are supported.

Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: <linux-mtd@lists.infradead.org>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: John Rigby <jcrigby@gmail.com>
---
 arch/powerpc/include/asm/mpc5121_nfc.h       |  100 +++
 arch/powerpc/platforms/512x/mpc512x_shared.c |    1 +
 drivers/mtd/nand/Kconfig                     |    7 +
 drivers/mtd/nand/Makefile                    |    1 +
 drivers/mtd/nand/mpc5121_nfc.c               |  855 ++++++++++++++++++++++++++
 5 files changed, 964 insertions(+), 0 deletions(-)
 create mode 100644 arch/powerpc/include/asm/mpc5121_nfc.h
 create mode 100644 drivers/mtd/nand/mpc5121_nfc.c

diff --git a/arch/powerpc/include/asm/mpc5121_nfc.h b/arch/powerpc/include/asm/mpc5121_nfc.h
new file mode 100644
index 0000000..b96a5b9
--- /dev/null
+++ b/arch/powerpc/include/asm/mpc5121_nfc.h
@@ -0,0 +1,100 @@
+/*
+ * Copyright 2004-2008 Freescale Semiconductor, Inc.
+ * Copyright 2009 Semihalf.
+ *
+ * Approved as OSADL project by a majority of OSADL members and funded
+ * by OSADL membership fees in 2009;  for details see www.osadl.org.
+ *
+ * Based on original driver from Freescale Semiconductor
+ * written by John Rigby <jrigby@freescale.com> on basis
+ * of drivers/mtd/nand/mxc_nand.c. Reworked and extended by
+ * Piotr Ziecik <kosmo@semihalf.com>.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#ifndef MPC5121_NFC_H
+#define MPC5121_NFC_H
+
+/* Addresses for NFC MAIN RAM BUFFER areas */
+#define NFC_MAIN_AREA(n)	((n) *  0x200)
+
+/* Addresses for NFC SPARE BUFFER areas */
+#define NFC_SPARE_BUFFERS	8
+#define NFC_SPARE_LEN		0x40
+#define NFC_SPARE_AREA(n)	(0x1000 + ((n) * NFC_SPARE_LEN))
+
+/* MPC5121 NFC registers */
+#define NFC_BUF_ADDR		0x1E04
+#define NFC_FLASH_ADDR		0x1E06
+#define NFC_FLASH_CMD		0x1E08
+#define NFC_CONFIG		0x1E0A
+#define NFC_ECC_STATUS1		0x1E0C
+#define NFC_ECC_STATUS2		0x1E0E
+#define NFC_SPAS		0x1E10
+#define NFC_WRPROT		0x1E12
+#define NFC_NF_WRPRST		0x1E18
+#define NFC_CONFIG1		0x1E1A
+#define NFC_CONFIG2		0x1E1C
+#define NFC_UNLOCKSTART_BLK0	0x1E20
+#define NFC_UNLOCKEND_BLK0	0x1E22
+#define NFC_UNLOCKSTART_BLK1	0x1E24
+#define NFC_UNLOCKEND_BLK1	0x1E26
+#define NFC_UNLOCKSTART_BLK2	0x1E28
+#define NFC_UNLOCKEND_BLK2	0x1E2A
+#define NFC_UNLOCKSTART_BLK3	0x1E2C
+#define NFC_UNLOCKEND_BLK3	0x1E2E
+
+/* Bit Definitions: NFC_BUF_ADDR */
+#define NFC_RBA_MASK		(7 << 0)
+#define NFC_ACTIVE_CS_SHIFT	5
+#define NFC_ACTIVE_CS_MASK	(3 << NFC_ACTIVE_CS_SHIFT)
+
+/* Bit Definitions: NFC_CONFIG */
+#define NFC_BLS_UNLOCKED	(1 << 1)
+
+/* Bit Definitions: NFC_CONFIG1 */
+#define NFC_ECC_4BIT		(1 << 0)
+#define NFC_FULL_PAGE_DMA	(1 << 1)
+#define NFC_SPARE_ONLY		(1 << 2)
+#define NFC_ECC_ENABLE		(1 << 3)
+#define NFC_INT_MASK		(1 << 4)
+#define NFC_BIG_ENDIAN		(1 << 5)
+#define NFC_RESET		(1 << 6)
+#define NFC_CE			(1 << 7)
+#define NFC_ONE_CYCLE		(1 << 8)
+#define NFC_PPB_32		(0 << 9)
+#define NFC_PPB_64		(1 << 9)
+#define NFC_PPB_128		(2 << 9)
+#define NFC_PPB_256		(3 << 9)
+#define NFC_PPB_MASK		(3 << 9)
+#define NFC_FULL_PAGE_INT	(1 << 11)
+
+/* Bit Definitions: NFC_CONFIG2 */
+#define NFC_COMMAND		(1 << 0)
+#define NFC_ADDRESS		(1 << 1)
+#define NFC_INPUT		(1 << 2)
+#define NFC_OUTPUT		(1 << 3)
+#define NFC_ID			(1 << 4)
+#define NFC_STATUS		(1 << 5)
+#define NFC_CMD_FAIL		(1 << 15)
+#define NFC_INT			(1 << 15)
+
+/* Bit Definitions: NFC_WRPROT */
+#define NFC_WPC_LOCK_TIGHT	(1 << 0)
+#define NFC_WPC_LOCK		(1 << 1)
+#define NFC_WPC_UNLOCK		(1 << 2)
+
+#endif /* MPC5121_NFC_H */
diff --git a/arch/powerpc/platforms/512x/mpc512x_shared.c b/arch/powerpc/platforms/512x/mpc512x_shared.c
index d8cd579..7135d89 100644
--- a/arch/powerpc/platforms/512x/mpc512x_shared.c
+++ b/arch/powerpc/platforms/512x/mpc512x_shared.c
@@ -71,6 +71,7 @@ void __init mpc512x_init_IRQ(void)
 static struct of_device_id __initdata of_bus_ids[] = {
 	{ .compatible = "fsl,mpc5121-immr", },
 	{ .compatible = "fsl,mpc5121-localbus", },
+	{ .compatible = "fsl,mpc5121-nfc", },
 	{},
 };
 
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 890936d..fb0d1c4 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -413,6 +413,13 @@ config MTD_NAND_FSL_UPM
 	  Enables support for NAND Flash chips wired onto Freescale PowerPC
 	  processor localbus with User-Programmable Machine support.
 
+config MTD_NAND_MPC5121_NFC
+	tristate "MPC5121 built-in NAND Flash Controller support"
+	depends on PPC_MPC512x
+	help
+	  This enables the driver for the NAND flash controller on the
+	  MPC5121 SoC.
+
 config MTD_NAND_MXC
 	tristate "MXC NAND support"
 	depends on ARCH_MX2 || ARCH_MX3
diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
index d33860a..563e812 100644
--- a/drivers/mtd/nand/Makefile
+++ b/drivers/mtd/nand/Makefile
@@ -39,5 +39,6 @@ obj-$(CONFIG_MTD_NAND_SH_FLCTL)		+= sh_flctl.o
 obj-$(CONFIG_MTD_NAND_MXC)		+= mxc_nand.o
 obj-$(CONFIG_MTD_NAND_SOCRATES)		+= socrates_nand.o
 obj-$(CONFIG_MTD_NAND_TXX9NDFMC)	+= txx9ndfmc.o
+obj-$(CONFIG_MTD_NAND_MPC5121_NFC)	+= mpc5121_nfc.o
 
 nand-objs := nand_base.o nand_bbt.o
diff --git a/drivers/mtd/nand/mpc5121_nfc.c b/drivers/mtd/nand/mpc5121_nfc.c
new file mode 100644
index 0000000..a8da4db
--- /dev/null
+++ b/drivers/mtd/nand/mpc5121_nfc.c
@@ -0,0 +1,855 @@
+/*
+ * Copyright 2004-2008 Freescale Semiconductor, Inc.
+ * Copyright 2009 Semihalf.
+ *
+ * Based on original driver from Freescale Semiconductor
+ * written by John Rigby <jrigby@freescale.com> on basis
+ * of drivers/mtd/nand/mxc_nand.c. Reworked and extended
+ * Piotr Ziecik <kosmo@semihalf.com>.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand.h>
+#include <linux/mtd/partitions.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+
+#include <asm/mpc512x.h>
+#include <asm/mpc5121_nfc.h>
+
+#define	DRV_NAME		"mpc5121_nfc"
+#define	DRV_VERSION		"0.5"
+
+/* Timeouts */
+#define NFC_RESET_TIMEOUT	1000		/* 1 ms */
+#define NFC_TIMEOUT		(HZ / 10)	/* 1/10 s */
+
+struct mpc5121_nfc_prv {
+	struct mtd_info		mtd;
+	struct nand_chip	chip;
+	int			irq;
+	void __iomem		*regs;
+	struct clk		*clk;
+	wait_queue_head_t	irq_waitq;
+	uint			column;
+	int			spareonly;
+	void __iomem		*csreg;
+};
+
+static void mpc5121_nfc_done(struct mtd_info *mtd);
+
+#ifdef CONFIG_MTD_PARTITIONS
+static const char *mpc5121_nfc_pprobes[] = { "cmdlinepart", NULL };
+#endif
+
+/* Read NFC register */
+static inline u16 nfc_read(struct mtd_info *mtd, uint reg)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct mpc5121_nfc_prv *prv = chip->priv;
+
+	return in_be16(prv->regs + reg);
+}
+
+/* Write NFC register */
+static inline void nfc_write(struct mtd_info *mtd, uint reg, u16 val)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct mpc5121_nfc_prv *prv = chip->priv;
+
+	out_be16(prv->regs + reg, val);
+}
+
+/* Set bits in NFC register */
+static inline void nfc_set(struct mtd_info *mtd, uint reg, u16 bits)
+{
+	nfc_write(mtd, reg, nfc_read(mtd, reg) | bits);
+}
+
+/* Clear bits in NFC register */
+static inline void nfc_clear(struct mtd_info *mtd, uint reg, u16 bits)
+{
+	nfc_write(mtd, reg, nfc_read(mtd, reg) & ~bits);
+}
+
+/* Invoke address cycle */
+static inline void mpc5121_nfc_send_addr(struct mtd_info *mtd, u16 addr)
+{
+	nfc_write(mtd, NFC_FLASH_ADDR, addr);
+	nfc_write(mtd, NFC_CONFIG2, NFC_ADDRESS);
+	mpc5121_nfc_done(mtd);
+}
+
+/* Invoke command cycle */
+static inline void mpc5121_nfc_send_cmd(struct mtd_info *mtd, u16 cmd)
+{
+	nfc_write(mtd, NFC_FLASH_CMD, cmd);
+	nfc_write(mtd, NFC_CONFIG2, NFC_COMMAND);
+	mpc5121_nfc_done(mtd);
+}
+
+/* Send data from NFC buffers to NAND flash */
+static inline void mpc5121_nfc_send_prog_page(struct mtd_info *mtd)
+{
+	nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
+	nfc_write(mtd, NFC_CONFIG2, NFC_INPUT);
+	mpc5121_nfc_done(mtd);
+}
+
+/* Receive data from NAND flash */
+static inline void mpc5121_nfc_send_read_page(struct mtd_info *mtd)
+{
+	nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
+	nfc_write(mtd, NFC_CONFIG2, NFC_OUTPUT);
+	mpc5121_nfc_done(mtd);
+}
+
+/* Receive ID from NAND flash */
+static inline void mpc5121_nfc_send_read_id(struct mtd_info *mtd)
+{
+	nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
+	nfc_write(mtd, NFC_CONFIG2, NFC_ID);
+	mpc5121_nfc_done(mtd);
+}
+
+/* Receive status from NAND flash */
+static inline void mpc5121_nfc_send_read_status(struct mtd_info *mtd)
+{
+	nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
+	nfc_write(mtd, NFC_CONFIG2, NFC_STATUS);
+	mpc5121_nfc_done(mtd);
+}
+
+/* NFC interrupt handler */
+static irqreturn_t mpc5121_nfc_irq(int irq, void *data)
+{
+	struct mtd_info *mtd = data;
+	struct nand_chip *chip = mtd->priv;
+	struct mpc5121_nfc_prv *prv = chip->priv;
+
+	nfc_set(mtd, NFC_CONFIG1, NFC_INT_MASK);
+	wake_up(&prv->irq_waitq);
+
+	return IRQ_HANDLED;
+}
+
+/* Wait for operation complete */
+static void mpc5121_nfc_done(struct mtd_info *mtd)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct mpc5121_nfc_prv *prv = chip->priv;
+	int rv;
+
+	if ((nfc_read(mtd, NFC_CONFIG2) & NFC_INT) == 0) {
+		nfc_clear(mtd, NFC_CONFIG1, NFC_INT_MASK);
+		rv = wait_event_timeout(prv->irq_waitq,
+			(nfc_read(mtd, NFC_CONFIG2) & NFC_INT), NFC_TIMEOUT);
+
+		if (!rv)
+			printk(KERN_WARNING DRV_NAME
+				": Timeout while waiting for interrupt.\n");
+	}
+
+	nfc_clear(mtd, NFC_CONFIG2, NFC_INT);
+}
+
+/* Do address cycle(s) */
+static void mpc5121_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
+{
+	struct nand_chip *chip = mtd->priv;
+	u32 pagemask = chip->pagemask;
+
+	if (column != -1) {
+		mpc5121_nfc_send_addr(mtd, column);
+		if (mtd->writesize > 512)
+			mpc5121_nfc_send_addr(mtd, column >> 8);
+	}
+
+	if (page != -1) {
+		do {
+			mpc5121_nfc_send_addr(mtd, page & 0xFF);
+			page >>= 8;
+			pagemask >>= 8;
+		} while (pagemask);
+	}
+}
+
+/* Control chip select signals */
+static void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip)
+{
+	if (chip < 0) {
+		nfc_clear(mtd, NFC_CONFIG1, NFC_CE);
+		return;
+	}
+
+	nfc_clear(mtd, NFC_BUF_ADDR, NFC_ACTIVE_CS_MASK);
+	nfc_set(mtd, NFC_BUF_ADDR, (chip << NFC_ACTIVE_CS_SHIFT) &
+							NFC_ACTIVE_CS_MASK);
+	nfc_set(mtd, NFC_CONFIG1, NFC_CE);
+}
+
+/* Init external chip select logic on ADS5121 board */
+static int ads5121_chipselect_init(struct mtd_info *mtd)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct mpc5121_nfc_prv *prv = chip->priv;
+	struct device_node *dn;
+
+	dn = of_find_compatible_node(NULL, NULL, "fsl,mpc5121ads-cpld");
+	if (dn) {
+		prv->csreg = of_iomap(dn, 0);
+		of_node_put(dn);
+		if (!prv->csreg)
+			return -ENOMEM;
+
+		/* CPLD Register 9 controls NAND /CE Lines */
+		prv->csreg += 9;
+		return 0;
+	}
+
+	return -EINVAL;
+}
+
+/* Control chips select signal on ADS5121 board */
+static void ads5121_select_chip(struct mtd_info *mtd, int chip)
+{
+	struct nand_chip *nand = mtd->priv;
+	struct mpc5121_nfc_prv *prv = nand->priv;
+	u8 v;
+
+	v = in_8(prv->csreg);
+	v |= 0x0F;
+
+	if (chip >= 0) {
+		mpc5121_nfc_select_chip(mtd, 0);
+		v &= ~(1 << chip);
+	} else
+		mpc5121_nfc_select_chip(mtd, -1);
+
+	out_8(prv->csreg, v);
+}
+
+/* Read NAND Ready/Busy signal */
+static int mpc5121_nfc_dev_ready(struct mtd_info *mtd)
+{
+	/*
+	 * NFC handles ready/busy signal internally. Therefore, this function
+	 * always returns status as ready.
+	 */
+	return 1;
+}
+
+/* Write command to NAND flash */
+static void mpc5121_nfc_command(struct mtd_info *mtd, unsigned command,
+							int column, int page)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct mpc5121_nfc_prv *prv = chip->priv;
+
+	prv->column = (column >= 0) ? column : 0;
+	prv->spareonly = 0;
+
+	switch (command) {
+	case NAND_CMD_PAGEPROG:
+		mpc5121_nfc_send_prog_page(mtd);
+		break;
+	/*
+	 * NFC does not support sub-page reads and writes,
+	 * so emulate them using full page transfers.
+	 */
+	case NAND_CMD_READ0:
+		column = 0;
+		break;
+
+	case NAND_CMD_READ1:
+		prv->column += 256;
+		command = NAND_CMD_READ0;
+		column = 0;
+		break;
+
+	case NAND_CMD_READOOB:
+		prv->spareonly = 1;
+		command = NAND_CMD_READ0;
+		column = 0;
+		break;
+
+	case NAND_CMD_SEQIN:
+		mpc5121_nfc_command(mtd, NAND_CMD_READ0, column, page);
+		column = 0;
+		break;
+
+	case NAND_CMD_ERASE1:
+	case NAND_CMD_ERASE2:
+	case NAND_CMD_READID:
+	case NAND_CMD_STATUS:
+		break;
+
+	default:
+		return;
+	}
+
+	mpc5121_nfc_send_cmd(mtd, command);
+	mpc5121_nfc_addr_cycle(mtd, column, page);
+
+	switch (command) {
+	case NAND_CMD_READ0:
+		if (mtd->writesize > 512)
+			mpc5121_nfc_send_cmd(mtd, NAND_CMD_READSTART);
+		mpc5121_nfc_send_read_page(mtd);
+		break;
+
+	case NAND_CMD_READID:
+		mpc5121_nfc_send_read_id(mtd);
+		break;
+
+	case NAND_CMD_STATUS:
+		mpc5121_nfc_send_read_status(mtd);
+		if (chip->options & NAND_BUSWIDTH_16)
+			prv->column = 1;
+		else
+			prv->column = 0;
+		break;
+	}
+}
+
+/* Copy data from/to NFC spare buffers. */
+static void mpc5121_nfc_copy_spare(struct mtd_info *mtd, uint offset,
+						u8 *buffer, uint size, int wr)
+{
+	struct nand_chip *nand = mtd->priv;
+	struct mpc5121_nfc_prv *prv = nand->priv;
+	uint o, s, sbsize, blksize;
+
+	/*
+	 * NAND spare area is available through NFC spare buffers.
+	 * The NFC divides spare area into (page_size / 512) chunks.
+	 * Each chunk is placed into separate spare memory area, using
+	 * first (spare_size / num_of_chunks) bytes of the buffer.
+	 *
+	 * For NAND device in which the spare area is not divided fully
+	 * by the number of chunks, number of used bytes in each spare
+	 * buffer is rounded down to the nearest even number of bytes,
+	 * and all remaining bytes are added to the last used spare area.
+	 *
+	 * For more information read section 26.6.10 of MPC5121e
+	 * Microcontroller Reference Manual, Rev. 3.
+	 */
+
+	/* Calculate number of valid bytes in each spare buffer */
+	sbsize = (mtd->oobsize / (mtd->writesize / 512)) & ~1;
+
+	while (size) {
+		/* Calculate spare buffer number */
+		s = offset / sbsize;
+		if (s > NFC_SPARE_BUFFERS - 1)
+			s = NFC_SPARE_BUFFERS - 1;
+
+		/*
+		 * Calculate offset to requested data block in selected spare
+		 * buffer and its size.
+		 */
+		o = offset - (s * sbsize);
+		blksize = min(sbsize - o, size);
+
+		if (wr)
+			memcpy_toio(prv->regs + NFC_SPARE_AREA(s) + o,
+							buffer, blksize);
+		else
+			memcpy_fromio(buffer,
+				prv->regs + NFC_SPARE_AREA(s) + o, blksize);
+
+		buffer += blksize;
+		offset += blksize;
+		size -= blksize;
+	};
+}
+
+/* Copy data from/to NFC main and spare buffers */
+static void mpc5121_nfc_buf_copy(struct mtd_info *mtd, u_char *buf, int len,
+									int wr)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct mpc5121_nfc_prv *prv = chip->priv;
+	uint c = prv->column;
+	uint l;
+
+	/* Handle spare area access */
+	if (prv->spareonly || c >= mtd->writesize) {
+		/* Calculate offset from beginning of spare area */
+		if (c >= mtd->writesize)
+			c -= mtd->writesize;
+
+		prv->column += len;
+		mpc5121_nfc_copy_spare(mtd, c, buf, len, wr);
+		return;
+	}
+
+	/*
+	 * Handle main area access - limit copy length to prevent
+	 * crossing main/spare boundary.
+	 */
+	l = min((uint)len, mtd->writesize - c);
+	prv->column += l;
+
+	if (wr)
+		memcpy_toio(prv->regs + NFC_MAIN_AREA(0) + c, buf, l);
+	else
+		memcpy_fromio(buf, prv->regs + NFC_MAIN_AREA(0) + c, l);
+
+	/* Handle crossing main/spare boundary */
+	if (l != len) {
+		buf += l;
+		len -= l;
+		mpc5121_nfc_buf_copy(mtd, buf, len, wr);
+	}
+}
+
+/* Read data from NFC buffers */
+static void mpc5121_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len)
+{
+	mpc5121_nfc_buf_copy(mtd, buf, len, 0);
+}
+
+/* Write data to NFC buffers */
+static void mpc5121_nfc_write_buf(struct mtd_info *mtd,
+						const u_char *buf, int len)
+{
+	mpc5121_nfc_buf_copy(mtd, (u_char *)buf, len, 1);
+}
+
+/* Compare buffer with NAND flash */
+static int mpc5121_nfc_verify_buf(struct mtd_info *mtd,
+						const u_char *buf, int len)
+{
+	u_char tmp[256];
+	uint bsize;
+
+	while (len) {
+		bsize = min(len, 256);
+		mpc5121_nfc_read_buf(mtd, tmp, bsize);
+
+		if (memcmp(buf, tmp, bsize))
+			return 1;
+
+		buf += bsize;
+		len -= bsize;
+	}
+
+	return 0;
+}
+
+/* Read byte from NFC buffers */
+static u8 mpc5121_nfc_read_byte(struct mtd_info *mtd)
+{
+	u8 tmp;
+
+	mpc5121_nfc_read_buf(mtd, &tmp, sizeof(tmp));
+
+	return tmp;
+}
+
+/* Read word from NFC buffers */
+static u16 mpc5121_nfc_read_word(struct mtd_info *mtd)
+{
+	u16 tmp;
+
+	mpc5121_nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp));
+
+	return tmp;
+}
+
+/*
+ * Read NFC configuration from Reset Config Word
+ *
+ * NFC is configured during reset in basis of information stored
+ * in Reset Config Word. There is no other way to set NAND block
+ * size, spare size and bus width.
+ */
+static int mpc5121_nfc_read_hw_config(struct mtd_info *mtd)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct mpc512x_reset_module *rm;
+	struct device_node *rmnode;
+	uint rcw_pagesize = 0;
+	uint rcw_sparesize = 0;
+	uint rcw_width;
+	uint rcwh;
+	uint romloc, ps;
+
+	rmnode = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-reset");
+	if (!rmnode) {
+		printk(KERN_ERR DRV_NAME ": Missing 'fsl,mpc5121-reset' "
+						"node in device tree!\n");
+		return -ENODEV;
+	}
+
+	rm = of_iomap(rmnode, 0);
+	if (!rm) {
+		printk(KERN_ERR DRV_NAME
+					": Error mapping reset module node!\n");
+		return -EBUSY;
+	}
+
+	rcwh = in_be32(&rm->rcwhr);
+
+	/* Bit 6: NFC bus width */
+	rcw_width = ((rcwh >> 6) & 0x1) ? 2 : 1;
+
+	/* Bit 7: NFC Page/Spare size */
+	ps = (rcwh >> 7) & 0x1;
+
+	/* Bits [22:21]: ROM Location */
+	romloc = (rcwh >> 21) & 0x3;
+
+	/* Decode RCW bits */
+	switch ((ps << 2) | romloc) {
+	case 0x00:
+	case 0x01:
+		rcw_pagesize = 512;
+		rcw_sparesize = 16;
+		break;
+	case 0x02:
+	case 0x03:
+		rcw_pagesize = 4096;
+		rcw_sparesize = 128;
+		break;
+	case 0x04:
+	case 0x05:
+		rcw_pagesize = 2048;
+		rcw_sparesize = 64;
+		break;
+	case 0x06:
+	case 0x07:
+		rcw_pagesize = 4096;
+		rcw_sparesize = 218;
+		break;
+	}
+
+	mtd->writesize = rcw_pagesize;
+	mtd->oobsize = rcw_sparesize;
+	if (rcw_width == 2)
+		chip->options |= NAND_BUSWIDTH_16;
+
+	printk(KERN_NOTICE DRV_NAME ": Configured for "
+						"%u-bit NAND, page size %u "
+						"with %u spare.\n",
+						rcw_width * 8, rcw_pagesize,
+						rcw_sparesize);
+	iounmap(rm);
+	of_node_put(rmnode);
+	return 0;
+}
+
+/* Free driver resources */
+static void mpc5121_nfc_free(struct device *dev, struct mtd_info *mtd)
+{
+	struct nand_chip *chip = mtd->priv;
+	struct mpc5121_nfc_prv *prv = chip->priv;
+
+	if (prv->clk) {
+		clk_disable(prv->clk);
+		clk_put(prv->clk);
+	}
+
+	if (prv->csreg)
+		iounmap(prv->csreg);
+}
+
+static int __init mpc5121_nfc_probe(struct of_device *op,
+					const struct of_device_id *match)
+{
+	struct device_node *rootnode, *dn = op->node;
+	struct device *dev = &op->dev;
+	struct mpc5121_nfc_prv *prv;
+	struct resource res;
+	struct mtd_info *mtd;
+#ifdef CONFIG_MTD_PARTITIONS
+	struct mtd_partition *parts;
+#endif
+	struct nand_chip *chip;
+	unsigned long regs_paddr, regs_size;
+	const uint *chips_no;
+	int resettime = 0;
+	int retval = 0;
+	int rev, len;
+
+	/*
+	 * Check SoC revision. This driver supports only NFC
+	 * in MPC5121 revision 2.
+	 */
+	rev = (mfspr(SPRN_SVR) >> 4) & 0xF;
+	if (rev != 2) {
+		printk(KERN_ERR DRV_NAME
+				": SoC revision %u is not supported!\n", rev);
+		return -ENXIO;
+	}
+
+	prv = devm_kzalloc(dev, sizeof(*prv), GFP_KERNEL);
+	if (!prv) {
+		printk(KERN_ERR DRV_NAME ": Memory exhausted!\n");
+		return -ENOMEM;
+	}
+
+	mtd = &prv->mtd;
+	chip = &prv->chip;
+
+	mtd->priv = chip;
+	chip->priv = prv;
+
+	/* Read NFC configuration from Reset Config Word */
+	retval = mpc5121_nfc_read_hw_config(mtd);
+	if (retval) {
+		printk(KERN_ERR DRV_NAME ": Unable to read NFC config!\n");
+		return retval;
+	}
+
+	prv->irq = irq_of_parse_and_map(dn, 0);
+	if (prv->irq == NO_IRQ) {
+		printk(KERN_ERR DRV_NAME ": Error mapping IRQ!\n");
+		return -EINVAL;
+	}
+
+	retval = of_address_to_resource(dn, 0, &res);
+	if (retval) {
+		printk(KERN_ERR DRV_NAME ": Error parsing memory region!\n");
+		return retval;
+	}
+
+	chips_no = of_get_property(dn, "chips", &len);
+	if (!chips_no || len != sizeof(*chips_no)) {
+		printk(KERN_ERR DRV_NAME ": Invalid/missing 'chips' "
+								"property!\n");
+		return -EINVAL;
+	}
+
+	regs_paddr = res.start;
+	regs_size = res.end - res.start + 1;
+
+	if (!devm_request_mem_region(dev, regs_paddr, regs_size, DRV_NAME)) {
+		printk(KERN_ERR DRV_NAME ": Error requesting memory region!\n");
+		return -EBUSY;
+	}
+
+	prv->regs = devm_ioremap(dev, regs_paddr, regs_size);
+	if (!prv->regs) {
+		printk(KERN_ERR DRV_NAME ": Error mapping memory region!\n");
+		return -ENOMEM;
+	}
+
+	mtd->name = "MPC5121 NAND";
+	chip->dev_ready = mpc5121_nfc_dev_ready;
+	chip->cmdfunc = mpc5121_nfc_command;
+	chip->read_byte = mpc5121_nfc_read_byte;
+	chip->read_word = mpc5121_nfc_read_word;
+	chip->read_buf = mpc5121_nfc_read_buf;
+	chip->write_buf = mpc5121_nfc_write_buf;
+	chip->verify_buf = mpc5121_nfc_verify_buf;
+	chip->select_chip = mpc5121_nfc_select_chip;
+	chip->options = NAND_NO_AUTOINCR | NAND_USE_FLASH_BBT;
+	chip->ecc.mode = NAND_ECC_SOFT;
+
+	/* Support external chip-select logic on ADS5121 board */
+	rootnode = of_find_node_by_path("/");
+	if (of_device_is_compatible(rootnode, "fsl,mpc5121ads")) {
+		retval = ads5121_chipselect_init(mtd);
+		if (retval) {
+			printk(KERN_ERR DRV_NAME ": Chipselect init error!\n");
+			of_node_put(rootnode);
+			return retval;
+		}
+
+		chip->select_chip = ads5121_select_chip;
+	}
+	of_node_put(rootnode);
+
+	/* Enable NFC clock */
+	prv->clk = clk_get(dev, "nfc_clk");
+	if (!prv->clk) {
+		printk(KERN_ERR DRV_NAME ": Unable to acquire NFC clock!\n");
+		retval = -ENODEV;
+		goto error;
+	}
+
+	clk_enable(prv->clk);
+
+	/* Reset NAND Flash controller */
+	nfc_set(mtd, NFC_CONFIG1, NFC_RESET);
+	while (nfc_read(mtd, NFC_CONFIG1) & NFC_RESET) {
+		if (resettime++ >= NFC_RESET_TIMEOUT) {
+			printk(KERN_ERR DRV_NAME
+					": Timeout while resetting NFC!\n");
+			retval = -EINVAL;
+			goto error;
+		}
+
+		udelay(1);
+	}
+
+	/* Enable write to NFC memory */
+	nfc_write(mtd, NFC_CONFIG, NFC_BLS_UNLOCKED);
+
+	/* Enable write to all NAND pages */
+	nfc_write(mtd, NFC_UNLOCKSTART_BLK0, 0x0000);
+	nfc_write(mtd, NFC_UNLOCKEND_BLK0, 0xFFFF);
+	nfc_write(mtd, NFC_WRPROT, NFC_WPC_UNLOCK);
+
+	/*
+	 * Setup NFC:
+	 *	- Big Endian transfers,
+	 *	- Interrupt after full page read/write.
+	 */
+	nfc_write(mtd, NFC_CONFIG1, NFC_BIG_ENDIAN | NFC_INT_MASK |
+							NFC_FULL_PAGE_INT);
+
+	/* Set spare area size */
+	nfc_write(mtd, NFC_SPAS, mtd->oobsize >> 1);
+
+	init_waitqueue_head(&prv->irq_waitq);
+	retval = devm_request_irq(dev, prv->irq, &mpc5121_nfc_irq, 0, DRV_NAME,
+									mtd);
+	if (retval) {
+		printk(KERN_ERR DRV_NAME ": Error requesting IRQ!\n");
+		goto error;
+	}
+
+	/* Detect NAND chips */
+	if (nand_scan(mtd, *chips_no)) {
+		printk(KERN_ERR DRV_NAME ": NAND Flash not found !\n");
+		devm_free_irq(dev, prv->irq, mtd);
+		retval = -ENXIO;
+		goto error;
+	}
+
+	/* Set erase block size */
+	switch (mtd->erasesize / mtd->writesize) {
+	case 32:
+		nfc_set(mtd, NFC_CONFIG1, NFC_PPB_32);
+		break;
+
+	case 64:
+		nfc_set(mtd, NFC_CONFIG1, NFC_PPB_64);
+		break;
+
+	case 128:
+		nfc_set(mtd, NFC_CONFIG1, NFC_PPB_128);
+		break;
+
+	case 256:
+		nfc_set(mtd, NFC_CONFIG1, NFC_PPB_256);
+		break;
+
+	default:
+		printk(KERN_ERR DRV_NAME ": Unsupported NAND flash!\n");
+		devm_free_irq(dev, prv->irq, mtd);
+		retval = -ENXIO;
+		goto error;
+	}
+
+	dev_set_drvdata(dev, mtd);
+
+	/* Register device in MTD */
+#ifdef CONFIG_MTD_PARTITIONS
+	retval = parse_mtd_partitions(mtd, mpc5121_nfc_pprobes, &parts, 0);
+#ifdef CONFIG_MTD_OF_PARTS
+	if (retval == 0)
+		retval = of_mtd_parse_partitions(dev, dn, &parts);
+#endif
+	if (retval < 0) {
+		printk(KERN_ERR DRV_NAME ": Error parsing MTD partitions!\n");
+		devm_free_irq(dev, prv->irq, mtd);
+		retval = -EINVAL;
+		goto error;
+	}
+
+	if (retval > 0)
+		retval = add_mtd_partitions(mtd, parts, retval);
+	else
+#endif
+		retval = add_mtd_device(mtd);
+
+	if (retval) {
+		printk(KERN_ERR DRV_NAME ": Error adding MTD device!\n");
+		devm_free_irq(dev, prv->irq, mtd);
+		goto error;
+	}
+
+	return 0;
+error:
+	mpc5121_nfc_free(dev, mtd);
+	return retval;
+}
+
+static int __exit mpc5121_nfc_remove(struct of_device *op)
+{
+	struct device *dev = &op->dev;
+	struct mtd_info *mtd = dev_get_drvdata(dev);
+	struct nand_chip *chip = mtd->priv;
+	struct mpc5121_nfc_prv *prv = chip->priv;
+
+	nand_release(mtd);
+	devm_free_irq(dev, prv->irq, mtd);
+	mpc5121_nfc_free(dev, mtd);
+
+	return 0;
+}
+
+static struct of_device_id mpc5121_nfc_match[] = {
+	{ .compatible = "fsl,mpc5121-nfc", },
+	{},
+};
+
+static struct of_platform_driver mpc5121_nfc_driver = {
+	.owner		= THIS_MODULE,
+	.name		= DRV_NAME,
+	.match_table	= mpc5121_nfc_match,
+	.probe		= mpc5121_nfc_probe,
+	.remove		= __exit_p(mpc5121_nfc_remove),
+	.suspend	= NULL,
+	.resume		= NULL,
+	.driver		= {
+		.name	= DRV_NAME,
+		.owner	= THIS_MODULE,
+	},
+};
+
+static int __init mpc5121_nfc_init(void)
+{
+	if (of_register_platform_driver(&mpc5121_nfc_driver) != 0) {
+		printk(KERN_ERR DRV_NAME ": Driver register failed!\n");
+		return -ENODEV;
+	}
+	return 0;
+}
+
+static void __exit mpc5121_nfc_cleanup(void)
+{
+	of_unregister_platform_driver(&mpc5121_nfc_driver);
+}
+
+module_init(mpc5121_nfc_init);
+module_exit(mpc5121_nfc_cleanup);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("MPC5121 NAND MTD driver");
+MODULE_LICENSE("GPL");
+MODULE_VERSION(DRV_VERSION);
-- 
1.6.0.6

[PATCH 07/12] mpc5121ads: Clean up and fix NAND description in mpc5121ads DTS.

[Wolfgang Denk]

From: Piotr Ziecik <kosmo@semihalf.com>

- Removed unused properties.
- Corrected NAND flash chip size.

Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: John Rigby <jcrigby@gmail.com>
---
 arch/powerpc/boot/dts/mpc5121ads.dts |   13 ++++---------
 1 files changed, 4 insertions(+), 9 deletions(-)

diff --git a/arch/powerpc/boot/dts/mpc5121ads.dts b/arch/powerpc/boot/dts/mpc5121ads.dts
index 1b83a9d..93fe12a 100644
--- a/arch/powerpc/boot/dts/mpc5121ads.dts
+++ b/arch/powerpc/boot/dts/mpc5121ads.dts
@@ -62,17 +62,12 @@
 		interrupt-parent = < &ipic >;
 		#address-cells = <1>;
 		#size-cells = <1>;
-		bank-width = <1>;
 		// ADS has two Hynix 512MB Nand flash chips in a single
-		// stacked package .
+		// stacked package.
 		chips = <2>;
-		nand0@0 {
-			label = "nand0";
-			reg = <0x00000000 0x02000000>; 	// first 32 MB of chip 0
-		};
-		nand1@20000000 {
-			label = "nand1";
-			reg = <0x20000000 0x02000000>; 	// first 32 MB of chip 1
+		nand@0 {
+			label = "nand";
+			reg = <0x00000000 0x40000000>;	// 512MB + 512MB
 		};
 	};
 
-- 
1.6.0.6

[PATCH 08/12] mpc5121: Added I2C support.

[Wolfgang Denk]

From: Piotr Ziecik <kosmo@semihalf.com>

- Enabled I2C interrupts on MPC5121.
- Updated Kconfig for i2c-mpc driver.

Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: <linux-i2c@vger.kernel.org>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: John Rigby <jcrigby@gmail.com>
---
 arch/powerpc/platforms/512x/mpc5121_ads.c    |    2 ++
 arch/powerpc/platforms/512x/mpc512x.h        |    1 +
 arch/powerpc/platforms/512x/mpc512x_shared.c |   24 ++++++++++++++++++++++++
 drivers/i2c/busses/Kconfig                   |    9 +++++----
 4 files changed, 32 insertions(+), 4 deletions(-)

diff --git a/arch/powerpc/platforms/512x/mpc5121_ads.c b/arch/powerpc/platforms/512x/mpc5121_ads.c
index 441abc4..a8976b4 100644
--- a/arch/powerpc/platforms/512x/mpc5121_ads.c
+++ b/arch/powerpc/platforms/512x/mpc5121_ads.c
@@ -42,6 +42,8 @@ static void __init mpc5121_ads_setup_arch(void)
 	for_each_compatible_node(np, "pci", "fsl,mpc5121-pci")
 		mpc83xx_add_bridge(np);
 #endif
+
+	mpc512x_init_i2c();
 }
 
 static void __init mpc5121_ads_init_IRQ(void)
diff --git a/arch/powerpc/platforms/512x/mpc512x.h b/arch/powerpc/platforms/512x/mpc512x.h
index 9c03693..f4db8a7 100644
--- a/arch/powerpc/platforms/512x/mpc512x.h
+++ b/arch/powerpc/platforms/512x/mpc512x.h
@@ -13,5 +13,6 @@
 #define __MPC512X_H__
 extern unsigned long mpc512x_find_ips_freq(struct device_node *node);
 extern void __init mpc512x_init_IRQ(void);
+extern void __init mpc512x_init_i2c(void);
 void __init mpc512x_declare_of_platform_devices(void);
 #endif				/* __MPC512X_H__ */
diff --git a/arch/powerpc/platforms/512x/mpc512x_shared.c b/arch/powerpc/platforms/512x/mpc512x_shared.c
index 7135d89..b776e45 100644
--- a/arch/powerpc/platforms/512x/mpc512x_shared.c
+++ b/arch/powerpc/platforms/512x/mpc512x_shared.c
@@ -65,6 +65,30 @@ void __init mpc512x_init_IRQ(void)
 	ipic_set_default_priority();
 }
 
+void __init mpc512x_init_i2c(void)
+{
+	struct device_node *np;
+	void __iomem *i2cctl;
+
+	/* Enable I2C interrupts */
+	np = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-i2c-ctrl");
+	if (np) {
+		i2cctl = of_iomap(np, 0);
+		if (i2cctl) {
+			/*
+			 * Set interrupt enable bits:
+			 *  - I2C-0: bit 24,
+			 *  - I2C-1: bit 26,
+			 *  - I2C-2: bit 28.
+			 */
+			out_be32(i2cctl, 0x15000000);
+			iounmap(i2cctl);
+		}
+
+		of_node_put(np);
+	}
+}
+
 /*
  * Nodes to do bus probe on, soc and localbus
  */
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index a48c8ae..57ed637 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -391,13 +391,14 @@ config I2C_IXP2000
 	  instead.
 
 config I2C_MPC
-	tristate "MPC107/824x/85xx/52xx/86xx"
+	tristate "MPC107/824x/85xx/512x/52xx/86xx"
 	depends on PPC32
 	help
 	  If you say yes to this option, support will be included for the
-	  built-in I2C interface on the MPC107/Tsi107/MPC8240/MPC8245 and
-	  MPC85xx/MPC8641 family processors. The driver may also work on 52xx
-	  family processors, though interrupts are known not to work.
+	  built-in I2C interface on the MPC107/Tsi107/MPC8240/MPC8245,
+	  MPC85xx/MPC8641 and MPC512x family processors. The driver may
+	  also work on 52xx family processors, though interrupts are known
+	  not to work.
 
 	  This driver can also be built as a module.  If so, the module
 	  will be called i2c-mpc.
-- 
1.6.0.6

[PATCH 09/12] mpc5121ads: Added I2C RTC node to mpc5121ads DTS.

[Wolfgang Denk]

From: Piotr Ziecik <kosmo@semihalf.com>

Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: John Rigby <jcrigby@gmail.com>
---
 arch/powerpc/boot/dts/mpc5121ads.dts |    5 +++++
 1 files changed, 5 insertions(+), 0 deletions(-)

diff --git a/arch/powerpc/boot/dts/mpc5121ads.dts b/arch/powerpc/boot/dts/mpc5121ads.dts
index 93fe12a..c2d9de9 100644
--- a/arch/powerpc/boot/dts/mpc5121ads.dts
+++ b/arch/powerpc/boot/dts/mpc5121ads.dts
@@ -210,6 +210,11 @@
 			interrupts = <9 0x8>;
 			interrupt-parent = < &ipic >;
 			fsl5200-clocking;
+
+			rtc@68 {
+				compatible = "stm,m41t80";
+				reg = <0x68>;
+			};
 		};
 
 		i2c@1720 {
-- 
1.6.0.6

[PATCH 10/12] mpc5121: Add MPC5121 Real time clock driver.

[Wolfgang Denk]

From: John Rigby <jrigby@freescale.com>

Based on Domen Puncer's rtc driver for 5200 posted to
the ppclinux mailing list:
	http://patchwork.ozlabs.org/linuxppc-embedded/patch?id=11675
but never commited anywhere.

Changes to Domen's original:

    Changed filenames/routine names from mpc5200* to mpc5121*
    Changed match to only care about compatible and use "fsl,"
    convention for compatible.

    Make alarms more sane by dealing with lack of second alarm resolution.

    Deal with the fact that most of the 5121 rtc registers are not persistent
    across a reset even with a battery attached:

	Use actual_time register for time keeping
	and target_time register as an offset to linux time

	The target_time register would normally be used for hibernation
	but hibernation does not work on current silicon

Signed-off-by: John Rigby <jrigby@freescale.com>
Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: <rtc-linux@googlegroups.com>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: John Rigby <jcrigby@gmail.com>
---
 drivers/rtc/Kconfig       |   10 +
 drivers/rtc/Makefile      |    1 +
 drivers/rtc/rtc-mpc5121.c |  408 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 419 insertions(+), 0 deletions(-)
 create mode 100644 drivers/rtc/rtc-mpc5121.c

diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 4e9851f..900d5b8 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -750,4 +750,14 @@ config RTC_DRV_PS3
 	  This driver can also be built as a module. If so, the module
 	  will be called rtc-ps3.
 
+config RTC_DRV_MPC5121
+	tristate "Freescale MPC5121 built-in RTC"
+	depends on RTC_CLASS
+	help
+	  If you say yes here you will get support for the
+	  built-in RTC MPC5121.
+
+	  This driver can also be built as a module. If so, the module
+	  will be called rtc-mpc5121.
+
 endif # RTC_CLASS
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index 6c0639a..8c6d6a7 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -51,6 +51,7 @@ obj-$(CONFIG_RTC_DRV_STARFIRE)	+= rtc-starfire.o
 obj-$(CONFIG_RTC_DRV_MAX6900)	+= rtc-max6900.o
 obj-$(CONFIG_RTC_DRV_MAX6902)	+= rtc-max6902.o
 obj-$(CONFIG_RTC_DRV_MV)	+= rtc-mv.o
+obj-$(CONFIG_RTC_DRV_MPC5121)	+= rtc-mpc5121.o
 obj-$(CONFIG_RTC_DRV_OMAP)	+= rtc-omap.o
 obj-$(CONFIG_RTC_DRV_PCF8563)	+= rtc-pcf8563.o
 obj-$(CONFIG_RTC_DRV_PCF8583)	+= rtc-pcf8583.o
diff --git a/drivers/rtc/rtc-mpc5121.c b/drivers/rtc/rtc-mpc5121.c
new file mode 100644
index 0000000..63460cb
--- /dev/null
+++ b/drivers/rtc/rtc-mpc5121.c
@@ -0,0 +1,408 @@
+/*
+ * Real-time clock driver for MPC5121
+ *
+ * Copyright 2007, Domen Puncer <domen.puncer@telargo.com>
+ * Copyright 2008, Freescale Semiconductor, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * History:
+ *
+ * Based on mpc5200_rtc.c written by Domen Puncer <domen.puncer@telargo.com>
+ *   posted to linuxppc-embedded mailing list:
+ *     http://patchwork.ozlabs.org/linuxppc-embedded/patch?id=11675
+ *   but never committed to any public tree.
+ *
+ * Author: John Rigby <jrigby@freescale.com>
+ *   Converted to 5121 rtc driver.
+ *
+ *   Make alarms more sane by dealing with lack of second alarm resolution.
+ *
+ *   Use actual_time time register for time keeping since it is persistent
+ *   and the normal rtc registers are not.  Use target_time register as an
+ *   offset to linux time.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/rtc.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+#include <linux/io.h>
+
+struct mpc5121_rtc_regs {
+	u8 set_time;		/* RTC + 0x00 */
+	u8 hour_set;		/* RTC + 0x01 */
+	u8 minute_set;		/* RTC + 0x02 */
+	u8 second_set;		/* RTC + 0x03 */
+
+	u8 set_date;		/* RTC + 0x04 */
+	u8 month_set;		/* RTC + 0x05 */
+	u8 weekday_set;		/* RTC + 0x06 */
+	u8 date_set;		/* RTC + 0x07 */
+
+	u8 write_sw;		/* RTC + 0x08 */
+	u8 sw_set;		/* RTC + 0x09 */
+	u16 year_set;		/* RTC + 0x0a */
+
+	u8 alm_enable;		/* RTC + 0x0c */
+	u8 alm_hour_set;	/* RTC + 0x0d */
+	u8 alm_min_set;		/* RTC + 0x0e */
+	u8 int_enable;		/* RTC + 0x0f */
+
+	u8 reserved1;
+	u8 hour;		/* RTC + 0x11 */
+	u8 minute;		/* RTC + 0x12 */
+	u8 second;		/* RTC + 0x13 */
+
+	u8 month;		/* RTC + 0x14 */
+	u8 wday_mday;		/* RTC + 0x15 */
+	u16 year;		/* RTC + 0x16 */
+
+	u8 int_alm;		/* RTC + 0x18 */
+	u8 int_sw;		/* RTC + 0x19 */
+	u8 alm_status;		/* RTC + 0x1a */
+	u8 sw_minute;		/* RTC + 0x1b */
+
+	u8 bus_error_1;		/* RTC + 0x1c */
+	u8 int_day;		/* RTC + 0x1d */
+	u8 int_min;		/* RTC + 0x1e */
+	u8 int_sec;		/* RTC + 0x1f */
+
+	/*
+	 * target_time:
+	 *	intended to be used for hibernation but hibernation
+	 *	does not work on silicon rev 1.5 so use it for non-volatile
+	 *	storage of offset between the actual_time register and linux
+	 *	time
+	 */
+	u32 target_time;	/* RTC + 0x20 */
+	/*
+	 * actual_time:
+	 * 	readonly time since VBAT_RTC was last connected
+	 */
+	u32 actual_time;	/* RTC + 0x24 */
+	u32 keep_alive;		/* RTC + 0x28 */
+};
+
+struct mpc5121_rtc_data {
+	unsigned irq;
+	unsigned irq_periodic;
+	struct mpc5121_rtc_regs __iomem *regs;
+	struct rtc_device *rtc;
+	struct rtc_wkalrm wkalarm;
+};
+
+/*
+ * Update second/minute/hour registers.
+ *
+ * This is just so alarm will work.
+ */
+static void mpc5121_rtc_update_smh(struct mpc5121_rtc_regs __iomem *regs,
+	struct rtc_time *tm)
+{
+	out_8(&regs->second_set, tm->tm_sec);
+	out_8(&regs->minute_set, tm->tm_min);
+	out_8(&regs->hour_set, tm->tm_hour);
+
+	/* set time sequence */
+	out_8(&regs->set_time, 0x1);
+	out_8(&regs->set_time, 0x3);
+	out_8(&regs->set_time, 0x1);
+	out_8(&regs->set_time, 0x0);
+}
+
+static int mpc5121_rtc_read_time(struct device *dev, struct rtc_time *tm)
+{
+	struct mpc5121_rtc_data *rtc = dev_get_drvdata(dev);
+	struct mpc5121_rtc_regs __iomem *regs = rtc->regs;
+	unsigned long now;
+
+	/*
+	 * linux time is actual_time plus the offset saved in target_time
+	 */
+	now = in_be32(&regs->actual_time) + in_be32(&regs->target_time);
+
+	rtc_time_to_tm(now, tm);
+
+	/*
+	 * update second minute hour registers
+	 * so alarms will work
+	 */
+	mpc5121_rtc_update_smh(regs, tm);
+
+	return 0;
+}
+
+static int mpc5121_rtc_set_time(struct device *dev, struct rtc_time *tm)
+{
+	struct mpc5121_rtc_data *rtc = dev_get_drvdata(dev);
+	struct mpc5121_rtc_regs __iomem *regs = rtc->regs;
+	int ret;
+	unsigned long now;
+
+
+	/*
+	 * The actual_time register is read only so we write the offset
+	 * between it and linux time to the target_time register.
+	 */
+	ret = rtc_tm_to_time(tm, &now);
+	if (ret == 0)
+		out_be32(&regs->target_time, now - in_be32(&regs->actual_time));
+
+	/*
+	 * update second minute hour registers
+	 * so alarms will work
+	 */
+	mpc5121_rtc_update_smh(regs, tm);
+
+	return 0;
+}
+
+static int mpc5121_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
+{
+	struct mpc5121_rtc_data *rtc = dev_get_drvdata(dev);
+	struct mpc5121_rtc_regs __iomem *regs = rtc->regs;
+
+	*alarm = rtc->wkalarm;
+
+	alarm->pending = in_8(&regs->alm_status);
+
+	return 0;
+}
+
+static int mpc5121_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
+{
+	struct mpc5121_rtc_data *rtc = dev_get_drvdata(dev);
+	struct mpc5121_rtc_regs __iomem *regs = rtc->regs;
+
+	/*
+	 * the alarm has no seconds so deal with it
+	 */
+	if (alarm->time.tm_sec) {
+		alarm->time.tm_sec = 0;
+		alarm->time.tm_min++;
+		if (alarm->time.tm_min >= 60) {
+			alarm->time.tm_min = 0;
+			alarm->time.tm_hour++;
+			if (alarm->time.tm_hour >= 24)
+				alarm->time.tm_hour = 0;
+		}
+	}
+
+	alarm->time.tm_mday = -1;
+	alarm->time.tm_mon = -1;
+	alarm->time.tm_year = -1;
+
+	out_8(&regs->alm_min_set, alarm->time.tm_min);
+	out_8(&regs->alm_hour_set, alarm->time.tm_hour);
+
+	out_8(&regs->alm_enable, alarm->enabled);
+
+	rtc->wkalarm = *alarm;
+	return 0;
+}
+
+static irqreturn_t mpc5121_rtc_handler(int irq, void *dev)
+{
+	struct mpc5121_rtc_data *rtc = dev_get_drvdata((struct device *)dev);
+	struct mpc5121_rtc_regs __iomem *regs = rtc->regs;
+
+	if (in_8(&regs->int_alm)) {
+		/* acknowledge and clear status */
+		out_8(&regs->int_alm, 1);
+		out_8(&regs->alm_status, 1);
+
+		rtc_update_irq(rtc->rtc, 1, RTC_IRQF | RTC_AF);
+		return IRQ_HANDLED;
+	}
+
+	return IRQ_NONE;
+}
+
+static irqreturn_t mpc5121_rtc_handler_upd(int irq, void *dev)
+{
+	struct mpc5121_rtc_data *rtc = dev_get_drvdata((struct device *)dev);
+	struct mpc5121_rtc_regs __iomem *regs = rtc->regs;
+
+	if (in_8(&regs->int_sec) && (in_8(&regs->int_enable) & 0x1)) {
+		/* acknowledge */
+		out_8(&regs->int_sec, 1);
+
+		rtc_update_irq(rtc->rtc, 1, RTC_IRQF | RTC_UF);
+		return IRQ_HANDLED;
+	}
+
+	return IRQ_NONE;
+}
+
+static int mpc5121_rtc_ioctl(struct device *dev, unsigned int cmd,
+							unsigned long arg)
+{
+	struct mpc5121_rtc_data *rtc = dev_get_drvdata(dev);
+	struct mpc5121_rtc_regs __iomem *regs = rtc->regs;
+
+	switch (cmd) {
+		/* alarm interrupt */
+	case RTC_AIE_ON:
+		out_8(&regs->alm_enable, 1);
+		rtc->wkalarm.enabled = 1;
+		break;
+	case RTC_AIE_OFF:
+		out_8(&regs->alm_enable, 0);
+		rtc->wkalarm.enabled = 0;
+		break;
+
+		/* update interrupt */
+	case RTC_UIE_ON:
+		out_8(&regs->int_enable,
+				(in_8(&regs->int_enable) & ~0x8) | 0x1);
+		break;
+	case RTC_UIE_OFF:
+		out_8(&regs->int_enable, in_8(&regs->int_enable) & ~0x1);
+		break;
+
+		/* no periodic interrupts */
+	case RTC_IRQP_READ:
+	case RTC_IRQP_SET:
+		return -ENOTTY;
+
+	default:
+		return -ENOIOCTLCMD;
+	}
+	return 0;
+}
+
+static const struct rtc_class_ops mpc5121_rtc_ops = {
+	.read_time = mpc5121_rtc_read_time,
+	.set_time = mpc5121_rtc_set_time,
+	.read_alarm = mpc5121_rtc_read_alarm,
+	.set_alarm = mpc5121_rtc_set_alarm,
+	.ioctl = mpc5121_rtc_ioctl,
+};
+
+static int __devinit mpc5121_rtc_probe(struct of_device *op,
+					const struct of_device_id *match)
+{
+	struct mpc5121_rtc_data *rtc;
+	int err = 0;
+	u32 ka;
+
+	rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
+	if (!rtc) {
+		err = -ENOMEM;
+		goto out;
+	}
+
+	rtc->regs = of_iomap(op->node, 0);
+
+	if (!rtc->regs) {
+		printk(KERN_ERR "%s: couldn't map io space\n", __func__);
+		err = -ENOSYS;
+		goto out_free;
+	}
+
+	device_init_wakeup(&op->dev, 1);
+
+	rtc->rtc = rtc_device_register("mpc5121-rtc", &op->dev,
+						&mpc5121_rtc_ops, THIS_MODULE);
+	if (IS_ERR(rtc->rtc)) {
+		err = PTR_ERR(rtc->rtc);
+		goto out_unmap;
+	}
+
+	dev_set_drvdata(&op->dev, rtc);
+
+	rtc->irq = irq_of_parse_and_map(op->node, 1);
+	err = request_irq(rtc->irq, mpc5121_rtc_handler, IRQF_DISABLED,
+						"mpc5121-rtc", &op->dev);
+	if (err) {
+		printk(KERN_ERR "%s: could not request irq: %i\n",
+							__func__, rtc->irq);
+		goto out_dispose;
+	}
+
+	rtc->irq_periodic = irq_of_parse_and_map(op->node, 0);
+	err = request_irq(rtc->irq_periodic, mpc5121_rtc_handler_upd,
+				 IRQF_DISABLED, "mpc5121-rtc_upd", &op->dev);
+	if (err) {
+		printk(KERN_ERR "%s: could not request irq: %i\n",
+						__func__, rtc->irq_periodic);
+		goto out_dispose2;
+	}
+
+	ka = in_be32(&rtc->regs->keep_alive);
+	if (ka & 0x02) {
+		printk(KERN_WARNING
+			"mpc5121-rtc: Battery or oscillator failure!\n");
+		out_be32(&rtc->regs->keep_alive, ka);
+	}
+
+	goto out;
+
+out_dispose2:
+	irq_dispose_mapping(rtc->irq_periodic);
+	free_irq(rtc->irq, &op->dev);
+out_dispose:
+	irq_dispose_mapping(rtc->irq);
+out_unmap:
+	iounmap(rtc->regs);
+out_free:
+	kfree(rtc);
+out:
+	return err;
+}
+
+static int __devexit mpc5121_rtc_remove(struct of_device *op)
+{
+	struct mpc5121_rtc_data *rtc = dev_get_drvdata(&op->dev);
+	struct mpc5121_rtc_regs __iomem *regs = rtc->regs;
+
+	/* disable interrupt, so there are no nasty surprises */
+	out_8(&regs->alm_enable, 0);
+	out_8(&regs->int_enable, in_8(&regs->int_enable) & ~0x1);
+
+	rtc_device_unregister(rtc->rtc);
+	iounmap(rtc->regs);
+	free_irq(rtc->irq, &op->dev);
+	free_irq(rtc->irq_periodic, &op->dev);
+	irq_dispose_mapping(rtc->irq);
+	irq_dispose_mapping(rtc->irq_periodic);
+	dev_set_drvdata(&op->dev, NULL);
+	kfree(rtc);
+
+	return 0;
+}
+
+static struct of_device_id mpc5121_rtc_match[] = {
+	{ .compatible = "fsl,mpc5121-rtc", },
+	{},
+};
+
+static struct of_platform_driver mpc5121_rtc_driver = {
+	.owner = THIS_MODULE,
+	.name = "mpc5121-rtc",
+	.match_table = mpc5121_rtc_match,
+	.probe = mpc5121_rtc_probe,
+	.remove = mpc5121_rtc_remove,
+};
+
+static int __init mpc5121_rtc_init(void)
+{
+	return of_register_platform_driver(&mpc5121_rtc_driver);
+}
+
+static void __exit mpc5121_rtc_exit(void)
+{
+	of_unregister_platform_driver(&mpc5121_rtc_driver);
+}
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("John Rigby <jrigby@freescale.com>");
+
+module_init(mpc5121_rtc_init);
+module_exit(mpc5121_rtc_exit);
-- 
1.6.0.6

[PATCH 11/12] mpc5121: Added MPC512x DMA driver.

[Wolfgang Denk]

From: Piotr Ziecik <kosmo@semihalf.com>

This patch adds initial version of MPC512x DMA driver.
Only memory to memory transfers are currenly supported.

Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: John Rigby <jcrigby@gmail.com>
---
 arch/powerpc/boot/dts/mpc5121ads.dts         |    2 +-
 arch/powerpc/platforms/512x/mpc512x_shared.c |    1 +
 drivers/dma/Kconfig                          |    7 +
 drivers/dma/Makefile                         |    1 +
 drivers/dma/mpc512x_dma.c                    |  642 ++++++++++++++++++++++++++
 drivers/dma/mpc512x_dma.h                    |  192 ++++++++
 6 files changed, 844 insertions(+), 1 deletions(-)
 create mode 100644 drivers/dma/mpc512x_dma.c
 create mode 100644 drivers/dma/mpc512x_dma.h

diff --git a/arch/powerpc/boot/dts/mpc5121ads.dts b/arch/powerpc/boot/dts/mpc5121ads.dts
index c2d9de9..e7f0e09 100644
--- a/arch/powerpc/boot/dts/mpc5121ads.dts
+++ b/arch/powerpc/boot/dts/mpc5121ads.dts
@@ -373,7 +373,7 @@
 		};
 
 		dma@14000 {
-			compatible = "fsl,mpc5121-dma2";
+			compatible = "fsl,mpc512x-dma";
 			reg = <0x14000 0x1800>;
 			interrupts = <65 0x8>;
 			interrupt-parent = < &ipic >;
diff --git a/arch/powerpc/platforms/512x/mpc512x_shared.c b/arch/powerpc/platforms/512x/mpc512x_shared.c
index b776e45..135fd6b 100644
--- a/arch/powerpc/platforms/512x/mpc512x_shared.c
+++ b/arch/powerpc/platforms/512x/mpc512x_shared.c
@@ -95,6 +95,7 @@ void __init mpc512x_init_i2c(void)
 static struct of_device_id __initdata of_bus_ids[] = {
 	{ .compatible = "fsl,mpc5121-immr", },
 	{ .compatible = "fsl,mpc5121-localbus", },
+	{ .compatible = "fsl,mpc5121-dma", },
 	{ .compatible = "fsl,mpc5121-nfc", },
 	{},
 };
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 3b3c01b..e734a7a 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -55,6 +55,13 @@ config FSL_DMA
 	  The Elo is the DMA controller on some 82xx and 83xx parts, and the
 	  Elo Plus is the DMA controller on 85xx and 86xx parts.
 
+config MPC512X_DMA
+	tristate "Freescale MPC512x built-in DMA engine support"
+	depends on PPC_MPC512x
+	select DMA_ENGINE
+	---help---
+	  Enable support for the Freescale MPC512x built-in DMA engine.
+
 config MV_XOR
 	bool "Marvell XOR engine support"
 	depends on PLAT_ORION
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index 2e5dc96..f02806c 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -5,6 +5,7 @@ obj-$(CONFIG_INTEL_IOATDMA) += ioatdma.o
 ioatdma-objs := ioat.o ioat_dma.o ioat_dca.o
 obj-$(CONFIG_INTEL_IOP_ADMA) += iop-adma.o
 obj-$(CONFIG_FSL_DMA) += fsldma.o
+obj-$(CONFIG_MPC512X_DMA) += mpc512x_dma.o
 obj-$(CONFIG_MV_XOR) += mv_xor.o
 obj-$(CONFIG_DW_DMAC) += dw_dmac.o
 obj-$(CONFIG_MX3_IPU) += ipu/
diff --git a/drivers/dma/mpc512x_dma.c b/drivers/dma/mpc512x_dma.c
new file mode 100644
index 0000000..1aac897
--- /dev/null
+++ b/drivers/dma/mpc512x_dma.c
@@ -0,0 +1,642 @@
+/*
+ * Copyright (C) Semihalf 2009
+ *
+ * Written by: Piotr Ziecik <kosmo@semihalf.com>
+ *
+ * Approved as OSADL project by a majority of OSADL members and funded
+ * by OSADL membership fees in 2009;  for details see www.osadl.org.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59
+ * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called COPYING.
+ */
+
+/*
+ * This is initial version of MPC5121 DMA driver. Only memory to memory
+ * transfers are supported (tested using dmatest module).
+ */
+
+#include <linux/module.h>
+#include <linux/dmaengine.h>
+#include <linux/dma-mapping.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+
+#include <linux/random.h>
+
+#include "mpc512x_dma.h"
+
+#define DRV_NAME	"mpc512x_dma"
+
+/* Convert struct dma_chan to struct mpc_dma_chan */
+static inline struct mpc_dma_chan *dma_chan_to_mpc_dma_chan(struct dma_chan *c)
+{
+	return container_of(c, struct mpc_dma_chan, chan);
+}
+
+/* Convert struct dma_chan to struct mpc_dma */
+static inline struct mpc_dma *dma_chan_to_mpc_dma(struct dma_chan *c)
+{
+	struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(c);
+	return container_of(mchan, struct mpc_dma, channels[c->chan_id]);
+}
+
+/*
+ * Execute all queued DMA descriptors.
+ *
+ * Following requirements must be met while calling mpc_dma_execute():
+ * 	a) mchan->lock is acquired,
+ * 	b) mchan->active list is empty,
+ * 	c) mchan->queued list contains at least one entry.
+ */
+static void mpc_dma_execute(struct mpc_dma_chan *mchan)
+{
+	struct mpc_dma *mdma = dma_chan_to_mpc_dma(&mchan->chan);
+	struct mpc_dma_desc *first = NULL;
+	struct mpc_dma_desc *prev = NULL;
+	struct mpc_dma_desc *mdesc;
+	int cid = mchan->chan.chan_id;
+
+	/* Move all queued descriptors to active list */
+	list_splice_tail_init(&mchan->queued, &mchan->active);
+
+	/* Chain descriptors into one transaction */
+	list_for_each_entry(mdesc, &mchan->active, node) {
+		if (!first)
+			first = mdesc;
+
+		if (!prev) {
+			prev = mdesc;
+			continue;
+		}
+
+		prev->tcd->dlast_sga = mdesc->tcd_paddr;
+		prev->tcd->e_sg = 1;
+		mdesc->tcd->start = 1;
+
+		prev = mdesc;
+	}
+
+	prev->tcd->start = 0;
+	prev->tcd->int_maj = 1;
+
+	/* Send first descriptor in chain into hardware */
+	memcpy_toio(&mdma->tcd[cid], first->tcd, sizeof(struct mpc_dma_tcd));
+	out_8(&mdma->regs->dmassrt, cid);
+}
+
+/* Handle interrupt on one half of DMA controller (32 channels) */
+static void mpc_dma_irq_process(struct mpc_dma *mdma, u32 is, u32 es, int off)
+{
+	struct mpc_dma_chan *mchan;
+	struct mpc_dma_desc *mdesc;
+	u32 status = is | es;
+	int ch;
+
+	while ((ch = fls(status) - 1) >= 0) {
+		status &= ~(1 << ch);
+		mchan = &mdma->channels[ch + off];
+
+		spin_lock(&mchan->lock);
+
+		/* Check error status */
+		if (es & (1 << ch))
+			list_for_each_entry(mdesc, &mchan->active, node)
+				mdesc->error = -EIO;
+
+		/* Execute queued descriptors */
+		list_splice_tail_init(&mchan->active, &mchan->completed);
+		if (!list_empty(&mchan->queued))
+			mpc_dma_execute(mchan);
+
+		spin_unlock(&mchan->lock);
+	}
+}
+
+/* Interrupt handler */
+static irqreturn_t mpc_dma_irq(int irq, void *data)
+{
+	struct mpc_dma *mdma = data;
+	uint es;
+
+	/* Save error status register */
+	es = in_be32(&mdma->regs->dmaes);
+	spin_lock(&mdma->error_status_lock);
+	if ((es & MPC_DMA_DMAES_VLD) && mdma->error_status == 0)
+		mdma->error_status = es;
+	spin_unlock(&mdma->error_status_lock);
+
+	/* Handle interrupt on each channel */
+	mpc_dma_irq_process(mdma, in_be32(&mdma->regs->dmainth),
+					in_be32(&mdma->regs->dmaerrh), 32);
+	mpc_dma_irq_process(mdma, in_be32(&mdma->regs->dmaintl),
+					in_be32(&mdma->regs->dmaerrl), 0);
+
+	/* Ack interrupt on all channels */
+	out_be32(&mdma->regs->dmainth, 0xFFFFFFFF);
+	out_be32(&mdma->regs->dmaintl, 0xFFFFFFFF);
+	out_be32(&mdma->regs->dmaerrh, 0xFFFFFFFF);
+	out_be32(&mdma->regs->dmaerrl, 0xFFFFFFFF);
+
+	/* Schedule tasklet */
+	tasklet_schedule(&mdma->tasklet);
+
+	return IRQ_HANDLED;
+}
+
+/* DMA Tasklet */
+static void mpc_dma_tasklet(unsigned long data)
+{
+	struct mpc_dma *mdma = (void *)data;
+	dma_cookie_t last_cookie = 0;
+	struct mpc_dma_chan *mchan;
+	struct mpc_dma_desc *mdesc;
+	struct dma_async_tx_descriptor *desc;
+	unsigned long flags;
+	LIST_HEAD(list);
+	uint es;
+	int i;
+
+	spin_lock_irqsave(&mdma->error_status_lock, flags);
+	es = mdma->error_status;
+	mdma->error_status = 0;
+	spin_unlock_irqrestore(&mdma->error_status_lock, flags);
+
+	/* Print nice error report */
+	if (es) {
+		dev_err(mdma->dma.dev,
+			"Hardware reported following error(s) on channel %u:\n",
+						      MPC_DMA_DMAES_ERRCHN(es));
+
+		if (es & MPC_DMA_DMAES_GPE)
+			dev_err(mdma->dma.dev, "- Group Priority Error\n");
+		if (es & MPC_DMA_DMAES_CPE)
+			dev_err(mdma->dma.dev, "- Channel Priority Error\n");
+		if (es & MPC_DMA_DMAES_SAE)
+			dev_err(mdma->dma.dev, "- Source Address Error\n");
+		if (es & MPC_DMA_DMAES_SOE)
+			dev_err(mdma->dma.dev, "- Source Offset"
+						" Configuration Error\n");
+		if (es & MPC_DMA_DMAES_DAE)
+			dev_err(mdma->dma.dev, "- Destination Address"
+								" Error\n");
+		if (es & MPC_DMA_DMAES_DOE)
+			dev_err(mdma->dma.dev, "- Destination Offset"
+						" Configuration Error\n");
+		if (es & MPC_DMA_DMAES_NCE)
+			dev_err(mdma->dma.dev, "- NBytes/Citter"
+						" Configuration Error\n");
+		if (es & MPC_DMA_DMAES_SGE)
+			dev_err(mdma->dma.dev, "- Scatter/Gather"
+						" Configuration Error\n");
+		if (es & MPC_DMA_DMAES_SBE)
+			dev_err(mdma->dma.dev, "- Source Bus Error\n");
+		if (es & MPC_DMA_DMAES_DBE)
+			dev_err(mdma->dma.dev, "- Destination Bus Error\n");
+	}
+
+	for (i = 0; i < mdma->dma.chancnt; i++) {
+		mchan = &mdma->channels[i];
+
+		/* Get all completed descriptors */
+		spin_lock_irqsave(&mchan->lock, flags);
+		if (!list_empty(&mchan->completed))
+			list_splice_tail_init(&mchan->completed, &list);
+		spin_unlock_irqrestore(&mchan->lock, flags);
+
+		if (list_empty(&list))
+			continue;
+
+		/* Execute callbacks and run dependencies */
+		list_for_each_entry(mdesc, &list, node) {
+			desc = &mdesc->desc;
+
+			if (desc->callback)
+				desc->callback(desc->callback_param);
+
+			last_cookie = desc->cookie;
+			dma_run_dependencies(desc);
+		}
+
+		/* Free descriptors */
+		spin_lock_irqsave(&mchan->lock, flags);
+		list_splice_tail_init(&list, &mchan->free);
+		mchan->completed_cookie = last_cookie;
+		spin_unlock_irqrestore(&mchan->lock, flags);
+	}
+}
+
+/* Submit descriptor to hardware */
+static dma_cookie_t mpc_dma_tx_submit(struct dma_async_tx_descriptor *txd)
+{
+	struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(txd->chan);
+	struct mpc_dma_desc *mdesc;
+	unsigned long flags;
+	dma_cookie_t cookie;
+
+	mdesc = container_of(txd, struct mpc_dma_desc, desc);
+
+	spin_lock_irqsave(&mchan->lock, flags);
+
+	/* Move descriptor to queue */
+	list_move_tail(&mdesc->node, &mchan->queued);
+
+	/* If channel is idle, execute all queued descriptors */
+	if (list_empty(&mchan->active))
+		mpc_dma_execute(mchan);
+
+	/* Update cookie */
+	cookie = mchan->chan.cookie + 1;
+	if (cookie <= 0)
+		cookie = 1;
+
+	mchan->chan.cookie = cookie;
+	mdesc->desc.cookie = cookie;
+
+	spin_unlock_irqrestore(&mchan->lock, flags);
+
+	return cookie;
+}
+
+/* Alloc channel resources */
+static int mpc_dma_alloc_chan_resources(struct dma_chan *chan)
+{
+	struct mpc_dma *mdma = dma_chan_to_mpc_dma(chan);
+	struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan);
+	struct mpc_dma_desc *mdesc;
+	struct mpc_dma_tcd *tcd;
+	dma_addr_t tcd_paddr;
+	unsigned long flags;
+	LIST_HEAD(descs);
+	int i;
+
+	/* Alloc DMA memory for Transfer Control Descriptors */
+	tcd = dma_alloc_coherent(mdma->dma.dev,
+			MPC_DMA_DESCRIPTORS * sizeof(struct mpc_dma_tcd),
+							&tcd_paddr, GFP_KERNEL);
+	if (!tcd)
+		return -ENOMEM;
+
+	/* Alloc descriptors for this channel */
+	for (i = 0; i < MPC_DMA_DESCRIPTORS; i++) {
+		mdesc = kzalloc(sizeof(struct mpc_dma_desc), GFP_KERNEL);
+		if (!mdesc) {
+			dev_notice(mdma->dma.dev, "Memory allocation error. "
+					"Allocated only %u descriptors\n", i);
+			break;
+		}
+
+		dma_async_tx_descriptor_init(&mdesc->desc, chan);
+		mdesc->desc.flags = DMA_CTRL_ACK;
+		mdesc->desc.tx_submit = mpc_dma_tx_submit;
+
+		mdesc->tcd = &tcd[i];
+		mdesc->tcd_paddr = tcd_paddr + (i * sizeof(struct mpc_dma_tcd));
+
+		list_add_tail(&mdesc->node, &descs);
+	}
+
+	/* Return error only if no descriptors were allocated */
+	if (i == 0) {
+		dma_free_coherent(mdma->dma.dev,
+			MPC_DMA_DESCRIPTORS * sizeof(struct mpc_dma_tcd),
+								tcd, tcd_paddr);
+		return -ENOMEM;
+	}
+
+	spin_lock_irqsave(&mchan->lock, flags);
+	mchan->tcd = tcd;
+	mchan->tcd_paddr = tcd_paddr;
+	list_splice_tail_init(&descs, &mchan->free);
+	spin_unlock_irqrestore(&mchan->lock, flags);
+
+	/* Enable Error Interrupt */
+	out_8(&mdma->regs->dmaseei, chan->chan_id);
+
+	return 0;
+}
+
+/* Free channel resources */
+static void mpc_dma_free_chan_resources(struct dma_chan *chan)
+{
+	struct mpc_dma *mdma = dma_chan_to_mpc_dma(chan);
+	struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan);
+	struct mpc_dma_desc *mdesc, *tmp;
+	struct mpc_dma_tcd *tcd;
+	dma_addr_t tcd_paddr;
+	unsigned long flags;
+	LIST_HEAD(descs);
+
+	spin_lock_irqsave(&mchan->lock, flags);
+
+	/* Channel must be idle */
+	BUG_ON(!list_empty(&mchan->prepared));
+	BUG_ON(!list_empty(&mchan->queued));
+	BUG_ON(!list_empty(&mchan->active));
+	BUG_ON(!list_empty(&mchan->completed));
+
+	/* Move data */
+	list_splice_tail_init(&mchan->free, &descs);
+	tcd = mchan->tcd;
+	tcd_paddr = mchan->tcd_paddr;
+
+	spin_unlock_irqrestore(&mchan->lock, flags);
+
+	/* Free DMA memory used by descriptors */
+	dma_free_coherent(mdma->dma.dev,
+			MPC_DMA_DESCRIPTORS * sizeof(struct mpc_dma_tcd),
+								tcd, tcd_paddr);
+
+	/* Free descriptors */
+	list_for_each_entry_safe(mdesc, tmp, &descs, node)
+		kfree(mdesc);
+
+	/* Disable Error Interrupt */
+	out_8(&mdma->regs->dmaceei, chan->chan_id);
+}
+
+/* Send all pending descriptor to hardware */
+static void mpc_dma_issue_pending(struct dma_chan *chan)
+{
+	/*
+	 * We are posting descriptors to the hardware as soon as
+	 * they are ready, so this function does nothing.
+	 */
+}
+
+/* Check request completion status */
+static enum dma_status
+mpc_dma_is_tx_complete(struct dma_chan *chan, dma_cookie_t cookie,
+					dma_cookie_t *done, dma_cookie_t *used)
+{
+	struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan);
+	unsigned long flags;
+	dma_cookie_t last_used;
+	dma_cookie_t last_complete;
+
+	spin_lock_irqsave(&mchan->lock, flags);
+	last_used = mchan->chan.cookie;
+	last_complete = mchan->completed_cookie;
+	spin_unlock_irqrestore(&mchan->lock, flags);
+
+	if (done)
+		*done = last_complete;
+
+	if (used)
+		*used = last_used;
+
+	return dma_async_is_complete(cookie, last_complete, last_used);
+}
+
+/* Prepare descriptor for memory to memory copy */
+static struct dma_async_tx_descriptor *
+mpc_dma_prep_memcpy(struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
+					size_t len, unsigned long flags)
+{
+	struct mpc_dma_chan *mchan = dma_chan_to_mpc_dma_chan(chan);
+	struct mpc_dma_desc *mdesc = NULL;
+	struct mpc_dma_tcd *tcd;
+	unsigned long iflags;
+
+	/* Get free descriptor */
+	spin_lock_irqsave(&mchan->lock, iflags);
+	if (!list_empty(&mchan->free)) {
+		mdesc = list_first_entry(&mchan->free, struct mpc_dma_desc,
+									node);
+		list_del(&mdesc->node);
+	}
+	spin_unlock_irqrestore(&mchan->lock, iflags);
+
+	if (!mdesc)
+		return NULL;
+
+	mdesc->error = 0;
+	tcd = mdesc->tcd;
+
+	/* Prepare Transfer Control Descriptor for this transaction */
+	memset(tcd, 0, sizeof(struct mpc_dma_tcd));
+
+	if (IS_ALIGNED(src | dst | len, 32)) {
+		tcd->ssize = MPC_DMA_TSIZE_32;
+		tcd->dsize = MPC_DMA_TSIZE_32;
+		tcd->soff = 32;
+		tcd->doff = 32;
+	} else if (IS_ALIGNED(src | dst | len, 16)) {
+		tcd->ssize = MPC_DMA_TSIZE_16;
+		tcd->dsize = MPC_DMA_TSIZE_16;
+		tcd->soff = 16;
+		tcd->doff = 16;
+	} else if (IS_ALIGNED(src | dst | len, 4)) {
+		tcd->ssize = MPC_DMA_TSIZE_4;
+		tcd->dsize = MPC_DMA_TSIZE_4;
+		tcd->soff = 4;
+		tcd->doff = 4;
+	} else if (IS_ALIGNED(src | dst | len, 2)) {
+		tcd->ssize = MPC_DMA_TSIZE_2;
+		tcd->dsize = MPC_DMA_TSIZE_2;
+		tcd->soff = 2;
+		tcd->doff = 2;
+	} else {
+		tcd->ssize = MPC_DMA_TSIZE_1;
+		tcd->dsize = MPC_DMA_TSIZE_1;
+		tcd->soff = 1;
+		tcd->doff = 1;
+	}
+
+	tcd->saddr = src;
+	tcd->daddr = dst;
+	tcd->nbytes = len;
+	tcd->biter = 1;
+	tcd->citer = 1;
+
+	/* Place descriptor in prepared list */
+	spin_lock_irqsave(&mchan->lock, iflags);
+	list_add_tail(&mdesc->node, &mchan->prepared);
+	spin_unlock_irqrestore(&mchan->lock, iflags);
+
+	return &mdesc->desc;
+}
+
+static int __init mpc_dma_probe(struct of_device *op,
+					const struct of_device_id *match)
+{
+	struct device_node *dn = op->node;
+	struct device *dev = &op->dev;
+	struct dma_device *dma;
+	struct mpc_dma *mdma;
+	struct mpc_dma_chan *mchan;
+	struct resource res;
+	ulong regs_start, regs_size;
+	int retval, i;
+
+	mdma = devm_kzalloc(dev, sizeof(struct mpc_dma), GFP_KERNEL);
+	if (!mdma) {
+		dev_err(dev, "Memory exhausted!\n");
+		return -ENOMEM;
+	}
+
+	mdma->irq = irq_of_parse_and_map(dn, 0);
+	if (mdma->irq == NO_IRQ) {
+		dev_err(dev, "Error mapping IRQ!\n");
+		return -EINVAL;
+	}
+
+	retval = of_address_to_resource(dn, 0, &res);
+	if (retval) {
+		dev_err(dev, "Error parsing memory region!\n");
+		return retval;
+	}
+
+	regs_start = res.start;
+	regs_size = res.end - res.start + 1;
+
+	if (!devm_request_mem_region(dev, regs_start, regs_size, DRV_NAME)) {
+		dev_err(dev, "Error requesting memory region!\n");
+		return -EBUSY;
+	}
+
+	mdma->regs = devm_ioremap(dev, regs_start, regs_size);
+	if (!mdma->regs) {
+		dev_err(dev, "Error mapping memory region!\n");
+		return -ENOMEM;
+	}
+
+	mdma->tcd = (struct mpc_dma_tcd *)((u8 *)(mdma->regs)
+							+ MPC_DMA_TCD_OFFSET);
+
+	retval = devm_request_irq(dev, mdma->irq, &mpc_dma_irq, 0, DRV_NAME,
+									mdma);
+	if (retval) {
+		dev_err(dev, "Error requesting IRQ!\n");
+		return -EINVAL;
+	}
+
+	spin_lock_init(&mdma->error_status_lock);
+
+	dma = &mdma->dma;
+	dma->dev = dev;
+	dma->chancnt = MPC_DMA_CHANNELS;
+	dma->device_alloc_chan_resources = mpc_dma_alloc_chan_resources;
+	dma->device_free_chan_resources = mpc_dma_free_chan_resources;
+	dma->device_issue_pending = mpc_dma_issue_pending;
+	dma->device_is_tx_complete = mpc_dma_is_tx_complete;
+	dma->device_prep_dma_memcpy = mpc_dma_prep_memcpy;
+
+	INIT_LIST_HEAD(&dma->channels);
+	dma_cap_set(DMA_MEMCPY, dma->cap_mask);
+
+	for (i = 0; i < dma->chancnt; i++) {
+		mchan = &mdma->channels[i];
+
+		mchan->chan.device = dma;
+		mchan->chan.chan_id = i;
+		mchan->chan.cookie = 1;
+		mchan->completed_cookie = mchan->chan.cookie;
+
+		INIT_LIST_HEAD(&mchan->free);
+		INIT_LIST_HEAD(&mchan->prepared);
+		INIT_LIST_HEAD(&mchan->queued);
+		INIT_LIST_HEAD(&mchan->active);
+		INIT_LIST_HEAD(&mchan->completed);
+
+		spin_lock_init(&mchan->lock);
+		list_add_tail(&mchan->chan.device_node, &dma->channels);
+	}
+
+	tasklet_init(&mdma->tasklet, mpc_dma_tasklet, (unsigned long)mdma);
+
+	/*
+	 * Configure DMA Engine:
+	 * - Dynamic clock,
+	 * - Round-robin group arbitration,
+	 * - Round-robin channel arbitration.
+	 */
+	out_be32(&mdma->regs->dmacr, MPC_DMA_DMACR_EDCG |
+				MPC_DMA_DMACR_ERGA | MPC_DMA_DMACR_ERCA);
+
+	/* Disable hardware DMA requests */
+	out_be32(&mdma->regs->dmaerqh, 0);
+	out_be32(&mdma->regs->dmaerql, 0);
+
+	/* Disable error interrupts */
+	out_be32(&mdma->regs->dmaeeih, 0);
+	out_be32(&mdma->regs->dmaeeil, 0);
+
+	/* Clear interrupts status */
+	out_be32(&mdma->regs->dmainth, 0xFFFFFFFF);
+	out_be32(&mdma->regs->dmaintl, 0xFFFFFFFF);
+	out_be32(&mdma->regs->dmaerrh, 0xFFFFFFFF);
+	out_be32(&mdma->regs->dmaerrl, 0xFFFFFFFF);
+
+	/* Route interrupts to IPIC */
+	out_be32(&mdma->regs->dmaihsa, 0);
+	out_be32(&mdma->regs->dmailsa, 0);
+
+	/* Register DMA engine */
+	dev_set_drvdata(dev, mdma);
+	retval = dma_async_device_register(dma);
+	if (retval)
+		devm_free_irq(dev, mdma->irq, mdma);
+
+	return retval;
+}
+
+static void __exit mpc_dma_remove(struct of_device *op)
+{
+	struct device *dev = &op->dev;
+	struct mpc_dma *mdma = dev_get_drvdata(dev);
+
+	devm_free_irq(dev, mdma->irq, mdma);
+}
+
+static struct of_device_id mpc_dma_match[] = {
+	{ .compatible = "fsl,mpc512x-dma", },
+	{},
+};
+
+static struct of_platform_driver mpc_dma_driver = {
+	.name		= DRV_NAME,
+	.owner		= THIS_MODULE,
+	.match_table	= mpc_dma_match,
+	.probe		= mpc_dma_probe,
+	.remove		= __exit_p(mpc_dma_remove),
+	.suspend	= NULL,
+	.resume		= NULL,
+	.driver		= {
+		.name	= DRV_NAME,
+		.owner	= THIS_MODULE,
+	},
+};
+
+static int __init mpc_dma_init(void)
+{
+	return of_register_platform_driver(&mpc_dma_driver);
+}
+
+static void __exit mpc_dma_exit(void)
+{
+	of_unregister_platform_driver(&mpc_dma_driver);
+}
+
+module_init(mpc_dma_init);
+module_exit(mpc_dma_exit);
+
+/* MODULE API */
+MODULE_VERSION("0.5");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Piotr Ziecik <kosmo@semihalf.com>");
diff --git a/drivers/dma/mpc512x_dma.h b/drivers/dma/mpc512x_dma.h
new file mode 100644
index 0000000..867415b
--- /dev/null
+++ b/drivers/dma/mpc512x_dma.h
@@ -0,0 +1,192 @@
+/*
+ * Copyright (C) Freescale Semicondutor, Inc. 2007, 2008.
+ * Copyright (C) Semihalf, 2009.
+ *
+ * Written by Piotr Ziecik <kosmo@semihalf.com>. Hardware description
+ * (defines, structures and comments) was taken from MPC5121 DMA driver
+ * written by Hongjun Chen <hong-jun.chen@freescale.com>.
+ *
+ * Approved as OSADL project by a majority of OSADL members and funded
+ * by OSADL membership fees in 2009;  for details see www.osadl.org.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59
+ * Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ *
+ * The full GNU General Public License is included in this distribution in the
+ * file called COPYING.
+ */
+#ifndef _MPC512X_DMA_H_
+#define _MPC512X_DMA_H_
+
+#include <linux/dmaengine.h>
+
+/* Number of DMA Transfer descriptors allocated per channel */
+#define MPC_DMA_DESCRIPTORS	64
+
+/* Macro definitions */
+#define MPC_DMA_CHANNELS	64
+#define MPC_DMA_TCD_OFFSET	0x1000
+
+/* Arbitration mode of group and channel */
+#define MPC_DMA_DMACR_EDCG	(1 << 31)
+#define MPC_DMA_DMACR_ERGA	(1 << 3)
+#define MPC_DMA_DMACR_ERCA	(1 << 2)
+
+/* Error codes */
+#define MPC_DMA_DMAES_VLD	(1 << 31)
+#define MPC_DMA_DMAES_GPE	(1 << 15)
+#define MPC_DMA_DMAES_CPE	(1 << 14)
+#define MPC_DMA_DMAES_ERRCHN(err) \
+				(((err) >> 8) & 0x3f)
+#define MPC_DMA_DMAES_SAE	(1 << 7)
+#define MPC_DMA_DMAES_SOE	(1 << 6)
+#define MPC_DMA_DMAES_DAE	(1 << 5)
+#define MPC_DMA_DMAES_DOE	(1 << 4)
+#define MPC_DMA_DMAES_NCE	(1 << 3)
+#define MPC_DMA_DMAES_SGE	(1 << 2)
+#define MPC_DMA_DMAES_SBE	(1 << 1)
+#define MPC_DMA_DMAES_DBE	(1 << 0)
+
+#define MPC_DMA_TSIZE_1		0x00
+#define MPC_DMA_TSIZE_2		0x01
+#define MPC_DMA_TSIZE_4		0x02
+#define MPC_DMA_TSIZE_16	0x04
+#define MPC_DMA_TSIZE_32	0x05
+
+/* MPC5121 DMA engine registers */
+struct __attribute__ ((__packed__)) mpc_dma_regs {
+	/* 0x00 */
+	u32 dmacr;		/* DMA control register */
+	u32 dmaes;		/* DMA error status */
+	/* 0x08 */
+	u32 dmaerqh;		/* DMA enable request high(channels 63~32) */
+	u32 dmaerql;		/* DMA enable request low(channels 31~0) */
+	u32 dmaeeih;		/* DMA enable error interrupt high(ch63~32) */
+	u32 dmaeeil;		/* DMA enable error interrupt low(ch31~0) */
+	/* 0x18 */
+	u8 dmaserq;		/* DMA set enable request */
+	u8 dmacerq;		/* DMA clear enable request */
+	u8 dmaseei;		/* DMA set enable error interrupt */
+	u8 dmaceei;		/* DMA clear enable error interrupt */
+	/* 0x1c */
+	u8 dmacint;		/* DMA clear interrupt request */
+	u8 dmacerr;		/* DMA clear error */
+	u8 dmassrt;		/* DMA set start bit */
+	u8 dmacdne;		/* DMA clear DONE status bit */
+	/* 0x20 */
+	u32 dmainth;		/* DMA interrupt request high(ch63~32) */
+	u32 dmaintl;		/* DMA interrupt request low(ch31~0) */
+	u32 dmaerrh;		/* DMA error high(ch63~32) */
+	u32 dmaerrl;		/* DMA error low(ch31~0) */
+	/* 0x30 */
+	u32 dmahrsh;		/* DMA hw request status high(ch63~32) */
+	u32 dmahrsl;		/* DMA hardware request status low(ch31~0) */
+	u32 dmaihsa;		/* DMA interrupt high select AXE(ch63~32) */
+	u32 dmailsa;		/* DMA interrupt low select AXE(ch31~0) */
+	/* 0x40 ~ 0xff */
+	u32 reserve0[48];	/* Reserved */
+	/* 0x100 */
+	u8 dchpri[MPC_DMA_CHANNELS];
+	/* DMA channels(0~63) priority */
+};
+
+struct __attribute__ ((__packed__)) mpc_dma_tcd {
+	/* 0x00 */
+	u32 saddr;		/* Source address */
+
+	u32 smod:5;		/* Source address modulo */
+	u32 ssize:3;		/* Source data transfer size */
+	u32 dmod:5;		/* Destination address modulo */
+	u32 dsize:3;		/* Destination data transfer size */
+	u32 soff:16;		/* Signed source address offset */
+
+	/* 0x08 */
+	u32 nbytes;		/* Inner "minor" byte count */
+	u32 slast;		/* Last source address adjustment */
+	u32 daddr;		/* Destination address */
+
+	/* 0x14 */
+	u32 citer_elink:1;	/* Enable channel-to-channel linking on
+				 * minor loop complete
+				 */
+	u32 citer_linkch:6;	/* Link channel for minor loop complete */
+	u32 citer:9;		/* Current "major" iteration count */
+	u32 doff:16;		/* Signed destination address offset */
+
+	/* 0x18 */
+	u32 dlast_sga;		/* Last Destination address adjustment/scatter
+				 * gather address
+				 */
+
+	/* 0x1c */
+	u32 biter_elink:1;	/* Enable channel-to-channel linking on major
+				 * loop complete
+				 */
+	u32 biter_linkch:6;
+	u32 biter:9;		/* Beginning "major" iteration count */
+	u32 bwc:2;		/* Bandwidth control */
+	u32 major_linkch:6;	/* Link channel number */
+	u32 done:1;		/* Channel done */
+	u32 active:1;		/* Channel active */
+	u32 major_elink:1;	/* Enable channel-to-channel linking on major
+				 * loop complete
+				 */
+	u32 e_sg:1;		/* Enable scatter/gather processing */
+	u32 d_req:1;		/* Disable request */
+	u32 int_half:1;		/* Enable an interrupt when major counter is
+				 * half complete
+				 */
+	u32 int_maj:1;		/* Enable an interrupt when major iteration
+				 * count completes
+				 */
+	u32 start:1;		/* Channel start */
+};
+
+struct mpc_dma_desc {
+	struct dma_async_tx_descriptor	desc;
+	struct mpc_dma_tcd		*tcd;
+	dma_addr_t			tcd_paddr;
+	int				error;
+	struct list_head		node;
+};
+
+struct mpc_dma_chan {
+	struct dma_chan			chan;
+	struct list_head		free;
+	struct list_head		prepared;
+	struct list_head		queued;
+	struct list_head		active;
+	struct list_head		completed;
+	struct mpc_dma_tcd		*tcd;
+	dma_addr_t			tcd_paddr;
+	dma_cookie_t			completed_cookie;
+
+	/* Lock for this structure */
+	spinlock_t			lock;
+};
+
+struct mpc_dma {
+	struct dma_device		dma;
+	struct tasklet_struct		tasklet;
+	struct mpc_dma_chan		channels[MPC_DMA_CHANNELS];
+	struct mpc_dma_regs __iomem	*regs;
+	struct mpc_dma_tcd __iomem	*tcd;
+	int				irq;
+	uint				error_status;
+
+	/* Lock for error_status field in this structure */
+	spinlock_t			error_status_lock;
+};
+
+#endif /* _MPC512X_DMA_H_ */
-- 
1.6.0.6

[PATCH 12/12] mpc5121: Added default config for MPC5121.

[Wolfgang Denk]

From: Piotr Ziecik <kosmo@semihalf.com>

Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: John Rigby <jcrigby@gmail.com>
---
 arch/powerpc/configs/mpc5121_defconfig | 1158 ++++++++++++++++++++++++++++++++
 1 files changed, 1158 insertions(+), 0 deletions(-)
 create mode 100644 arch/powerpc/configs/mpc5121_defconfig

diff --git a/arch/powerpc/configs/mpc5121_defconfig b/arch/powerpc/configs/mpc5121_defconfig
new file mode 100644
index 0000000..87b5f15
--- /dev/null
+++ b/arch/powerpc/configs/mpc5121_defconfig
@@ -0,0 +1,1158 @@
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.29-rc5
+# Fri Feb 27 14:08:31 2009
+#
+# CONFIG_PPC64 is not set
+
+#
+# Processor support
+#
+CONFIG_6xx=y
+# CONFIG_PPC_85xx is not set
+# CONFIG_PPC_8xx is not set
+# CONFIG_40x is not set
+# CONFIG_44x is not set
+# CONFIG_E200 is not set
+CONFIG_PPC_FPU=y
+# CONFIG_ALTIVEC is not set
+CONFIG_PPC_STD_MMU=y
+CONFIG_PPC_STD_MMU_32=y
+# CONFIG_PPC_MM_SLICES is not set
+# CONFIG_SMP is not set
+CONFIG_NOT_COHERENT_CACHE=y
+CONFIG_PPC32=y
+CONFIG_WORD_SIZE=32
+# CONFIG_ARCH_PHYS_ADDR_T_64BIT is not set
+CONFIG_MMU=y
+CONFIG_GENERIC_CMOS_UPDATE=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_TIME_VSYSCALL=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_GENERIC_HARDIRQS=y
+# CONFIG_HAVE_SETUP_PER_CPU_AREA is not set
+CONFIG_IRQ_PER_CPU=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_HAVE_LATENCYTOP_SUPPORT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+CONFIG_ARCH_HAS_ILOG2_U32=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+# CONFIG_ARCH_NO_VIRT_TO_BUS is not set
+CONFIG_PPC=y
+CONFIG_EARLY_PRINTK=y
+CONFIG_GENERIC_NVRAM=y
+CONFIG_SCHED_OMIT_FRAME_POINTER=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_PPC_OF=y
+CONFIG_OF=y
+# CONFIG_PPC_UDBG_16550 is not set
+# CONFIG_GENERIC_TBSYNC is not set
+CONFIG_AUDIT_ARCH=y
+CONFIG_GENERIC_BUG=y
+CONFIG_DEFAULT_UIMAGE=y
+# CONFIG_PPC_DCR_NATIVE is not set
+# CONFIG_PPC_DCR_MMIO is not set
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+
+#
+# RCU Subsystem
+#
+CONFIG_CLASSIC_RCU=y
+# CONFIG_TREE_RCU is not set
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_PREEMPT_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=16
+# CONFIG_GROUP_SCHED is not set
+# CONFIG_CGROUPS is not set
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+# CONFIG_RELAY is not set
+CONFIG_NAMESPACES=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
+CONFIG_SYSCTL=y
+# CONFIG_EMBEDDED is not set
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_PCI_QUIRKS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+# CONFIG_PROFILING is not set
+CONFIG_HAVE_OPROFILE=y
+# CONFIG_KPROBES is not set
+CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y
+CONFIG_HAVE_IOREMAP_PROT=y
+CONFIG_HAVE_KPROBES=y
+CONFIG_HAVE_KRETPROBES=y
+CONFIG_HAVE_ARCH_TRACEHOOK=y
+CONFIG_HAVE_CLK=y
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+CONFIG_IOSCHED_DEADLINE=y
+# CONFIG_IOSCHED_CFQ is not set
+# CONFIG_DEFAULT_AS is not set
+CONFIG_DEFAULT_DEADLINE=y
+# CONFIG_DEFAULT_CFQ is not set
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="deadline"
+# CONFIG_FREEZER is not set
+CONFIG_PPC_MSI_BITMAP=y
+
+#
+# Platform support
+#
+CONFIG_PPC_MULTIPLATFORM=y
+CONFIG_CLASSIC32=y
+# CONFIG_PPC_CHRP is not set
+CONFIG_PPC_MPC512x=y
+CONFIG_PPC_MPC5121=y
+CONFIG_MPC5121_ADS=y
+# CONFIG_MPC5121_GENERIC is not set
+# CONFIG_PPC_MPC52xx is not set
+# CONFIG_PPC_PMAC is not set
+# CONFIG_PPC_CELL is not set
+# CONFIG_PPC_CELL_NATIVE is not set
+# CONFIG_PPC_82xx is not set
+# CONFIG_PQ2ADS is not set
+# CONFIG_PPC_83xx is not set
+# CONFIG_PPC_86xx is not set
+# CONFIG_EMBEDDED6xx is not set
+CONFIG_IPIC=y
+# CONFIG_MPIC is not set
+# CONFIG_MPIC_WEIRD is not set
+# CONFIG_PPC_I8259 is not set
+# CONFIG_PPC_RTAS is not set
+# CONFIG_MMIO_NVRAM is not set
+# CONFIG_PPC_MPC106 is not set
+# CONFIG_PPC_970_NAP is not set
+# CONFIG_PPC_INDIRECT_IO is not set
+# CONFIG_GENERIC_IOMAP is not set
+# CONFIG_CPU_FREQ is not set
+# CONFIG_TAU is not set
+# CONFIG_QUICC_ENGINE is not set
+# CONFIG_FSL_ULI1575 is not set
+# CONFIG_SIMPLE_GPIO is not set
+
+#
+# Kernel options
+#
+# CONFIG_HIGHMEM is not set
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+# CONFIG_HIGH_RES_TIMERS is not set
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+# CONFIG_HZ_100 is not set
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_300 is not set
+CONFIG_HZ_1000=y
+CONFIG_HZ=1000
+# CONFIG_SCHED_HRTICK is not set
+CONFIG_PREEMPT_NONE=y
+# CONFIG_PREEMPT_VOLUNTARY is not set
+# CONFIG_PREEMPT is not set
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+# CONFIG_IOMMU_HELPER is not set
+CONFIG_PPC_NEED_DMA_SYNC_OPS=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y
+CONFIG_ARCH_HAS_WALK_MEMORY=y
+CONFIG_ARCH_ENABLE_MEMORY_HOTREMOVE=y
+# CONFIG_KEXEC is not set
+# CONFIG_CRASH_DUMP is not set
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_MIGRATION is not set
+# CONFIG_PHYS_ADDR_T_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_UNEVICTABLE_LRU is not set
+CONFIG_PPC_4K_PAGES=y
+# CONFIG_PPC_16K_PAGES is not set
+# CONFIG_PPC_64K_PAGES is not set
+CONFIG_FORCE_MAX_ZONEORDER=11
+CONFIG_PROC_DEVICETREE=y
+# CONFIG_CMDLINE_BOOL is not set
+CONFIG_EXTRA_TARGETS=""
+# CONFIG_PM is not set
+# CONFIG_SECCOMP is not set
+CONFIG_ISA_DMA_API=y
+
+#
+# Bus options
+#
+CONFIG_ZONE_DMA=y
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_PPC_INDIRECT_PCI=y
+CONFIG_FSL_SOC=y
+CONFIG_FSL_PCI=y
+CONFIG_PPC_PCI_CHOICE=y
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+CONFIG_PCI_SYSCALL=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCIEAER=y
+# CONFIG_PCIEASPM is not set
+CONFIG_ARCH_SUPPORTS_MSI=y
+CONFIG_PCI_MSI=y
+# CONFIG_PCI_LEGACY is not set
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCCARD is not set
+# CONFIG_HOTPLUG_PCI is not set
+# CONFIG_HAS_RAPIDIO is not set
+
+#
+# Advanced setup
+#
+# CONFIG_ADVANCED_OPTIONS is not set
+
+#
+# Default settings for advanced configuration options are used
+#
+CONFIG_LOWMEM_SIZE=0x30000000
+CONFIG_PAGE_OFFSET=0xc0000000
+CONFIG_KERNEL_START=0xc0000000
+CONFIG_PHYSICAL_START=0x00000000
+CONFIG_TASK_SIZE=0xc0000000
+CONFIG_CONSISTENT_START=0xff100000
+CONFIG_CONSISTENT_SIZE=0x00200000
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_COMPAT_NET_DEV_OPS=y
+CONFIG_PACKET=y
+# CONFIG_PACKET_MMAP is not set
+CONFIG_UNIX=y
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+# CONFIG_IP_MULTICAST is not set
+# CONFIG_IP_ADVANCED_ROUTER is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_PNP=y
+# CONFIG_IP_PNP_DHCP is not set
+# CONFIG_IP_PNP_BOOTP is not set
+# CONFIG_IP_PNP_RARP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+# CONFIG_INET_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IPV6 is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_PHONET is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_STANDALONE=y
+# CONFIG_PREVENT_FIRMWARE_BUILD is not set
+CONFIG_FW_LOADER=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+# CONFIG_MTD_CONCAT is not set
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_TESTS is not set
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+# CONFIG_MTD_OF_PARTS is not set
+# CONFIG_MTD_AR7_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLKDEVS=y
+CONFIG_MTD_BLOCK=y
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_INTEL_VR_NOR is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+# CONFIG_MTD_NAND_CAFE is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_NAND_FSL_ELBC is not set
+CONFIG_MTD_NAND_MPC5121_NFC=y
+# CONFIG_MTD_ONENAND is not set
+
+#
+# LPDDR flash memory drivers
+#
+# CONFIG_MTD_LPDDR is not set
+# CONFIG_MTD_QINFO_PROBE is not set
+
+#
+# UBI - Unsorted block images
+#
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=4096
+CONFIG_MTD_UBI_BEB_RESERVE=1
+# CONFIG_MTD_UBI_GLUEBI is not set
+
+#
+# UBI debugging options
+#
+# CONFIG_MTD_UBI_DEBUG is not set
+CONFIG_OF_DEVICE=y
+CONFIG_OF_I2C=y
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=1
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_BLK_DEV_XIP=y
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_HD is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_PHANTOM is not set
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+CONFIG_EEPROM_AT24=y
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_HAVE_IDE=y
+# CONFIG_IDE is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+# CONFIG_SCSI is not set
+# CONFIG_SCSI_DMA is not set
+# CONFIG_SCSI_NETLINK is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+
+#
+# Enable only one of the two stacks, unless you know what you are doing
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+# CONFIG_I2O is not set
+# CONFIG_MACINTOSH_DRIVERS is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+# CONFIG_TUN is not set
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+CONFIG_MARVELL_PHY=y
+CONFIG_DAVICOM_PHY=y
+CONFIG_QSEMI_PHY=y
+CONFIG_LXT_PHY=y
+CONFIG_CICADA_PHY=y
+CONFIG_VITESSE_PHY=y
+CONFIG_SMSC_PHY=y
+CONFIG_BROADCOM_PHY=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_REALTEK_PHY=y
+CONFIG_NATIONAL_PHY=y
+CONFIG_STE10XP=y
+CONFIG_LSI_ET1011C_PHY=y
+CONFIG_FIXED_PHY=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=y
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+# CONFIG_IBM_NEW_EMAC_ZMII is not set
+# CONFIG_IBM_NEW_EMAC_RGMII is not set
+# CONFIG_IBM_NEW_EMAC_TAH is not set
+# CONFIG_IBM_NEW_EMAC_EMAC4 is not set
+# CONFIG_IBM_NEW_EMAC_NO_FLOW_CTRL is not set
+# CONFIG_IBM_NEW_EMAC_MAL_CLR_ICINTSTAT is not set
+# CONFIG_IBM_NEW_EMAC_MAL_COMMON_ERR is not set
+# CONFIG_NET_PCI is not set
+# CONFIG_B44 is not set
+# CONFIG_ATL2 is not set
+CONFIG_FS_ENET=y
+CONFIG_FS_ENET_MPC5121_FEC=y
+CONFIG_FS_ENET_FEC_TX_ALIGN_WORKAROUND=y
+CONFIG_FS_ENET_HAS_FEC=y
+CONFIG_FS_ENET_MDIO_FEC=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+# CONFIG_WLAN_80211 is not set
+# CONFIG_IWLWIFI_LEDS is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_CONSOLE_TRANSLATIONS=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_DEVKMEM is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_UARTLITE is not set
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+CONFIG_SERIAL_MPC52xx=y
+CONFIG_SERIAL_MPC52xx_CONSOLE=y
+CONFIG_SERIAL_MPC52xx_CONSOLE_BAUD=115200
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_HVC_UDBG is not set
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_NVRAM is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# PC SMBus host controller drivers
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+CONFIG_I2C_MPC=y
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_SIMTEC is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Graphics adapter I2C/DDC channel drivers
+#
+# CONFIG_I2C_VOODOO3 is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_STUB is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_DS1682 is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_PCF8575 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+# CONFIG_SPI is not set
+CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y
+# CONFIG_GPIOLIB is not set
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_THERMAL_HWMON is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_REGULATOR is not set
+
+#
+# Multimedia devices
+#
+
+#
+# Multimedia core support
+#
+# CONFIG_VIDEO_DEV is not set
+# CONFIG_DVB_CORE is not set
+# CONFIG_VIDEO_MEDIA is not set
+
+#
+# Multimedia drivers
+#
+# CONFIG_DAB is not set
+
+#
+# Graphics support
+#
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+
+#
+# Console display driver support
+#
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_DUMMY_CONSOLE=y
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_UWB is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+# CONFIG_EDAC is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc1"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+CONFIG_RTC_DRV_M41T80=y
+# CONFIG_RTC_DRV_M41T80_WDT is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_CMOS is not set
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+# CONFIG_RTC_DRV_PPC is not set
+CONFIG_RTC_DRV_MPC5121=y
+CONFIG_DMADEVICES=y
+
+#
+# DMA Devices
+#
+# CONFIG_FSL_DMA is not set
+CONFIG_MPC512X_DMA=y
+CONFIG_DMA_ENGINE=y
+
+#
+# DMA Clients
+#
+# CONFIG_NET_DMA is not set
+CONFIG_DMATEST=m
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+CONFIG_EXT2_FS_XIP=y
+# CONFIG_EXT3_FS is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_FS_XIP=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_FILE_LOCKING=y
+# CONFIG_XFS_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_DNOTIFY is not set
+# CONFIG_INOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_AUTOFS_FS is not set
+# CONFIG_AUTOFS4_FS is not set
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+# CONFIG_MSDOS_FS is not set
+# CONFIG_VFAT_FS is not set
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+# CONFIG_PROC_KCORE is not set
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+# CONFIG_HUGETLB_PAGE is not set
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+# CONFIG_JFFS2_FS_WBUF_VERIFY is not set
+# CONFIG_JFFS2_SUMMARY is not set
+# CONFIG_JFFS2_FS_XATTR is not set
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+# CONFIG_JFFS2_LZO is not set
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_UBIFS_FS=y
+# CONFIG_UBIFS_FS_XATTR is not set
+# CONFIG_UBIFS_FS_ADVANCED_COMPR is not set
+CONFIG_UBIFS_FS_LZO=y
+CONFIG_UBIFS_FS_ZLIB=y
+# CONFIG_UBIFS_FS_DEBUG is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+CONFIG_ROOT_NFS=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=y
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=y
+# CONFIG_SUNRPC_REGISTER_V4 is not set
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_RPCSEC_GSS_SPKM3 is not set
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_NLS is not set
+# CONFIG_DLM is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC16=y
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_LZO_COMPRESS=y
+CONFIG_LZO_DECOMPRESS=y
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_HAVE_LMB=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FRAME_WARN=1024
+# CONFIG_MAGIC_SYSRQ is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_KERNEL is not set
+CONFIG_DEBUG_BUGVERBOSE=y
+CONFIG_DEBUG_MEMORY_INIT=y
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_LATENCYTOP is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+CONFIG_HAVE_FUNCTION_TRACER=y
+CONFIG_HAVE_DYNAMIC_FTRACE=y
+CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y
+
+#
+# Tracers
+#
+# CONFIG_DYNAMIC_PRINTK_DEBUG is not set
+# CONFIG_SAMPLES is not set
+CONFIG_HAVE_ARCH_KGDB=y
+CONFIG_PRINT_STACK_DEPTH=64
+# CONFIG_IRQSTACKS is not set
+# CONFIG_BOOTX_TEXT is not set
+# CONFIG_PPC_EARLY_DEBUG is not set
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+# CONFIG_SECURITY_FILE_CAPABILITIES is not set
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_MANAGER2 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+# CONFIG_CRYPTO_AES is not set
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=y
+CONFIG_CRYPTO_LZO=y
+
+#
+# Random Number Generation
+#
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
+CONFIG_PPC_CLOCK=y
+# CONFIG_VIRTUALIZATION is not set
-- 
1.6.0.6

Re: [PATCH 04/12] mpc5121: Added reset module registers representation.

[Scott Wood]

Wolfgang Denk wrote:
> From: Piotr Ziecik <kosmo@semihalf.com>
> 
> Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
> Signed-off-by: Wolfgang Denk <wd@denx.de>
> Cc: Grant Likely <grant.likely@secretlab.ca>
> Cc: John Rigby <jcrigby@gmail.com>
> ---
>  arch/powerpc/include/asm/mpc512x.h |   13 +++++++++++++
>  1 files changed, 13 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/powerpc/include/asm/mpc512x.h b/arch/powerpc/include/asm/mpc512x.h
> index c48a165..ea50d8d 100644
> --- a/arch/powerpc/include/asm/mpc512x.h
> +++ b/arch/powerpc/include/asm/mpc512x.h
> @@ -16,6 +16,19 @@
>  #ifndef __ASM_POWERPC_MPC512x_H__
>  #define __ASM_POWERPC_MPC512x_H__
>  
> +/* MPC512x Reset module registers */
> +struct mpc512x_reset_module {
> +	u32	rcwlr;	/* Reset Configuration Word Low Register */
> +	u32	rcwhr;	/* Reset Configuration Word High Register */
> +	u32	reserved1;
> +	u32	reserved2;
> +	u32	rsr;	/* Reset Status Register */
> +	u32	rmr;	/* Reset Mode Register */
> +	u32	rpr;	/* Reset Protection Register */
> +	u32	rcr;	/* Reset Control Register */
> +	u32	rcer;	/* Reset Control Enable Register */
> +} __attribute__ ((__packed__));
> +

83xx has the same registers; we should define it in a non-512x-specific 
header.

-Scott

Re: [PATCH 02/12] fs_enet: Add MPC5121 FEC support.

[Grant Likely]

On Wed, May 6, 2009 at 2:15 PM, Wolfgang Denk <wd@denx.de> wrote:
> From: John Rigby <jrigby@freescale.com>
>
> Add support for MPC512x to fs_enet driver
>
> =A0 =A0drivers/net/fs_enet/*
> =A0 =A0 =A0 =A0Enable fs_enet driver to work 5121 FEC
> =A0 =A0 =A0 =A0Enable it with CONFIG_FS_ENET_MPC5121_FEC
>
> Signed-off-by: John Rigby <jrigby@freescale.com>
> Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
> Signed-off-by: Wolfgang Denk <wd@denx.de>
> Cc: <netdev@vger.kernel.org>
> Cc: Grant Likely <grant.likely@secretlab.ca>
> Cc: John Rigby <jcrigby@gmail.com>
> ---
> =A0arch/powerpc/include/asm/mpc5121_fec.h | =A0111 ++++++++++++++++++++++=
++++++++++
> =A0drivers/net/fs_enet/Kconfig =A0 =A0 =A0 =A0 =A0 =A0| =A0 10 ++-
> =A0drivers/net/fs_enet/fs_enet-main.c =A0 =A0 | =A0 =A07 ++
> =A0drivers/net/fs_enet/fs_enet.h =A0 =A0 =A0 =A0 =A0| =A0 =A06 ++
> =A0drivers/net/fs_enet/mac-fec.c =A0 =A0 =A0 =A0 =A0| =A0 30 ++++++++-
> =A0drivers/net/fs_enet/mii-fec.c =A0 =A0 =A0 =A0 =A0| =A0 =A07 ++
> =A06 files changed, 166 insertions(+), 5 deletions(-)
> =A0create mode 100644 arch/powerpc/include/asm/mpc5121_fec.h
>
> diff --git a/arch/powerpc/include/asm/mpc5121_fec.h b/arch/powerpc/includ=
e/asm/mpc5121_fec.h
> new file mode 100644
> index 0000000..6bddf0b
> --- /dev/null
> +++ b/arch/powerpc/include/asm/mpc5121_fec.h
> @@ -0,0 +1,111 @@
> +/*
> + * Copyright (C) 2007,2008 Freescale Semiconductor, Inc. All rights rese=
rved.
> + *
> + * Author: John Rigby, <jrigby@freescale.com>
> + *
> + * Modified version of drivers/net/fec.h:
> + *
> + * =A0 =A0 fec.h =A0-- =A0Fast Ethernet Controller for Motorola ColdFire=
 SoC
> + * =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0processors.
> + *
> + * =A0 =A0 (C) Copyright 2000-2005, Greg Ungerer (gerg@snapgear.com)
> + * =A0 =A0 (C) Copyright 2000-2001, Lineo (www.lineo.com)
> + *
> + * This is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +#ifndef MPC5121_FEC_H
> +#define MPC5121_FEC_H
> +
> +typedef struct fec {
> + =A0 =A0 =A0 u32 fec_reserved0;
> + =A0 =A0 =A0 u32 fec_ievent; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* Interrup=
t event reg */
> + =A0 =A0 =A0 u32 fec_imask; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* Interr=
upt mask reg */
> + =A0 =A0 =A0 u32 fec_reserved1;
> + =A0 =A0 =A0 u32 fec_r_des_active; =A0 =A0 =A0 =A0 =A0 /* Receive descri=
ptor reg */
> + =A0 =A0 =A0 u32 fec_x_des_active; =A0 =A0 =A0 =A0 =A0 /* Transmit descr=
iptor reg */
> + =A0 =A0 =A0 u32 fec_reserved2[3];
> + =A0 =A0 =A0 u32 fec_ecntrl; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* Ethernet=
 control reg */
> + =A0 =A0 =A0 u32 fec_reserved3[6];
> + =A0 =A0 =A0 u32 fec_mii_data; =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* MII manage=
 frame reg */
> + =A0 =A0 =A0 u32 fec_mii_speed; =A0 =A0 =A0 =A0 =A0 =A0 =A0/* MII speed =
control reg */
> + =A0 =A0 =A0 u32 fec_reserved4[7];
> + =A0 =A0 =A0 u32 fec_mib_ctrlstat; =A0 =A0 =A0 =A0 =A0 /* MIB control/st=
atus reg */
> + =A0 =A0 =A0 u32 fec_reserved5[7];
> + =A0 =A0 =A0 u32 fec_r_cntrl; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* Receive =
control reg */
> + =A0 =A0 =A0 u32 fec_reserved6[15];
> + =A0 =A0 =A0 u32 fec_x_cntrl; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* Transmit=
 Control reg */
> + =A0 =A0 =A0 u32 fec_reserved7[7];
> + =A0 =A0 =A0 u32 fec_addr_low; =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* Low 32bits=
 MAC address */
> + =A0 =A0 =A0 u32 fec_addr_high; =A0 =A0 =A0 =A0 =A0 =A0 =A0/* High 16bit=
s MAC address */
> + =A0 =A0 =A0 u32 fec_opd; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* Opco=
de + Pause duration */
> + =A0 =A0 =A0 u32 fec_reserved8[10];
> + =A0 =A0 =A0 u32 fec_hash_table_high; =A0 =A0 =A0 =A0/* High 32bits hash=
 table */
> + =A0 =A0 =A0 u32 fec_hash_table_low; =A0 =A0 =A0 =A0 /* Low 32bits hash =
table */
> + =A0 =A0 =A0 u32 fec_grp_hash_table_high; =A0 =A0/* High 32bits hash tab=
le */
> + =A0 =A0 =A0 u32 fec_grp_hash_table_low; =A0 =A0 /* Low 32bits hash tabl=
e */
> + =A0 =A0 =A0 u32 fec_reserved9[7];
> + =A0 =A0 =A0 u32 fec_x_wmrk; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* FIFO tra=
nsmit water mark */
> + =A0 =A0 =A0 u32 fec_reserved10;
> + =A0 =A0 =A0 u32 fec_r_bound; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* FIFO rec=
eive bound reg */
> + =A0 =A0 =A0 u32 fec_r_fstart; =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* FIFO recei=
ve start reg */
> + =A0 =A0 =A0 u32 fec_reserved11[11];
> + =A0 =A0 =A0 u32 fec_r_des_start; =A0 =A0 =A0 =A0 =A0 =A0/* Receive desc=
riptor ring */
> + =A0 =A0 =A0 u32 fec_x_des_start; =A0 =A0 =A0 =A0 =A0 =A0/* Transmit des=
criptor ring */
> + =A0 =A0 =A0 u32 fec_r_buff_size; =A0 =A0 =A0 =A0 =A0 =A0/* Maximum rece=
ive buff size */
> + =A0 =A0 =A0 u32 fec_reserved12[26];
> + =A0 =A0 =A0 u32 fec_dma_control; =A0 =A0 =A0 =A0 =A0 =A0/* DMA Endian a=
nd other ctrl */
> +} fec_t;
> +
> +/*
> + * =A0 =A0 Define the buffer descriptor structure.
> + */
> +typedef struct bufdesc {
> + =A0 =A0 =A0 ushort =A0cbd_sc; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* Contro=
l and status info */
> + =A0 =A0 =A0 ushort =A0cbd_datlen; =A0 =A0 =A0 =A0 =A0 =A0 /* Data lengt=
h */
> + =A0 =A0 =A0 uint =A0 =A0cbd_bufaddr; =A0 =A0 =A0 =A0 =A0 =A0/* Buffer a=
ddress */
> +} cbd_t;
> +
> +/*
> + * =A0 =A0 The following definitions courtesy of commproc.h, which where
> + * =A0 =A0 Copyright (c) 1997 Dan Malek (dmalek@jlc.net).
> + */
> +#define BD_SC_WRAP =A0 =A0 =A0 =A0 =A0 =A0 ((ushort)0x2000)
> +
> +/*
> + * Buffer descriptor control/status used by Ethernet receive.
> + */
> +#define BD_ENET_RX_EMPTY =A0 =A0 =A0 ((ushort)0x8000)
> +#define BD_ENET_RX_WRAP =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0((ushort)0x2000)
> +#define BD_ENET_RX_INTR =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0((ushort)0x1000)
> +#define BD_ENET_RX_LAST =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0((ushort)0x0800)
> +#define BD_ENET_RX_FIRST =A0 =A0 =A0 ((ushort)0x0400)
> +#define BD_ENET_RX_MISS =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0((ushort)0x0100)
> +#define BD_ENET_RX_LG =A0 =A0 =A0 =A0 =A0((ushort)0x0020)
> +#define BD_ENET_RX_NO =A0 =A0 =A0 =A0 =A0((ushort)0x0010)
> +#define BD_ENET_RX_SH =A0 =A0 =A0 =A0 =A0((ushort)0x0008)
> +#define BD_ENET_RX_CR =A0 =A0 =A0 =A0 =A0((ushort)0x0004)
> +#define BD_ENET_RX_OV =A0 =A0 =A0 =A0 =A0((ushort)0x0002)
> +#define BD_ENET_RX_CL =A0 =A0 =A0 =A0 =A0((ushort)0x0001)
> +#define BD_ENET_RX_STATS =A0 =A0 =A0 ((ushort)0x013f) =A0 =A0 =A0 =A0/* =
All status bits */
> +
> +/*
> + * Buffer descriptor control/status used by Ethernet transmit.
> + */
> +#define BD_ENET_TX_READY =A0 =A0 =A0 ((ushort)0x8000)
> +#define BD_ENET_TX_PAD =A0 =A0 =A0 =A0 ((ushort)0x4000)
> +#define BD_ENET_TX_WRAP =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0((ushort)0x2000)
> +#define BD_ENET_TX_INTR =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0((ushort)0x1000)
> +#define BD_ENET_TX_LAST =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0((ushort)0x0800)
> +#define BD_ENET_TX_TC =A0 =A0 =A0 =A0 =A0((ushort)0x0400)
> +#define BD_ENET_TX_DEF =A0 =A0 =A0 =A0 ((ushort)0x0200)
> +#define BD_ENET_TX_HB =A0 =A0 =A0 =A0 =A0((ushort)0x0100)
> +#define BD_ENET_TX_LC =A0 =A0 =A0 =A0 =A0((ushort)0x0080)
> +#define BD_ENET_TX_RL =A0 =A0 =A0 =A0 =A0((ushort)0x0040)
> +#define BD_ENET_TX_UN =A0 =A0 =A0 =A0 =A0((ushort)0x0002)
> +#define BD_ENET_TX_CSL =A0 =A0 =A0 =A0 ((ushort)0x0001)
> +#define BD_ENET_TX_STATS =A0 =A0 =A0 ((ushort)0x03ff) =A0 =A0 =A0 =A0/* =
All status bits */
> +
> +#endif /* MPC5121_FEC_H */
> diff --git a/drivers/net/fs_enet/Kconfig b/drivers/net/fs_enet/Kconfig
> index 562ea68..fc073b5 100644
> --- a/drivers/net/fs_enet/Kconfig
> +++ b/drivers/net/fs_enet/Kconfig
> @@ -1,9 +1,13 @@
> =A0config FS_ENET
> =A0 =A0 =A0 =A0tristate "Freescale Ethernet Driver"
> - =A0 =A0 =A0 depends on CPM1 || CPM2
> + =A0 =A0 =A0 depends on CPM1 || CPM2 || PPC_MPC512x
> =A0 =A0 =A0 =A0select MII
> =A0 =A0 =A0 =A0select PHYLIB
>
> +config FS_ENET_MPC5121_FEC
> + =A0 =A0 =A0 def_bool y if (FS_ENET && PPC_MPC512x)
> + =A0 =A0 =A0 select FS_ENET_HAS_FEC
> +
> =A0config FS_ENET_HAS_SCC
> =A0 =A0 =A0 =A0bool "Chip has an SCC usable for ethernet"
> =A0 =A0 =A0 =A0depends on FS_ENET && (CPM1 || CPM2)
> @@ -16,13 +20,13 @@ config FS_ENET_HAS_FCC
>
> =A0config FS_ENET_HAS_FEC
> =A0 =A0 =A0 =A0bool "Chip has an FEC usable for ethernet"
> - =A0 =A0 =A0 depends on FS_ENET && CPM1
> + =A0 =A0 =A0 depends on FS_ENET && (CPM1 || FS_ENET_MPC5121_FEC)
> =A0 =A0 =A0 =A0select FS_ENET_MDIO_FEC
> =A0 =A0 =A0 =A0default y
>
> =A0config FS_ENET_MDIO_FEC
> =A0 =A0 =A0 =A0tristate "MDIO driver for FEC"
> - =A0 =A0 =A0 depends on FS_ENET && CPM1
> + =A0 =A0 =A0 depends on FS_ENET && (CPM1 || FS_ENET_MPC5121_FEC)
>
> =A0config FS_ENET_MDIO_FCC
> =A0 =A0 =A0 =A0tristate "MDIO driver for FCC"
> diff --git a/drivers/net/fs_enet/fs_enet-main.c b/drivers/net/fs_enet/fs_=
enet-main.c
> index f996a1a..4170d33 100644
> --- a/drivers/net/fs_enet/fs_enet-main.c
> +++ b/drivers/net/fs_enet/fs_enet-main.c
> @@ -1183,11 +1183,18 @@ static struct of_device_id fs_enet_match[] =3D {
> =A0 =A0 =A0 =A0},
> =A0#endif
> =A0#ifdef CONFIG_FS_ENET_HAS_FEC
> +#ifdef CONFIG_FS_ENET_MPC5121_FEC
> + =A0 =A0 =A0 {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 .compatible =3D "fsl,mpc5121-fec",
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 .data =3D (void *)&fs_fec_ops,
> + =A0 =A0 =A0 },
> +#else
> =A0 =A0 =A0 =A0{
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0.compatible =3D "fsl,pq1-fec-enet",
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0.data =3D (void *)&fs_fec_ops,
> =A0 =A0 =A0 =A0},
> =A0#endif
> +#endif

Hmmm.  A lot of these #ifdefs in here.  Does this have a multiplatform
impact?  Not to mention the fact that it's just plain ugly.  :-)

g.

--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.

Re: [PATCH 01/12] fs_enet: Use defines to set driver tunables.

[Grant Likely]

On Wed, May 6, 2009 at 2:15 PM, Wolfgang Denk <wd@denx.de> wrote:
> From: Piotr Ziecik <kosmo@semihalf.com>
>
> Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
> Signed-off-by: Wolfgang Denk <wd@denx.de>
> Cc: <netdev@vger.kernel.org>
> Cc: Grant Likely <grant.likely@secretlab.ca>
> Cc: John Rigby <jcrigby@gmail.com>

Not seeing much benefit to this patch, and the (non-existant) patch
description doesn't really help me here either.

g.

-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.

Re: [PATCH 03/12] fs_enet: Add FEC TX Alignment workaround for MPC5121.

[Grant Likely]

On Wed, May 6, 2009 at 2:15 PM, Wolfgang Denk <wd@denx.de> wrote:
> From: John Rigby <jrigby@freescale.com>
>
> The FEC on 5121 has problems with misaligned tx buffers.
> The RM says any alignment is ok but empirical results
> show that packet buffers ending in 0x1E will sometimes
> hang the FEC. =A0Other bad alignment does not hang but will
> cause silent TX failures resulting in about a 1% packet
> loss as tested by ping -f from a remote host.
>
> This patch is a work around that copies every tx packet
> to an aligned skb before sending.

OUCH!

> diff --git a/drivers/net/fs_enet/fs_enet-main.c b/drivers/net/fs_enet/fs_=
enet-main.c
> index 4170d33..c83ffc3 100644
> --- a/drivers/net/fs_enet/fs_enet-main.c
> +++ b/drivers/net/fs_enet/fs_enet-main.c
> @@ -594,6 +594,37 @@ void fs_cleanup_bds(struct net_device *dev)
>
> =A0/*********************************************************************=
*************/
>
> +#ifdef CONFIG_FS_ENET_FEC_TX_ALIGN_WORKAROUND
> +static struct sk_buff *tx_skb_align_workaround(struct net_device *dev,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 struct sk_buff *skb)
> +{
> + =A0 =A0 =A0 struct sk_buff *new_skb;
> +
> + =A0 =A0 =A0 /* Alloc new skb */
> + =A0 =A0 =A0 new_skb =3D dev_alloc_skb(ENET_RX_FRSIZE + 32);
> + =A0 =A0 =A0 if (!new_skb) {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 printk(KERN_WARNING DRV_MODULE_NAME
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ": %s Memor=
y squeeze, dropping tx packet.\n",
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 dev->name);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 return NULL;
> + =A0 =A0 =A0 }
> +
> + =A0 =A0 =A0 /* Make sure new skb is properly aligned */
> + =A0 =A0 =A0 skb_align(new_skb, 32);
> +
> + =A0 =A0 =A0 /* Copy data to new skb ... */
> + =A0 =A0 =A0 skb_copy_from_linear_data(skb, new_skb->data, skb->len);
> + =A0 =A0 =A0 skb_put(new_skb, skb->len);
> +
> + =A0 =A0 =A0 /* ... and free an old one */
> + =A0 =A0 =A0 dev_kfree_skb_any(skb);
> +
> + =A0 =A0 =A0 return new_skb;
> +}
> +#else
> +#define tx_skb_align_workaround(dev, skb) (skb)
> +#endif

Another use of #ifdef blocks.  What is the multiplatform impact?

g.

--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.

Re: [PATCH 04/12] mpc5121: Added reset module registers representation.

[Grant Likely]

On Wed, May 6, 2009 at 2:15 PM, Wolfgang Denk <wd@denx.de> wrote:
> From: Piotr Ziecik <kosmo@semihalf.com>
>
> Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
> Signed-off-by: Wolfgang Denk <wd@denx.de>
> Cc: Grant Likely <grant.likely@secretlab.ca>
> Cc: John Rigby <jcrigby@gmail.com>

No patch description.  I would also like to see this patch merged with
the actual user of it since it is so small.

> ---
> =A0arch/powerpc/include/asm/mpc512x.h | =A0 13 +++++++++++++
> =A01 files changed, 13 insertions(+), 0 deletions(-)
>
> diff --git a/arch/powerpc/include/asm/mpc512x.h b/arch/powerpc/include/as=
m/mpc512x.h
> index c48a165..ea50d8d 100644
> --- a/arch/powerpc/include/asm/mpc512x.h
> +++ b/arch/powerpc/include/asm/mpc512x.h
> @@ -16,6 +16,19 @@
> =A0#ifndef __ASM_POWERPC_MPC512x_H__
> =A0#define __ASM_POWERPC_MPC512x_H__
>
> +/* MPC512x Reset module registers */
> +struct mpc512x_reset_module {
> + =A0 =A0 =A0 u32 =A0 =A0 rcwlr; =A0/* Reset Configuration Word Low Regis=
ter */
> + =A0 =A0 =A0 u32 =A0 =A0 rcwhr; =A0/* Reset Configuration Word High Regi=
ster */
> + =A0 =A0 =A0 u32 =A0 =A0 reserved1;
> + =A0 =A0 =A0 u32 =A0 =A0 reserved2;
> + =A0 =A0 =A0 u32 =A0 =A0 rsr; =A0 =A0/* Reset Status Register */
> + =A0 =A0 =A0 u32 =A0 =A0 rmr; =A0 =A0/* Reset Mode Register */
> + =A0 =A0 =A0 u32 =A0 =A0 rpr; =A0 =A0/* Reset Protection Register */
> + =A0 =A0 =A0 u32 =A0 =A0 rcr; =A0 =A0/* Reset Control Register */
> + =A0 =A0 =A0 u32 =A0 =A0 rcer; =A0 /* Reset Control Enable Register */
> +} __attribute__ ((__packed__));

__attribute__((__packed__)); is unnecessary.

g.

--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.

Re: [PATCH 05/12] mpc5121ads: Added Reset Module node to DTS.

[Grant Likely]

On Wed, May 6, 2009 at 2:15 PM, Wolfgang Denk <wd@denx.de> wrote:
> From: Piotr Ziecik <kosmo@semihalf.com>
>
> Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
> Signed-off-by: Wolfgang Denk <wd@denx.de>
> Cc: Grant Likely <grant.likely@secretlab.ca>
> Cc: John Rigby <jcrigby@gmail.com>

Missing patch description.  Otherwise looks okay.

g.

> ---
> =A0arch/powerpc/boot/dts/mpc5121ads.dts | =A0 =A05 +++++
> =A01 files changed, 5 insertions(+), 0 deletions(-)
>
> diff --git a/arch/powerpc/boot/dts/mpc5121ads.dts b/arch/powerpc/boot/dts=
/mpc5121ads.dts
> index c2b8dbf..1b83a9d 100644
> --- a/arch/powerpc/boot/dts/mpc5121ads.dts
> +++ b/arch/powerpc/boot/dts/mpc5121ads.dts
> @@ -166,6 +166,11 @@
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupt-parent =3D < &ip=
ic >;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0};
>
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 reset@e00 { =A0 =A0 // Reset module
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "fsl,mpc5121=
-reset";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0xe00 0x100>;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 };
> +
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0clock@f00 { =A0 =A0 // Clock control
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0compatible =3D "fsl,mpc512=
1-clock";
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0reg =3D <0xf00 0x100>;
> --
> 1.6.0.6
>
>



--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.

Re: [PATCH 02/12] fs_enet: Add MPC5121 FEC support.

[David Miller]

Would you be offended if I tell you that this is a horrible patch
submission?

Your introductory email indicates 16 patches, yet the series indicates
there were 12, and that intro email is only posted to the linuxppc-dev
list for people to read.  Nobody on netdev nor other interested
parties that get CC:'d along the line are able to read what this patch
series is about.

Since only some patches are CC:'d to netdev I have no idea if I should
apply these or they are dependent on some other patches in the series
that you didn't send here to netdev.

What a mess... how can any maintainer figure out what patch is what,
and what tree you expect these patches to even get applied to?

I'm definitely sending all of the copies I have received to /dev/null,
you need to submit this work properly.

Re: [PATCH 02/12] fs_enet: Add MPC5121 FEC support.

[Scott Wood]

Wolfgang Denk wrote:
> +/*
> + *	Define the buffer descriptor structure.
> + */
> +typedef struct bufdesc {
> +	ushort	cbd_sc;			/* Control and status info */
> +	ushort	cbd_datlen;		/* Data length */
> +	uint	cbd_bufaddr;		/* Buffer address */
> +} cbd_t;
> +
> +/*
> + *	The following definitions courtesy of commproc.h, which where
> + *	Copyright (c) 1997 Dan Malek (dmalek@jlc.net).
> + */
> +#define BD_SC_WRAP		((ushort)0x2000)
> +
> +/*
> + * Buffer descriptor control/status used by Ethernet receive.
> + */
> +#define BD_ENET_RX_EMPTY	((ushort)0x8000)
> +#define BD_ENET_RX_WRAP		((ushort)0x2000)
> +#define BD_ENET_RX_INTR		((ushort)0x1000)
> +#define BD_ENET_RX_LAST		((ushort)0x0800)
> +#define BD_ENET_RX_FIRST	((ushort)0x0400)
> +#define BD_ENET_RX_MISS		((ushort)0x0100)
> +#define BD_ENET_RX_LG		((ushort)0x0020)
> +#define BD_ENET_RX_NO		((ushort)0x0010)
> +#define BD_ENET_RX_SH		((ushort)0x0008)
> +#define BD_ENET_RX_CR		((ushort)0x0004)
> +#define BD_ENET_RX_OV		((ushort)0x0002)
> +#define BD_ENET_RX_CL		((ushort)0x0001)
> +#define BD_ENET_RX_STATS	((ushort)0x013f)	/* All status bits */
> +
> +/*
> + * Buffer descriptor control/status used by Ethernet transmit.
> + */
> +#define BD_ENET_TX_READY	((ushort)0x8000)
> +#define BD_ENET_TX_PAD		((ushort)0x4000)
> +#define BD_ENET_TX_WRAP		((ushort)0x2000)
> +#define BD_ENET_TX_INTR		((ushort)0x1000)
> +#define BD_ENET_TX_LAST		((ushort)0x0800)
> +#define BD_ENET_TX_TC		((ushort)0x0400)
> +#define BD_ENET_TX_DEF		((ushort)0x0200)
> +#define BD_ENET_TX_HB		((ushort)0x0100)
> +#define BD_ENET_TX_LC		((ushort)0x0080)
> +#define BD_ENET_TX_RL		((ushort)0x0040)
> +#define BD_ENET_TX_UN		((ushort)0x0002)
> +#define BD_ENET_TX_CSL		((ushort)0x0001)
> +#define BD_ENET_TX_STATS	((ushort)0x03ff)	/* All status bits */

All of the above is duplicative (with even the same names) of stuff in 
asm/cpm.h.  Beyond just the duplication, what happens if both CPM2 and 
512x are enabled in the same kernel?

-Scott

Re: [PATCH 06/12] mpc5121: Added NAND Flash Controller driver.

[Grant Likely]

On Wed, May 6, 2009 at 2:15 PM, Wolfgang Denk <wd@denx.de> wrote:
> From: Piotr Ziecik <kosmo@semihalf.com>
>
> This patch adds NAND Flash Controller driver for MPC5121
> revision 2. All device features, except hardware ECC and
> power management, are supported.
>
> Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
> Signed-off-by: Wolfgang Denk <wd@denx.de>
> Cc: <linux-mtd@lists.infradead.org>
> Cc: Grant Likely <grant.likely@secretlab.ca>
> Cc: John Rigby <jcrigby@gmail.com>
> ---
> =A0arch/powerpc/include/asm/mpc5121_nfc.h =A0 =A0 =A0 | =A0100 +++
> =A0arch/powerpc/platforms/512x/mpc512x_shared.c | =A0 =A01 +
> =A0drivers/mtd/nand/Kconfig =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 | =A0=
 =A07 +
> =A0drivers/mtd/nand/Makefile =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0=
 =A01 +
> =A0drivers/mtd/nand/mpc5121_nfc.c =A0 =A0 =A0 =A0 =A0 =A0 =A0 | =A0855 ++=
++++++++++++++++++++++++
> =A05 files changed, 964 insertions(+), 0 deletions(-)
> =A0create mode 100644 arch/powerpc/include/asm/mpc5121_nfc.h
> =A0create mode 100644 drivers/mtd/nand/mpc5121_nfc.c
>
> diff --git a/arch/powerpc/include/asm/mpc5121_nfc.h b/arch/powerpc/includ=
e/asm/mpc5121_nfc.h
> new file mode 100644
> index 0000000..b96a5b9
> --- /dev/null
> +++ b/arch/powerpc/include/asm/mpc5121_nfc.h
[... bunch of #defines trimmed]

There is only one user of this.  It should be moved into the driver .c
file.  Otherwise okay.

> diff --git a/arch/powerpc/platforms/512x/mpc512x_shared.c b/arch/powerpc/=
platforms/512x/mpc512x_shared.c
> index d8cd579..7135d89 100644
> --- a/arch/powerpc/platforms/512x/mpc512x_shared.c
> +++ b/arch/powerpc/platforms/512x/mpc512x_shared.c
> @@ -71,6 +71,7 @@ void __init mpc512x_init_IRQ(void)
> =A0static struct of_device_id __initdata of_bus_ids[] =3D {
> =A0 =A0 =A0 =A0{ .compatible =3D "fsl,mpc5121-immr", },
> =A0 =A0 =A0 =A0{ .compatible =3D "fsl,mpc5121-localbus", },
> + =A0 =A0 =A0 { .compatible =3D "fsl,mpc5121-nfc", },

This doesn't look right.  Shouldn't the NAND controller be hanging of
the IMMR node?

> =A0 =A0 =A0 =A0{},
> =A0};
>
> diff --git a/drivers/mtd/nand/mpc5121_nfc.c b/drivers/mtd/nand/mpc5121_nf=
c.c
> new file mode 100644
> index 0000000..a8da4db
> --- /dev/null
> +++ b/drivers/mtd/nand/mpc5121_nfc.c
> @@ -0,0 +1,855 @@
> +/*
> + * Copyright 2004-2008 Freescale Semiconductor, Inc.
> + * Copyright 2009 Semihalf.
> + *
> + * Based on original driver from Freescale Semiconductor
> + * written by John Rigby <jrigby@freescale.com> on basis
> + * of drivers/mtd/nand/mxc_nand.c. Reworked and extended
> + * Piotr Ziecik <kosmo@semihalf.com>.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version 2
> + * of the License, or (at your option) any later version.
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301, USA.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/init.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/mtd/mtd.h>
> +#include <linux/mtd/nand.h>
> +#include <linux/mtd/partitions.h>
> +#include <linux/of_device.h>
> +#include <linux/of_platform.h>
> +
> +#include <asm/mpc512x.h>
> +#include <asm/mpc5121_nfc.h>
> +
> +#define =A0 =A0 =A0 =A0DRV_NAME =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0"mpc5121_=
nfc"
> +#define =A0 =A0 =A0 =A0DRV_VERSION =A0 =A0 =A0 =A0 =A0 =A0 "0.5"

Is this really necessary (especially the DRV_VERSION thing)?

> +/* Wait for operation complete */
> +static void mpc5121_nfc_done(struct mtd_info *mtd)
> +{
> + =A0 =A0 =A0 struct nand_chip *chip =3D mtd->priv;
> + =A0 =A0 =A0 struct mpc5121_nfc_prv *prv =3D chip->priv;
> + =A0 =A0 =A0 int rv;
> +
> + =A0 =A0 =A0 if ((nfc_read(mtd, NFC_CONFIG2) & NFC_INT) =3D=3D 0) {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 nfc_clear(mtd, NFC_CONFIG1, NFC_INT_MASK);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 rv =3D wait_event_timeout(prv->irq_waitq,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 (nfc_read(mtd, NFC_CONFIG2)=
 & NFC_INT), NFC_TIMEOUT);
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (!rv)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 printk(KERN_WARNING DRV_NAM=
E

Throughout this driver printk() calls should really be dev_*() calls.

> +/*
> + * Read NFC configuration from Reset Config Word
> + *
> + * NFC is configured during reset in basis of information stored
> + * in Reset Config Word. There is no other way to set NAND block
> + * size, spare size and bus width.
> + */
> +static int mpc5121_nfc_read_hw_config(struct mtd_info *mtd)
> +{
> + =A0 =A0 =A0 struct nand_chip *chip =3D mtd->priv;
> + =A0 =A0 =A0 struct mpc512x_reset_module *rm;
> + =A0 =A0 =A0 struct device_node *rmnode;
> + =A0 =A0 =A0 uint rcw_pagesize =3D 0;
> + =A0 =A0 =A0 uint rcw_sparesize =3D 0;
> + =A0 =A0 =A0 uint rcw_width;
> + =A0 =A0 =A0 uint rcwh;
> + =A0 =A0 =A0 uint romloc, ps;
> +
> + =A0 =A0 =A0 rmnode =3D of_find_compatible_node(NULL, NULL, "fsl,mpc5121=
-reset");
> + =A0 =A0 =A0 if (!rmnode) {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 printk(KERN_ERR DRV_NAME ": Missing 'fsl,mp=
c5121-reset' "
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 "node in device tree!\n");
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 return -ENODEV;
> + =A0 =A0 =A0 }

A little ugly, but I won't gripe too much about it.  I'd rather see a
platform code export some kind of api for manipulating the reset
module (I assume that multiple drivers will need to fiddle with it),
but I'm willing to be pragmatic here in the interest of getting it
merged.  It can always be reworked later with little risk.

> +static struct of_platform_driver mpc5121_nfc_driver =3D {
> + =A0 =A0 =A0 .owner =A0 =A0 =A0 =A0 =A0=3D THIS_MODULE,
> + =A0 =A0 =A0 .name =A0 =A0 =A0 =A0 =A0 =3D DRV_NAME,
> + =A0 =A0 =A0 .match_table =A0 =A0=3D mpc5121_nfc_match,
> + =A0 =A0 =A0 .probe =A0 =A0 =A0 =A0 =A0=3D mpc5121_nfc_probe,
> + =A0 =A0 =A0 .remove =A0 =A0 =A0 =A0 =3D __exit_p(mpc5121_nfc_remove),
> + =A0 =A0 =A0 .suspend =A0 =A0 =A0 =A0=3D NULL,
> + =A0 =A0 =A0 .resume =A0 =A0 =A0 =A0 =3D NULL,

2 unnecessary lines.  gcc initializes unset fields to 0.

> + =A0 =A0 =A0 .driver =A0 =A0 =A0 =A0 =3D {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 .name =A0 =3D DRV_NAME,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 .owner =A0=3D THIS_MODULE,
> + =A0 =A0 =A0 },

Duplicate settings.  Don't need to set both .name/.owner and
.driver.name and .driver.owner.

> +};
> +
> +static int __init mpc5121_nfc_init(void)
> +{
> + =A0 =A0 =A0 if (of_register_platform_driver(&mpc5121_nfc_driver) !=3D 0=
) {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 printk(KERN_ERR DRV_NAME ": Driver register=
 failed!\n");
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 return -ENODEV;
> + =A0 =A0 =A0 }
> + =A0 =A0 =A0 return 0;

Heh.  "return of_register_platform_driver(&mpc5121_nfc_driver);" is
sufficient and accepted here.

> +}
> +
> +static void __exit mpc5121_nfc_cleanup(void)
> +{
> + =A0 =A0 =A0 of_unregister_platform_driver(&mpc5121_nfc_driver);
> +}
> +
> +module_init(mpc5121_nfc_init);

Please move this line to just below the mpc5121_nfc_init function.

> +module_exit(mpc5121_nfc_cleanup);
> +
> +MODULE_AUTHOR("Freescale Semiconductor, Inc.");
> +MODULE_DESCRIPTION("MPC5121 NAND MTD driver");
> +MODULE_LICENSE("GPL");
> +MODULE_VERSION(DRV_VERSION);

As I alluded to above, I really don't like the MODULE_VERSION think in
mainline code.

I only skimmed the driver, but that being said, other than my comments
it looks pretty good to me.

g.


--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.

Re: [PATCH 07/12] mpc5121ads: Clean up and fix NAND description in mpc5121ads DTS.

[Grant Likely]

On Wed, May 6, 2009 at 2:15 PM, Wolfgang Denk <wd@denx.de> wrote:
> From: Piotr Ziecik <kosmo@semihalf.com>
>
> - Removed unused properties.
> - Corrected NAND flash chip size.
>
> Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
> Signed-off-by: Wolfgang Denk <wd@denx.de>
> Cc: Grant Likely <grant.likely@secretlab.ca>
> Cc: John Rigby <jcrigby@gmail.com>

Looks okay to me.

g.

> ---
> =A0arch/powerpc/boot/dts/mpc5121ads.dts | =A0 13 ++++---------
> =A01 files changed, 4 insertions(+), 9 deletions(-)
>
> diff --git a/arch/powerpc/boot/dts/mpc5121ads.dts b/arch/powerpc/boot/dts=
/mpc5121ads.dts
> index 1b83a9d..93fe12a 100644
> --- a/arch/powerpc/boot/dts/mpc5121ads.dts
> +++ b/arch/powerpc/boot/dts/mpc5121ads.dts
> @@ -62,17 +62,12 @@
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupt-parent =3D < &ipic >;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0#address-cells =3D <1>;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0#size-cells =3D <1>;
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 bank-width =3D <1>;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0// ADS has two Hynix 512MB Nand flash chip=
s in a single
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 // stacked package .
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 // stacked package.
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0chips =3D <2>;
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 nand0@0 {
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 label =3D "nand0";
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x00000000 0x02000=
000>; =A0// first 32 MB of chip 0
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 };
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 nand1@20000000 {
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 label =3D "nand1";
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x20000000 0x02000=
000>; =A0// first 32 MB of chip 1
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 nand@0 {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 label =3D "nand";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x00000000 0x40000=
000>; =A0// 512MB + 512MB
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0};
> =A0 =A0 =A0 =A0};
>
> --
> 1.6.0.6
>
>



--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.

Re: [PATCH 08/12] mpc5121: Added I2C support.

[Grant Likely]

On Wed, May 6, 2009 at 2:15 PM, Wolfgang Denk <wd@denx.de> wrote:
> From: Piotr Ziecik <kosmo@semihalf.com>
>
> - Enabled I2C interrupts on MPC5121.
> - Updated Kconfig for i2c-mpc driver.

I think this workaround belongs in the driver itself.

g.

>
> Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
> Signed-off-by: Wolfgang Denk <wd@denx.de>
> Cc: <linux-i2c@vger.kernel.org>
> Cc: Grant Likely <grant.likely@secretlab.ca>
> Cc: John Rigby <jcrigby@gmail.com>
> ---
> =A0arch/powerpc/platforms/512x/mpc5121_ads.c =A0 =A0| =A0 =A02 ++
> =A0arch/powerpc/platforms/512x/mpc512x.h =A0 =A0 =A0 =A0| =A0 =A01 +
> =A0arch/powerpc/platforms/512x/mpc512x_shared.c | =A0 24 ++++++++++++++++=
++++++++
> =A0drivers/i2c/busses/Kconfig =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 | =A0 =
=A09 +++++----
> =A04 files changed, 32 insertions(+), 4 deletions(-)
>
> diff --git a/arch/powerpc/platforms/512x/mpc5121_ads.c b/arch/powerpc/pla=
tforms/512x/mpc5121_ads.c
> index 441abc4..a8976b4 100644
> --- a/arch/powerpc/platforms/512x/mpc5121_ads.c
> +++ b/arch/powerpc/platforms/512x/mpc5121_ads.c
> @@ -42,6 +42,8 @@ static void __init mpc5121_ads_setup_arch(void)
> =A0 =A0 =A0 =A0for_each_compatible_node(np, "pci", "fsl,mpc5121-pci")
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0mpc83xx_add_bridge(np);
> =A0#endif
> +
> + =A0 =A0 =A0 mpc512x_init_i2c();
> =A0}
>
> =A0static void __init mpc5121_ads_init_IRQ(void)
> diff --git a/arch/powerpc/platforms/512x/mpc512x.h b/arch/powerpc/platfor=
ms/512x/mpc512x.h
> index 9c03693..f4db8a7 100644
> --- a/arch/powerpc/platforms/512x/mpc512x.h
> +++ b/arch/powerpc/platforms/512x/mpc512x.h
> @@ -13,5 +13,6 @@
> =A0#define __MPC512X_H__
> =A0extern unsigned long mpc512x_find_ips_freq(struct device_node *node);
> =A0extern void __init mpc512x_init_IRQ(void);
> +extern void __init mpc512x_init_i2c(void);
> =A0void __init mpc512x_declare_of_platform_devices(void);
> =A0#endif =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* __MPC512X_H_=
_ */
> diff --git a/arch/powerpc/platforms/512x/mpc512x_shared.c b/arch/powerpc/=
platforms/512x/mpc512x_shared.c
> index 7135d89..b776e45 100644
> --- a/arch/powerpc/platforms/512x/mpc512x_shared.c
> +++ b/arch/powerpc/platforms/512x/mpc512x_shared.c
> @@ -65,6 +65,30 @@ void __init mpc512x_init_IRQ(void)
> =A0 =A0 =A0 =A0ipic_set_default_priority();
> =A0}
>
> +void __init mpc512x_init_i2c(void)
> +{
> + =A0 =A0 =A0 struct device_node *np;
> + =A0 =A0 =A0 void __iomem *i2cctl;
> +
> + =A0 =A0 =A0 /* Enable I2C interrupts */
> + =A0 =A0 =A0 np =3D of_find_compatible_node(NULL, NULL, "fsl,mpc5121-i2c=
-ctrl");
> + =A0 =A0 =A0 if (np) {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 i2cctl =3D of_iomap(np, 0);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (i2cctl) {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 /*
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0* Set interrupt enable b=
its:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0* =A0- I2C-0: bit 24,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0* =A0- I2C-1: bit 26,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0* =A0- I2C-2: bit 28.
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0*/
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 out_be32(i2cctl, 0x15000000=
);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 iounmap(i2cctl);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 }
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 of_node_put(np);
> + =A0 =A0 =A0 }
> +}
> +
> =A0/*
> =A0* Nodes to do bus probe on, soc and localbus
> =A0*/
> diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
> index a48c8ae..57ed637 100644
> --- a/drivers/i2c/busses/Kconfig
> +++ b/drivers/i2c/busses/Kconfig
> @@ -391,13 +391,14 @@ config I2C_IXP2000
> =A0 =A0 =A0 =A0 =A0instead.
>
> =A0config I2C_MPC
> - =A0 =A0 =A0 tristate "MPC107/824x/85xx/52xx/86xx"
> + =A0 =A0 =A0 tristate "MPC107/824x/85xx/512x/52xx/86xx"
> =A0 =A0 =A0 =A0depends on PPC32
> =A0 =A0 =A0 =A0help
> =A0 =A0 =A0 =A0 =A0If you say yes to this option, support will be include=
d for the
> - =A0 =A0 =A0 =A0 built-in I2C interface on the MPC107/Tsi107/MPC8240/MPC=
8245 and
> - =A0 =A0 =A0 =A0 MPC85xx/MPC8641 family processors. The driver may also =
work on 52xx
> - =A0 =A0 =A0 =A0 family processors, though interrupts are known not to w=
ork.
> + =A0 =A0 =A0 =A0 built-in I2C interface on the MPC107/Tsi107/MPC8240/MPC=
8245,
> + =A0 =A0 =A0 =A0 MPC85xx/MPC8641 and MPC512x family processors. The driv=
er may
> + =A0 =A0 =A0 =A0 also work on 52xx family processors, though interrupts =
are known
> + =A0 =A0 =A0 =A0 not to work.
>
> =A0 =A0 =A0 =A0 =A0This driver can also be built as a module. =A0If so, t=
he module
> =A0 =A0 =A0 =A0 =A0will be called i2c-mpc.
> --
> 1.6.0.6
>
>



--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.

Re: [PATCH 09/12] mpc5121ads: Added I2C RTC node to mpc5121ads DTS.

[Grant Likely]

On Wed, May 6, 2009 at 2:15 PM, Wolfgang Denk <wd@denx.de> wrote:
> From: Piotr Ziecik <kosmo@semihalf.com>
>
> Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
> Signed-off-by: Wolfgang Denk <wd@denx.de>
> Cc: Grant Likely <grant.likely@secretlab.ca>

Acked-by: Grant Likely <grant.likely@secretlab.ca>

> Cc: John Rigby <jcrigby@gmail.com>
> ---
> =A0arch/powerpc/boot/dts/mpc5121ads.dts | =A0 =A05 +++++
> =A01 files changed, 5 insertions(+), 0 deletions(-)
>
> diff --git a/arch/powerpc/boot/dts/mpc5121ads.dts b/arch/powerpc/boot/dts=
/mpc5121ads.dts
> index 93fe12a..c2d9de9 100644
> --- a/arch/powerpc/boot/dts/mpc5121ads.dts
> +++ b/arch/powerpc/boot/dts/mpc5121ads.dts
> @@ -210,6 +210,11 @@
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupts =3D <9 0x8>;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupt-parent =3D < &ip=
ic >;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0fsl5200-clocking;
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 rtc@68 {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =
=3D "stm,m41t80";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 reg =3D <0x=
68>;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 };
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0};
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0i2c@1720 {
> --
> 1.6.0.6
>
>



--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.

Re: [PATCH 10/12] mpc5121: Add MPC5121 Real time clock driver.

[Grant Likely]

On Wed, May 6, 2009 at 2:15 PM, Wolfgang Denk <wd@denx.de> wrote:
> From: John Rigby <jrigby@freescale.com>
>
> Based on Domen Puncer's rtc driver for 5200 posted to
> the ppclinux mailing list:
> =A0 =A0 =A0 =A0http://patchwork.ozlabs.org/linuxppc-embedded/patch?id=3D1=
1675
> but never commited anywhere.
>
> Changes to Domen's original:
>
> =A0 =A0Changed filenames/routine names from mpc5200* to mpc5121*
> =A0 =A0Changed match to only care about compatible and use "fsl,"
> =A0 =A0convention for compatible.
>
> =A0 =A0Make alarms more sane by dealing with lack of second alarm resolut=
ion.
>
> =A0 =A0Deal with the fact that most of the 5121 rtc registers are not per=
sistent
> =A0 =A0across a reset even with a battery attached:
>
> =A0 =A0 =A0 =A0Use actual_time register for time keeping
> =A0 =A0 =A0 =A0and target_time register as an offset to linux time
>
> =A0 =A0 =A0 =A0The target_time register would normally be used for hibern=
ation
> =A0 =A0 =A0 =A0but hibernation does not work on current silicon
>
> Signed-off-by: John Rigby <jrigby@freescale.com>
> Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
> Signed-off-by: Wolfgang Denk <wd@denx.de>
> Cc: <rtc-linux@googlegroups.com>
> Cc: Grant Likely <grant.likely@secretlab.ca>
> Cc: John Rigby <jcrigby@gmail.com>

On a *very* cursory review, I don't see anything here I object to.
And it does not look dangerous.

Acked-by: Grant Likely <grant.likely@secretlab.ca>

> ---
> =A0drivers/rtc/Kconfig =A0 =A0 =A0 | =A0 10 +
> =A0drivers/rtc/Makefile =A0 =A0 =A0| =A0 =A01 +
> =A0drivers/rtc/rtc-mpc5121.c | =A0408 +++++++++++++++++++++++++++++++++++=
++++++++++
> =A03 files changed, 419 insertions(+), 0 deletions(-)
> =A0create mode 100644 drivers/rtc/rtc-mpc5121.c
>
> diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
> index 4e9851f..900d5b8 100644
> --- a/drivers/rtc/Kconfig
> +++ b/drivers/rtc/Kconfig
> @@ -750,4 +750,14 @@ config RTC_DRV_PS3
> =A0 =A0 =A0 =A0 =A0This driver can also be built as a module. If so, the =
module
> =A0 =A0 =A0 =A0 =A0will be called rtc-ps3.
>
> +config RTC_DRV_MPC5121
> + =A0 =A0 =A0 tristate "Freescale MPC5121 built-in RTC"
> + =A0 =A0 =A0 depends on RTC_CLASS
> + =A0 =A0 =A0 help
> + =A0 =A0 =A0 =A0 If you say yes here you will get support for the
> + =A0 =A0 =A0 =A0 built-in RTC MPC5121.
> +
> + =A0 =A0 =A0 =A0 This driver can also be built as a module. If so, the m=
odule
> + =A0 =A0 =A0 =A0 will be called rtc-mpc5121.
> +
> =A0endif # RTC_CLASS
> diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
> index 6c0639a..8c6d6a7 100644
> --- a/drivers/rtc/Makefile
> +++ b/drivers/rtc/Makefile
> @@ -51,6 +51,7 @@ obj-$(CONFIG_RTC_DRV_STARFIRE) =A0 =A0 =A0 =A0+=3D rtc-=
starfire.o
> =A0obj-$(CONFIG_RTC_DRV_MAX6900) =A0+=3D rtc-max6900.o
> =A0obj-$(CONFIG_RTC_DRV_MAX6902) =A0+=3D rtc-max6902.o
> =A0obj-$(CONFIG_RTC_DRV_MV) =A0 =A0 =A0 +=3D rtc-mv.o
> +obj-$(CONFIG_RTC_DRV_MPC5121) =A0+=3D rtc-mpc5121.o
> =A0obj-$(CONFIG_RTC_DRV_OMAP) =A0 =A0 +=3D rtc-omap.o
> =A0obj-$(CONFIG_RTC_DRV_PCF8563) =A0+=3D rtc-pcf8563.o
> =A0obj-$(CONFIG_RTC_DRV_PCF8583) =A0+=3D rtc-pcf8583.o
> diff --git a/drivers/rtc/rtc-mpc5121.c b/drivers/rtc/rtc-mpc5121.c
> new file mode 100644
> index 0000000..63460cb
> --- /dev/null
> +++ b/drivers/rtc/rtc-mpc5121.c
> @@ -0,0 +1,408 @@
> +/*
> + * Real-time clock driver for MPC5121
> + *
> + * Copyright 2007, Domen Puncer <domen.puncer@telargo.com>
> + * Copyright 2008, Freescale Semiconductor, Inc. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +/*
> + * History:
> + *
> + * Based on mpc5200_rtc.c written by Domen Puncer <domen.puncer@telargo.=
com>
> + * =A0 posted to linuxppc-embedded mailing list:
> + * =A0 =A0 http://patchwork.ozlabs.org/linuxppc-embedded/patch?id=3D1167=
5
> + * =A0 but never committed to any public tree.
> + *
> + * Author: John Rigby <jrigby@freescale.com>
> + * =A0 Converted to 5121 rtc driver.
> + *
> + * =A0 Make alarms more sane by dealing with lack of second alarm resolu=
tion.
> + *
> + * =A0 Use actual_time time register for time keeping since it is persis=
tent
> + * =A0 and the normal rtc registers are not. =A0Use target_time register=
 as an
> + * =A0 offset to linux time.
> + *
> + */
> +
> +#include <linux/module.h>
> +#include <linux/rtc.h>
> +#include <linux/of_device.h>
> +#include <linux/of_platform.h>
> +#include <linux/io.h>
> +
> +struct mpc5121_rtc_regs {
> + =A0 =A0 =A0 u8 set_time; =A0 =A0 =A0 =A0 =A0 =A0/* RTC + 0x00 */
> + =A0 =A0 =A0 u8 hour_set; =A0 =A0 =A0 =A0 =A0 =A0/* RTC + 0x01 */
> + =A0 =A0 =A0 u8 minute_set; =A0 =A0 =A0 =A0 =A0/* RTC + 0x02 */
> + =A0 =A0 =A0 u8 second_set; =A0 =A0 =A0 =A0 =A0/* RTC + 0x03 */
> +
> + =A0 =A0 =A0 u8 set_date; =A0 =A0 =A0 =A0 =A0 =A0/* RTC + 0x04 */
> + =A0 =A0 =A0 u8 month_set; =A0 =A0 =A0 =A0 =A0 /* RTC + 0x05 */
> + =A0 =A0 =A0 u8 weekday_set; =A0 =A0 =A0 =A0 /* RTC + 0x06 */
> + =A0 =A0 =A0 u8 date_set; =A0 =A0 =A0 =A0 =A0 =A0/* RTC + 0x07 */
> +
> + =A0 =A0 =A0 u8 write_sw; =A0 =A0 =A0 =A0 =A0 =A0/* RTC + 0x08 */
> + =A0 =A0 =A0 u8 sw_set; =A0 =A0 =A0 =A0 =A0 =A0 =A0/* RTC + 0x09 */
> + =A0 =A0 =A0 u16 year_set; =A0 =A0 =A0 =A0 =A0 /* RTC + 0x0a */
> +
> + =A0 =A0 =A0 u8 alm_enable; =A0 =A0 =A0 =A0 =A0/* RTC + 0x0c */
> + =A0 =A0 =A0 u8 alm_hour_set; =A0 =A0 =A0 =A0/* RTC + 0x0d */
> + =A0 =A0 =A0 u8 alm_min_set; =A0 =A0 =A0 =A0 /* RTC + 0x0e */
> + =A0 =A0 =A0 u8 int_enable; =A0 =A0 =A0 =A0 =A0/* RTC + 0x0f */
> +
> + =A0 =A0 =A0 u8 reserved1;
> + =A0 =A0 =A0 u8 hour; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0/* RTC + 0x11 */
> + =A0 =A0 =A0 u8 minute; =A0 =A0 =A0 =A0 =A0 =A0 =A0/* RTC + 0x12 */
> + =A0 =A0 =A0 u8 second; =A0 =A0 =A0 =A0 =A0 =A0 =A0/* RTC + 0x13 */
> +
> + =A0 =A0 =A0 u8 month; =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* RTC + 0x14 */
> + =A0 =A0 =A0 u8 wday_mday; =A0 =A0 =A0 =A0 =A0 /* RTC + 0x15 */
> + =A0 =A0 =A0 u16 year; =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* RTC + 0x16 */
> +
> + =A0 =A0 =A0 u8 int_alm; =A0 =A0 =A0 =A0 =A0 =A0 /* RTC + 0x18 */
> + =A0 =A0 =A0 u8 int_sw; =A0 =A0 =A0 =A0 =A0 =A0 =A0/* RTC + 0x19 */
> + =A0 =A0 =A0 u8 alm_status; =A0 =A0 =A0 =A0 =A0/* RTC + 0x1a */
> + =A0 =A0 =A0 u8 sw_minute; =A0 =A0 =A0 =A0 =A0 /* RTC + 0x1b */
> +
> + =A0 =A0 =A0 u8 bus_error_1; =A0 =A0 =A0 =A0 /* RTC + 0x1c */
> + =A0 =A0 =A0 u8 int_day; =A0 =A0 =A0 =A0 =A0 =A0 /* RTC + 0x1d */
> + =A0 =A0 =A0 u8 int_min; =A0 =A0 =A0 =A0 =A0 =A0 /* RTC + 0x1e */
> + =A0 =A0 =A0 u8 int_sec; =A0 =A0 =A0 =A0 =A0 =A0 /* RTC + 0x1f */
> +
> + =A0 =A0 =A0 /*
> + =A0 =A0 =A0 =A0* target_time:
> + =A0 =A0 =A0 =A0* =A0 =A0 =A0intended to be used for hibernation but hib=
ernation
> + =A0 =A0 =A0 =A0* =A0 =A0 =A0does not work on silicon rev 1.5 so use it =
for non-volatile
> + =A0 =A0 =A0 =A0* =A0 =A0 =A0storage of offset between the actual_time r=
egister and linux
> + =A0 =A0 =A0 =A0* =A0 =A0 =A0time
> + =A0 =A0 =A0 =A0*/
> + =A0 =A0 =A0 u32 target_time; =A0 =A0 =A0 =A0/* RTC + 0x20 */
> + =A0 =A0 =A0 /*
> + =A0 =A0 =A0 =A0* actual_time:
> + =A0 =A0 =A0 =A0* =A0 =A0 =A0readonly time since VBAT_RTC was last conne=
cted
> + =A0 =A0 =A0 =A0*/
> + =A0 =A0 =A0 u32 actual_time; =A0 =A0 =A0 =A0/* RTC + 0x24 */
> + =A0 =A0 =A0 u32 keep_alive; =A0 =A0 =A0 =A0 /* RTC + 0x28 */
> +};
> +
> +struct mpc5121_rtc_data {
> + =A0 =A0 =A0 unsigned irq;
> + =A0 =A0 =A0 unsigned irq_periodic;
> + =A0 =A0 =A0 struct mpc5121_rtc_regs __iomem *regs;
> + =A0 =A0 =A0 struct rtc_device *rtc;
> + =A0 =A0 =A0 struct rtc_wkalrm wkalarm;
> +};
> +
> +/*
> + * Update second/minute/hour registers.
> + *
> + * This is just so alarm will work.
> + */
> +static void mpc5121_rtc_update_smh(struct mpc5121_rtc_regs __iomem *regs=
,
> + =A0 =A0 =A0 struct rtc_time *tm)
> +{
> + =A0 =A0 =A0 out_8(&regs->second_set, tm->tm_sec);
> + =A0 =A0 =A0 out_8(&regs->minute_set, tm->tm_min);
> + =A0 =A0 =A0 out_8(&regs->hour_set, tm->tm_hour);
> +
> + =A0 =A0 =A0 /* set time sequence */
> + =A0 =A0 =A0 out_8(&regs->set_time, 0x1);
> + =A0 =A0 =A0 out_8(&regs->set_time, 0x3);
> + =A0 =A0 =A0 out_8(&regs->set_time, 0x1);
> + =A0 =A0 =A0 out_8(&regs->set_time, 0x0);
> +}
> +
> +static int mpc5121_rtc_read_time(struct device *dev, struct rtc_time *tm=
)
> +{
> + =A0 =A0 =A0 struct mpc5121_rtc_data *rtc =3D dev_get_drvdata(dev);
> + =A0 =A0 =A0 struct mpc5121_rtc_regs __iomem *regs =3D rtc->regs;
> + =A0 =A0 =A0 unsigned long now;
> +
> + =A0 =A0 =A0 /*
> + =A0 =A0 =A0 =A0* linux time is actual_time plus the offset saved in tar=
get_time
> + =A0 =A0 =A0 =A0*/
> + =A0 =A0 =A0 now =3D in_be32(&regs->actual_time) + in_be32(&regs->target=
_time);
> +
> + =A0 =A0 =A0 rtc_time_to_tm(now, tm);
> +
> + =A0 =A0 =A0 /*
> + =A0 =A0 =A0 =A0* update second minute hour registers
> + =A0 =A0 =A0 =A0* so alarms will work
> + =A0 =A0 =A0 =A0*/
> + =A0 =A0 =A0 mpc5121_rtc_update_smh(regs, tm);
> +
> + =A0 =A0 =A0 return 0;
> +}
> +
> +static int mpc5121_rtc_set_time(struct device *dev, struct rtc_time *tm)
> +{
> + =A0 =A0 =A0 struct mpc5121_rtc_data *rtc =3D dev_get_drvdata(dev);
> + =A0 =A0 =A0 struct mpc5121_rtc_regs __iomem *regs =3D rtc->regs;
> + =A0 =A0 =A0 int ret;
> + =A0 =A0 =A0 unsigned long now;
> +
> +
> + =A0 =A0 =A0 /*
> + =A0 =A0 =A0 =A0* The actual_time register is read only so we write the =
offset
> + =A0 =A0 =A0 =A0* between it and linux time to the target_time register.
> + =A0 =A0 =A0 =A0*/
> + =A0 =A0 =A0 ret =3D rtc_tm_to_time(tm, &now);
> + =A0 =A0 =A0 if (ret =3D=3D 0)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 out_be32(&regs->target_time, now - in_be32(=
&regs->actual_time));
> +
> + =A0 =A0 =A0 /*
> + =A0 =A0 =A0 =A0* update second minute hour registers
> + =A0 =A0 =A0 =A0* so alarms will work
> + =A0 =A0 =A0 =A0*/
> + =A0 =A0 =A0 mpc5121_rtc_update_smh(regs, tm);
> +
> + =A0 =A0 =A0 return 0;
> +}
> +
> +static int mpc5121_rtc_read_alarm(struct device *dev, struct rtc_wkalrm =
*alarm)
> +{
> + =A0 =A0 =A0 struct mpc5121_rtc_data *rtc =3D dev_get_drvdata(dev);
> + =A0 =A0 =A0 struct mpc5121_rtc_regs __iomem *regs =3D rtc->regs;
> +
> + =A0 =A0 =A0 *alarm =3D rtc->wkalarm;
> +
> + =A0 =A0 =A0 alarm->pending =3D in_8(&regs->alm_status);
> +
> + =A0 =A0 =A0 return 0;
> +}
> +
> +static int mpc5121_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *=
alarm)
> +{
> + =A0 =A0 =A0 struct mpc5121_rtc_data *rtc =3D dev_get_drvdata(dev);
> + =A0 =A0 =A0 struct mpc5121_rtc_regs __iomem *regs =3D rtc->regs;
> +
> + =A0 =A0 =A0 /*
> + =A0 =A0 =A0 =A0* the alarm has no seconds so deal with it
> + =A0 =A0 =A0 =A0*/
> + =A0 =A0 =A0 if (alarm->time.tm_sec) {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 alarm->time.tm_sec =3D 0;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 alarm->time.tm_min++;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (alarm->time.tm_min >=3D 60) {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 alarm->time.tm_min =3D 0;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 alarm->time.tm_hour++;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if (alarm->time.tm_hour >=
=3D 24)
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 alarm->time=
.tm_hour =3D 0;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 }
> + =A0 =A0 =A0 }
> +
> + =A0 =A0 =A0 alarm->time.tm_mday =3D -1;
> + =A0 =A0 =A0 alarm->time.tm_mon =3D -1;
> + =A0 =A0 =A0 alarm->time.tm_year =3D -1;
> +
> + =A0 =A0 =A0 out_8(&regs->alm_min_set, alarm->time.tm_min);
> + =A0 =A0 =A0 out_8(&regs->alm_hour_set, alarm->time.tm_hour);
> +
> + =A0 =A0 =A0 out_8(&regs->alm_enable, alarm->enabled);
> +
> + =A0 =A0 =A0 rtc->wkalarm =3D *alarm;
> + =A0 =A0 =A0 return 0;
> +}
> +
> +static irqreturn_t mpc5121_rtc_handler(int irq, void *dev)
> +{
> + =A0 =A0 =A0 struct mpc5121_rtc_data *rtc =3D dev_get_drvdata((struct de=
vice *)dev);
> + =A0 =A0 =A0 struct mpc5121_rtc_regs __iomem *regs =3D rtc->regs;
> +
> + =A0 =A0 =A0 if (in_8(&regs->int_alm)) {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* acknowledge and clear status */
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 out_8(&regs->int_alm, 1);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 out_8(&regs->alm_status, 1);
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 rtc_update_irq(rtc->rtc, 1, RTC_IRQF | RTC_=
AF);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 return IRQ_HANDLED;
> + =A0 =A0 =A0 }
> +
> + =A0 =A0 =A0 return IRQ_NONE;
> +}
> +
> +static irqreturn_t mpc5121_rtc_handler_upd(int irq, void *dev)
> +{
> + =A0 =A0 =A0 struct mpc5121_rtc_data *rtc =3D dev_get_drvdata((struct de=
vice *)dev);
> + =A0 =A0 =A0 struct mpc5121_rtc_regs __iomem *regs =3D rtc->regs;
> +
> + =A0 =A0 =A0 if (in_8(&regs->int_sec) && (in_8(&regs->int_enable) & 0x1)=
) {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* acknowledge */
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 out_8(&regs->int_sec, 1);
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 rtc_update_irq(rtc->rtc, 1, RTC_IRQF | RTC_=
UF);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 return IRQ_HANDLED;
> + =A0 =A0 =A0 }
> +
> + =A0 =A0 =A0 return IRQ_NONE;
> +}
> +
> +static int mpc5121_rtc_ioctl(struct device *dev, unsigned int cmd,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 unsigned long arg)
> +{
> + =A0 =A0 =A0 struct mpc5121_rtc_data *rtc =3D dev_get_drvdata(dev);
> + =A0 =A0 =A0 struct mpc5121_rtc_regs __iomem *regs =3D rtc->regs;
> +
> + =A0 =A0 =A0 switch (cmd) {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* alarm interrupt */
> + =A0 =A0 =A0 case RTC_AIE_ON:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 out_8(&regs->alm_enable, 1);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 rtc->wkalarm.enabled =3D 1;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 break;
> + =A0 =A0 =A0 case RTC_AIE_OFF:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 out_8(&regs->alm_enable, 0);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 rtc->wkalarm.enabled =3D 0;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 break;
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* update interrupt */
> + =A0 =A0 =A0 case RTC_UIE_ON:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 out_8(&regs->int_enable,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 (in_8(&regs=
->int_enable) & ~0x8) | 0x1);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 break;
> + =A0 =A0 =A0 case RTC_UIE_OFF:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 out_8(&regs->int_enable, in_8(&regs->int_en=
able) & ~0x1);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 break;
> +
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 /* no periodic interrupts */
> + =A0 =A0 =A0 case RTC_IRQP_READ:
> + =A0 =A0 =A0 case RTC_IRQP_SET:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 return -ENOTTY;
> +
> + =A0 =A0 =A0 default:
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 return -ENOIOCTLCMD;
> + =A0 =A0 =A0 }
> + =A0 =A0 =A0 return 0;
> +}
> +
> +static const struct rtc_class_ops mpc5121_rtc_ops =3D {
> + =A0 =A0 =A0 .read_time =3D mpc5121_rtc_read_time,
> + =A0 =A0 =A0 .set_time =3D mpc5121_rtc_set_time,
> + =A0 =A0 =A0 .read_alarm =3D mpc5121_rtc_read_alarm,
> + =A0 =A0 =A0 .set_alarm =3D mpc5121_rtc_set_alarm,
> + =A0 =A0 =A0 .ioctl =3D mpc5121_rtc_ioctl,
> +};
> +
> +static int __devinit mpc5121_rtc_probe(struct of_device *op,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 const struct of_device_id *match)
> +{
> + =A0 =A0 =A0 struct mpc5121_rtc_data *rtc;
> + =A0 =A0 =A0 int err =3D 0;
> + =A0 =A0 =A0 u32 ka;
> +
> + =A0 =A0 =A0 rtc =3D kzalloc(sizeof(*rtc), GFP_KERNEL);
> + =A0 =A0 =A0 if (!rtc) {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 err =3D -ENOMEM;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 goto out;
> + =A0 =A0 =A0 }
> +
> + =A0 =A0 =A0 rtc->regs =3D of_iomap(op->node, 0);
> +
> + =A0 =A0 =A0 if (!rtc->regs) {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 printk(KERN_ERR "%s: couldn't map io space\=
n", __func__);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 err =3D -ENOSYS;
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 goto out_free;
> + =A0 =A0 =A0 }
> +
> + =A0 =A0 =A0 device_init_wakeup(&op->dev, 1);
> +
> + =A0 =A0 =A0 rtc->rtc =3D rtc_device_register("mpc5121-rtc", &op->dev,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 &mpc5121_rtc_ops, THIS_MODULE);
> + =A0 =A0 =A0 if (IS_ERR(rtc->rtc)) {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 err =3D PTR_ERR(rtc->rtc);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 goto out_unmap;
> + =A0 =A0 =A0 }
> +
> + =A0 =A0 =A0 dev_set_drvdata(&op->dev, rtc);
> +
> + =A0 =A0 =A0 rtc->irq =3D irq_of_parse_and_map(op->node, 1);
> + =A0 =A0 =A0 err =3D request_irq(rtc->irq, mpc5121_rtc_handler, IRQF_DIS=
ABLED,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 "mpc5121-rtc", &op->dev);
> + =A0 =A0 =A0 if (err) {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 printk(KERN_ERR "%s: could not request irq:=
 %i\n",
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 __func__, rtc->irq);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 goto out_dispose;
> + =A0 =A0 =A0 }
> +
> + =A0 =A0 =A0 rtc->irq_periodic =3D irq_of_parse_and_map(op->node, 0);
> + =A0 =A0 =A0 err =3D request_irq(rtc->irq_periodic, mpc5121_rtc_handler_=
upd,
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0IRQF_DIS=
ABLED, "mpc5121-rtc_upd", &op->dev);
> + =A0 =A0 =A0 if (err) {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 printk(KERN_ERR "%s: could not request irq:=
 %i\n",
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 __func__, rtc->irq_periodic);
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 goto out_dispose2;
> + =A0 =A0 =A0 }
> +
> + =A0 =A0 =A0 ka =3D in_be32(&rtc->regs->keep_alive);
> + =A0 =A0 =A0 if (ka & 0x02) {
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 printk(KERN_WARNING
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 "mpc5121-rtc: Battery or os=
cillator failure!\n");
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 out_be32(&rtc->regs->keep_alive, ka);
> + =A0 =A0 =A0 }
> +
> + =A0 =A0 =A0 goto out;
> +
> +out_dispose2:
> + =A0 =A0 =A0 irq_dispose_mapping(rtc->irq_periodic);
> + =A0 =A0 =A0 free_irq(rtc->irq, &op->dev);
> +out_dispose:
> + =A0 =A0 =A0 irq_dispose_mapping(rtc->irq);
> +out_unmap:
> + =A0 =A0 =A0 iounmap(rtc->regs);
> +out_free:
> + =A0 =A0 =A0 kfree(rtc);
> +out:
> + =A0 =A0 =A0 return err;
> +}
> +
> +static int __devexit mpc5121_rtc_remove(struct of_device *op)
> +{
> + =A0 =A0 =A0 struct mpc5121_rtc_data *rtc =3D dev_get_drvdata(&op->dev);
> + =A0 =A0 =A0 struct mpc5121_rtc_regs __iomem *regs =3D rtc->regs;
> +
> + =A0 =A0 =A0 /* disable interrupt, so there are no nasty surprises */
> + =A0 =A0 =A0 out_8(&regs->alm_enable, 0);
> + =A0 =A0 =A0 out_8(&regs->int_enable, in_8(&regs->int_enable) & ~0x1);
> +
> + =A0 =A0 =A0 rtc_device_unregister(rtc->rtc);
> + =A0 =A0 =A0 iounmap(rtc->regs);
> + =A0 =A0 =A0 free_irq(rtc->irq, &op->dev);
> + =A0 =A0 =A0 free_irq(rtc->irq_periodic, &op->dev);
> + =A0 =A0 =A0 irq_dispose_mapping(rtc->irq);
> + =A0 =A0 =A0 irq_dispose_mapping(rtc->irq_periodic);
> + =A0 =A0 =A0 dev_set_drvdata(&op->dev, NULL);
> + =A0 =A0 =A0 kfree(rtc);
> +
> + =A0 =A0 =A0 return 0;
> +}
> +
> +static struct of_device_id mpc5121_rtc_match[] =3D {
> + =A0 =A0 =A0 { .compatible =3D "fsl,mpc5121-rtc", },
> + =A0 =A0 =A0 {},
> +};
> +
> +static struct of_platform_driver mpc5121_rtc_driver =3D {
> + =A0 =A0 =A0 .owner =3D THIS_MODULE,
> + =A0 =A0 =A0 .name =3D "mpc5121-rtc",
> + =A0 =A0 =A0 .match_table =3D mpc5121_rtc_match,
> + =A0 =A0 =A0 .probe =3D mpc5121_rtc_probe,
> + =A0 =A0 =A0 .remove =3D mpc5121_rtc_remove,
> +};
> +
> +static int __init mpc5121_rtc_init(void)
> +{
> + =A0 =A0 =A0 return of_register_platform_driver(&mpc5121_rtc_driver);
> +}
> +
> +static void __exit mpc5121_rtc_exit(void)
> +{
> + =A0 =A0 =A0 of_unregister_platform_driver(&mpc5121_rtc_driver);
> +}
> +
> +MODULE_LICENSE("GPL");
> +MODULE_AUTHOR("John Rigby <jrigby@freescale.com>");
> +
> +module_init(mpc5121_rtc_init);
> +module_exit(mpc5121_rtc_exit);
> --
> 1.6.0.6
>
>



--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.

Re: [PATCH 10/12] mpc5121: Add MPC5121 Real time clock driver.

[Wolfram Sang]

[-- Attachment #1: Type: text/plain, Size: 675 bytes --]

On Wed, May 06, 2009 at 10:15:17PM +0200, Wolfgang Denk wrote:
> From: John Rigby <jrigby@freescale.com>
> 
> Based on Domen Puncer's rtc driver for 5200 posted to
> the ppclinux mailing list:
> 	http://patchwork.ozlabs.org/linuxppc-embedded/patch?id=11675
> but never commited anywhere.
> 
> Changes to Domen's original:
> 
>     Changed filenames/routine names from mpc5200* to mpc5121*

Why not changing it to mpc5xxx? From a glimpse, it should still work on
MPC5200, too.

Regards,

   Wolfram

-- 
Pengutronix e.K.                           | Wolfram Sang                |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 197 bytes --]

Re: [PATCH 11/12] mpc5121: Added MPC512x DMA driver.

[Grant Likely]

On Wed, May 6, 2009 at 2:15 PM, Wolfgang Denk <wd@denx.de> wrote:
> From: Piotr Ziecik <kosmo@semihalf.com>
>
> This patch adds initial version of MPC512x DMA driver.
> Only memory to memory transfers are currenly supported.
>
> Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
> Signed-off-by: Wolfgang Denk <wd@denx.de>
> Cc: Grant Likely <grant.likely@secretlab.ca>
> Cc: John Rigby <jcrigby@gmail.com>

Don't have time to review this in detail right now, but three quick comment=
s:

> =A0drivers/dma/mpc512x_dma.c =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0=
642 ++++++++++++++++++++++++++
> =A0drivers/dma/mpc512x_dma.h =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0| =A0=
192 ++++++++

It looks to me like these two files should be merged.

> diff --git a/arch/powerpc/boot/dts/mpc5121ads.dts b/arch/powerpc/boot/dts=
/mpc5121ads.dts
> index c2d9de9..e7f0e09 100644
> --- a/arch/powerpc/boot/dts/mpc5121ads.dts
> +++ b/arch/powerpc/boot/dts/mpc5121ads.dts
> @@ -373,7 +373,7 @@
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0};
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0dma@14000 {
> - =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "fsl,mpc5121=
-dma2";
> + =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 compatible =3D "fsl,mpc512x=
-dma";

Nack.  Compatible values should not use wildcards.  Be specific.  And
be specific about what it is compatible to if another part implements
the same device.

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0reg =3D <0x14000 0x1800>;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupts =3D <65 0x8>;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0interrupt-parent =3D < &ip=
ic >;
> diff --git a/arch/powerpc/platforms/512x/mpc512x_shared.c b/arch/powerpc/=
platforms/512x/mpc512x_shared.c
> index b776e45..135fd6b 100644
> --- a/arch/powerpc/platforms/512x/mpc512x_shared.c
> +++ b/arch/powerpc/platforms/512x/mpc512x_shared.c
> @@ -95,6 +95,7 @@ void __init mpc512x_init_i2c(void)
> =A0static struct of_device_id __initdata of_bus_ids[] =3D {
> =A0 =A0 =A0 =A0{ .compatible =3D "fsl,mpc5121-immr", },
> =A0 =A0 =A0 =A0{ .compatible =3D "fsl,mpc5121-localbus", },
> + =A0 =A0 =A0 { .compatible =3D "fsl,mpc5121-dma", },

This doesn't look right either.  Shouldn't the dma device hang off the
IMMR node?

g.

--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.

Re: [PATCH 02/12] fs_enet: Add MPC5121 FEC support.

[Scott Wood]

Grant Likely wrote:
>>  #ifdef CONFIG_FS_ENET_HAS_FEC
>> +#ifdef CONFIG_FS_ENET_MPC5121_FEC
>> +       {
>> +               .compatible = "fsl,mpc5121-fec",
>> +               .data = (void *)&fs_fec_ops,
>> +       },
>> +#else
>>        {
>>                .compatible = "fsl,pq1-fec-enet",
>>                .data = (void *)&fs_fec_ops,
>>        },
>>  #endif
>> +#endif
> 
> Hmmm.  A lot of these #ifdefs in here.  Does this have a multiplatform
> impact?  Not to mention the fact that it's just plain ugly.  :-)

Multiplatform between 512x and 8xx is currently impossible for other 
reasons (512x and CPM2 is another matter).  That said, less ifdefs would 
be nice.

-Scott

Re: [PATCH 12/12] mpc5121: Added default config for MPC5121.

[Grant Likely]

On Wed, May 6, 2009 at 2:15 PM, Wolfgang Denk <wd@denx.de> wrote:
> From: Piotr Ziecik <kosmo@semihalf.com>
>
> Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
> Signed-off-by: Wolfgang Denk <wd@denx.de>
> Cc: Grant Likely <grant.likely@secretlab.ca>
> Cc: John Rigby <jcrigby@gmail.com>

Wait till about -rc2 time to do defconfig patches.

g.

Re: [PATCH 04/12] mpc5121: Added reset module registers representation.

[Wolfgang Denk]

Dear Scott,

in message <4A01F33B.2090100@freescale.com> you wrote:
>
> > --- a/arch/powerpc/include/asm/mpc512x.h
> > +++ b/arch/powerpc/include/asm/mpc512x.h
...
> 83xx has the same registers; we should define it in a non-512x-specific 
> header.

Agreed. Any suggestion where?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
I know engineers. They love to change things.             - Dr. McCoy

Re: [PATCH 02/12] fs_enet: Add MPC5121 FEC support.

[Wolfgang Denk]

Dear Grant,

in message <fa686aa40905061333q29c263c8p24856c048e30f4d0@mail.gmail.com> you wrote:
>
...
> > #ifdef CONFIG_FS_ENET_HAS_FEC
> > +#ifdef CONFIG_FS_ENET_MPC5121_FEC
> > +    {
> > +        .compatible = "fsl,mpc5121-fec",
> > +        .data = (void *)&fs_fec_ops,
> > +    },
> > +#else
> >    {
> >        .compatible = "fsl,pq1-fec-enet",
> >        .data = (void *)&fs_fec_ops,
> >    },
> > #endif
> > +#endif
>
> Hmmm.  A lot of these #ifdefs in here.  Does this have a multiplatform
> impact?  Not to mention the fact that it's just plain ugly.  :-)

Agreed that it's ugly, but duplicatio9ng the code would have been even
worse. I don't think that it has multiplatform - at least not as long
as you don't ask for one image that runs on 83xx and on 512x.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
Our business is run on trust.  We trust you will pay in advance.

Re: [PATCH 01/12] fs_enet: Use defines to set driver tunables.

[Wolfgang Denk]

Dear Grant,

In message <fa686aa40905061335q3a3c4cc7r33d77df655100531@mail.gmail.com> you wrote:
> On Wed, May 6, 2009 at 2:15 PM, Wolfgang Denk <wd@denx.de> wrote:
> > From: Piotr Ziecik <kosmo@semihalf.com>
> >
> > Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
> > Signed-off-by: Wolfgang Denk <wd@denx.de>
> > Cc: <netdev@vger.kernel.org>
> > Cc: Grant Likely <grant.likely@secretlab.ca>
> > Cc: John Rigby <jcrigby@gmail.com>
> 
> Not seeing much benefit to this patch, and the (non-existant) patch
> description doesn't really help me here either.

Please see next patch which then uses the ability to change the
defaults.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
Program maintenance is an entropy-increasing process,  and  even  its
most skilfull execution only delays the subsidence of the system into
unfixable obsolescence.       - Fred Brooks, "The Mythical Man Month"

Re: [PATCH 02/12] fs_enet: Add MPC5121 FEC support.

[Wolfgang Denk]

Dear David,

In message <20090506.134003.261424694.davem@davemloft.net> you wrote:
> 
> Would you be offended if I tell you that this is a horrible patch
> submission?
> 
> Your introductory email indicates 16 patches, yet the series indicates
> there were 12, and that intro email is only posted to the linuxppc-dev
> list for people to read.  Nobody on netdev nor other interested
> parties that get CC:'d along the line are able to read what this patch
> series is about.

Of course I am not offended, as you are absolutely right with your
comment. I'm angry with myself, as I actually intended to do exactly
what you find missing, but then forgot to write the file in the
editor :-(

> I'm definitely sending all of the copies I have received to /dev/null,
> you need to submit this work properly.

OK. What exactly should I do?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
If I have seen further it is by standing on the shoulders of  giants.
              - Isaac Newton, Letter to Robert Hooke, 5 February 1676

Re: [PATCH 02/12] fs_enet: Add MPC5121 FEC support.

[Wolfgang Denk]

Dear Scott,

in message <4A01F602.2010601@freescale.com> you wrote:
>
> All of the above is duplicative (with even the same names) of stuff in 
> asm/cpm.h.  Beyond just the duplication, what happens if both CPM2 and 

OK, I can try to reuse the definitions from that file.

> 512x are enabled in the same kernel?

Hm... both architectures look sufficiently different to me that I
don't see sense in trying such a thing. Do you think that needs to be
supported?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
"You ain't experienced..." "Well, nor are you." "That's true. But the
point is ... the point is ... the point is we've been not experienced
for a lot longer than you. We've got  a  lot  of  experience  of  not
having any experience."           - Terry Pratchett, _Witches Abroad_

Re: [PATCH 03/12] fs_enet: Add FEC TX Alignment workaround for MPC5121.

[Wolfgang Denk]

Dear Grant Likely,

In message <fa686aa40905061337w6aa82f5aj787618ba108e528f@mail.gmail.com> you wrote:
>
> > The FEC on 5121 has problems with misaligned tx buffers.
> > The RM says any alignment is ok but empirical results
> > show that packet buffers ending in 0x1E will sometimes
> > hang the FEC. Other bad alignment does not hang but will
> > cause silent TX failures resulting in about a 1% packet
> > loss as tested by ping -f from a remote host.
> >
> > This patch is a work around that copies every tx packet
> > to an aligned skb before sending.
>
> OUCH!

Yes :-(

> > +#else
> > +#define tx_skb_align_workaround(dev, skb) (skb)
> > +#endif
>
> Another use of #ifdef blocks.  What is the multiplatform impact?

Hm... Can you recommend a better way to solve the problem? Suggestions
are welcome.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
You don't have to worry about me. I might have been born yesterday...
but I stayed up all night.

Re: [PATCH 04/12] mpc5121: Added reset module registers representation.

[Wolfgang Denk]

Dear Grant Likely,

In message <fa686aa40905061339u171559b8va45c210b3e63cf83@mail.gmail.com> you wrote:
>
> No patch description.  I would also like to see this patch merged with
> the actual user of it since it is so small.

Will do. As for description - the Subject says it all.

> > +} __attribute__ ((__packed__));
> 
> __attribute__((__packed__)); is unnecessary.

OK.

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
Applying computer technology is simply finding the  right  wrench  to
pound in the correct screw.

Re: [PATCH 05/12] mpc5121ads: Added Reset Module node to DTS.

[Wolfgang Denk]

Dear Grant Likely,

In message <fa686aa40905061340s212385b1r8be4e2f7505bd0a0@mail.gmail.com> you wrote:
> On Wed, May 6, 2009 at 2:15 PM, Wolfgang Denk <wd@denx.de> wrote:
> > From: Piotr Ziecik <kosmo@semihalf.com>
> >
> > Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
> > Signed-off-by: Wolfgang Denk <wd@denx.de>
> > Cc: Grant Likely <grant.likely@secretlab.ca>
> > Cc: John Rigby <jcrigby@gmail.com>
> 
> Missing patch description.  Otherwise looks okay.

This is a repeating complaint. Do I really need an extra  description
for a trivial patch that does exactly what the Subject: says?

What is recommended practice in such a case?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
 The software required `Windows 95 or better', so I installed Linux.

Re: [PATCH 08/12] mpc5121: Added I2C support.

[Wolfgang Denk]

Dear Grant Likely,

In message <fa686aa40905061401k319313c5q89fd3e245c30808f@mail.gmail.com> you wrote:
> On Wed, May 6, 2009 at 2:15 PM, Wolfgang Denk <wd@denx.de> wrote:
> > From: Piotr Ziecik <kosmo@semihalf.com>
> >
> > - Enabled I2C interrupts on MPC5121.
> > - Updated Kconfig for i2c-mpc driver.
> 
> I think this workaround belongs in the driver itself.

Sorry, I don't get it. Which workaround? What exactly should I change?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
Time is an illusion perpetrated by the manufacturers of space.

Re: [PATCH 12/12] mpc5121: Added default config for MPC5121.

[Wolfgang Denk]

Dear Grant Likely,

In message <fa686aa40905061408s3360b774y756262e3e15d17bd@mail.gmail.com> you wrote:
>
> Wait till about -rc2 time to do defconfig patches.

Would it offend you if I continue to include these (and you have to
ignore them)? Posting a "complete" patch set that includs a defconfig
allows users much easier testing...

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
WARNING:  This Product Attracts Every Other Piece  of  Matter in  the
Universe, Including the Products of Other Manufacturers, with a Force
Proportional  to the Product of the Masses and Inversely Proportional
to the Distance Between Them.

Re: [PATCH 02/12] fs_enet: Add MPC5121 FEC support.

[Grant Likely]

On Wed, May 6, 2009 at 4:01 PM, Wolfgang Denk <wd@denx.de> wrote:
> Dear Grant,
>
> in message <fa686aa40905061333q29c263c8p24856c048e30f4d0@mail.gmail.com> =
you wrote:
>>
> ...
>> > #ifdef CONFIG_FS_ENET_HAS_FEC
>> > +#ifdef CONFIG_FS_ENET_MPC5121_FEC
>> > + =A0 =A0{
>> > + =A0 =A0 =A0 =A0.compatible =3D "fsl,mpc5121-fec",
>> > + =A0 =A0 =A0 =A0.data =3D (void *)&fs_fec_ops,
>> > + =A0 =A0},
>> > +#else
>> > =A0 =A0{
>> > =A0 =A0 =A0 =A0.compatible =3D "fsl,pq1-fec-enet",
>> > =A0 =A0 =A0 =A0.data =3D (void *)&fs_fec_ops,
>> > =A0 =A0},
>> > #endif
>> > +#endif
>>
>> Hmmm. =A0A lot of these #ifdefs in here. =A0Does this have a multiplatfo=
rm
>> impact? =A0Not to mention the fact that it's just plain ugly. =A0:-)
>
> Agreed that it's ugly, but duplicatio9ng the code would have been even
> worse. I don't think that it has multiplatform - at least not as long
> as you don't ask for one image that runs on 83xx and on 512x.

Actually, I *am* asking for one image that runs on 83xx, 52xx and
521x.  I already can and do build and test a single image which boots
on all my 52xx boards, on my 8349 board, and on my G4 Mac.

g.

--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.

Re: [PATCH 02/12] fs_enet: Add MPC5121 FEC support.

[Grant Likely]

On Wed, May 6, 2009 at 4:09 PM, Wolfgang Denk <wd@denx.de> wrote:
> Dear Scott,
>
> in message <4A01F602.2010601@freescale.com> you wrote:
>>
>> All of the above is duplicative (with even the same names) of stuff in
>> asm/cpm.h. =A0Beyond just the duplication, what happens if both CPM2 and
>
> OK, I can try to reuse the definitions from that file.
>
>> 512x are enabled in the same kernel?
>
> Hm... both architectures look sufficiently different to me that I
> don't see sense in trying such a thing. Do you think that needs to be
> supported?

Yes!  :-)  It's not hard to do and it keeps the driver cleaner
(IMNSHO).  I don't think it is quite possible at the moment due to
cache coherency issues, but with Becky's recently merged dma ops
changes it should be fixable.

Cheers,
g.

--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.

Re: [PATCH 10/12] mpc5121: Add MPC5121 Real time clock driver.

[Grant Likely]

On Wed, May 6, 2009 at 3:06 PM, Wolfram Sang <w.sang@pengutronix.de> wrote:
> On Wed, May 06, 2009 at 10:15:17PM +0200, Wolfgang Denk wrote:
>> From: John Rigby <jrigby@freescale.com>
>>
>> Based on Domen Puncer's rtc driver for 5200 posted to
>> the ppclinux mailing list:
>> =A0 =A0 =A0 http://patchwork.ozlabs.org/linuxppc-embedded/patch?id=3D116=
75
>> but never commited anywhere.
>>
>> Changes to Domen's original:
>>
>> =A0 =A0 Changed filenames/routine names from mpc5200* to mpc5121*
>
> Why not changing it to mpc5xxx? From a glimpse, it should still work on
> MPC5200, too.

If this is true, the I heartily agree with Wolfram.  :-)

g.

--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.

Re: [PATCH 01/12] fs_enet: Use defines to set driver tunables.

[Grant Likely]

On Wed, May 6, 2009 at 4:02 PM, Wolfgang Denk <wd@denx.de> wrote:
> Dear Grant,
>
> In message <fa686aa40905061335q3a3c4cc7r33d77df655100531@mail.gmail.com> you wrote:
>> On Wed, May 6, 2009 at 2:15 PM, Wolfgang Denk <wd@denx.de> wrote:
>> > From: Piotr Ziecik <kosmo@semihalf.com>
>> >
>> > Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
>> > Signed-off-by: Wolfgang Denk <wd@denx.de>
>> > Cc: <netdev@vger.kernel.org>
>> > Cc: Grant Likely <grant.likely@secretlab.ca>
>> > Cc: John Rigby <jcrigby@gmail.com>
>>
>> Not seeing much benefit to this patch, and the (non-existant) patch
>> description doesn't really help me here either.
>
> Please see next patch which then uses the ability to change the
> defaults.

Please state that in the patch description when you repost it.  :-P

g.


-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.

Re: [PATCH 02/12] fs_enet: Add MPC5121 FEC support.

[Wolfgang Denk]

Dear Grant,

In message <fa686aa40905061529u11b231afle3b5bb10a2334ad0@mail.gmail.com> you wrote:
>
> > Agreed that it's ugly, but duplicatio9ng the code would have been even
> > worse. I don't think that it has multiplatform - at least not as long
> > as you don't ask for one image that runs on 83xx and on 512x.
> 
> Actually, I *am* asking for one image that runs on 83xx, 52xx and
> 521x.  I already can and do build and test a single image which boots
> on all my 52xx boards, on my 8349 board, and on my G4 Mac.

He. I was afraid you'd say that ;-)

In this case I need a helping hand as I can't figure out how to make
this work. Any suggestions?

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
"Here's a fish hangs in the net like a poor man's right in  the  law.
'Twill hardly come out."     - Shakespeare, Pericles, Act II, Scene 1

Re: [PATCH 03/12] fs_enet: Add FEC TX Alignment workaround for MPC5121.

[Grant Likely]

On Wed, May 6, 2009 at 4:12 PM, Wolfgang Denk <wd@denx.de> wrote:
> Dear Grant Likely,
>
> In message <fa686aa40905061337w6aa82f5aj787618ba108e528f@mail.gmail.com> =
you wrote:
>>
>> > The FEC on 5121 has problems with misaligned tx buffers.
>> > The RM says any alignment is ok but empirical results
>> > show that packet buffers ending in 0x1E will sometimes
>> > hang the FEC. Other bad alignment does not hang but will
>> > cause silent TX failures resulting in about a 1% packet
>> > loss as tested by ping -f from a remote host.
>> >
>> > This patch is a work around that copies every tx packet
>> > to an aligned skb before sending.
>>
>> OUCH!
>
> Yes :-(
>
>> > +#else
>> > +#define tx_skb_align_workaround(dev, skb) (skb)
>> > +#endif
>>
>> Another use of #ifdef blocks. =A0What is the multiplatform impact?
>
> Hm... Can you recommend a better way to solve the problem? Suggestions
> are welcome.

I'd rather see a runtime selectable workaround.  ie. enable it based
on the compatible property.

g.

--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.

Re: [PATCH 05/12] mpc5121ads: Added Reset Module node to DTS.

[Grant Likely]

On Wed, May 6, 2009 at 4:16 PM, Wolfgang Denk <wd@denx.de> wrote:
> Dear Grant Likely,
>
> In message <fa686aa40905061340s212385b1r8be4e2f7505bd0a0@mail.gmail.com> =
you wrote:
>> On Wed, May 6, 2009 at 2:15 PM, Wolfgang Denk <wd@denx.de> wrote:
>> > From: Piotr Ziecik <kosmo@semihalf.com>
>> >
>> > Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
>> > Signed-off-by: Wolfgang Denk <wd@denx.de>
>> > Cc: Grant Likely <grant.likely@secretlab.ca>
>> > Cc: John Rigby <jcrigby@gmail.com>
>>
>> Missing patch description. =A0Otherwise looks okay.
>
> This is a repeating complaint. Do I really need an extra =A0description
> for a trivial patch that does exactly what the Subject: says?

Fair enough.  I was going through your series pretty quickly and this
one doesn't really need it.

However, in this particular case, I think I would rather see both .dts
rework patches put into the same patch so it can be reviewed all at
once.

g.


--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.

Re: [PATCH 12/12] mpc5121: Added default config for MPC5121.

[Grant Likely]

On Wed, May 6, 2009 at 4:23 PM, Wolfgang Denk <wd@denx.de> wrote:
> Dear Grant Likely,
>
> In message <fa686aa40905061408s3360b774y756262e3e15d17bd@mail.gmail.com> you wrote:
>>
>> Wait till about -rc2 time to do defconfig patches.
>
> Would it offend you if I continue to include these (and you have to
> ignore them)? Posting a "complete" patch set that includs a defconfig
> allows users much easier testing...

Yes, that's fine.  My preference is if they appear at the end of the series.

g.

-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.

Re: [PATCH 08/12] mpc5121: Added I2C support.

[Grant Likely]

On Wed, May 6, 2009 at 4:19 PM, Wolfgang Denk <wd@denx.de> wrote:
> Dear Grant Likely,
>
> In message <fa686aa40905061401k319313c5q89fd3e245c30808f@mail.gmail.com> you wrote:
>> On Wed, May 6, 2009 at 2:15 PM, Wolfgang Denk <wd@denx.de> wrote:
>> > From: Piotr Ziecik <kosmo@semihalf.com>
>> >
>> > - Enabled I2C interrupts on MPC5121.
>> > - Updated Kconfig for i2c-mpc driver.
>>
>> I think this workaround belongs in the driver itself.
>
> Sorry, I don't get it. Which workaround? What exactly should I change?

Sorry, I misread the patch.  Never mind.

g.

-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.

Re: [PATCH 08/12] mpc5121: Added I2C support.

[Grant Likely]

On Wed, May 6, 2009 at 4:51 PM, Grant Likely <grant.likely@secretlab.ca> wr=
ote:
> On Wed, May 6, 2009 at 4:19 PM, Wolfgang Denk <wd@denx.de> wrote:
>> Dear Grant Likely,
>>
>> In message <fa686aa40905061401k319313c5q89fd3e245c30808f@mail.gmail.com>=
 you wrote:
>>> On Wed, May 6, 2009 at 2:15 PM, Wolfgang Denk <wd@denx.de> wrote:
>>> > From: Piotr Ziecik <kosmo@semihalf.com>
>>> >
>>> > - Enabled I2C interrupts on MPC5121.
>>> > - Updated Kconfig for i2c-mpc driver.
>>>
>>> I think this workaround belongs in the driver itself.
>>
>> Sorry, I don't get it. Which workaround? What exactly should I change?
>
> Sorry, I misread the patch. =A0Never mind.

Actually, on 3rd reading, I think my first impression was correct
(even if I was wrong about it being a workaround).  This code in
mpc512x_init_i2c() is only relevant for i2c busses (it isn't shared
with any other drivers).  Therefore, it belongs with the i2c bus
itself.  It does not belong in platform code.

Cheers,
g.

--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.

Re: [PATCH 08/12] mpc5121: Added I2C support.

[Wolfgang Grandegger]

Grant Likely wrote:
> On Wed, May 6, 2009 at 4:51 PM, Grant Likely <grant.likely@secretlab.ca> wrote:
>> On Wed, May 6, 2009 at 4:19 PM, Wolfgang Denk <wd@denx.de> wrote:
>>> Dear Grant Likely,
>>>
>>> In message <fa686aa40905061401k319313c5q89fd3e245c30808f@mail.gmail.com> you wrote:
>>>> On Wed, May 6, 2009 at 2:15 PM, Wolfgang Denk <wd@denx.de> wrote:
>>>>> From: Piotr Ziecik <kosmo@semihalf.com>
>>>>>
>>>>> - Enabled I2C interrupts on MPC5121.
>>>>> - Updated Kconfig for i2c-mpc driver.
>>>> I think this workaround belongs in the driver itself.
>>> Sorry, I don't get it. Which workaround? What exactly should I change?
>> Sorry, I misread the patch.  Never mind.
> 
> Actually, on 3rd reading, I think my first impression was correct
> (even if I was wrong about it being a workaround).  This code in
> mpc512x_init_i2c() is only relevant for i2c busses (it isn't shared
> with any other drivers).  Therefore, it belongs with the i2c bus
> itself.  It does not belong in platform code.

Right. Furthermore, the i2c-mpc.c should be extened to support bus speed
setting for the MPC512x, which has been merged recently (see commit id
f2bd5efe).

Wolfgang.

Re: [PATCH 09/12] mpc5121ads: Added I2C RTC node to mpc5121ads DTS.

[Wolfgang Grandegger]

Wolfgang Denk wrote:
> From: Piotr Ziecik <kosmo@semihalf.com>
> 
> Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
> Signed-off-by: Wolfgang Denk <wd@denx.de>
> Cc: Grant Likely <grant.likely@secretlab.ca>
> Cc: John Rigby <jcrigby@gmail.com>
> ---
>  arch/powerpc/boot/dts/mpc5121ads.dts |    5 +++++
>  1 files changed, 5 insertions(+), 0 deletions(-)
> 
> diff --git a/arch/powerpc/boot/dts/mpc5121ads.dts b/arch/powerpc/boot/dts/mpc5121ads.dts
> index 93fe12a..c2d9de9 100644
> --- a/arch/powerpc/boot/dts/mpc5121ads.dts
> +++ b/arch/powerpc/boot/dts/mpc5121ads.dts
> @@ -210,6 +210,11 @@
>  			interrupts = <9 0x8>;
>  			interrupt-parent = < &ipic >;
>  			fsl5200-clocking;

The above line is obsolete since -rc4. Please check the revised bindings
in Documentation/powerpc/dts-bindings/fsl/i2c.txt. You may even want:

                        clock-frequency = <100000>;

Wolfgang.

Re: [PATCH 06/12] mpc5121: Added NAND Flash Controller driver.

[David Jander]

On Wednesday 06 May 2009 22:15:13 Wolfgang Denk wrote:
> --- /dev/null
> +++ b/drivers/mtd/nand/mpc5121_nfc.c
>[...]
> +/* Init external chip select logic on ADS5121 board */
> +static int ads5121_chipselect_init(struct mtd_info *mtd)
> +{
> +	struct nand_chip *chip = mtd->priv;
> +	struct mpc5121_nfc_prv *prv = chip->priv;
> +	struct device_node *dn;
> +
> +	dn = of_find_compatible_node(NULL, NULL, "fsl,mpc5121ads-cpld");
> +	if (dn) {
> +		prv->csreg = of_iomap(dn, 0);
> +		of_node_put(dn);
> +		if (!prv->csreg)
> +			return -ENOMEM;
> +
> +		/* CPLD Register 9 controls NAND /CE Lines */
> +		prv->csreg += 9;
> +		return 0;
> +	}
> +
> +	return -EINVAL;
> +}
> +
> +/* Control chips select signal on ADS5121 board */
> +static void ads5121_select_chip(struct mtd_info *mtd, int chip)
> +{
> +	struct nand_chip *nand = mtd->priv;
> +	struct mpc5121_nfc_prv *prv = nand->priv;
> +	u8 v;
> +
> +	v = in_8(prv->csreg);
> +	v |= 0x0F;
> +
> +	if (chip >= 0) {
> +		mpc5121_nfc_select_chip(mtd, 0);
> +		v &= ~(1 << chip);
> +	} else
> +		mpc5121_nfc_select_chip(mtd, -1);
> +
> +	out_8(prv->csreg, v);
> +}

I am just a humble beginner, but isn't this platform dependend code supposed 
to be in /arch/powerpc/platforms/.... ?

>[...]
> +static int __init mpc5121_nfc_probe(struct of_device *op,
> +					const struct of_device_id *match)
> +{
> +	struct device_node *rootnode, *dn = op->node;
> +	struct device *dev = &op->dev;
> +	struct mpc5121_nfc_prv *prv;
> +	struct resource res;
> +	struct mtd_info *mtd;
> +#ifdef CONFIG_MTD_PARTITIONS
> +	struct mtd_partition *parts;
> +#endif
> +	struct nand_chip *chip;
> +	unsigned long regs_paddr, regs_size;
> +	const uint *chips_no;
> +	int resettime = 0;
> +	int retval = 0;
> +	int rev, len;
> +
> +	/*
> +	 * Check SoC revision. This driver supports only NFC
> +	 * in MPC5121 revision 2.
> +	 */
> +	rev = (mfspr(SPRN_SVR) >> 4) & 0xF;
> +	if (rev != 2) {
> +		printk(KERN_ERR DRV_NAME
> +				": SoC revision %u is not supported!\n", rev);
> +		return -ENXIO;
> +	}
> +
> +	prv = devm_kzalloc(dev, sizeof(*prv), GFP_KERNEL);
> +	if (!prv) {
> +		printk(KERN_ERR DRV_NAME ": Memory exhausted!\n");
> +		return -ENOMEM;
> +	}
> +
> +	mtd = &prv->mtd;
> +	chip = &prv->chip;
> +
> +	mtd->priv = chip;
> +	chip->priv = prv;
> +
> +	/* Read NFC configuration from Reset Config Word */
> +	retval = mpc5121_nfc_read_hw_config(mtd);
> +	if (retval) {
> +		printk(KERN_ERR DRV_NAME ": Unable to read NFC config!\n");
> +		return retval;
> +	}
> +
> +	prv->irq = irq_of_parse_and_map(dn, 0);
> +	if (prv->irq == NO_IRQ) {
> +		printk(KERN_ERR DRV_NAME ": Error mapping IRQ!\n");
> +		return -EINVAL;
> +	}
> +
> +	retval = of_address_to_resource(dn, 0, &res);
> +	if (retval) {
> +		printk(KERN_ERR DRV_NAME ": Error parsing memory region!\n");
> +		return retval;
> +	}
> +
> +	chips_no = of_get_property(dn, "chips", &len);
> +	if (!chips_no || len != sizeof(*chips_no)) {
> +		printk(KERN_ERR DRV_NAME ": Invalid/missing 'chips' "
> +								"property!\n");
> +		return -EINVAL;
> +	}
> +
> +	regs_paddr = res.start;
> +	regs_size = res.end - res.start + 1;
> +
> +	if (!devm_request_mem_region(dev, regs_paddr, regs_size, DRV_NAME)) {
> +		printk(KERN_ERR DRV_NAME ": Error requesting memory region!\n");
> +		return -EBUSY;
> +	}
> +
> +	prv->regs = devm_ioremap(dev, regs_paddr, regs_size);
> +	if (!prv->regs) {
> +		printk(KERN_ERR DRV_NAME ": Error mapping memory region!\n");
> +		return -ENOMEM;
> +	}
> +
> +	mtd->name = "MPC5121 NAND";
> +	chip->dev_ready = mpc5121_nfc_dev_ready;
> +	chip->cmdfunc = mpc5121_nfc_command;
> +	chip->read_byte = mpc5121_nfc_read_byte;
> +	chip->read_word = mpc5121_nfc_read_word;
> +	chip->read_buf = mpc5121_nfc_read_buf;
> +	chip->write_buf = mpc5121_nfc_write_buf;
> +	chip->verify_buf = mpc5121_nfc_verify_buf;
> +	chip->select_chip = mpc5121_nfc_select_chip;
> +	chip->options = NAND_NO_AUTOINCR | NAND_USE_FLASH_BBT;
> +	chip->ecc.mode = NAND_ECC_SOFT;
> +
> +	/* Support external chip-select logic on ADS5121 board */
> +	rootnode = of_find_node_by_path("/");
> +	if (of_device_is_compatible(rootnode, "fsl,mpc5121ads")) {
> +		retval = ads5121_chipselect_init(mtd);
> +		if (retval) {
> +			printk(KERN_ERR DRV_NAME ": Chipselect init error!\n");
> +			of_node_put(rootnode);
> +			return retval;
> +		}
> +
> +		chip->select_chip = ads5121_select_chip;
> +	}

Hmmm, I guess it would be overkill to build some sort of generic framework for 
providing special chip-select functions here.... but it just doesn't look 
clean like this.... oh well.

Best regards,

-- 
David Jander
Protonic Holland.

Re: [PATCH 02/12] fs_enet: Add MPC5121 FEC support.

[David Jander]

On Thursday 07 May 2009 00:29:59 Grant Likely wrote:
> On Wed, May 6, 2009 at 4:01 PM, Wolfgang Denk <wd@denx.de> wrote:
> > Dear Grant,
> >
> > in message <fa686aa40905061333q29c263c8p24856c048e30f4d0@mail.gmail.com>
> > you wrote:
> >
> > ...
> >
> >> > #ifdef CONFIG_FS_ENET_HAS_FEC
> >> > +#ifdef CONFIG_FS_ENET_MPC5121_FEC
> >> > + =A0 =A0{
> >> > + =A0 =A0 =A0 =A0.compatible =3D "fsl,mpc5121-fec",
> >> > + =A0 =A0 =A0 =A0.data =3D (void *)&fs_fec_ops,
> >> > + =A0 =A0},
> >> > +#else
> >> > =A0 =A0{
> >> > =A0 =A0 =A0 =A0.compatible =3D "fsl,pq1-fec-enet",
> >> > =A0 =A0 =A0 =A0.data =3D (void *)&fs_fec_ops,
> >> > =A0 =A0},
> >> > #endif
> >> > +#endif
> >>
> >> Hmmm. =A0A lot of these #ifdefs in here. =A0Does this have a multiplat=
form
> >> impact? =A0Not to mention the fact that it's just plain ugly. =A0:-)
> >
> > Agreed that it's ugly, but duplicatio9ng the code would have been even
> > worse. I don't think that it has multiplatform - at least not as long
> > as you don't ask for one image that runs on 83xx and on 512x.
>
> Actually, I *am* asking for one image that runs on 83xx, 52xx and
> 521x.  I already can and do build and test a single image which boots
> on all my 52xx boards, on my 8349 board, and on my G4 Mac.

Cool! I also want that! We have different boards with 5200 and 5121e's and =
it=20
would be terrific if one day we'd be able to use just one kernel for all of=
=20
them!

(Sorry for being a me-too-er)

Best regards,

=2D-=20
David Jander
Protonic Holland.

Re: [PATCH 02/12] fs_enet: Add MPC5121 FEC support.

[Kumar Gala]

On May 6, 2009, at 5:01 PM, Wolfgang Denk wrote:

> Dear Grant,
>
> in message <fa686aa40905061333q29c263c8p24856c048e30f4d0@mail.gmail.com 
> > you wrote:
>>
> ...
>>> #ifdef CONFIG_FS_ENET_HAS_FEC
>>> +#ifdef CONFIG_FS_ENET_MPC5121_FEC
>>> +    {
>>> +        .compatible = "fsl,mpc5121-fec",
>>> +        .data = (void *)&fs_fec_ops,
>>> +    },
>>> +#else
>>>   {
>>>       .compatible = "fsl,pq1-fec-enet",
>>>       .data = (void *)&fs_fec_ops,
>>>   },
>>> #endif
>>> +#endif
>>
>> Hmmm.  A lot of these #ifdefs in here.  Does this have a  
>> multiplatform
>> impact?  Not to mention the fact that it's just plain ugly.  :-)
>
> Agreed that it's ugly, but duplicatio9ng the code would have been even
> worse. I don't think that it has multiplatform - at least not as long
> as you don't ask for one image that runs on 83xx and on 512x.

We do ask for that.  The fedora ppc6xx kernel should work on any 6xx/ 
7xx/7xxx based core chip.  We should NOT be breaking such capability  
in drivers.

- k

Re: [PATCH 02/12] fs_enet: Add MPC5121 FEC support.

[Grant Likely]

On Wed, May 6, 2009 at 4:41 PM, Wolfgang Denk <wd@denx.de> wrote:
> Dear Grant,
>
> In message <fa686aa40905061529u11b231afle3b5bb10a2334ad0@mail.gmail.com> =
you wrote:
>>
>> > Agreed that it's ugly, but duplicatio9ng the code would have been even
>> > worse. I don't think that it has multiplatform - at least not as long
>> > as you don't ask for one image that runs on 83xx and on 512x.
>>
>> Actually, I *am* asking for one image that runs on 83xx, 52xx and
>> 521x. =A0I already can and do build and test a single image which boots
>> on all my 52xx boards, on my 8349 board, and on my G4 Mac.
>
> He. I was afraid you'd say that ;-)
>
> In this case I need a helping hand as I can't figure out how to make
> this work. Any suggestions?

Hmmm, it is rather ugly because the layout of fec_t is so different.
Easiest solution would be to duplicate the driver in its entirety, but
as you say it results in a lot of duplicate code.  It might be the
lesser of many weevils though.

Second easiest would be to factor out all the common code in the
driver into a separate .c file that gets included by a 'wrapper' .c
file for each config which first includes the correct definition of
fec_t.  This approach solves the duplicate code problem, but it also
fell out of the ugly tree and hit every branch on the way down.

ie: the wrappers would look something like this:

fs_enet_cpm1.c:
#include <asm/cpm1.h>
#include "fs_enet_main.c"

fs_enet_cpm2.c:
#include <asm/cpm2.h>
#include "fs_enet_main.c"

fs_enet_512x.c:
#include <asm/mpc512x.h>
#include "fs_enet_main.c"

And then the makefile would be something along the lines of:
obj-${CONFIG_FS_ENET_CPM1_ +=3D fs_enet_cpm1.o
obj-${CONFIG_FS_ENET_CPM2_ +=3D fs_enet_cpm2.o
obj-${CONFIG_FS_ENET_MPC512x_ +=3D fs_enet_512x.o

A brief look at the driver suggests that access to the fec_t structure
is restricted to the fec-mii.c and mac-fec.c files.  It might be
appropriate to duplicate just those files and do some form of
fs_enet_ops to select between them.

While on the topic, it looks to me like the driver could really use
some refactoring love.  Having multiple definitions of "fec_t" is
confusing and potentially lead to hard to find bugs if the wrong
header gets included by anyone.  I'd like to see all the fec specific
stuff in arch/powerpc/include/asm moved into drivers/net/fs_enet and
renamed to reflect the hardware it is associate with.  Stuff like
"fec_t" is far to generic, not to mention that typedefs are
discouraged now.

Regardless, I feel your pain.  It is not a pretty situation.

g.

--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.

Re: [PATCH 02/12] fs_enet: Add MPC5121 FEC support.

[John Rigby]

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Wolfgang,

Welcome to my world and why I gave up on this months ago.

Everyone else,

One thing to consider here is a rewrite with the goal of a new improved fec
driver that would work on both 5121 and the various mx platforms that also
have this same fec core.

Also don't forget that the register map is the same on 512x, mx and coldfire
platforms but not on the other ppc platforms so if you want to one binary to
rule them all you will need to have an offest table or some such.

John

On Thu, May 7, 2009 at 8:09 AM, Grant Likely <grant.likely@secretlab.ca>wrote:

> On Wed, May 6, 2009 at 4:41 PM, Wolfgang Denk <wd@denx.de> wrote:
> > Dear Grant,
> >
> > In message <fa686aa40905061529u11b231afle3b5bb10a2334ad0@mail.gmail.com>
> you wrote:
> >>
> >> > Agreed that it's ugly, but duplicatio9ng the code would have been even
> >> > worse. I don't think that it has multiplatform - at least not as long
> >> > as you don't ask for one image that runs on 83xx and on 512x.
> >>
> >> Actually, I *am* asking for one image that runs on 83xx, 52xx and
> >> 521x.  I already can and do build and test a single image which boots
> >> on all my 52xx boards, on my 8349 board, and on my G4 Mac.
> >
> > He. I was afraid you'd say that ;-)
> >
> > In this case I need a helping hand as I can't figure out how to make
> > this work. Any suggestions?
>
> Hmmm, it is rather ugly because the layout of fec_t is so different.
> Easiest solution would be to duplicate the driver in its entirety, but
> as you say it results in a lot of duplicate code.  It might be the
> lesser of many weevils though.
>
> Second easiest would be to factor out all the common code in the
> driver into a separate .c file that gets included by a 'wrapper' .c
> file for each config which first includes the correct definition of
> fec_t.  This approach solves the duplicate code problem, but it also
> fell out of the ugly tree and hit every branch on the way down.
>
> ie: the wrappers would look something like this:
>
> fs_enet_cpm1.c:
> #include <asm/cpm1.h>
> #include "fs_enet_main.c"
>
> fs_enet_cpm2.c:
> #include <asm/cpm2.h>
> #include "fs_enet_main.c"
>
> fs_enet_512x.c:
> #include <asm/mpc512x.h>
> #include "fs_enet_main.c"
>
> And then the makefile would be something along the lines of:
> obj-${CONFIG_FS_ENET_CPM1_ += fs_enet_cpm1.o
> obj-${CONFIG_FS_ENET_CPM2_ += fs_enet_cpm2.o
> obj-${CONFIG_FS_ENET_MPC512x_ += fs_enet_512x.o
>
> A brief look at the driver suggests that access to the fec_t structure
> is restricted to the fec-mii.c and mac-fec.c files.  It might be
> appropriate to duplicate just those files and do some form of
> fs_enet_ops to select between them.
>
> While on the topic, it looks to me like the driver could really use
> some refactoring love.  Having multiple definitions of "fec_t" is
> confusing and potentially lead to hard to find bugs if the wrong
> header gets included by anyone.  I'd like to see all the fec specific
> stuff in arch/powerpc/include/asm moved into drivers/net/fs_enet and
> renamed to reflect the hardware it is associate with.  Stuff like
> "fec_t" is far to generic, not to mention that typedefs are
> discouraged now.
>
> Regardless, I feel your pain.  It is not a pretty situation.
>
> g.
>
> --
> Grant Likely, B.Sc., P.Eng.
> Secret Lab Technologies Ltd.
>

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Re: [PATCH 08/12] mpc5121: Added I2C support.

[John Rigby]

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Ok, the interrupt enabling should happen in the driver.  Should it key off
compatible or should a new property be added like the existing 5200 clocking
property?

On Wed, May 6, 2009 at 8:41 PM, Grant Likely <grant.likely@secretlab.ca>wrote:

> On Wed, May 6, 2009 at 4:51 PM, Grant Likely <grant.likely@secretlab.ca>
> wrote:
> > On Wed, May 6, 2009 at 4:19 PM, Wolfgang Denk <wd@denx.de> wrote:
> >> Dear Grant Likely,
> >>
> >> In message <fa686aa40905061401k319313c5q89fd3e245c30808f@mail.gmail.com>
> you wrote:
> >>> On Wed, May 6, 2009 at 2:15 PM, Wolfgang Denk <wd@denx.de> wrote:
> >>> > From: Piotr Ziecik <kosmo@semihalf.com>
> >>> >
> >>> > - Enabled I2C interrupts on MPC5121.
> >>> > - Updated Kconfig for i2c-mpc driver.
> >>>
> >>> I think this workaround belongs in the driver itself.
> >>
> >> Sorry, I don't get it. Which workaround? What exactly should I change?
> >
> > Sorry, I misread the patch.  Never mind.
>
> Actually, on 3rd reading, I think my first impression was correct
> (even if I was wrong about it being a workaround).  This code in
> mpc512x_init_i2c() is only relevant for i2c busses (it isn't shared
> with any other drivers).  Therefore, it belongs with the i2c bus
> itself.  It does not belong in platform code.
>
> Cheers,
> g.
>
> --
> Grant Likely, B.Sc., P.Eng.
> Secret Lab Technologies Ltd.
>

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Re: [PATCH 06/12] mpc5121: Added NAND Flash Controller driver.

[John Rigby]

[-- Attachment #1: Type: text/plain, Size: 826 bytes --]

On Wed, May 6, 2009 at 2:59 PM, Grant Likely <grant.likely@secretlab.ca>wrote:

>
>
> > diff --git a/arch/powerpc/platforms/512x/mpc512x_shared.c
> b/arch/powerpc/platforms/512x/mpc512x_shared.c
> > index d8cd579..7135d89 100644
> > --- a/arch/powerpc/platforms/512x/mpc512x_shared.c
> > +++ b/arch/powerpc/platforms/512x/mpc512x_shared.c
> > @@ -71,6 +71,7 @@ void __init mpc512x_init_IRQ(void)
> >  static struct of_device_id __initdata of_bus_ids[] = {
> >        { .compatible = "fsl,mpc5121-immr", },
> >        { .compatible = "fsl,mpc5121-localbus", },
> > +       { .compatible = "fsl,mpc5121-nfc", },
>
> This doesn't look right.  Shouldn't the NAND controller be hanging of
> the IMMR node?
>

I just wanted to confirm that NFC is in its own memory space.   It has its
own mapping and is not part of the IMMR space.

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Re: [PATCH 03/12] fs_enet: Add FEC TX Alignment workaround for MPC5121.

[John Rigby]

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I was having deja-vu with this and realized that I have fixed at least some
of the objections to this patch.

Wolfgang you may want to look at the patch in my 5121 git tree here:

http://git.denx.de/?p=linux-mpc512x.git;a=commit;h=2950be3be42af7449941c3340998c27ef918f10f

It does runtime tx packet alignment  It also has fewer ifdefs and trys to
share more code.  It also has a header that explains everything including
that fact that there is not a runtime conflict sine the only other ppc that
has fec is 8xx which is not in the same family.

On Wed, May 6, 2009 at 4:42 PM, Grant Likely <grant.likely@secretlab.ca>wrote:

> On Wed, May 6, 2009 at 4:12 PM, Wolfgang Denk <wd@denx.de> wrote:
> > Dear Grant Likely,
> >
> > In message <fa686aa40905061337w6aa82f5aj787618ba108e528f@mail.gmail.com>
> you wrote:
> >>
> >> > The FEC on 5121 has problems with misaligned tx buffers.
> >> > The RM says any alignment is ok but empirical results
> >> > show that packet buffers ending in 0x1E will sometimes
> >> > hang the FEC. Other bad alignment does not hang but will
> >> > cause silent TX failures resulting in about a 1% packet
> >> > loss as tested by ping -f from a remote host.
> >> >
> >> > This patch is a work around that copies every tx packet
> >> > to an aligned skb before sending.
> >>
> >> OUCH!
> >
> > Yes :-(
> >
> >> > +#else
> >> > +#define tx_skb_align_workaround(dev, skb) (skb)
> >> > +#endif
> >>
> >> Another use of #ifdef blocks.  What is the multiplatform impact?
> >
> > Hm... Can you recommend a better way to solve the problem? Suggestions
> > are welcome.
>
> I'd rather see a runtime selectable workaround.  ie. enable it based
> on the compatible property.
>
> g.
>
> --
> Grant Likely, B.Sc., P.Eng.
> Secret Lab Technologies Ltd.
>

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Re: [rtc-linux] Re: [PATCH 10/12] mpc5121: Add MPC5121 Real time clock driver.

[John Rigby]

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Can we get 5121 support in and add 5200 support later?  They are not
identical.

On Wed, May 6, 2009 at 4:40 PM, Grant Likely <grant.likely@secretlab.ca>wrote:

>
> On Wed, May 6, 2009 at 3:06 PM, Wolfram Sang <w.sang@pengutronix.de>
> wrote:
> > On Wed, May 06, 2009 at 10:15:17PM +0200, Wolfgang Denk wrote:
> >> From: John Rigby <jrigby@freescale.com>
> >>
> >> Based on Domen Puncer's rtc driver for 5200 posted to
> >> the ppclinux mailing list:
> >>       http://patchwork.ozlabs.org/linuxppc-embedded/patch?id=11675
> >> but never commited anywhere.
> >>
> >> Changes to Domen's original:
> >>
> >>     Changed filenames/routine names from mpc5200* to mpc5121*
> >
> > Why not changing it to mpc5xxx? From a glimpse, it should still work on
> > MPC5200, too.
>
> If this is true, the I heartily agree with Wolfram.  :-)
>
> g.
>
> --
> Grant Likely, B.Sc., P.Eng.
> Secret Lab Technologies Ltd.
>
> --~--~---------~--~----~------------~-------~--~----~
> You received this message because you are subscribed to "rtc-linux".
> Membership options at http://groups.google.com/group/rtc-linux .
> Please read http://groups.google.com/group/rtc-linux/web/checklist
> before submitting a driver.
> -~----------~----~----~----~------~----~------~--~---
>
>

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Re: [PATCH 11/12] mpc5121: Added MPC512x DMA driver.

[John Rigby]

[-- Attachment #1: Type: text/plain, Size: 2476 bytes --]

On Wed, May 6, 2009 at 3:07 PM, Grant Likely <grant.likely@secretlab.ca>wrote:

> On Wed, May 6, 2009 at 2:15 PM, Wolfgang Denk <wd@denx.de> wrote:
> > From: Piotr Ziecik <kosmo@semihalf.com>
> >
> > This patch adds initial version of MPC512x DMA driver.
> > Only memory to memory transfers are currenly supported.
> >
> > Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
> > Signed-off-by: Wolfgang Denk <wd@denx.de>
> > Cc: Grant Likely <grant.likely@secretlab.ca>
> > Cc: John Rigby <jcrigby@gmail.com>
>
> Don't have time to review this in detail right now, but three quick
> comments:
>
> >  drivers/dma/mpc512x_dma.c                    |  642
> ++++++++++++++++++++++++++
> >  drivers/dma/mpc512x_dma.h                    |  192 ++++++++
>
> It looks to me like these two files should be merged.
>
> > diff --git a/arch/powerpc/boot/dts/mpc5121ads.dts
> b/arch/powerpc/boot/dts/mpc5121ads.dts
> > index c2d9de9..e7f0e09 100644
> > --- a/arch/powerpc/boot/dts/mpc5121ads.dts
> > +++ b/arch/powerpc/boot/dts/mpc5121ads.dts
> > @@ -373,7 +373,7 @@
> >                };
> >
> >                dma@14000 {
> > -                       compatible = "fsl,mpc5121-dma2";
> > +                       compatible = "fsl,mpc512x-dma";
>
> Nack.  Compatible values should not use wildcards.  Be specific.  And
> be specific about what it is compatible to if another part implements
> the same device.

The internal name for the dma module was dma2 that is where the orginal name
came from.  There is a dma2 in some 8xxx but last I looked it is not at all
the same.  I would vote for fsl,mpc5121-dma.

>
>
> >                        reg = <0x14000 0x1800>;
> >                        interrupts = <65 0x8>;
> >                        interrupt-parent = < &ipic >;
> > diff --git a/arch/powerpc/platforms/512x/mpc512x_shared.c
> b/arch/powerpc/platforms/512x/mpc512x_shared.c
> > index b776e45..135fd6b 100644
> > --- a/arch/powerpc/platforms/512x/mpc512x_shared.c
> > +++ b/arch/powerpc/platforms/512x/mpc512x_shared.c
> > @@ -95,6 +95,7 @@ void __init mpc512x_init_i2c(void)
> >  static struct of_device_id __initdata of_bus_ids[] = {
> >        { .compatible = "fsl,mpc5121-immr", },
> >        { .compatible = "fsl,mpc5121-localbus", },
> > +       { .compatible = "fsl,mpc5121-dma", },
>
> This doesn't look right either.  Shouldn't the dma device hang off the
> IMMR node?

Yes dma is part of IMMR.

>
>
> g.
>
> --
> Grant Likely, B.Sc., P.Eng.
> Secret Lab Technologies Ltd.
>

[-- Attachment #2: Type: text/html, Size: 3779 bytes --]

Re: [PATCH 08/12] mpc5121: Added I2C support.

[Grant Likely]

On Thu, May 7, 2009 at 8:12 PM, John Rigby <jcrigby@gmail.com> wrote:
> Ok, the interrupt enabling should happen in the driver.=A0 Should it key =
off
> compatible or should a new property be added like the existing 5200 clock=
ing
> property?

key off compatible.  And the 5200 clocking property has been depreciated.

g.

--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.

Re: [PATCH 06/12] mpc5121: Added NAND Flash Controller driver.

[Grant Likely]

On Thu, May 7, 2009 at 8:22 PM, John Rigby <jcrigby@gmail.com> wrote:
>
>
> On Wed, May 6, 2009 at 2:59 PM, Grant Likely <grant.likely@secretlab.ca>
> wrote:
>>
>>
>> > diff --git a/arch/powerpc/platforms/512x/mpc512x_shared.c
>> > b/arch/powerpc/platforms/512x/mpc512x_shared.c
>> > index d8cd579..7135d89 100644
>> > --- a/arch/powerpc/platforms/512x/mpc512x_shared.c
>> > +++ b/arch/powerpc/platforms/512x/mpc512x_shared.c
>> > @@ -71,6 +71,7 @@ void __init mpc512x_init_IRQ(void)
>> > =A0static struct of_device_id __initdata of_bus_ids[] =3D {
>> > =A0 =A0 =A0 =A0{ .compatible =3D "fsl,mpc5121-immr", },
>> > =A0 =A0 =A0 =A0{ .compatible =3D "fsl,mpc5121-localbus", },
>> > + =A0 =A0 =A0 { .compatible =3D "fsl,mpc5121-nfc", },
>>
>> This doesn't look right. =A0Shouldn't the NAND controller be hanging of
>> the IMMR node?
>
> I just wanted to confirm that NFC is in its own memory space. =A0 It has =
its
> own mapping and is not part of the IMMR space.

Hmmm... I wonder then if it might be better to have an IPB node, and
hang all the IPB connected nodes off of it.

g.

--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.

Re: [PATCH 06/12] mpc5121: Added NAND Flash Controller driver.

[John Rigby]

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Did you choose to not support hardware ECC so you could use the spare area?
The original driver only supported hardware ECC but unfortuneatly the
hardware ECC includes the spare area so the spare area cannot be written
separately.

On Wed, May 6, 2009 at 2:15 PM, Wolfgang Denk <wd@denx.de> wrote:

> From: Piotr Ziecik <kosmo@semihalf.com>
>
> This patch adds NAND Flash Controller driver for MPC5121
> revision 2. All device features, except hardware ECC and
> power management, are supported.
>
> Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
> Signed-off-by: Wolfgang Denk <wd@denx.de>
> Cc: <linux-mtd@lists.infradead.org>
> Cc: Grant Likely <grant.likely@secretlab.ca>
> Cc: John Rigby <jcrigby@gmail.com>
> ---
>  arch/powerpc/include/asm/mpc5121_nfc.h       |  100 +++
>  arch/powerpc/platforms/512x/mpc512x_shared.c |    1 +
>  drivers/mtd/nand/Kconfig                     |    7 +
>  drivers/mtd/nand/Makefile                    |    1 +
>  drivers/mtd/nand/mpc5121_nfc.c               |  855
> ++++++++++++++++++++++++++
>  5 files changed, 964 insertions(+), 0 deletions(-)
>  create mode 100644 arch/powerpc/include/asm/mpc5121_nfc.h
>  create mode 100644 drivers/mtd/nand/mpc5121_nfc.c
>
> diff --git a/arch/powerpc/include/asm/mpc5121_nfc.h
> b/arch/powerpc/include/asm/mpc5121_nfc.h
> new file mode 100644
> index 0000000..b96a5b9
> --- /dev/null
> +++ b/arch/powerpc/include/asm/mpc5121_nfc.h
> @@ -0,0 +1,100 @@
> +/*
> + * Copyright 2004-2008 Freescale Semiconductor, Inc.
> + * Copyright 2009 Semihalf.
> + *
> + * Approved as OSADL project by a majority of OSADL members and funded
> + * by OSADL membership fees in 2009;  for details see www.osadl.org.
> + *
> + * Based on original driver from Freescale Semiconductor
> + * written by John Rigby <jrigby@freescale.com> on basis
> + * of drivers/mtd/nand/mxc_nand.c. Reworked and extended by
> + * Piotr Ziecik <kosmo@semihalf.com>.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version 2
> + * of the License, or (at your option) any later version.
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301, USA.
> + */
> +
> +#ifndef MPC5121_NFC_H
> +#define MPC5121_NFC_H
> +
> +/* Addresses for NFC MAIN RAM BUFFER areas */
> +#define NFC_MAIN_AREA(n)       ((n) *  0x200)
> +
> +/* Addresses for NFC SPARE BUFFER areas */
> +#define NFC_SPARE_BUFFERS      8
> +#define NFC_SPARE_LEN          0x40
> +#define NFC_SPARE_AREA(n)      (0x1000 + ((n) * NFC_SPARE_LEN))
> +
> +/* MPC5121 NFC registers */
> +#define NFC_BUF_ADDR           0x1E04
> +#define NFC_FLASH_ADDR         0x1E06
> +#define NFC_FLASH_CMD          0x1E08
> +#define NFC_CONFIG             0x1E0A
> +#define NFC_ECC_STATUS1                0x1E0C
> +#define NFC_ECC_STATUS2                0x1E0E
> +#define NFC_SPAS               0x1E10
> +#define NFC_WRPROT             0x1E12
> +#define NFC_NF_WRPRST          0x1E18
> +#define NFC_CONFIG1            0x1E1A
> +#define NFC_CONFIG2            0x1E1C
> +#define NFC_UNLOCKSTART_BLK0   0x1E20
> +#define NFC_UNLOCKEND_BLK0     0x1E22
> +#define NFC_UNLOCKSTART_BLK1   0x1E24
> +#define NFC_UNLOCKEND_BLK1     0x1E26
> +#define NFC_UNLOCKSTART_BLK2   0x1E28
> +#define NFC_UNLOCKEND_BLK2     0x1E2A
> +#define NFC_UNLOCKSTART_BLK3   0x1E2C
> +#define NFC_UNLOCKEND_BLK3     0x1E2E
> +
> +/* Bit Definitions: NFC_BUF_ADDR */
> +#define NFC_RBA_MASK           (7 << 0)
> +#define NFC_ACTIVE_CS_SHIFT    5
> +#define NFC_ACTIVE_CS_MASK     (3 << NFC_ACTIVE_CS_SHIFT)
> +
> +/* Bit Definitions: NFC_CONFIG */
> +#define NFC_BLS_UNLOCKED       (1 << 1)
> +
> +/* Bit Definitions: NFC_CONFIG1 */
> +#define NFC_ECC_4BIT           (1 << 0)
> +#define NFC_FULL_PAGE_DMA      (1 << 1)
> +#define NFC_SPARE_ONLY         (1 << 2)
> +#define NFC_ECC_ENABLE         (1 << 3)
> +#define NFC_INT_MASK           (1 << 4)
> +#define NFC_BIG_ENDIAN         (1 << 5)
> +#define NFC_RESET              (1 << 6)
> +#define NFC_CE                 (1 << 7)
> +#define NFC_ONE_CYCLE          (1 << 8)
> +#define NFC_PPB_32             (0 << 9)
> +#define NFC_PPB_64             (1 << 9)
> +#define NFC_PPB_128            (2 << 9)
> +#define NFC_PPB_256            (3 << 9)
> +#define NFC_PPB_MASK           (3 << 9)
> +#define NFC_FULL_PAGE_INT      (1 << 11)
> +
> +/* Bit Definitions: NFC_CONFIG2 */
> +#define NFC_COMMAND            (1 << 0)
> +#define NFC_ADDRESS            (1 << 1)
> +#define NFC_INPUT              (1 << 2)
> +#define NFC_OUTPUT             (1 << 3)
> +#define NFC_ID                 (1 << 4)
> +#define NFC_STATUS             (1 << 5)
> +#define NFC_CMD_FAIL           (1 << 15)
> +#define NFC_INT                        (1 << 15)
> +
> +/* Bit Definitions: NFC_WRPROT */
> +#define NFC_WPC_LOCK_TIGHT     (1 << 0)
> +#define NFC_WPC_LOCK           (1 << 1)
> +#define NFC_WPC_UNLOCK         (1 << 2)
> +
> +#endif /* MPC5121_NFC_H */
> diff --git a/arch/powerpc/platforms/512x/mpc512x_shared.c
> b/arch/powerpc/platforms/512x/mpc512x_shared.c
> index d8cd579..7135d89 100644
> --- a/arch/powerpc/platforms/512x/mpc512x_shared.c
> +++ b/arch/powerpc/platforms/512x/mpc512x_shared.c
> @@ -71,6 +71,7 @@ void __init mpc512x_init_IRQ(void)
>  static struct of_device_id __initdata of_bus_ids[] = {
>        { .compatible = "fsl,mpc5121-immr", },
>        { .compatible = "fsl,mpc5121-localbus", },
> +       { .compatible = "fsl,mpc5121-nfc", },
>        {},
>  };
>
> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
> index 890936d..fb0d1c4 100644
> --- a/drivers/mtd/nand/Kconfig
> +++ b/drivers/mtd/nand/Kconfig
> @@ -413,6 +413,13 @@ config MTD_NAND_FSL_UPM
>          Enables support for NAND Flash chips wired onto Freescale PowerPC
>          processor localbus with User-Programmable Machine support.
>
> +config MTD_NAND_MPC5121_NFC
> +       tristate "MPC5121 built-in NAND Flash Controller support"
> +       depends on PPC_MPC512x
> +       help
> +         This enables the driver for the NAND flash controller on the
> +         MPC5121 SoC.
> +
>  config MTD_NAND_MXC
>        tristate "MXC NAND support"
>        depends on ARCH_MX2 || ARCH_MX3
> diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
> index d33860a..563e812 100644
> --- a/drivers/mtd/nand/Makefile
> +++ b/drivers/mtd/nand/Makefile
> @@ -39,5 +39,6 @@ obj-$(CONFIG_MTD_NAND_SH_FLCTL)               +=
> sh_flctl.o
>  obj-$(CONFIG_MTD_NAND_MXC)             += mxc_nand.o
>  obj-$(CONFIG_MTD_NAND_SOCRATES)                += socrates_nand.o
>  obj-$(CONFIG_MTD_NAND_TXX9NDFMC)       += txx9ndfmc.o
> +obj-$(CONFIG_MTD_NAND_MPC5121_NFC)     += mpc5121_nfc.o
>
>  nand-objs := nand_base.o nand_bbt.o
> diff --git a/drivers/mtd/nand/mpc5121_nfc.c
> b/drivers/mtd/nand/mpc5121_nfc.c
> new file mode 100644
> index 0000000..a8da4db
> --- /dev/null
> +++ b/drivers/mtd/nand/mpc5121_nfc.c
> @@ -0,0 +1,855 @@
> +/*
> + * Copyright 2004-2008 Freescale Semiconductor, Inc.
> + * Copyright 2009 Semihalf.
> + *
> + * Based on original driver from Freescale Semiconductor
> + * written by John Rigby <jrigby@freescale.com> on basis
> + * of drivers/mtd/nand/mxc_nand.c. Reworked and extended
> + * Piotr Ziecik <kosmo@semihalf.com>.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version 2
> + * of the License, or (at your option) any later version.
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
> + * MA 02110-1301, USA.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/init.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/mtd/mtd.h>
> +#include <linux/mtd/nand.h>
> +#include <linux/mtd/partitions.h>
> +#include <linux/of_device.h>
> +#include <linux/of_platform.h>
> +
> +#include <asm/mpc512x.h>
> +#include <asm/mpc5121_nfc.h>
> +
> +#define        DRV_NAME                "mpc5121_nfc"
> +#define        DRV_VERSION             "0.5"
> +
> +/* Timeouts */
> +#define NFC_RESET_TIMEOUT      1000            /* 1 ms */
> +#define NFC_TIMEOUT            (HZ / 10)       /* 1/10 s */
> +
> +struct mpc5121_nfc_prv {
> +       struct mtd_info         mtd;
> +       struct nand_chip        chip;
> +       int                     irq;
> +       void __iomem            *regs;
> +       struct clk              *clk;
> +       wait_queue_head_t       irq_waitq;
> +       uint                    column;
> +       int                     spareonly;
> +       void __iomem            *csreg;
> +};
> +
> +static void mpc5121_nfc_done(struct mtd_info *mtd);
> +
> +#ifdef CONFIG_MTD_PARTITIONS
> +static const char *mpc5121_nfc_pprobes[] = { "cmdlinepart", NULL };
> +#endif
> +
> +/* Read NFC register */
> +static inline u16 nfc_read(struct mtd_info *mtd, uint reg)
> +{
> +       struct nand_chip *chip = mtd->priv;
> +       struct mpc5121_nfc_prv *prv = chip->priv;
> +
> +       return in_be16(prv->regs + reg);
> +}
> +
> +/* Write NFC register */
> +static inline void nfc_write(struct mtd_info *mtd, uint reg, u16 val)
> +{
> +       struct nand_chip *chip = mtd->priv;
> +       struct mpc5121_nfc_prv *prv = chip->priv;
> +
> +       out_be16(prv->regs + reg, val);
> +}
> +
> +/* Set bits in NFC register */
> +static inline void nfc_set(struct mtd_info *mtd, uint reg, u16 bits)
> +{
> +       nfc_write(mtd, reg, nfc_read(mtd, reg) | bits);
> +}
> +
> +/* Clear bits in NFC register */
> +static inline void nfc_clear(struct mtd_info *mtd, uint reg, u16 bits)
> +{
> +       nfc_write(mtd, reg, nfc_read(mtd, reg) & ~bits);
> +}
> +
> +/* Invoke address cycle */
> +static inline void mpc5121_nfc_send_addr(struct mtd_info *mtd, u16 addr)
> +{
> +       nfc_write(mtd, NFC_FLASH_ADDR, addr);
> +       nfc_write(mtd, NFC_CONFIG2, NFC_ADDRESS);
> +       mpc5121_nfc_done(mtd);
> +}
> +
> +/* Invoke command cycle */
> +static inline void mpc5121_nfc_send_cmd(struct mtd_info *mtd, u16 cmd)
> +{
> +       nfc_write(mtd, NFC_FLASH_CMD, cmd);
> +       nfc_write(mtd, NFC_CONFIG2, NFC_COMMAND);
> +       mpc5121_nfc_done(mtd);
> +}
> +
> +/* Send data from NFC buffers to NAND flash */
> +static inline void mpc5121_nfc_send_prog_page(struct mtd_info *mtd)
> +{
> +       nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
> +       nfc_write(mtd, NFC_CONFIG2, NFC_INPUT);
> +       mpc5121_nfc_done(mtd);
> +}
> +
> +/* Receive data from NAND flash */
> +static inline void mpc5121_nfc_send_read_page(struct mtd_info *mtd)
> +{
> +       nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
> +       nfc_write(mtd, NFC_CONFIG2, NFC_OUTPUT);
> +       mpc5121_nfc_done(mtd);
> +}
> +
> +/* Receive ID from NAND flash */
> +static inline void mpc5121_nfc_send_read_id(struct mtd_info *mtd)
> +{
> +       nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
> +       nfc_write(mtd, NFC_CONFIG2, NFC_ID);
> +       mpc5121_nfc_done(mtd);
> +}
> +
> +/* Receive status from NAND flash */
> +static inline void mpc5121_nfc_send_read_status(struct mtd_info *mtd)
> +{
> +       nfc_clear(mtd, NFC_BUF_ADDR, NFC_RBA_MASK);
> +       nfc_write(mtd, NFC_CONFIG2, NFC_STATUS);
> +       mpc5121_nfc_done(mtd);
> +}
> +
> +/* NFC interrupt handler */
> +static irqreturn_t mpc5121_nfc_irq(int irq, void *data)
> +{
> +       struct mtd_info *mtd = data;
> +       struct nand_chip *chip = mtd->priv;
> +       struct mpc5121_nfc_prv *prv = chip->priv;
> +
> +       nfc_set(mtd, NFC_CONFIG1, NFC_INT_MASK);
> +       wake_up(&prv->irq_waitq);
> +
> +       return IRQ_HANDLED;
> +}
> +
> +/* Wait for operation complete */
> +static void mpc5121_nfc_done(struct mtd_info *mtd)
> +{
> +       struct nand_chip *chip = mtd->priv;
> +       struct mpc5121_nfc_prv *prv = chip->priv;
> +       int rv;
> +
> +       if ((nfc_read(mtd, NFC_CONFIG2) & NFC_INT) == 0) {
> +               nfc_clear(mtd, NFC_CONFIG1, NFC_INT_MASK);
> +               rv = wait_event_timeout(prv->irq_waitq,
> +                       (nfc_read(mtd, NFC_CONFIG2) & NFC_INT),
> NFC_TIMEOUT);
> +
> +               if (!rv)
> +                       printk(KERN_WARNING DRV_NAME
> +                               ": Timeout while waiting for
> interrupt.\n");
> +       }
> +
> +       nfc_clear(mtd, NFC_CONFIG2, NFC_INT);
> +}
> +
> +/* Do address cycle(s) */
> +static void mpc5121_nfc_addr_cycle(struct mtd_info *mtd, int column, int
> page)
> +{
> +       struct nand_chip *chip = mtd->priv;
> +       u32 pagemask = chip->pagemask;
> +
> +       if (column != -1) {
> +               mpc5121_nfc_send_addr(mtd, column);
> +               if (mtd->writesize > 512)
> +                       mpc5121_nfc_send_addr(mtd, column >> 8);
> +       }
> +
> +       if (page != -1) {
> +               do {
> +                       mpc5121_nfc_send_addr(mtd, page & 0xFF);
> +                       page >>= 8;
> +                       pagemask >>= 8;
> +               } while (pagemask);
> +       }
> +}
> +
> +/* Control chip select signals */
> +static void mpc5121_nfc_select_chip(struct mtd_info *mtd, int chip)
> +{
> +       if (chip < 0) {
> +               nfc_clear(mtd, NFC_CONFIG1, NFC_CE);
> +               return;
> +       }
> +
> +       nfc_clear(mtd, NFC_BUF_ADDR, NFC_ACTIVE_CS_MASK);
> +       nfc_set(mtd, NFC_BUF_ADDR, (chip << NFC_ACTIVE_CS_SHIFT) &
> +
> NFC_ACTIVE_CS_MASK);
> +       nfc_set(mtd, NFC_CONFIG1, NFC_CE);
> +}
> +
> +/* Init external chip select logic on ADS5121 board */
> +static int ads5121_chipselect_init(struct mtd_info *mtd)
> +{
> +       struct nand_chip *chip = mtd->priv;
> +       struct mpc5121_nfc_prv *prv = chip->priv;
> +       struct device_node *dn;
> +
> +       dn = of_find_compatible_node(NULL, NULL, "fsl,mpc5121ads-cpld");
> +       if (dn) {
> +               prv->csreg = of_iomap(dn, 0);
> +               of_node_put(dn);
> +               if (!prv->csreg)
> +                       return -ENOMEM;
> +
> +               /* CPLD Register 9 controls NAND /CE Lines */
> +               prv->csreg += 9;
> +               return 0;
> +       }
> +
> +       return -EINVAL;
> +}
> +
> +/* Control chips select signal on ADS5121 board */
> +static void ads5121_select_chip(struct mtd_info *mtd, int chip)
> +{
> +       struct nand_chip *nand = mtd->priv;
> +       struct mpc5121_nfc_prv *prv = nand->priv;
> +       u8 v;
> +
> +       v = in_8(prv->csreg);
> +       v |= 0x0F;
> +
> +       if (chip >= 0) {
> +               mpc5121_nfc_select_chip(mtd, 0);
> +               v &= ~(1 << chip);
> +       } else
> +               mpc5121_nfc_select_chip(mtd, -1);
> +
> +       out_8(prv->csreg, v);
> +}
> +
> +/* Read NAND Ready/Busy signal */
> +static int mpc5121_nfc_dev_ready(struct mtd_info *mtd)
> +{
> +       /*
> +        * NFC handles ready/busy signal internally. Therefore, this
> function
> +        * always returns status as ready.
> +        */
> +       return 1;
> +}
> +
> +/* Write command to NAND flash */
> +static void mpc5121_nfc_command(struct mtd_info *mtd, unsigned command,
> +                                                       int column, int
> page)
> +{
> +       struct nand_chip *chip = mtd->priv;
> +       struct mpc5121_nfc_prv *prv = chip->priv;
> +
> +       prv->column = (column >= 0) ? column : 0;
> +       prv->spareonly = 0;
> +
> +       switch (command) {
> +       case NAND_CMD_PAGEPROG:
> +               mpc5121_nfc_send_prog_page(mtd);
> +               break;
> +       /*
> +        * NFC does not support sub-page reads and writes,
> +        * so emulate them using full page transfers.
> +        */
> +       case NAND_CMD_READ0:
> +               column = 0;
> +               break;
> +
> +       case NAND_CMD_READ1:
> +               prv->column += 256;
> +               command = NAND_CMD_READ0;
> +               column = 0;
> +               break;
> +
> +       case NAND_CMD_READOOB:
> +               prv->spareonly = 1;
> +               command = NAND_CMD_READ0;
> +               column = 0;
> +               break;
> +
> +       case NAND_CMD_SEQIN:
> +               mpc5121_nfc_command(mtd, NAND_CMD_READ0, column, page);
> +               column = 0;
> +               break;
> +
> +       case NAND_CMD_ERASE1:
> +       case NAND_CMD_ERASE2:
> +       case NAND_CMD_READID:
> +       case NAND_CMD_STATUS:
> +               break;
> +
> +       default:
> +               return;
> +       }
> +
> +       mpc5121_nfc_send_cmd(mtd, command);
> +       mpc5121_nfc_addr_cycle(mtd, column, page);
> +
> +       switch (command) {
> +       case NAND_CMD_READ0:
> +               if (mtd->writesize > 512)
> +                       mpc5121_nfc_send_cmd(mtd, NAND_CMD_READSTART);
> +               mpc5121_nfc_send_read_page(mtd);
> +               break;
> +
> +       case NAND_CMD_READID:
> +               mpc5121_nfc_send_read_id(mtd);
> +               break;
> +
> +       case NAND_CMD_STATUS:
> +               mpc5121_nfc_send_read_status(mtd);
> +               if (chip->options & NAND_BUSWIDTH_16)
> +                       prv->column = 1;
> +               else
> +                       prv->column = 0;
> +               break;
> +       }
> +}
> +
> +/* Copy data from/to NFC spare buffers. */
> +static void mpc5121_nfc_copy_spare(struct mtd_info *mtd, uint offset,
> +                                               u8 *buffer, uint size, int
> wr)
> +{
> +       struct nand_chip *nand = mtd->priv;
> +       struct mpc5121_nfc_prv *prv = nand->priv;
> +       uint o, s, sbsize, blksize;
> +
> +       /*
> +        * NAND spare area is available through NFC spare buffers.
> +        * The NFC divides spare area into (page_size / 512) chunks.
> +        * Each chunk is placed into separate spare memory area, using
> +        * first (spare_size / num_of_chunks) bytes of the buffer.
> +        *
> +        * For NAND device in which the spare area is not divided fully
> +        * by the number of chunks, number of used bytes in each spare
> +        * buffer is rounded down to the nearest even number of bytes,
> +        * and all remaining bytes are added to the last used spare area.
> +        *
> +        * For more information read section 26.6.10 of MPC5121e
> +        * Microcontroller Reference Manual, Rev. 3.
> +        */
> +
> +       /* Calculate number of valid bytes in each spare buffer */
> +       sbsize = (mtd->oobsize / (mtd->writesize / 512)) & ~1;
> +
> +       while (size) {
> +               /* Calculate spare buffer number */
> +               s = offset / sbsize;
> +               if (s > NFC_SPARE_BUFFERS - 1)
> +                       s = NFC_SPARE_BUFFERS - 1;
> +
> +               /*
> +                * Calculate offset to requested data block in selected
> spare
> +                * buffer and its size.
> +                */
> +               o = offset - (s * sbsize);
> +               blksize = min(sbsize - o, size);
> +
> +               if (wr)
> +                       memcpy_toio(prv->regs + NFC_SPARE_AREA(s) + o,
> +                                                       buffer, blksize);
> +               else
> +                       memcpy_fromio(buffer,
> +                               prv->regs + NFC_SPARE_AREA(s) + o,
> blksize);
> +
> +               buffer += blksize;
> +               offset += blksize;
> +               size -= blksize;
> +       };
> +}
> +
> +/* Copy data from/to NFC main and spare buffers */
> +static void mpc5121_nfc_buf_copy(struct mtd_info *mtd, u_char *buf, int
> len,
> +                                                                       int
> wr)
> +{
> +       struct nand_chip *chip = mtd->priv;
> +       struct mpc5121_nfc_prv *prv = chip->priv;
> +       uint c = prv->column;
> +       uint l;
> +
> +       /* Handle spare area access */
> +       if (prv->spareonly || c >= mtd->writesize) {
> +               /* Calculate offset from beginning of spare area */
> +               if (c >= mtd->writesize)
> +                       c -= mtd->writesize;
> +
> +               prv->column += len;
> +               mpc5121_nfc_copy_spare(mtd, c, buf, len, wr);
> +               return;
> +       }
> +
> +       /*
> +        * Handle main area access - limit copy length to prevent
> +        * crossing main/spare boundary.
> +        */
> +       l = min((uint)len, mtd->writesize - c);
> +       prv->column += l;
> +
> +       if (wr)
> +               memcpy_toio(prv->regs + NFC_MAIN_AREA(0) + c, buf, l);
> +       else
> +               memcpy_fromio(buf, prv->regs + NFC_MAIN_AREA(0) + c, l);
> +
> +       /* Handle crossing main/spare boundary */
> +       if (l != len) {
> +               buf += l;
> +               len -= l;
> +               mpc5121_nfc_buf_copy(mtd, buf, len, wr);
> +       }
> +}
> +
> +/* Read data from NFC buffers */
> +static void mpc5121_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int
> len)
> +{
> +       mpc5121_nfc_buf_copy(mtd, buf, len, 0);
> +}
> +
> +/* Write data to NFC buffers */
> +static void mpc5121_nfc_write_buf(struct mtd_info *mtd,
> +                                               const u_char *buf, int len)
> +{
> +       mpc5121_nfc_buf_copy(mtd, (u_char *)buf, len, 1);
> +}
> +
> +/* Compare buffer with NAND flash */
> +static int mpc5121_nfc_verify_buf(struct mtd_info *mtd,
> +                                               const u_char *buf, int len)
> +{
> +       u_char tmp[256];
> +       uint bsize;
> +
> +       while (len) {
> +               bsize = min(len, 256);
> +               mpc5121_nfc_read_buf(mtd, tmp, bsize);
> +
> +               if (memcmp(buf, tmp, bsize))
> +                       return 1;
> +
> +               buf += bsize;
> +               len -= bsize;
> +       }
> +
> +       return 0;
> +}
> +
> +/* Read byte from NFC buffers */
> +static u8 mpc5121_nfc_read_byte(struct mtd_info *mtd)
> +{
> +       u8 tmp;
> +
> +       mpc5121_nfc_read_buf(mtd, &tmp, sizeof(tmp));
> +
> +       return tmp;
> +}
> +
> +/* Read word from NFC buffers */
> +static u16 mpc5121_nfc_read_word(struct mtd_info *mtd)
> +{
> +       u16 tmp;
> +
> +       mpc5121_nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp));
> +
> +       return tmp;
> +}
> +
> +/*
> + * Read NFC configuration from Reset Config Word
> + *
> + * NFC is configured during reset in basis of information stored
> + * in Reset Config Word. There is no other way to set NAND block
> + * size, spare size and bus width.
> + */
> +static int mpc5121_nfc_read_hw_config(struct mtd_info *mtd)
> +{
> +       struct nand_chip *chip = mtd->priv;
> +       struct mpc512x_reset_module *rm;
> +       struct device_node *rmnode;
> +       uint rcw_pagesize = 0;
> +       uint rcw_sparesize = 0;
> +       uint rcw_width;
> +       uint rcwh;
> +       uint romloc, ps;
> +
> +       rmnode = of_find_compatible_node(NULL, NULL, "fsl,mpc5121-reset");
> +       if (!rmnode) {
> +               printk(KERN_ERR DRV_NAME ": Missing 'fsl,mpc5121-reset' "
> +                                               "node in device tree!\n");
> +               return -ENODEV;
> +       }
> +
> +       rm = of_iomap(rmnode, 0);
> +       if (!rm) {
> +               printk(KERN_ERR DRV_NAME
> +                                       ": Error mapping reset module
> node!\n");
> +               return -EBUSY;
> +       }
> +
> +       rcwh = in_be32(&rm->rcwhr);
> +
> +       /* Bit 6: NFC bus width */
> +       rcw_width = ((rcwh >> 6) & 0x1) ? 2 : 1;
> +
> +       /* Bit 7: NFC Page/Spare size */
> +       ps = (rcwh >> 7) & 0x1;
> +
> +       /* Bits [22:21]: ROM Location */
> +       romloc = (rcwh >> 21) & 0x3;
> +
> +       /* Decode RCW bits */
> +       switch ((ps << 2) | romloc) {
> +       case 0x00:
> +       case 0x01:
> +               rcw_pagesize = 512;
> +               rcw_sparesize = 16;
> +               break;
> +       case 0x02:
> +       case 0x03:
> +               rcw_pagesize = 4096;
> +               rcw_sparesize = 128;
> +               break;
> +       case 0x04:
> +       case 0x05:
> +               rcw_pagesize = 2048;
> +               rcw_sparesize = 64;
> +               break;
> +       case 0x06:
> +       case 0x07:
> +               rcw_pagesize = 4096;
> +               rcw_sparesize = 218;
> +               break;
> +       }
> +
> +       mtd->writesize = rcw_pagesize;
> +       mtd->oobsize = rcw_sparesize;
> +       if (rcw_width == 2)
> +               chip->options |= NAND_BUSWIDTH_16;
> +
> +       printk(KERN_NOTICE DRV_NAME ": Configured for "
> +                                               "%u-bit NAND, page size %u
> "
> +                                               "with %u spare.\n",
> +                                               rcw_width * 8,
> rcw_pagesize,
> +                                               rcw_sparesize);
> +       iounmap(rm);
> +       of_node_put(rmnode);
> +       return 0;
> +}
> +
> +/* Free driver resources */
> +static void mpc5121_nfc_free(struct device *dev, struct mtd_info *mtd)
> +{
> +       struct nand_chip *chip = mtd->priv;
> +       struct mpc5121_nfc_prv *prv = chip->priv;
> +
> +       if (prv->clk) {
> +               clk_disable(prv->clk);
> +               clk_put(prv->clk);
> +       }
> +
> +       if (prv->csreg)
> +               iounmap(prv->csreg);
> +}
> +
> +static int __init mpc5121_nfc_probe(struct of_device *op,
> +                                       const struct of_device_id *match)
> +{
> +       struct device_node *rootnode, *dn = op->node;
> +       struct device *dev = &op->dev;
> +       struct mpc5121_nfc_prv *prv;
> +       struct resource res;
> +       struct mtd_info *mtd;
> +#ifdef CONFIG_MTD_PARTITIONS
> +       struct mtd_partition *parts;
> +#endif
> +       struct nand_chip *chip;
> +       unsigned long regs_paddr, regs_size;
> +       const uint *chips_no;
> +       int resettime = 0;
> +       int retval = 0;
> +       int rev, len;
> +
> +       /*
> +        * Check SoC revision. This driver supports only NFC
> +        * in MPC5121 revision 2.
> +        */
> +       rev = (mfspr(SPRN_SVR) >> 4) & 0xF;
> +       if (rev != 2) {
> +               printk(KERN_ERR DRV_NAME
> +                               ": SoC revision %u is not supported!\n",
> rev);
> +               return -ENXIO;
> +       }
> +
> +       prv = devm_kzalloc(dev, sizeof(*prv), GFP_KERNEL);
> +       if (!prv) {
> +               printk(KERN_ERR DRV_NAME ": Memory exhausted!\n");
> +               return -ENOMEM;
> +       }
> +
> +       mtd = &prv->mtd;
> +       chip = &prv->chip;
> +
> +       mtd->priv = chip;
> +       chip->priv = prv;
> +
> +       /* Read NFC configuration from Reset Config Word */
> +       retval = mpc5121_nfc_read_hw_config(mtd);
> +       if (retval) {
> +               printk(KERN_ERR DRV_NAME ": Unable to read NFC config!\n");
> +               return retval;
> +       }
> +
> +       prv->irq = irq_of_parse_and_map(dn, 0);
> +       if (prv->irq == NO_IRQ) {
> +               printk(KERN_ERR DRV_NAME ": Error mapping IRQ!\n");
> +               return -EINVAL;
> +       }
> +
> +       retval = of_address_to_resource(dn, 0, &res);
> +       if (retval) {
> +               printk(KERN_ERR DRV_NAME ": Error parsing memory
> region!\n");
> +               return retval;
> +       }
> +
> +       chips_no = of_get_property(dn, "chips", &len);
> +       if (!chips_no || len != sizeof(*chips_no)) {
> +               printk(KERN_ERR DRV_NAME ": Invalid/missing 'chips' "
> +
> "property!\n");
> +               return -EINVAL;
> +       }
> +
> +       regs_paddr = res.start;
> +       regs_size = res.end - res.start + 1;
> +
> +       if (!devm_request_mem_region(dev, regs_paddr, regs_size, DRV_NAME))
> {
> +               printk(KERN_ERR DRV_NAME ": Error requesting memory
> region!\n");
> +               return -EBUSY;
> +       }
> +
> +       prv->regs = devm_ioremap(dev, regs_paddr, regs_size);
> +       if (!prv->regs) {
> +               printk(KERN_ERR DRV_NAME ": Error mapping memory
> region!\n");
> +               return -ENOMEM;
> +       }
> +
> +       mtd->name = "MPC5121 NAND";
> +       chip->dev_ready = mpc5121_nfc_dev_ready;
> +       chip->cmdfunc = mpc5121_nfc_command;
> +       chip->read_byte = mpc5121_nfc_read_byte;
> +       chip->read_word = mpc5121_nfc_read_word;
> +       chip->read_buf = mpc5121_nfc_read_buf;
> +       chip->write_buf = mpc5121_nfc_write_buf;
> +       chip->verify_buf = mpc5121_nfc_verify_buf;
> +       chip->select_chip = mpc5121_nfc_select_chip;
> +       chip->options = NAND_NO_AUTOINCR | NAND_USE_FLASH_BBT;
> +       chip->ecc.mode = NAND_ECC_SOFT;
> +
> +       /* Support external chip-select logic on ADS5121 board */
> +       rootnode = of_find_node_by_path("/");
> +       if (of_device_is_compatible(rootnode, "fsl,mpc5121ads")) {
> +               retval = ads5121_chipselect_init(mtd);
> +               if (retval) {
> +                       printk(KERN_ERR DRV_NAME ": Chipselect init
> error!\n");
> +                       of_node_put(rootnode);
> +                       return retval;
> +               }
> +
> +               chip->select_chip = ads5121_select_chip;
> +       }
> +       of_node_put(rootnode);
> +
> +       /* Enable NFC clock */
> +       prv->clk = clk_get(dev, "nfc_clk");
> +       if (!prv->clk) {
> +               printk(KERN_ERR DRV_NAME ": Unable to acquire NFC
> clock!\n");
> +               retval = -ENODEV;
> +               goto error;
> +       }
> +
> +       clk_enable(prv->clk);
> +
> +       /* Reset NAND Flash controller */
> +       nfc_set(mtd, NFC_CONFIG1, NFC_RESET);
> +       while (nfc_read(mtd, NFC_CONFIG1) & NFC_RESET) {
> +               if (resettime++ >= NFC_RESET_TIMEOUT) {
> +                       printk(KERN_ERR DRV_NAME
> +                                       ": Timeout while resetting
> NFC!\n");
> +                       retval = -EINVAL;
> +                       goto error;
> +               }
> +
> +               udelay(1);
> +       }
> +
> +       /* Enable write to NFC memory */
> +       nfc_write(mtd, NFC_CONFIG, NFC_BLS_UNLOCKED);
> +
> +       /* Enable write to all NAND pages */
> +       nfc_write(mtd, NFC_UNLOCKSTART_BLK0, 0x0000);
> +       nfc_write(mtd, NFC_UNLOCKEND_BLK0, 0xFFFF);
> +       nfc_write(mtd, NFC_WRPROT, NFC_WPC_UNLOCK);
> +
> +       /*
> +        * Setup NFC:
> +        *      - Big Endian transfers,
> +        *      - Interrupt after full page read/write.
> +        */
> +       nfc_write(mtd, NFC_CONFIG1, NFC_BIG_ENDIAN | NFC_INT_MASK |
> +                                                       NFC_FULL_PAGE_INT);
> +
> +       /* Set spare area size */
> +       nfc_write(mtd, NFC_SPAS, mtd->oobsize >> 1);
> +
> +       init_waitqueue_head(&prv->irq_waitq);
> +       retval = devm_request_irq(dev, prv->irq, &mpc5121_nfc_irq, 0,
> DRV_NAME,
> +
> mtd);
> +       if (retval) {
> +               printk(KERN_ERR DRV_NAME ": Error requesting IRQ!\n");
> +               goto error;
> +       }
> +
> +       /* Detect NAND chips */
> +       if (nand_scan(mtd, *chips_no)) {
> +               printk(KERN_ERR DRV_NAME ": NAND Flash not found !\n");
> +               devm_free_irq(dev, prv->irq, mtd);
> +               retval = -ENXIO;
> +               goto error;
> +       }
> +
> +       /* Set erase block size */
> +       switch (mtd->erasesize / mtd->writesize) {
> +       case 32:
> +               nfc_set(mtd, NFC_CONFIG1, NFC_PPB_32);
> +               break;
> +
> +       case 64:
> +               nfc_set(mtd, NFC_CONFIG1, NFC_PPB_64);
> +               break;
> +
> +       case 128:
> +               nfc_set(mtd, NFC_CONFIG1, NFC_PPB_128);
> +               break;
> +
> +       case 256:
> +               nfc_set(mtd, NFC_CONFIG1, NFC_PPB_256);
> +               break;
> +
> +       default:
> +               printk(KERN_ERR DRV_NAME ": Unsupported NAND flash!\n");
> +               devm_free_irq(dev, prv->irq, mtd);
> +               retval = -ENXIO;
> +               goto error;
> +       }
> +
> +       dev_set_drvdata(dev, mtd);
> +
> +       /* Register device in MTD */
> +#ifdef CONFIG_MTD_PARTITIONS
> +       retval = parse_mtd_partitions(mtd, mpc5121_nfc_pprobes, &parts, 0);
> +#ifdef CONFIG_MTD_OF_PARTS
> +       if (retval == 0)
> +               retval = of_mtd_parse_partitions(dev, dn, &parts);
> +#endif
> +       if (retval < 0) {
> +               printk(KERN_ERR DRV_NAME ": Error parsing MTD
> partitions!\n");
> +               devm_free_irq(dev, prv->irq, mtd);
> +               retval = -EINVAL;
> +               goto error;
> +       }
> +
> +       if (retval > 0)
> +               retval = add_mtd_partitions(mtd, parts, retval);
> +       else
> +#endif
> +               retval = add_mtd_device(mtd);
> +
> +       if (retval) {
> +               printk(KERN_ERR DRV_NAME ": Error adding MTD device!\n");
> +               devm_free_irq(dev, prv->irq, mtd);
> +               goto error;
> +       }
> +
> +       return 0;
> +error:
> +       mpc5121_nfc_free(dev, mtd);
> +       return retval;
> +}
> +
> +static int __exit mpc5121_nfc_remove(struct of_device *op)
> +{
> +       struct device *dev = &op->dev;
> +       struct mtd_info *mtd = dev_get_drvdata(dev);
> +       struct nand_chip *chip = mtd->priv;
> +       struct mpc5121_nfc_prv *prv = chip->priv;
> +
> +       nand_release(mtd);
> +       devm_free_irq(dev, prv->irq, mtd);
> +       mpc5121_nfc_free(dev, mtd);
> +
> +       return 0;
> +}
> +
> +static struct of_device_id mpc5121_nfc_match[] = {
> +       { .compatible = "fsl,mpc5121-nfc", },
> +       {},
> +};
> +
> +static struct of_platform_driver mpc5121_nfc_driver = {
> +       .owner          = THIS_MODULE,
> +       .name           = DRV_NAME,
> +       .match_table    = mpc5121_nfc_match,
> +       .probe          = mpc5121_nfc_probe,
> +       .remove         = __exit_p(mpc5121_nfc_remove),
> +       .suspend        = NULL,
> +       .resume         = NULL,
> +       .driver         = {
> +               .name   = DRV_NAME,
> +               .owner  = THIS_MODULE,
> +       },
> +};
> +
> +static int __init mpc5121_nfc_init(void)
> +{
> +       if (of_register_platform_driver(&mpc5121_nfc_driver) != 0) {
> +               printk(KERN_ERR DRV_NAME ": Driver register failed!\n");
> +               return -ENODEV;
> +       }
> +       return 0;
> +}
> +
> +static void __exit mpc5121_nfc_cleanup(void)
> +{
> +       of_unregister_platform_driver(&mpc5121_nfc_driver);
> +}
> +
> +module_init(mpc5121_nfc_init);
> +module_exit(mpc5121_nfc_cleanup);
> +
> +MODULE_AUTHOR("Freescale Semiconductor, Inc.");
> +MODULE_DESCRIPTION("MPC5121 NAND MTD driver");
> +MODULE_LICENSE("GPL");
> +MODULE_VERSION(DRV_VERSION);
> --
> 1.6.0.6
>
>

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Re: [PATCH 02/12] fs_enet: Add MPC5121 FEC support.

[David Miller]

From: John Rigby <jcrigby@gmail.com>
Date: Thu, 7 May 2009 20:02:53 -0600

> Also don't forget that the register map is the same on 512x, mx and
> coldfire platforms but not on the other ppc platforms so if you want
> to one binary to rule them all you will need to have an offest table
> or some such.

I would suggest using ->read_reg() ->write_reg() methods for abstracting
this.  That's how we handle all of the different way ESP scsi chips
have their registers wired up.

I/O register reads take hundreds, if not thousands of CPU cycles so,
relatively speaking, the indirection costs absolutely nothing.

Re: [rtc-linux] Re: [PATCH 10/12] mpc5121: Add MPC5121 Real time clock driver.

[Grant Likely]

On Thu, May 7, 2009 at 8:41 PM, John Rigby <jcrigby@gmail.com> wrote:
> Can we get 5121 support in and add 5200 support later?=A0 They are not
> identical.

That is fine by me, but since it is known that it will eventually
support both, I'd like it to be renamed to 5xxx before it is merged to
avoid a later rename patch.

g.

> On Wed, May 6, 2009 at 4:40 PM, Grant Likely <grant.likely@secretlab.ca>
> wrote:
>>
>> On Wed, May 6, 2009 at 3:06 PM, Wolfram Sang <w.sang@pengutronix.de>
>> wrote:
>> > On Wed, May 06, 2009 at 10:15:17PM +0200, Wolfgang Denk wrote:
>> >> From: John Rigby <jrigby@freescale.com>
>> >>
>> >> Based on Domen Puncer's rtc driver for 5200 posted to
>> >> the ppclinux mailing list:
>> >> =A0 =A0 =A0 http://patchwork.ozlabs.org/linuxppc-embedded/patch?id=3D=
11675
>> >> but never commited anywhere.
>> >>
>> >> Changes to Domen's original:
>> >>
>> >> =A0 =A0 Changed filenames/routine names from mpc5200* to mpc5121*
>> >
>> > Why not changing it to mpc5xxx? From a glimpse, it should still work o=
n
>> > MPC5200, too.
>>
>> If this is true, the I heartily agree with Wolfram. =A0:-)
>>
>> g.
>>
>> --
>> Grant Likely, B.Sc., P.Eng.
>> Secret Lab Technologies Ltd.
>>
>> --~--~---------~--~----~------------~-------~--~----~
>> You received this message because you are subscribed to "rtc-linux".
>> Membership options at http://groups.google.com/group/rtc-linux .
>> Please read http://groups.google.com/group/rtc-linux/web/checklist
>> before submitting a driver.
>> -~----------~----~----~----~------~----~------~--~---
>>
>
>
> _______________________________________________
> Linuxppc-dev mailing list
> Linuxppc-dev@ozlabs.org
> https://ozlabs.org/mailman/listinfo/linuxppc-dev
>



--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.

Re: [rtc-linux] Re: [PATCH 10/12] mpc5121: Add MPC5121 Real time clock driver.

[Alessandro Zummo]

On Fri, 8 May 2009 09:53:20 -0600
Grant Likely <grant.likely@secretlab.ca> wrote:

> That is fine by me, but since it is known that it will eventually
> support both, I'd like it to be renamed to 5xxx before it is merged to
> avoid a later rename patch.

 or 52xx ?

-- 

 Best regards,

 Alessandro Zummo,
  Tower Technologies - Torino, Italy

  http://www.towertech.it

Re: [rtc-linux] Re: [PATCH 10/12] mpc5121: Add MPC5121 Real time clock driver.

[Alessandro Zummo]

On Fri, 8 May 2009 09:53:20 -0600
Grant Likely <grant.likely@secretlab.ca> wrote:

> That is fine by me, but since it is known that it will eventually
> support both, I'd like it to be renamed to 5xxx before it is merged to
> avoid a later rename patch.

 sorry, forget my last email, I misread the codes.

-- 

 Best regards,

 Alessandro Zummo,
  Tower Technologies - Torino, Italy

  http://www.towertech.it

Re: [rtc-linux] Re: [PATCH 10/12] mpc5121: Add MPC5121 Real time clock driver.

[Wolfgang Denk]

Dear Alessandro Zummo,

In message <20090508180944.1304a8b7@i1501.lan.towertech.it> you wrote:
> On Fri, 8 May 2009 09:53:20 -0600
> Grant Likely <grant.likely@secretlab.ca> wrote:
> 
> > That is fine by me, but since it is known that it will eventually
> > support both, I'd like it to be renamed to 5xxx before it is merged to
> > avoid a later rename patch.
> 
>  or 52xx ?

No, because the current version is for MPC5>1<2x

Best regards,

Wolfgang Denk

-- 
DENX Software Engineering GmbH,     MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de
Misquotation is, in fact, the pride and privilege of the  learned.  A
widely-read  man  never  quotes  accurately,  for  the rather obvious
reason that he has read too widely.
                - Hesketh Pearson _Common Misquotations_ introduction

Re: [PATCH 02/12] fs_enet: Add MPC5121 FEC support.

[David Jander]

On Friday 08 May 2009 09:52:51 David Miller wrote:
> From: John Rigby <jcrigby@gmail.com>
> Date: Thu, 7 May 2009 20:02:53 -0600
>
> > Also don't forget that the register map is the same on 512x, mx and
> > coldfire platforms but not on the other ppc platforms so if you want
> > to one binary to rule them all you will need to have an offest table
> > or some such.
>
> I would suggest using ->read_reg() ->write_reg() methods for abstracting
> this.  That's how we handle all of the different way ESP scsi chips
> have their registers wired up.
>
> I/O register reads take hundreds, if not thousands of CPU cycles so,
> relatively speaking, the indirection costs absolutely nothing.

I fear the memory-mapped I/O of the PowerPC SoC is *slightly* faster, so in 
terms of cycle count, this WILL matter, although depending on how much 
register-I/O the driver does, overall performance impact _may_ still be 
negligible. I suggest testing this (benchmarks) before and after the change.

Best regsards,

-- 
David Jander
Protonic Holland.

Re: [PATCH 06/12] mpc5121: Added NAND Flash Controller driver.

[Piotr Zięcik]

=46riday 08 May 2009 05:30:15 John Rigby napisa=B3(a):
> Did you choose to not support hardware ECC so you could use the spare are=
a?
> The original driver only supported hardware ECC but unfortuneatly the
> hardware ECC includes the spare area so the spare area cannot be written
> separately.

In short yes. There are fundamental problems which you described. Flash=20
filesystems expect that ECC is calculated from main area only and writes to=
=20
spare area not change it. MPC5121 NAND flash controller calculates ECC from=
=20
both areas except few bytes holding ECC. This makes flash filesystems=20
unusable when we turn on hardware ECC.

This could be fixed by disabling spare area usage in flash filesystems but
this probably requires changes in the MTD/filesystem infrastructure.

=2D-=20
Best Regards.
Piotr Zi=EAcik

Re: [PATCH 02/12] fs_enet: Add MPC5121 FEC support.

[Piotr Zięcik]

Thursday 07 May 2009 00:39:25 Grant Likely napisa=B3(a):
> >> 512x are enabled in the same kernel?
> >
> > Hm... both architectures look sufficiently different to me that I
> > don't see sense in trying such a thing. Do you think that needs to be
> > supported?
>
> Yes!  :-)  It's not hard to do and it keeps the driver cleaner
> (IMNSHO).  I don't think it is quite possible at the moment due to
> cache coherency issues, but with Becky's recently merged dma ops
> changes it should be fixable.

Could you elaborate on the cache coherency issues in MPC5121
=46EC context? Especially how these issues are related to the driver
binary compatibility.=20

MPC5121 support was added to drivers/net/fs_enet. MPC52xx uses
drivers/net/fec_mpc52xx.c. Do you think that creating one universal
driver from these two is now possible? You said that it should be easy,
however you also said that cache coherency issues makes this imposible.

=2D-=20
Best Regards.
Piotr Ziecik

Re: [PATCH 02/12] fs_enet: Add MPC5121 FEC support.

[Grant Likely]

2009/5/14 Piotr Zi=EAcik <kosmo@semihalf.com>:
> Thursday 07 May 2009 00:39:25 Grant Likely napisa=B3(a):
>> >> 512x are enabled in the same kernel?
>> >
>> > Hm... both architectures look sufficiently different to me that I
>> > don't see sense in trying such a thing. Do you think that needs to be
>> > supported?
>>
>> Yes! =A0:-) =A0It's not hard to do and it keeps the driver cleaner
>> (IMNSHO). =A0I don't think it is quite possible at the moment due to
>> cache coherency issues, but with Becky's recently merged dma ops
>> changes it should be fixable.
>
> Could you elaborate on the cache coherency issues in MPC5121
> FEC context? Especially how these issues are related to the driver
> binary compatibility.
>
> MPC5121 support was added to drivers/net/fs_enet. MPC52xx uses
> drivers/net/fec_mpc52xx.c. Do you think that creating one universal
> driver from these two is now possible? You said that it should be easy,
> however you also said that cache coherency issues makes this imposible.

Not impossible.  Hard.

The mpc5200 is a cache coherent part.  Bestcomm memory accesses are
noticed (snooped) by the cache, and it will flush out cache lines
appropriately to maintain coherency.

The mpc5121 bus design is non-coherent.  The e300 core is essentially
the same as on the 5200, and the core can do snooping, but the
multiport memory controller on the 5121 doesn't support bus snooping
so the cache is not automatically maintained in a consistent state.
On this part Linux needs to manually flush the relevant cache lines
before initiating DMA transfers, and invalidiate them afterwards.

All of this doesn't actually affect the driver code at all.  It's all
handled by the kernel and the DMA apis.  What it does affect is
multiplatform kernels.  The DMA behaviour is set at compile time, not
run time, depending on the setting of CONFIG_NON_COHERENT_CACHE (see
arch/powerpc/platforms/Kconfig.cputype).  A kernel which has it on
won't run properly on a platform which has it off, and visa-versa.

So, while the MPC5200 and MPC5121 (and MPC83xx) all have the same
core, it isn't currently possible to build a single kernel which will
boot on both the MPC5200 and the MPC5121.  The solution (i think) is
to kill CONFIG_NON_COHERENT_CACHE and have the platform setup code set
the appropriate dmaops at platform init time.

Cheers,
g.

>
> --
> Best Regards.
> Piotr Ziecik
>



--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.

Re: [PATCH 08/12] mpc5121: Added I2C support.

[Piotr Zięcik]

> Right. Furthermore, the i2c-mpc.c should be extened to support bus speed
> setting for the MPC512x, which has been merged recently (see commit id
> f2bd5efe).

I have simple question about bus speed setting support. Existing=20
implementation uses default safe speed if there is no 'clock-frequency'=20
property in i2c node. Comments in code suggest that this behaviour is left=
=20
for backward compatibility only. Should I make the 'clock-frequency'
property mandatory for a new type of I2C controller (MPC5121) ?

=2D-=20
Best Regards.
Piotr Zi=EAcik

Re: [PATCH 08/12] mpc5121: Added I2C support.

[Grant Likely]

2009/5/18 Piotr Zi=EAcik <kosmo@semihalf.com>:
>> Right. Furthermore, the i2c-mpc.c should be extened to support bus speed
>> setting for the MPC512x, which has been merged recently (see commit id
>> f2bd5efe).
>
> I have simple question about bus speed setting support. Existing
> implementation uses default safe speed if there is no 'clock-frequency'
> property in i2c node. Comments in code suggest that this behaviour is lef=
t
> for backward compatibility only. Should I make the 'clock-frequency'
> property mandatory for a new type of I2C controller (MPC5121) ?

yes.  At least in documentation, but I wouldn't do extra work to
disable that behaviour for 5121 boards.

g.

--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.

Re: [PATCH 08/12] mpc5121: Added I2C support.

[Wolfgang Grandegger]

Piotr Zięcik wrote:
>> Right. Furthermore, the i2c-mpc.c should be extened to support bus speed
>> setting for the MPC512x, which has been merged recently (see commit id
>> f2bd5efe).
> 
> I have simple question about bus speed setting support. Existing 
> implementation uses default safe speed if there is no 'clock-frequency' 
> property in i2c node. Comments in code suggest that this behaviour is left 
> for backward compatibility only. Should I make the 'clock-frequency'
> property mandatory for a new type of I2C controller (MPC5121) ?

I don't think so, for the same backward compatibility reason as for the
other boards. But the DTS file might be changed to use clock-frequency.
BTW, when I wrote the code I already had the MPC512x in mind. IIRC, the
FDR table and the function scanning it for the MPC52xx should work for
the MPC512x as well. It's mainly a matter of using the proper function
to get the source clock frequency and fiddling with multiple-arch support.

Wolfgang.

Re: [PATCH 02/12] fs_enet: Add MPC5121 FEC support.

[Benjamin Herrenschmidt]

On Thu, 2009-05-14 at 08:00 -0600, Grant Likely wrote:
> 
> All of this doesn't actually affect the driver code at all.  It's all
> handled by the kernel and the DMA apis.  What it does affect is
> multiplatform kernels.  The DMA behaviour is set at compile time, not
> run time, depending on the setting of CONFIG_NON_COHERENT_CACHE (see
> arch/powerpc/platforms/Kconfig.cputype).  A kernel which has it on
> won't run properly on a platform which has it off, and visa-versa.

We are close to the point where we can make this a runtime option
though, by just having a different set of dma_ops hooked in.

Cheers,
Ben.

Re: [PATCH 11/12] mpc5121: Added MPC512x DMA driver.

[Hongjun Chen]

[-- Attachment #1: Type: text/plain, Size: 1355 bytes --]

Since you have reuse most part of our BSP, why should you reinvent wheel for MPC512x DMA? We have one ready DMA driver, which has been used by AC97, ATA, VIU etc.




Hongjun Chen
2009-05-19



发件人： Wolfgang Denk
发送时间： 2009-05-07 04:15:18
收件人： linuxppc-dev@ozlabs.org
抄送： Piotr Ziecik; Wolfgang Denk
主题： [PATCH 11/12] mpc5121: Added MPC512x DMA driver.

From: Piotr Ziecik <kosmo@semihalf.com>

This patch adds initial version of MPC512x DMA driver.
Only memory to memory transfers are currenly supported.

Signed-off-by: Piotr Ziecik <kosmo@semihalf.com>
Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Grant Likely <grant.likely@secretlab.ca>
Cc: John Rigby <jcrigby@gmail.com>
---
 arch/powerpc/boot/dts/mpc5121ads.dts         |    2 +-
 arch/powerpc/platforms/512x/mpc512x_shared.c |    1 +
 drivers/dma/Kconfig                          |    7 +
 drivers/dma/Makefile                         |    1 +
 drivers/dma/mpc512x_dma.c                    |  642 ++++++++++++++++++++++++++
 drivers/dma/mpc512x_dma.h                    |  192 ++++++++
 6 files changed, 844 insertions(+), 1 deletions(-)
 create mode 100644 drivers/dma/mpc512x_dma.c
 create mode 100644 drivers/dma/mpc512x_dma.h
_______________________________________________
Linuxppc-dev mailing list
Linuxppc-dev@ozlabs.org
https://ozlabs.org/mailman/listinfo/linuxppc-dev

[-- Attachment #2: Type: text/html, Size: 4230 bytes --]

Re: [PATCH 08/12] mpc5121: Added I2C support.

[Piotr Zięcik]

Monday 18 May 2009 16:29:04 Wolfgang Grandegger napisa=B3(a):
> > I have simple question about bus speed setting support. Existing
> > implementation uses default safe speed if there is no 'clock-frequency'
> > property in i2c node. Comments in code suggest that this behaviour is
> > left for backward compatibility only. Should I make the 'clock-frequenc=
y'
> > property mandatory for a new type of I2C controller (MPC5121) ?
>
> I don't think so, for the same backward compatibility reason as for the
> other boards. But the DTS file might be changed to use clock-frequency.

In my opinion implementing "backward compatilility" for MPC5121 is not good
idea. MPC5121 I2C support is completly new thing in mainline. Simply, there=
 is=20
no DTS with which I have to be compatible. Adding backward compatibility
with nothing may be confusing.

=2D-=20
Best Regards,
Piotr Zi=EAcik

Re: [PATCH 11/12] mpc5121: Added MPC512x DMA driver.

[Piotr Zięcik]

Tuesday 19 May 2009 03:37:47 Hongjun Chen wrote:
> Since you have reuse most part of our BSP, why should you reinvent wheel
> for MPC512x DMA? We have one ready DMA driver, which has been used by AC9=
7,
> ATA, VIU etc.
>

Answer is simple. The old one does not fit Linux DMA API. New one uses=20
existing infrastructure which makes DMA engine aviable for existing consume=
rs
in Linux kernel. For example network stack. Support for I/O <-> memory=20
transfers will be added when more consumers arrive.

=2D-=20
Best Regards.
Piotr Zi=EAcik

Re: [PATCH 08/12] mpc5121: Added I2C support.

[Wolfgang Grandegger]

Piotr Zięcik wrote:
> Monday 18 May 2009 16:29:04 Wolfgang Grandegger napisał(a):
>>> I have simple question about bus speed setting support. Existing
>>> implementation uses default safe speed if there is no 'clock-frequency'
>>> property in i2c node. Comments in code suggest that this behaviour is
>>> left for backward compatibility only. Should I make the 'clock-frequency'
>>> property mandatory for a new type of I2C controller (MPC5121) ?
>> I don't think so, for the same backward compatibility reason as for the
>> other boards. But the DTS file might be changed to use clock-frequency.
> 
> In my opinion implementing "backward compatilility" for MPC5121 is not good
> idea. MPC5121 I2C support is completly new thing in mainline. Simply, there is 
> no DTS with which I have to be compatible. Adding backward compatibility
> with nothing may be confusing.

There is a port for the  MPC5121 in mainline since 2.6.25 including DTS
file:

http://lxr.linux.no/linux+v2.6.25/arch/powerpc/boot/dts/mpc5121ads.dts

If it was really usable or even used is another question. But it's fine
for me be more restrictive, e.g. print a warning when save values are
selected.

Wolfgang.

Re: [PATCH 02/12] fs_enet: Add MPC5121 FEC support.

[Piotr Zięcik]

Tuesday 19 May 2009 00:17:31 Benjamin Herrenschmidt wrote:
>
> We are close to the point where we can make this a runtime option
> though, by just having a different set of dma_ops hooked in.
>

Is somebody currently working on it? If yes, where we can see
code ?

=2D-=20
Best Regards.
Piotr Zi=EAcik

Re: [PATCH 02/12] fs_enet: Add MPC5121 FEC support.

[Benjamin Herrenschmidt]

On Tue, 2009-05-19 at 13:26 +0200, Piotr Zięcik wrote:
> Tuesday 19 May 2009 00:17:31 Benjamin Herrenschmidt wrote:
> >
> > We are close to the point where we can make this a runtime option
> > though, by just having a different set of dma_ops hooked in.
> >
> 
> Is somebody currently working on it? If yes, where we can see
> code ?

Well, the current upstream code has the dma ops support. Becky is
massaging that more for swiotlb support which has been submitted to the
linuxppc-dev list. We haven't yet added runtime support rather than
compile time for non-cache coherent platforms, but it's becoming
reasonably easy to add now (though still needs to be done).

Cheers,
Ben

Re: Re: [PATCH 11/12] mpc5121: Added MPC512x DMA driver.

[Hongjun Chen]

[-- Attachment #1: Type: text/plain, Size: 836 bytes --]

Hi John,

Did you use DMA driver in our FEC driver before?

Best Regards,



Hongjun Chen
2009-05-20



发件人： Piotr Zięcik
发送时间： 2009-05-19 16:05:05
收件人： Hongjun Chen
抄送： Wolfgang Denk; linuxppc-dev@ozlabs.org
主题： Re: [PATCH 11/12] mpc5121: Added MPC512x DMA driver.

Tuesday 19 May 2009 03:37:47 Hongjun Chen wrote:
> Since you have reuse most part of our BSP, why should you reinvent wheel
> for MPC512x DMA? We have one ready DMA driver, which has been used by AC97,
> ATA, VIU etc.
>

Answer is simple. The old one does not fit Linux DMA API. New one uses 
existing infrastructure which makes DMA engine aviable for existing consumers
in Linux kernel. For example network stack. Support for I/O  <- > memory 
transfers will be added when more consumers arrive.

-- 
Best Regards.
Piotr Zięcik

[-- Attachment #2: Type: text/html, Size: 3654 bytes --]

Re: [PATCH 02/12] fs_enet: Add MPC5121 FEC support.

[Piotr Zięcik]

Thursday 14 May 2009 16:00:33 Grant Likely wrote:
> > MPC5121 support was added to drivers/net/fs_enet. MPC52xx uses
> > drivers/net/fec_mpc52xx.c. Do you think that creating one universal
> > driver from these two is now possible? You said that it should be easy,
> > however you also said that cache coherency issues makes this imposible.
>
> Not impossible.  Hard.

I thought a bit more about merging FEC drivers and I see one problem more.
Driver fs_enet works with FEC's with own DMA engine and fec_mpc52xx.c uses 
BestComm. Integration of these two drivers will need a DMA abstraction layer 
to keep everything clean. Unfortuanetly BestComm driver does not provide any 
abstraction - it only exports set of functions to deal with specific 
hardware: FEC and PATA.

More #ifdef's will be needed to remove linking with BestComm driver if kernel 
will be compiled without 52xx support and resulting code will not be much 
better than existing one. Especially that new DMA abstraction layer probably 
will be quite complex.

-- 
Best Regards.
Piotr Ziecik

Re: [PATCH 02/12] fs_enet: Add MPC5121 FEC support.

[Grant Likely]

2009/5/21 Piotr Zi=EAcik <kosmo@semihalf.com>:
> Thursday 14 May 2009 16:00:33 Grant Likely wrote:
>> > MPC5121 support was added to drivers/net/fs_enet. MPC52xx uses
>> > drivers/net/fec_mpc52xx.c. Do you think that creating one universal
>> > driver from these two is now possible? You said that it should be easy=
,
>> > however you also said that cache coherency issues makes this imposible=
.
>>
>> Not impossible. =A0Hard.
>
> I thought a bit more about merging FEC drivers and I see one problem more=
.
> Driver fs_enet works with FEC's with own DMA engine and fec_mpc52xx.c use=
s
> BestComm. Integration of these two drivers will need a DMA abstraction la=
yer
> to keep everything clean. Unfortuanetly BestComm driver does not provide =
any
> abstraction - it only exports set of functions to deal with specific
> hardware: FEC and PATA.
>
> More #ifdef's will be needed to remove linking with BestComm driver if ke=
rnel
> will be compiled without 52xx support and resulting code will not be much
> better than existing one. Especially that new DMA abstraction layer proba=
bly
> will be quite complex.

If it looks too ugly, then just fork the driver.

g.

--=20
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.